Image sensor structure and manufacturing method thereof

Abstract

An image sensor structure and a method for manufacturing the same include a semiconductor device, a plurality of image sensor devices formed in a semiconductor substrate, an interconnect structure formed on the semiconductor substrate, and a composite grid structure on the semiconductor substrate. The composite grid structure includes a tungsten grid, an oxide grid above the tungsten grid, and an adhesion enhancement grid separating the tungsten grid from the oxide grid.

Description

Technical Field

[0001] The present disclosure relates to an image sensor, and more particularly to an image sensor grid and a manufacturing method thereof. Background Art

[0002] Integrated circuits (ICs) with image sensors are used in a wide range of modern electronic devices. In recent years, complementary metal-oxide semiconductor (CMOS) image sensors have begun to see widespread use, primarily replacing charge-coupled device (CCD) image sensors. Compared to CCD image sensors, CMOS image sensors are increasingly popular due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. CMOS image sensors include front-side illuminated (FSI) and back-side illuminated (BSI) image sensors. Summary of the Invention

[0003] In some embodiments, an image sensor structure includes a semiconductor substrate, a plurality of image sensor elements formed in the semiconductor substrate, an interconnect structure formed on the semiconductor substrate, and a composite mesh structure on the semiconductor substrate. The composite mesh structure includes a tungsten mesh, an oxide mesh above the tungsten mesh, and an adhesion enhancement mesh separating the tungsten mesh from the oxide mesh.

[0004] In some embodiments, an image sensor structure includes a semiconductor substrate, a plurality of photodiodes in the semiconductor substrate, an interconnect structure on the semiconductor substrate, and a composite mesh structure on the semiconductor substrate. The composite mesh structure includes an oxide mesh and a metal mesh between the oxide mesh and the semiconductor substrate, and the composite mesh structure lacks an oxide / metal interface.

[0005] In some embodiments, a method for fabricating an image sensor structure includes forming a photodiode in a substrate; forming an interconnect structure on the substrate; depositing a metal grid layer on the substrate, depositing an adhesion enhancing layer on the metal grid layer, and depositing an oxide grid layer on the adhesion enhancing layer; and etching the metal grid layer, the adhesion enhancing layer, and the oxide grid layer to form metal grid lines, adhesion enhancing grid lines extending respectively over the metal grid lines, and oxide grid lines extending respectively over the adhesion enhancing grid lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1The following detailed description will provide a better understanding of the present disclosure. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1 to 5 are cross-sectional views of various intermediate stages of fabricating a backside illuminated (BSI) CMOS image sensor (BSI-CIS) structure according to various embodiments of the present disclosure;

[0008] Figure 6A is a cross-sectional view of an intermediate stage of manufacturing a BSI-CIS structure according to various embodiments of the present disclosure;

[0009] Figure 6B For example Figure 6A A top view of an intermediate stage of the fabricated BSI-CIS structure shown in FIG;

[0010] Figure 7A is a cross-sectional view of an intermediate stage of manufacturing a BSI-CIS structure according to various embodiments of the present disclosure;

[0011] Figure 7B For example Figure 7A A top view of an intermediate stage of the fabricated BSI-CIS structure shown in FIG;

[0012] Figure 8 is a cross-sectional view of an intermediate stage of manufacturing a BSI-CIS structure according to various embodiments of the present disclosure;

[0013] Figure 9 Illustrate a method of manufacturing a BSI-CIS structure according to some embodiments;

[0014] Figure 10 is a cross-sectional view of a BSI-CIS structure according to some embodiments of the present disclosure.

[0015]

Explanation of symbols

[0016] AA: Pixel array area

[0017] BA: Bonding pad area

[0018] PA: surrounding area

[0019] SA: Cutting line area

[0020] BB:Bonding Ball

[0021] BW: Bonded Wire

[0022] CP: Conductive Adhesive Pad

[0023] PD: Component

[0024] SE: Image sensor

[0025] PI: Pixel Area

[0026] E1: Nitride / Tungsten Interface

[0027] E2: Nitride / Oxide Interface

[0028] M: Method

[0029] O1: hole

[0030] O2: Opening

[0031] PM1: Patterned mask layer

[0032] GP: Grid Pattern

[0033] GL: Grid Lines

[0034] GLx: Grid Lines

[0035] GLy: Grid lines

[0036] W1: bottom width

[0037] W2: Top width

[0038] W3: bottom width

[0039] W4: Top width

[0040] W5: bottom width

[0041] W6: Top width

[0042] W7: bottom width

[0043] W8: Top width

[0044] W9: Top width

[0045] 110:Substrate

[0046] 110b: dorsal

[0047] 110f: front side

[0048] 110T: Groove

[0049] 120: Isolation Features

[0050] 130: Transistor gate structure

[0051] 132: Gate dielectric layer

[0052] 134: Gate electrode

[0053] 136: sidewall spacer

[0054] 140: Dielectric structure

[0055] 150: conductive inner connection layer

[0056] 160: Backside deep trench isolation structure

[0057] 180: Anti-reflective coating

[0058] 200: buffer layer

[0059] 200': Patterned buffer layer

[0060] 202b: bottom part

[0061] 202g: Buffer grid

[0062] 210: Barrier layer

[0063] 210': Patterned barrier layer

[0064] 212: Barrier Grid

[0065] 220:Metal mesh layer

[0066] 220': Patterned metal mesh layer

[0067] 222:Metal grid

[0068] 230: Adhesion enhancement layer

[0069] 230': Patterned adhesion enhancing layer

[0070] 232: Adhesion Enhanced Grid

[0071] 240: Overlapping dielectric grid layers

[0072] 240': Patterning the first dielectric grid layer

[0073] 242: First dielectric grid

[0074] 242m: Main segment

[0075] 242t: tapered top section

[0076] 250: Second dielectric grid layer

[0077] 250': Patterning the second dielectric grid layer

[0078] 252: Second dielectric grid

[0079] 260: Composite grid structure

[0080] 270: Color filter

[0081] 280: Microlens

[0082] S11~S17: Blocks

[0083] 900: Support substrate DETAILED DESCRIPTION

[0084] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. In addition, the disclosure may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not substantially define the relationship between the various embodiments and / or configurations discussed.

[0085] Additionally, spatially relative terms, such as "below," "beneath," "below," "above," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0086] A CMOS image sensor (CIS) includes multiple pixel regions, each of which has an image sensing element, such as a photodiode. A backside illuminated (BSI) CMOS image sensor (BSI-CIS) is a semiconductor device that can efficiently capture photons and generate a corresponding electrical signal. BSI-CIS devices are used in consumer electronics and other applications, replacing front-illuminated sensors. This is because these BSI-CIS devices have higher efficiency, provide higher resolution, and reduce manufacturing costs. To form a BSI sensor, image sensing elements such as photodiodes are formed in a substrate along with logic circuitry and internal connection structures. BSI sensors can generate electrical signals based on stimulation from photons that pass through the back side of the substrate and reach the image sensing elements.

[0087] The intensity of the electrical signal (e.g., current signal) depends on the intensity of the incident light received by the individual light detecting elements. BSI sensors can be manufactured as a matrix of image sensing elements. The signal outputs of these sensors can be aggregated to produce a digital, pixelated image. Over time, the semiconductor industry has continuously reduced the size of the pixel area in order to increase the number of pixel areas in the BSI-CIS integrated chip. Increasing the number of pixel areas in the BSI-CIS integrated chip can further improve the resolution of the image captured by the BSI-CIS integrated chip. However, as the size of the pixel area becomes smaller, the pixel areas become closer and the interference between adjacent pixel areas increases.

[0088] To reduce optical crosstalk between pixel regions and / or improve the resolution of images captured by a BSI-CIS integrated chip, light received by different image sensor elements arranged in an array can be directed through a composite grid structure. The composite grid structure is formed from a metal grid and an oxide grid stacked on the metal grid. The composite grid structure is designed to isolate light and / or filter specific spectrums. The robustness of the composite grid structure is designed to minimize or prevent light loss, which can degrade quantum efficiency (QE) (e.g., the percentage of photon-to-electron conversion), angular response, and the 10dB signal-to-noise ratio (SNR10) of the BSI image sensor. However, as the critical dimension (CD) of the grid lines decreases, the adhesion strength between the oxide grid and the metal grid decreases, leading to peeling defects in the composite grid structure, thereby degrading the robustness of the composite grid structure. In some embodiments of the present disclosure, an additional adhesion enhancement layer is inserted between the oxide grid and the metal grid to provide improved adhesion between the metal grid and the oxide grid. Therefore, delamination defects in the composite mesh structure can be alleviated even if the mesh lines have reduced critical dimensions.

[0089] Figures 1 to 8 Methods for fabricating a composite mesh structure for a backside CMOS image sensor (BSI-CIS) structure according to various embodiments of the present disclosure are illustrated. Figure 9 The process flow shown schematically reflects Figures 1 to 8 Throughout the various views and exemplary embodiments, like reference numerals are used to designate like elements. It should be understood that the same reference numerals may be used to designate like elements. Figures 1 to 8 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the methods. The order of the operations / processes is interchangeable.

[0090] Figure 1 A substrate 110 having a front side 110f and a back side 110b is illustrated and bonded to a support substrate 900. In the depicted embodiment, substrate 110 may be a semiconductor substrate comprising silicon. Alternatively or additionally, substrate 110 may comprise another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaAs, GaP, and / or GaASP; or a combination thereof. Substrate 110 may be a semiconductor on insulator (SOI). In some embodiments, substrate 110 may comprise a doped epitaxial layer, a concentration-graded semiconductor layer, and / or a semiconductor layer overlying another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer. In some embodiments, substrate 110 may be thinned by etching and / or mechanical grinding the front side 110f of substrate 110 after being bonded to support substrate 900. Thinning the substrate 110 allows radiation to more easily transmit to image sensing devices subsequently formed within the substrate 110 .

[0091] refer to Figure 2 . One or more isolation features 120 are formed in the front side 110f of the substrate 110. The isolation features 120 include shallow trench isolation (STI) structures and / or local oxidation of silicon (LOCOS) structures. The isolation features 120 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof. The isolation features 120 may be formed by any suitable process. For example, forming the STI structures 120 includes etching trenches in the front side 110f of the substrate 110 (e.g., by using dry etching and / or wet etching), and filling the trenches with one or more dielectric materials (e.g., SiO2) (e.g., by using a chemical vapor deposition process). A chemical mechanical polishing (CMP) process may be performed to planarize the isolation features 120 with the front side 110f of the substrate 110.

[0092] refer to Figure 3. The image sensing elements SE are formed in respective pixel areas PI of the substrate 110. The image sensing elements SE detect the intensity (brightness) of radiation entering from the back side 110b of the substrate 110. In some embodiments, the image sensing elements SE can be used to detect visible light. Alternatively, the image sensing elements SE can be used to detect infrared (IR), ultraviolet (UV), X-rays, microwaves, other radiation types, or combinations thereof. Furthermore, in certain embodiments, the image sensing elements SE can be used to exhibit sensitivity to specific wavelengths of light, such as red (R), green (G), or blue (B) wavelengths. In such cases, the image sensing elements SE can be used to detect the intensity (brightness) of light having a specific wavelength. The image sensing elements SE can be arranged as pixels in a pixel array.

[0093] In some embodiments, the image sensing elements SE may include light detectors, such as photodiodes, that detect the intensity (brightness) of different wavelengths. For example, the image sensing elements SE may include photodiodes configured to detect red, green, and / or blue wavelengths. In such embodiments, the image sensing elements SE may include doped regions having n-type and / or p-type dopants, for example, formed in the substrate 110 by implanting one or more dopant species via the front side 110f of the substrate 110. For example, the image sensing elements SE (e.g., photodiodes) may be formed by selectively performing a first implantation process (e.g., based on a mask layer) to form first regions having a first dopant type (e.g., n-type), and subsequently performing a second implantation process to form second regions adjacent to the respective first regions and having a second dopant type different from the first dopant type (e.g., p-type), thereby forming PN junctions. These PN junctions may serve as the photodiodes SE in the substrate 110. In some embodiments, a floating diffusion well (not shown) may also be formed using either the first implantation process or the second implantation process.

[0094] One or more transistor gate structures 130 are formed on the front side 110 f of the substrate 110 within the pixel region PI. In various embodiments, the one or more transistor gate structures 130 are gates of a transfer transistor, a source follower transistor, a column select transistor, and / or a reset transistor of the BSI-CIS integrated wafer. In some embodiments, the one or more transistor gate structures 130 can be formed by depositing a gate dielectric film and a gate electrode film on the front side 110 f of the substrate 110. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric layer 132 and a gate electrode 134 on the gate dielectric layer 132. Sidewall spacers 136 can be formed along the outer sidewalls of the gate electrode 134. In some embodiments, the sidewall spacers 136 can be formed by depositing a spacer layer (e.g., a nitride, an oxide, etc.) onto the front side 110 f of the substrate 110 and anisotropically etching the spacer layer to form the sidewall spacers 136. The formation of the photodiode and transistor including the respective gate structures 130 may be referred to as a front-end-of-line (FEOL) process.

[0095] refer to Figure 4The conductive interconnect layer 150 is formed within the dielectric structure 140, which is formed on the front side 110f of the substrate 110. The formation of the dielectric structure 140 and the conductive interconnect layer 150 may be referred to as a back-end-of-line (BEOL) process, and the dielectric structure 140 and the conductive interconnect layer 150 may be collectively referred to as an interconnect structure. The dielectric structure 140 includes multiple stacked interlayer dielectric (ILD) layers, while the conductive interconnect layer 150 includes alternating layers of conductive lines and vias (e.g., laterally extending metal lines and vertically extending metal vias). In some embodiments, one or more of the conductive interconnect layers 150 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by depositing an ILD layer on the front side 110f of the substrate 110, etching the ILD layer to form vias and / or trenches, filling the vias and / or trenches with a conductive material (e.g., metal), and planarizing excess conductive material outside the vias and / or trenches using, for example, a chemical mechanical polishing (CMP) process. In some embodiments, the ILD layer can be deposited using a physical vapor deposition technique (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc.), and the conductive material can be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the conductive interconnect layer 150 can include, for example, tungsten, copper, or aluminum copper.

[0096] In some embodiments, after the BEOL process is completed, the support substrate 900 may be removed from the back side 110b of the substrate 110. Figure 5 As shown in FIG, after the dielectric structure 140 and the conductive interconnect layer 150 are formed on the front side 110f of the substrate 110, the first Figure 4The structure is flipped about a horizontal axis, and the support substrate 900 is then removed. Thereafter, a backside deep trench isolation (BDTI) structure 160 is formed in the substrate 110 through the backside 110b of the substrate 110. In some embodiments, the backside 110b of the substrate 110 can be patterned using suitable photolithography and etching techniques to form trenches 110T in the substrate 110, followed by filling the trenches 110T with one or more dielectric materials using suitable deposition techniques to form the isolation features 160. A chemical mechanical polishing (CMP) process is then performed to planarize the dielectric material and the backside 110b of the substrate 110, thereby forming the BDTI structure 160 in the substrate 110. The BDTI structure 160 may comprise, for example, an oxide (e.g., SiO2). In some embodiments, the BDTI structures 160 extending from the backside 110b are aligned with the STI structures 120 extending from the front side 110f. The BDTI structure 160 and the STI structure 120 may surround each of the pixel regions PI to provide electrical isolation between adjacent pixel regions PI, thereby reducing interference between the adjacent pixel regions PI.

[0097] refer to Figure 6A . An antireflective coating (ARC) 180 is selectively formed on the back side 110b of the substrate 100. The ARC 180 is a liner layer that prevents incident light rays from being reflected away from the back side 110b of the substrate. The ARC 180 may include a high-k material (e.g., a material having a k value (i.e., a dielectric constant) greater than 3.9), such as hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), or any other high-k material. The ARC 180 may be deposited using a sputtering process, a CVD process, an ALD process, or any other suitable deposition technique. The thickness of the ARC 180 may range, for example, from about 10 angstroms to about 500 angstroms.

[0098] After forming ARC 180, a buffer layer 200 may be deposited on ARC 180 to provide a substantially planar surface upon which layers 210-250, which will subsequently form the composite mesh structure, may be formed. In some embodiments, buffer layer 200 comprises a material that is substantially optically transparent to the wavelength of light to be received by image sensor element SE. In some embodiments, buffer layer 200 comprises silicon oxide (e.g., SiO2) or a low-k dielectric material. Low-k dielectric materials have a k value (dielectric constant) less than approximately 3.9. Some low-k dielectric materials have a k value less than approximately 3.5 and may have a k value less than approximately 2.5. In some embodiments, buffer layer 200 may be deposited on ARC 180 using, for example, CVD, ALD, PECVD, PEALD, PVD, or the like, or a combination thereof. The thickness of buffer layer 200 may range, for example, from approximately 500 angstroms to approximately 1500 angstroms. In some embodiments, buffer layer 200 has a thickness of approximately 1000 angstroms.

[0099] Barrier layer 210 is formed on buffer layer 200 using a suitable deposition technique. In some embodiments, one or more materials of barrier layer 210 are selected to reduce outdiffusion of metal from the subsequently formed metal grid into buffer layer 200. Furthermore, one or more materials of barrier layer 210 are also selected to provide enhanced adhesion between the subsequently formed metal grid and the underlying oxide material in buffer layer 200. In some embodiments, barrier layer 210 comprises a nitride material, such as titanium nitride (TiN), tantalum nitride (TaN), or the like, or a combination thereof, to achieve satisfactory metal diffusion reduction and / or satisfactory adhesion enhancement. In some embodiments, barrier layer 210 can be deposited on buffer layer 200 using, for example, CVD, ALD, PECVD, PEALD, PVD, or the like, or a combination thereof. The thickness of barrier layer 210 can range, for example, from about 200 angstroms to about 400 angstroms. In some embodiments, barrier layer 210 has a thickness of about 300 angstroms. An excessively thin barrier layer 210 may result in insufficient suppression of metal diffusion out of the metal grid and / or insufficient adhesion strength between the metal grid and the underlying oxide material. An excessively thick barrier layer 210 may result in the formation of a subsequently formed color filter (e.g., Figure 8 Unwanted apertures in the color filter 270 shown in FIG.

[0100] The metal grid layer 220 is formed on the barrier layer 210 using a suitable deposition technique. In some embodiments, the metal layer 108 includes tungsten, which has good gap-filling properties and good light reflectivity to isolate optical paths within subsequently formed color filters, but other suitable metals may be used. In some embodiments, the metal grid layer 220 may be deposited on the barrier layer 210 using, for example, CVD, ALD, PECVD, PEALD, PVD, the like, or a combination thereof. The thickness of the metal grid layer 220 may range, for example, from about 1000 angstroms to about 3000 angstroms. In some embodiments, the thickness of the metal grid layer 220 is about 2000 angstroms. An excessively thin metal grid layer 220 may result in insufficient optical isolation of subsequently formed color filters. An excessively thick metal grid layer 220 may result in insufficient optical isolation of subsequently formed color filters (e.g., Figure 8 Unwanted apertures in the color filter 270 shown in FIG.

[0101] The adhesion enhancing layer 230 is formed on the metal mesh layer 220 using a suitable deposition technique. In some embodiments, the adhesion enhancing layer 230 includes a nitride material that provides better adhesion strength to the underlying metal mesh layer 220 and the overlying dielectric mesh layer 240. In more detail, if the metal mesh layer 220 is formed of tungsten and the dielectric mesh layer 240 is formed of oxide, the nitride layer 230 can provide stronger adhesion strength to the tungsten mesh layer 220 and the oxide mesh layer 240 compared to the case where the oxide mesh layer 240 is directly deposited on the tungsten mesh layer 220. In this way, delamination defects in the composite mesh structure subsequently formed by the layers 200-250 can be reduced, thereby improving the robustness of the composite mesh structure and thus the optical isolation between the pixel areas PI. In some embodiments, the adhesion enhancing layer 230 includes, for example, silicon nitride (Si 1-x N, x is greater than 0.01), titanium nitride (TiN), but other suitable materials that provide stronger adhesion strength to tungsten can be used. The adhesion enhancing layer 230 and the barrier layer 210 include the same chemical element (e.g., nitrogen) because both the adhesion enhancing layer and the barrier layer are formed of nitride materials. It is worth noting that in some embodiments, the barrier layer 210 does not contain Si. 1-x N, because when Si 1-x When the N grid is interposed between the W grid and the back side 110 b of the substrate, the optical performance of the BSI-CIS may be degraded.

[0102] In some embodiments, the adhesion enhancing layer 230 can be deposited on the metal mesh layer 220 using, for example, CVD, ALD, PECVD, PEALD, PVD, the like, or a combination thereof. The thickness of the adhesion enhancing layer 230 can range, for example, from about 100 angstroms to about 2000 angstroms. In some embodiments, the thickness of the adhesion enhancing layer 230 is about 300 angstroms. An excessively thin adhesion enhancing layer 230 may result in insufficient adhesion strength to tungsten. An excessively thick adhesion enhancing layer 230 may result in a subsequently formed color filter (e.g., Figure 8 Unwanted apertures in the color filter 270 shown in FIG.

[0103] In some embodiments, the adhesion enhancement layer 230 is made of a single material such as Si 1-x In some other embodiments, the adhesion enhancement layer 230 is a single layer film formed of Si 1-x N layer and stacked on Si 1-x TiN layer on N, or TiN layer and Si stacked on TiN layer 1-x N layer formed multilayer film. In which the adhesion enhancement layer 230 is made of Si 1-x In some embodiments, N is formed, Si 1-x The N layer 230 is opaque to light having a wavelength ranging from about 10 nm to about 1000 nm, thereby improving optical isolation between adjacent pixel regions PI. 1-x The N layer 230 has a refractive index (RI) in a range from about 1.5 to about 2.5. In some embodiments where the adhesion enhancement layer 230 is formed of TiN, the TiN layer 230 has a sheet resistance (Rs) in a range from about 80Ω per unit square area to about 120Ω per unit square area.

[0104] A first dielectric grid layer 240 is formed on the adhesion-enhancing layer 230 using a suitable deposition technique. In some embodiments, the material of the first dielectric grid layer 240 is substantially optically transparent to the wavelength of light intended to be received by the image sensor element SE, but has a refractive index lower than that of the subsequently formed color filter. Due to its low refractive index, the dielectric grid formed by the first dielectric grid layer 240 can function as a light guide, directing light to the color filter and effectively increasing the size of the color filter. Furthermore, due to its low refractive index, the dielectric grid formed by the first dielectric grid layer 240 can be used to provide optical isolation between adjacent pixel areas PI. Light that strikes the boundary between the color filter and the dielectric grid can undergo total internal reflection within the color filter due to the difference in refractive index. In some embodiments, the first dielectric grid layer 240 comprises an oxide material, such as silicon oxide (SiO2) or hafnium oxide (HfO2), although other suitable materials with a refractive index lower than that of the color filter may also be used.

[0105] Because the oxide material of the dielectric mesh layer 240 is separated from the underlying tungsten mesh layer 220 by the adhesion enhancement layer 230, the composite mesh structure subsequently formed by the layers 200-250 can lack oxide / tungsten interfaces, which have weaker adhesion strengths than the nitride / tungsten interfaces E1 and nitride / oxide interfaces E2, thereby reducing delamination defects in the composite mesh structure. In some embodiments, the dielectric mesh layer 240 can be deposited on the adhesion enhancement layer 230 using, for example, CVD, ALD, PECVD, PEALD, PVD, the like, or a combination thereof. The thickness of the dielectric mesh layer 240 can range, for example, from about 2000 angstroms to about 4000 angstroms. In some embodiments, the thickness of the dielectric mesh layer 240 is about 3200 angstroms, which can be greater than the thicknesses of the adhesion enhancement layer 230, the metal mesh layer 220, the barrier layer 210, and the buffer layer 200. An excessively thin dielectric grid layer 240 may result in insufficient gridline-to-gridline spacing, making it impossible to form a color filter having sufficient thickness. An excessively thick dielectric grid layer 240 may result in unsatisfactory quantum efficiency because the oxide material of the dielectric grid layer 240 is optically transparent to the wavelength of light to be received by the image sensor element SE.

[0106] The second dielectric mesh layer 250 is formed on the first dielectric mesh layer 240 using a suitable deposition technique. The second dielectric mesh layer 250 can serve as a hard mask layer for patterning underlying layers to form a composite mesh structure. In some embodiments, the second dielectric mesh layer 250 comprises silicon oxynitride (SiON), although other suitable materials having different etch selectivities compared to the underlying first dielectric mesh layer 240 may also be used. In some embodiments, the second dielectric mesh layer 250 can be deposited on the first dielectric mesh layer 240 using, for example, CVD, ALD, PECVD, PEALD, PVD, the like, or a combination thereof. The thickness of the second dielectric mesh layer 250 can range, for example, from about 1000 angstroms to about 2000 angstroms. In some embodiments, the thickness of the second dielectric mesh layer 250 is about 1500 angstroms.

[0107] Figure 6A A cross-sectional view of the patterned mask layer PM1 formed on the second dielectric mesh layer 250 is also illustrated, and Figure 6B A top view of a patterned mask layer PM1 is shown. The patterned mask layer PM1 may include an organic material, such as a photoresist material, and may be formed using a spin-on coating process, followed by patterning the photoresist material using a suitable lithography technique to form a plurality of apertures O1 extending through the patterned mask layer PM1. For example, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. In more detail, a photomask (not shown) may be placed over the photoresist material, which may then be exposed to a radiation beam, which may be an ultraviolet (UV) or excimer laser, such as a krypton fluoride (KrF) excimer laser, or an argon fluoride (ArF) excimer laser. Exposure of the photoresist material may be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation may be performed to harden the exposed photoresist material, and a developer may be used to remove the exposed or unexposed portions of the photoresist material depending on whether a positive or negative resist is used. Figure 6A and Figure 6B The holes O1 illustrated in FIG are formed in the patterned photoresist layer PM1. In some embodiments, the holes O1 are arranged in rows and columns so that the patterned photoresist layer PM has the following structure: Figure 6B Grid pattern illustrated in top view.

[0108] After forming the patterned mask layer PM1, a patterning process is performed on the underlying layers 250-200 to transfer the pattern of the holes O1 in the patterned mask layer PM1 to the underlying layers 250-200, thereby resulting in openings O2 extending through the patterned second dielectric mesh layer 250', the patterned first dielectric mesh layer 240', the patterned adhesion enhancing layer 230', the patterned metal mesh layer 220', the patterned barrier layer 210', and the patterned buffer layer 200', as shown. Figure 7A and Figure 7B exemplified in, among which Figure 7A is a cross-sectional view of the obtained structure and Figure 7B A top view of the obtained structure.

[0109] Because the patterned layers 250'-200' are formed using the mask layer PM1 (eg Figure 6A and Figure 6B As shown in FIG ( ), the patterned layers 250 ′- 200 ′ are patterned as an etching mask, so the patterned layers 250 ′- 200 ′ inherit the grid pattern from the mask layer PM1. Figure 7B As illustrated in FIG, when viewed from above, the patterned second dielectric grid layer 250′ includes a second dielectric grid 252 having a grid pattern GP, ​​as shown in FIG. Figure 7B As illustrated in FIG, when viewed from above, the patterned first dielectric grid layer 240′ includes a first dielectric grid 242 having a grid pattern GP, ​​as shown in FIG. Figure 7B As illustrated in FIG, when viewed from above, the patterned adhesion enhancing layer 230′ includes an adhesion enhancing grid 232 having a grid pattern GP, ​​and as shown in FIG. Figure 7B As shown in FIG. 1 , when viewed from above, the patterned metal grid layer 220 ′, the patterned barrier layer 210 ′, and the patterned buffer layer 200 ′ respectively include a metal grid 222 having a grid pattern GP, ​​a barrier grid 212, and a buffer grid 202 g. Figure 7B As illustrated in FIG, when viewed from above, the stacked grids 202g, 212, 222, 232, 242, 252 may be referred to in combination as a composite grid structure 260 having a grid pattern GP.

[0110] like Figure 7BAs shown in , grid pattern GP includes grid lines GL that define a plurality of openings O2 (interchangeably referred to as gridline-to-gridline gaps) that correspond one-to-one to pixel areas PI. Thus, openings O2 can be arranged in a periodic pattern according to the pixel array corresponding to image sensor element SE. In some embodiments, grid lines GLx extend in a direction perpendicular to grid lines GLy. Because adhesion enhancing grid 232 (e.g., a nitride grid) includes a grid pattern GP identical to the grid patterns of metal grid 222 (e.g., a tungsten grid) and first dielectric grid 242 (e.g., an oxide grid), adhesion enhancing grid 232 can completely separate metal grid 222 from first dielectric grid 242. In this manner, composite mesh structure 260 lacks an oxide / tungsten interface that exhibits poor adhesion strength, thereby reducing delamination defects that may occur in composite mesh structure 260 during subsequent cleaning steps, as discussed in greater detail below.

[0111] In some embodiments, the patterning process used to form the composite mesh structure 260 involves one or more etching processes, such as one or more dry etching processes and / or one or more wet etching processes. For example, the patterning process may include a dry etching process (e.g., plasma etching) using a fluorine-containing etchant (e.g., CF4, SF6, or other fluorine-containing etchants). A dry etching process using a fluorine-containing etchant may result in the formation of undesirable byproducts (e.g., tungsten-containing polymer residues) on the sidewalls of the composite mesh structure 260.

[0112] An ultrasonic cleaning process is then performed to remove byproducts from the composite mesh structure 260. The ultrasonic cleaning process includes using a mechanical agitation generator for agitating the wafer including the composite mesh structure 260 in a cleaning solution, such as deionized water (DI water), other suitable solutions, etc., to enhance the cleaning process. The mechanical agitation generator can provide a stirring frequency in a range from about 1 MHz to about 100 MHz, although other suitable stirring frequencies may be used. Notably, if a composite mesh structure including a metal mesh and an oxide mesh contacting the metal mesh is subjected to an ultrasonic cleaning process, the oxide mesh may delaminate from the metal mesh due to insufficient adhesion strength at the oxide / tungsten interface. However, the ultrasonic cleaning process will not result in delamination defects in the composite mesh structure 260 or will result in fewer delamination defects in the composite mesh structure 260 because the composite mesh structure 260 lacks any oxide / tungsten interface.

[0113] In some embodiments, the etching process does not penetrate the buffer layer 200 ′, such that the buffer layer 200 ′ includes a bottom portion 202 b below the buffer grid 202 g and extending across the back side 110 b of the substrate. In some other embodiments, the etching process may penetrate the buffer layer 200 ′ to expose the ARC 180 .

[0114] In some embodiments, the grid lines GL of the barrier grid 212 formed of TiN have a width that increases with increasing distance from the back side 110b of the substrate. For example, the TiN grid lines have a bottom width W1 and a top width W2 that is greater than the bottom width W1. The bottom width W1 may be, for example, in a range from about 71 nm to about 89 nm (e.g., about 82 nm), and the top width W2 may be, for example, in a range from about 81 nm to about 99 nm (e.g., about 88 nm). The grid lines of the metal grid 222 formed of tungsten have a width that decreases with increasing distance from the back side 110b of the substrate. For example, the tungsten grid lines have a bottom width W3 in a range from about 81 nm to about 99 nm, comparable to the top width W2 of the TiN grid 212, and a top width W4 that is less than the bottom width W3. For example, the top width W4 may be in a range from about 54 nm to about 66 nm (e.g., about 63 nm).

[0115] In some embodiments, Si 1-x The grid lines GL of the adhesion enhancement grid 232 formed by the N have a width that increases as the distance from the back side 110b of the substrate increases. 1-x The N gridlines have a bottom width W5 in a range from about 54 nm to about 66 nm, comparable to the top width W4 of the tungsten gridlines, and a top width W6 greater than the bottom width W5. For example, top width W6 may be in a range from about 76.5 nm to about 93.5 nm (e.g., about 88 nm).

[0116] In some embodiments, the grid lines GL of the dielectric mesh 242 formed of oxide have a main segment 242m extending upward from the adhesion enhancing mesh 232 and a tapered top segment 242t extending upward from the main segment 242m. The main segment 242m has a width that remains substantially constant as the distance from the back side 110b of the substrate increases, and the tapered top segment 242t has a width that decreases as the distance from the back side 110b of the substrate increases. For example, the main segment 242m has a width comparable to that of Si 1-xThe top width W6 of the N grid lines may have a bottom width W7 in the range of 76.5 nm to about 93.5 nm, and a top width W8 comparable to bottom width W7. The top segment has a bottom width comparable to top width W8 of the main segment 242m, and a top width W9 less than its bottom width. For example, top width W9 may be in the range of about 63 nm to about 77 nm (e.g., about 71 nm). In some embodiments, the grid lines of the dielectric mesh 252 formed of SiON have a width that remains substantially constant as the distance from the back side 110b of the substrate increases. For example, the SiNO grid lines have a width in the range of about 63 nm to about 77 nm (e.g., about 71 nm).

[0117] Although the composite mesh structure 260 has the aforementioned exemplary nanoscale width of the grid lines GL, which can lead to an increased risk of delamination or cracking, the absence of an oxide / tungsten interface in the composite mesh structure 260 can reduce the risk of delamination or cracking. Thus, even if the width of the grid lines continues to scale down, for example, to a range from about 10 angstroms to about 500 angstroms, improved robustness of the composite mesh structure 260 can be achieved. In some embodiments, the adhesion enhancement mesh 232 has a thickness (measured perpendicular to the back side 110b of the substrate 100) that is less than the thickness of the underlying metal mesh 222 and the overlying dielectric mesh 242. In some embodiments, the grid lines GL are vertically aligned with a corresponding one of the DTI structures 160 and a corresponding one of the STI structures 120.

[0118] Once the composite mesh structure 260 is formed, a color filter 270 corresponding to the image sensor being manufactured is formed in the opening O2. The resulting structure is shown in FIG. Figure 8 In some embodiments, the color filter 270 fills the opening O2, wherein the upper surface thereof is approximately flush with the upper surface of the composite mesh structure 260. The color filter 270 has a specific color, such as red, green, and blue, and is configured to transmit the specific color and block other colors.

[0119] The process for forming color filter 270 may include forming a color filter layer for each of the color designations and patterning the color filter layer. The color filter layer may be formed so as to fill the open O2 and cover the composite mesh structure 260. Before patterning the color filter layer, the color filter layer may then be planarized and / or etched back to be approximately flush with the upper surface of the composite mesh structure 260. In some embodiments, planarizing and / or etching back the color filter layer may result in color filter 270 having a highest position that is lower than the highest position of the composite mesh structure 260.

[0120] Once the formation of the color filters 270 is complete, microlenses 280 are formed on the respective color filters 270. The process for forming the microlenses 280 may include forming one or more microlens layers on the color filters 270 and the composite mesh structure 260. The microlens layer(s) may be formed using one or more methods such as vapor deposition, ALD, spin coating, etc. After forming the microlens layer, the microlens layer is patterned to define the footprint of the corresponding microlenses. For example, a photoresist layer masking selected areas of the microlens layer may be formed on the microlens layer, used as a mask during etching of the microlens layer, and subsequently removed. If the microlens layer is patterned, one or more reflow and / or heating processes are performed on the patterned microlens layer to round the corners of the patterned microlens layer, thereby resulting in microlenses having rounded surfaces.

[0121] Figure 9 A method M for forming a BSI-CIS structure according to some embodiments is illustrated. Although method M is illustrated and / or described as a series of actions or events, it will be understood that the method is not limited to the illustrated order or actions. Thus, in some embodiments, the actions may be performed in a different order than illustrated and / or may be performed in parallel. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events, which may be performed at separate times or in parallel with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other actions or events not illustrated may be included.

[0122] At block S11 , image sensing elements are formed in separate pixel regions in a substrate. Figures 1 to 3 Cross-sectional views illustrating some embodiments corresponding to the actions in block S11.

[0123] At block S12 , BEOL interconnect structures are formed on the front side of the substrate. Figure 4 Cross-sectional views illustrating some embodiments corresponding to the actions in block S12.

[0124] At block S13 , a DTI structure is formed extending from the back side of the substrate into the substrate. Figure 5 Cross-sectional views illustrating some embodiments corresponding to the actions in block S13.

[0125] At block S14 , a tungsten mesh layer, an adhesion enhancement layer, and an oxide mesh layer are sequentially formed on the back side of the substrate. Figure 6A Cross-sectional views illustrating some embodiments corresponding to the actions in block S14.

[0126] At block S15 , the tungsten mesh layer, the adhesion enhancement layer, and the oxide mesh layer are patterned to form a composite mesh structure. Figure 7A and Figure 7BThe cross-sectional views and top views of some embodiments corresponding to the action in block S15 are respectively illustrated.

[0127] At block S16, color filters are formed in the respective gridline-to-gridline gaps. At block S17, microlenses are formed on the respective color filters. Figure 8 Cross-sectional views illustrating some embodiments corresponding to the actions in blocks S16 and S17.

[0128] Figure 10 : is a cross-sectional view of a BSI-CIS structure according to some embodiments of the present disclosure. The BSI-CIS structure includes a pixel array area AA, a peripheral area PA, a bonding pad area BA (also known as an E-pad area), and a scribe line area SA. The pixel array area AA contains an array of pixel areas PI. Each pixel area PI includes an image sensing element SE that can sense or detect radiation having a specific wavelength, which can correspond to different colors of light. The peripheral area PA may include other elements PD that remain optically dark. For example, the element PD may be a digital element, such as an application-specific integrated circuit (ASIC) element or a system-on-chip (SOC) element. The other elements PD may be reference pixels used to establish a baseline for light intensity for the BSI-CIS structure. The bonding pad area BA may include one or more conductive bonding pads or E-pads CP, through which electrical connections between the BSI-CIS structure and external elements can be established. For example, bonding wires BW are attached to conductive bonding pads CP via bonding balls BB. The scribe line area SA may be a region that separates one semiconductor die (including the bonding pad area BA, the peripheral area PA, and the pixel array area AA) from an adjacent semiconductor die (not shown). The scribe line area SA is cut later in the manufacturing process to separate adjacent dies before the dies are packaged and sold as integrated circuit wafers. The scribe line area SA is cut in a manner that does not damage the semiconductor elements in each die.

[0129] Adding an adhesion-enhancing mesh between the lower tungsten mesh and the upper oxide mesh will result in no or negligible impact on the optical performance of the BSI-CIS integrated chip. For example, the adhesion-enhancing mesh can result in less than 1% change in quantum efficiency (QE), interference performance, angular response, and / or a 10dB signal-to-noise ratio (SNR10). The BSI-CIS devices discussed above are some examples used to describe the improved composite mesh structure. However, the improved composite mesh structure described above can also be integrated into other image sensors, such as FSI image sensors. In such cases, the improved composite structure will be disposed on the front side 110f of the substrate 110, with the BEOL interconnect structure interposed between the composite structure and the substrate 110.

[0130] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, that not all advantages are necessarily disclosed herein, and that not all specific advantages are required for all embodiments. One advantage is that delamination defects in a composite mesh structure can be reduced by adding an adhesion-enhancing mesh between the tungsten mesh and the oxide mesh. Another advantage is that the composite mesh structure can remain robust after an ultrasonic cleaning process because the composite mesh structure lacks any oxide / tungsten interface that is susceptible to delamination during the ultrasonic cleaning process.

[0131] In some embodiments, an image sensor structure includes a semiconductor device, a plurality of image sensor devices formed in a semiconductor substrate, an interconnect structure formed on the semiconductor substrate, and a composite grid structure on the semiconductor substrate. The composite grid structure includes a tungsten grid, an oxide grid above the tungsten grid, and an adhesion-enhancing grid separating the tungsten grid from the oxide grid. In some embodiments, the adhesion-enhancing grid is formed of a nitride material. In some embodiments, the adhesion-enhancing grid comprises a plurality of gridlines. Each of the gridlines has a width that increases with increasing distance from the semiconductor substrate. In some embodiments, the tungsten grid comprises a plurality of gridlines, each of which has a width that decreases with increasing distance from the semiconductor substrate. In some embodiments, the oxide grid comprises a plurality of gridlines, each of which has a tapered top segment. In some embodiments, the adhesion-enhancing grid comprises a plurality of gridlines, each of which has a width within a range from approximately 10 angstroms to approximately 500 angstroms. In some embodiments, the adhesion-enhancing grid has a refractive index within a range from approximately 1.5 to approximately 2.5. In some embodiments, the adhesion-enhancing grid has a sheet resistance within a range from approximately 80 Ω per unit square area to approximately 120 Ω per unit square area. In some embodiments, the composite mesh structure further includes a barrier mesh between the tungsten mesh and the semiconductor substrate. In some embodiments, the barrier mesh and the adhesion enhancement mesh have the same chemical element. In some embodiments, the composite mesh structure further includes an oxynitride mesh on the oxide mesh.

[0132] In some embodiments, the image sensor structure includes a semiconductor substrate, a plurality of photodiodes in the semiconductor substrate, an internal connection structure on the semiconductor substrate, and a composite grid structure on the semiconductor substrate. The composite grid structure includes an oxide grid and a metal grid between the oxide grid and the semiconductor substrate, and the composite grid structure lacks an oxide / metal interface. In some embodiments, the composite grid structure further includes a nitride grid, the nitride grid forming a nitride / metal interface with a top surface of the metal grid. In some embodiments, the nitride grid also forms a nitride / oxide interface with a bottom surface of the oxide grid. In some embodiments, the nitride grid has a thickness less than a thickness of the metal grid. In some embodiments, the nitride grid has a thickness less than a thickness of the oxide grid. In some embodiments, the image sensor structure further includes a plurality of color filters extending through the nitride grid. In some embodiments, the image sensor structure further includes a plurality of microlenses, respectively on these color filters.

[0133] In some embodiments, a method includes forming a photodiode in a substrate; forming an interconnect structure on the substrate; depositing a metal grid layer on the substrate, depositing an adhesion enhancing layer on the metal grid layer, and depositing an oxide grid layer on the adhesion enhancing layer; and etching the metal grid layer, the adhesion enhancing layer, and the oxide grid layer to form metal grid lines, adhesion enhancing grid lines extending above the metal grid lines, and oxide grid lines extending above the adhesion enhancing grid lines. In some embodiments, the method further includes forming a buffer layer on the substrate before depositing the metal grid layer, and forming a barrier layer on the buffer layer; and etching the barrier layer and the buffer layer to form a plurality of barrier grid lines extending below the metal grid lines, and buffer grid lines extending below the barrier grid lines.

[0134] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor structure, characterized in that: Include: a semiconductor substrate; A plurality of image sensing elements are formed in the semiconductor substrate; an interconnect structure formed on the semiconductor substrate; and A composite grid structure is provided on the semiconductor substrate, wherein the composite grid structure comprises: a tungsten grid comprising a plurality of tungsten grid lines, each of the plurality of tungsten grid lines having a first thickness and a width that decreases with increasing distance from the semiconductor substrate; an oxide grid formed on the tungsten grid, the oxide grid comprising a plurality of oxide grid lines, each of the oxide grid lines having a second thickness and comprising a main segment and a tapered top segment, wherein the second thickness of the oxide grid is greater than the first thickness of the tungsten grid, and the material of the oxide grid comprises silicon oxide (SiO2) or hafnium oxide (HfO2); an adhesion enhancing grid, interposed between the tungsten grid and the oxide grid, formed of a nitride material and comprising a plurality of adhesion enhancing grid lines, wherein each of the plurality of adhesion enhancing grid lines has a third thickness and a width that increases with increasing distance from the semiconductor substrate, wherein the third thickness of the adhesion enhancing grid is less than the first thickness of the tungsten grid, and the adhesion enhancing grid forms a metal / nitride interface with the tungsten grid and a nitride / oxide interface with the oxide grid; and A barrier grid is disposed between the tungsten grid and the semiconductor substrate and below the adhesion enhancement grid, wherein the barrier grid is formed of a titanium-containing material that is different from the nitride material of the adhesion enhancement grid.

2. The image sensor structure according to claim 1, wherein: The first thickness of the tungsten mesh is between 100 nm and 300 nm, the second thickness of the oxide mesh is between 200 nm and 400 nm, and the third thickness of the adhesion enhancement mesh is between 10 nm and 30 nm.

3. The image sensor structure according to claim 1, wherein: The nitride material of the adhesion enhancement grid includes silicon nitride.

4. The image sensor structure according to claim 1, wherein: Also includes: A plurality of color filters extend through the adhesion enhancing grid.

5. The image sensor structure according to claim 1, wherein: The main segment of the oxide grid has a width that remains constant as a distance from the semiconductor substrate increases, and the tapered top segment of the oxide grid has a width that decreases as a distance from the semiconductor substrate increases.

6. The image sensor structure according to claim 1, wherein: The adhesion enhancing grid lines of the adhesion enhancing grid each have a width in a range from 10 angstroms to 500 angstroms.

7. The image sensor structure according to claim 1, wherein: The adhesion enhancing grid has a refractive index in a range from 1.5 to 2.

5.

8. The image sensor structure according to claim 1, wherein: The adhesion enhancement grid has a sheet resistance in a range from 80Ω per unit square area to 120Ω per unit square area.

9. The image sensor structure according to claim 1, wherein: The titanium-containing material of the barrier grid includes titanium nitride or tantalum nitride.

10. The image sensor structure according to claim 1, wherein: The barrier mesh and the adhesion enhancing mesh have a same chemical element.

11. The image sensor structure according to claim 1, wherein: The composite grid structure further includes an oxynitride grid on the oxide grid.

12. An image sensor structure, characterized in that: Include: a semiconductor substrate; a plurality of photodiodes in the semiconductor substrate; an interconnect structure on the semiconductor substrate; and A composite mesh structure on the semiconductor substrate, wherein the composite mesh structure lacks an oxide / metal interface and comprises: a tungsten grid comprising a plurality of tungsten grid lines, each of the plurality of tungsten grid lines having a first thickness and a width that decreases with increasing distance from the semiconductor substrate; an oxide grid formed on the tungsten grid, the oxide grid comprising a plurality of oxide grid lines, each of the oxide grid lines having a second thickness and comprising a main segment and a tapered top segment, wherein the second thickness of the oxide grid is greater than the first thickness of the tungsten grid, and the material of the oxide grid comprises silicon oxide (SiO2) or hafnium oxide (HfO2); an adhesion enhancing grid, interposed between the tungsten grid and the oxide grid, formed of a nitride material and comprising a plurality of adhesion enhancing grid lines, wherein each of the plurality of adhesion enhancing grid lines has a third thickness and a width that increases with increasing distance from the semiconductor substrate, wherein the third thickness of the adhesion enhancing grid is less than the first thickness of the tungsten grid, and the adhesion enhancing grid forms a metal / nitride interface with the tungsten grid and a nitride / oxide interface with the oxide grid; and A barrier grid is disposed between the tungsten grid and the semiconductor substrate and below the adhesion enhancement grid, wherein the barrier grid is formed of a titanium-containing material that is different from the nitride material of the adhesion enhancement grid.

13. The image sensor structure according to claim 12, wherein: The titanium-containing material of the barrier grid includes titanium nitride or tantalum nitride.

14. The image sensor structure according to claim 12, wherein: Also includes: A backside deep trench isolation structure is provided in the semiconductor substrate, wherein the composite mesh structure is disposed above the backside deep trench isolation structure.

15. The image sensor structure according to claim 12, wherein: The adhesion enhancing grid lines of the adhesion enhancing grid each have a width in a range from 10 angstroms to 500 angstroms.

16. The image sensor structure according to claim 12, wherein: The adhesion enhancing grid has a refractive index in a range from 1.5 to 2.

5.

17. The image sensor structure according to claim 12, wherein: Also includes: A plurality of color filters extend through the adhesion enhancing grid.

18. The image sensor structure according to claim 17, wherein: Also includes: A plurality of micro lenses are respectively disposed on the plurality of color filters.

19. A method for manufacturing an image sensor structure, characterized in that: The following steps are involved: forming a plurality of photodiodes in a substrate; forming an internal connection structure on the substrate; depositing a barrier grid layer on the substrate, a tungsten grid layer on the barrier grid layer, an adhesion enhancing layer on the tungsten grid layer, and an oxide grid layer on the adhesion enhancing layer, wherein the barrier grid layer is formed of a titanium-containing material, the adhesion enhancing layer is formed of a nitride material, the titanium-containing material of the barrier grid layer is different from the nitride material of the adhesion enhancing layer, and the material of the oxide grid layer includes silicon oxide (SiO2) or hafnium oxide (HfO2); and etching the tungsten mesh layer, the adhesion enhancement layer, and the oxide mesh layer to form a barrier mesh, a tungsten mesh disposed above the barrier mesh, an adhesion enhancement mesh disposed above the tungsten mesh, and an oxide mesh disposed above the adhesion enhancement mesh, wherein the barrier grid comprises a plurality of barrier grid lines, the tungsten grid comprises a plurality of tungsten grid lines respectively extending above the plurality of barrier grid lines, the adhesion enhancement grid comprises a plurality of adhesion enhancement grid lines respectively extending above the plurality of tungsten grid lines, and the oxide grid comprises a plurality of oxide grid lines respectively extending above the plurality of adhesion enhancement grid lines, Each of the plurality of tungsten grid lines has a first thickness and a width that decreases as a distance from the substrate increases, wherein each of the plurality of oxide gridlines has a second thickness and includes a main segment and a tapered top segment, wherein the second thickness of the oxide grid is greater than the first thickness of the tungsten grid, and Each of the plurality of adhesion enhancing grid lines has a third thickness and a width that increases with increasing distance from the substrate, wherein the third thickness of the adhesion enhancing grid is less than the first thickness of the tungsten grid, and the adhesion enhancing grid forms a metal / nitride interface with the tungsten grid and a nitride / oxide interface with the oxide grid.

20. The method according to claim 19, characterized in that It also includes the following steps: Before depositing the barrier grid layer, forming a buffer layer on the substrate; and The buffer layer is etched to form a plurality of buffer grid lines respectively extending under the plurality of barrier grid lines.

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