RF amplifier with series coupled output bondwire array and parallel capacitor bondwire array

Abstract

This disclosure relates to an RF amplifier having an array of series-coupled output bond lines and an array of parallel capacitor bond lines. Various embodiments relate to packaged radio frequency (RF) amplifier devices implementing separate bond lines, wherein the direct ground connection of the output capacitor is replaced by a set of bond lines connected to ground in the opposite direction to the wires connecting the transistor output to the output pad. This is done to reduce the influence of mutual inductance among the various bond lines associated with the output of the RF amplifier device.

Description

[0001] The various embodiments disclosed herein generally relate to amplifier circuits that include bonding wires as inductors. Background Technology

[0002] Packaged radio frequency (RF) transistors can be coupled to other passive components using bonded wire arrays. These bonded wire arrays act as inductors, and some are designed as part of, for example, passive input and output circuitry associated with the packaged RF transistor. These bonded wire arrays interact with each other due to mutual inductance, which affects the characteristics of the circuits using the bonded wire arrays. Summary of the Invention

[0003] According to a first aspect of the present invention, a packaged radio frequency (RF) amplifier device is provided, comprising:

[0004] device substrate;

[0005] An input pin, which is coupled to the device substrate;

[0006] An output pin, which is coupled to the device substrate;

[0007] A transistor die coupled to the device substrate, wherein the transistor die includes a transistor, a transistor input coupled to the input pin, and a transistor output coupled to the output pin;

[0008] An output impedance matching circuit is coupled to the output pin and the transistor output terminal, wherein the output impedance matching circuit includes...

[0009] The first set of bonding wires is coupled between the output pin and the transistor output.

[0010] The output capacitor includes a first terminal and a second terminal.

[0011] The second set of bonding wires is coupled between the transistor output and the first terminal of the output capacitor, and

[0012] A third set of bonding wires is coupled between the second terminal of the output capacitor and the ground reference node, wherein the third set of bonding wires is substantially parallel to the first and second sets of bonding wires.

[0013] According to one or more embodiments, the output capacitor is an integrated passive device.

[0014] According to one or more embodiments, the first and second terminals of the output capacitor are on opposite sides of the integrated passive device.

[0015] According to one or more embodiments, the first and second terminals of the output capacitor are on the same side of the integrated passive device.

[0016] According to one or more embodiments, the bonding wires in the third set of bonding wires shield the bonding wires in the first set of bonding wires from the bonding wires in the second set of bonding wires.

[0017] According to one or more embodiments, the third set of bonding wires shields the first set of bonding wires from the second set of bonding wires.

[0018] According to one or more embodiments, the grounding reference node is a flange.

[0019] According to one or more embodiments, the ground reference node is a ground pad on the transistor die.

[0020] According to one or more embodiments, the first bonding wire, the second set of bonding wires, and the third set of bonding wires have profiles configured to increase electromagnetic coupling between the first and third sets of bonding wires, decrease electromagnetic coupling between the first and second sets of bonding wires, and decrease electromagnetic coupling between the second and third sets of bonding wires.

[0021] According to one or more embodiments, the packaged RF amplifier device further includes an input impedance matching circuit, which includes...

[0022] First connection node,

[0023] An input parallel capacitor has a first terminal connected to ground and a second terminal connected to the first connection node.

[0024] The fourth set of bonding wires is coupled between the input pin and the first connection node.

[0025] The fifth set of bonding wires is coupled between the first connection node and the transistor input terminal.

[0026] According to a second aspect of the present invention, a method for manufacturing an RF amplifier device is provided, the method comprising the following steps:

[0027] Couple the input pins to the device substrate;

[0028] Couple the output pin to the device substrate;

[0029] A transistor die is coupled to the device substrate between the input and output pins, wherein the transistor die includes a transistor and a transistor input terminal;

[0030] An output impedance matching circuit is coupled between the output pin and the transistor output terminal, wherein the output impedance matching circuit includes...

[0031] The first set of bonding wires is coupled between the output pin and the transistor output.

[0032] The output capacitor includes a first terminal and a second terminal.

[0033] The second set of bonding wires is coupled between the transistor output and the first terminal of the output capacitor, and

[0034] A third set of bonding wires is coupled between the second terminal of the output capacitor and the ground reference node, wherein the third set of bonding wires is substantially parallel to the first and second sets of bonding wires.

[0035] According to one or more embodiments, coupling the output impedance matching circuit between the output pin and the transistor output includes coupling a first set of bonding wires between the output pin and the transistor output, coupling the output capacitor to the device substrate, wherein the output capacitor includes a first end and a second end, coupling a second set of bonding wires between the transistor output and the first end of the output capacitor, and coupling a third set of bonding wires between the second end of the output capacitor and the ground reference node.

[0036] According to one or more embodiments, the output capacitor is an integrated passive device.

[0037] According to one or more embodiments, the first and second terminals of the output capacitor are on opposite sides of the integrated passive device.

[0038] According to one or more embodiments, the first and second terminals of the output capacitor are on the same side of the integrated passive device.

[0039] According to one or more embodiments, the bonding wires in the third set of bonding wires are located between the bonding wires in the first set of bonding wires and the bonding wires in the second set of bonding wires.

[0040] According to one or more embodiments, the method further includes coupling an input impedance matching circuit between the input pin and the transistor input terminal, wherein coupling the input impedance matching circuit includes coupling an input parallel capacitor having a first end and a second end to the device substrate, coupling the first end to ground and coupling the second end to a first connection node, coupling a fourth set of bonding wires between the input pin and the first connection node, and coupling a fifth set of bonding wires between the first connection node and the transistor input terminal.

[0041] According to a third aspect of the present invention, a radio frequency (RF) amplifier is provided, comprising:

[0042] A transistor die, which has a transistor and a transistor output terminal;

[0043] An output impedance matching circuit is coupled to the output pin and the transistor output terminal, wherein the output impedance matching circuit includes...

[0044] The first set of bonding wires is coupled between the output pin and the transistor output.

[0045] The output capacitor includes a first terminal and a second terminal.

[0046] The second set of bonding wires is coupled between the transistor output and the first terminal of the output capacitor, and

[0047] A third set of bonding wires is coupled between the second terminal of the output capacitor and the ground reference node, wherein the third set of bonding wires is substantially parallel to the first and second sets of bonding wires.

[0048] According to one or more embodiments, the output capacitor is an integrated passive device.

[0049] According to one or more embodiments, the bonding wires in the third set of bonding wires are located between the bonding wires in the first set of bonding wires and the bonding wires in the second set of bonding wires. Attached Figure Description

[0050] A more complete understanding of the subject matter can be obtained by referring to the detailed embodiments and claims when the following figures are considered in conjunction with them, wherein similar reference numerals in the figures refer to similar elements.

[0051] Figure 1 This is a schematic diagram of an RF power amplifier circuit;

[0052] Figure 2 It is a manifestation Figure 1 A top view of the layout of an RF amplifier device, an example of a circuit;

[0053] Figure 3 include Figure 2 A cross-sectional side view along line 3-3;

[0054] Figure 4 This is a schematic diagram of an embodiment of an RF power amplifier circuit using decoupled bonding wires;

[0055] Figure 5 It is a manifestation Figure 4 A top view of an embodiment of the layout of an RF amplifier device, representing an example of the circuit.

[0056] Figure 6 Including according to the example embodiments Figure 5 A cross-sectional side view along line 6-6;

[0057] Figure 7 It is a manifestation Figure 4 A top view of another embodiment of the layout of an RF amplifier device, an example of the circuit;

[0058] Figure 8 It shows that it can be used Figure 5 and 7 A top view of an embodiment of the output parallel capacitor used in the device;

[0059] Figure 9 It shows that it can be used Figure 5 and 7 A top view of an embodiment of the output parallel capacitor used in the device;

[0060] Figure 10 It shows the use Figure 8 The bond wires of the parallel capacitors are connected Figure 5 A simplified side view of the device;

[0061] Figure 11 It shows the use Figure 9 The bond wires of the parallel capacitors are connected Figure 5 A simplified side view of the device;

[0062] Figure 12 It shows the use Figure 8 The bond wires of the parallel capacitors are connected Figure 7 A simplified side view of the device;

[0063] Figure 13 It shows the use Figure 9 The bond wires of the parallel capacitors are connected Figure 7 A simplified side view of the device; and

[0064] Figure 14 It is used to manufacture packaged RF power amplifier devices (e.g., Figure 5 or Figure 7 The flowchart describes a method for constructing an RF power amplifier device, which includes embodiments of input and output impedance matching circuits according to various example embodiments. Detailed Implementation

[0065] The description and accompanying drawings illustrate the principles of the invention. It will thus be understood that those skilled in the art will be able to design various arrangements, which, although not explicitly described or shown herein, embody the principles of the invention and are included within its scope. Furthermore, all examples cited herein are primarily intended for illustrative purposes to aid the reader in understanding the principles of the invention and to deepen the understanding of the concepts provided by the inventors, and all examples should be considered as not being limited to such specific cited examples and conditions. Additionally, unless otherwise specified (e.g., “or additionally” or “or in alternatives”), the term “or” as used herein refers to a non-exclusive or (i.e., and / or). Moreover, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[0066] When present in power amplifier circuits using packaged RF transistors, mutual inductance can negatively impact the overall performance and operating characteristics of the power amplifier circuit. This paper discloses an embodiment of a power amplifier circuit architecture using a "split" bond wire array, which reduces the potential negative impact of bond wire mutual inductance at the output of the power amplifier circuit.

[0067] Figure 1 This is a schematic diagram of an RF power amplifier circuit 100. Circuit 100 includes an input 102 (e.g., a first conductive package pin), an input impedance matching circuit 110, a transistor 140, an output impedance matching circuit 150, and an output pin 104 (e.g., a second conductive package pin). Each of the input 102 and the output 104 may be more generally referred to as an "RF input / output (I / O)".

[0068] Input 102 and output 104 may each include a conductor configured to enable electrical coupling of circuit 100 to an external circuit system (not shown). More specifically, input 102 and output 104 are physically positioned between the outside and inside of a device package. Input impedance matching circuit 110 is electrically coupled between input 102 and a first terminal 142 (e.g., the gate terminal) of transistor 140. Similarly, output impedance matching circuit 150 is electrically coupled between a second terminal 144 (e.g., the drain terminal) of transistor 140 and output 104. A third terminal 145 (e.g., the source terminal) of transistor 140 is coupled to a ground reference node.

[0069] Transistor 140 is the primary active component of circuit 100. Transistor 140 includes a control terminal 142 and two conductive terminals 144 and 145, which are spatially and electrically separated by a variable conductivity channel. For example, transistor 140 may be a field-effect transistor (FET) comprising a gate terminal (control terminal 142), a drain terminal (first conductive terminal 144), and a source terminal (second conductive terminal 145). Using the nomenclature commonly used for FETs, the gate terminal 142 of transistor 140 is coupled to input impedance matching circuit 110, the drain terminal 144 of transistor 140 is coupled to output impedance matching circuit 150, and the source terminal 145 of transistor 140 is coupled to ground (or another reference voltage). By changing the control signal supplied to the gate terminal of transistor 140, the current between the conductive terminals 144 and 145 of transistor 140 can be modulated.

[0070] As described above, the input impedance matching circuit 110 is electrically coupled between the input 102 and the first terminal 142 (e.g., the gate terminal) of the transistor 140. The input impedance matching circuit 110 is configured to transform (e.g., raise) the gate impedance of the transistor 140 at node 102 to a higher (e.g., intermediate or higher) impedance level (e.g., in the range from about 2 ohms to about 10 ohms or higher).

[0071] The input impedance matching circuit 110 includes a first series inductor element 112 (e.g., a first set of bond wires) coupled between the input 102 and the first node 115 (also referred to as the "connection node"). In addition to establishing an electrical connection between the input 102 and the node 115, the first inductor element 112 can also add reactance to the final transformed impedance provided by the input impedance matching circuit 110.

[0072] A series inductor 116 (e.g., a second set of bond wires) is coupled between input 102 (or more specifically, inductor 112 or connection node 115) and control terminal 142 of transistor 140. Therefore, inductors 112 and 116 are connected in series between input 102 and control terminal 142 of transistor 140. A first terminal of parallel capacitor 114 is coupled to connection node 115, and a second terminal of parallel capacitor 114 is coupled to ground (or another reference voltage).

[0073] On the output side of circuit 100, an output impedance matching circuit 150 is coupled between the first conductive terminal 144 (e.g., the drain terminal) of transistor 140 and output 104. The output impedance matching circuit 150 is configured to match the output impedance of circuit 100 to the input impedance of external circuitry or components (not shown) that can be coupled to output 104. The output impedance matching circuit 150 can have any of a plurality of different circuit configurations, and Figure 1Only one example is shown. More specifically, in Figure 1 In the non-limiting example shown, the output impedance matching circuit 150 includes two inductor elements 152 and 154 and a parallel capacitor 156. The first inductor element 152 (e.g., a third set of bond wires) is coupled between a first conductive terminal 144 (e.g., the drain terminal) of transistor 140 and the output 104. The second inductor element 154 (e.g., a fourth set of bond wires) is coupled between the first conductive terminal 144 of transistor 140 and a node 159 corresponding to another RF low impedance point. The second terminal of the parallel capacitor 156 is coupled to ground (or to another reference voltage).

[0074] For example, Figure 2 It is a manifestation Figure 1 The diagram shows a top view of the layout of an example of the circuit 100 for an RF amplifier device 200, which can be used to provide portions of the amplifier and matching network in a Doherty amplifier. Additionally, two examples of the RF amplifier device 200 can be incorporated into a package to provide two amplifiers for use in a Doherty amplifier. Figure 3 include Figure 2 A cross-sectional side view along line 3-3.

[0075] Device 200 includes a flange 201 (or "device substrate"), which comprises a rigid conductive substrate with sufficient thickness to provide structural support for various electronic components and elements of device 200. Additionally, flange 201 can serve as a heat sink for transistor die 240 and other devices mounted on flange 201. Flange 201 has a top surface and a bottom surface (in... Figure 2 Only the central part of the top surface is visible, and the perimeter of the device 200 is basically rectangular.

[0076] Flange 201 is formed of a conductive material and can be used to provide a ground reference node for device 200. For example, various components and elements may have ends electrically coupled to flange 201, and flange 201 may be electrically coupled to system ground when device 200 is integrated into a larger power system. At least the top surface of flange 201 is formed of a layer of conductive material, and all of flange 201 may be formed of a bulk conductive material.

[0077] Isolation structure ( Figure 3 The isolation structure 203 is attached to the top surface of the flange 201. The isolation structure 203, formed of a rigid electrically insulating material, provides electrical isolation between the conductive components of the device (e.g., between pins 202, 204 and flange 201). The isolation structure 203 has a frame shape, comprising a substantially closed quadrilateral structure with a central opening. The isolation structure 203 may have a substantially rectangular shape, or the isolation may have another shape (e.g., a ring, an ellipse, etc.).

[0078] A portion of the top surface of the flange 201 exposed through the opening in the isolation structure 203 is referred to herein as the “active region” of the device 200. The transistor die 240, along with integrated passive device (IPD) assemblies 213 and 255, is placed within the active device region of the device 200, as will be described in more detail later. For example, the transistor die 240 and IPD assemblies 213 and 255 may be coupled to the top surface of the flange 201 using conductive epoxy, solder, solder bumps, sintering, and / or eutectic bonding.

[0079] Device 200 accommodates display circuit 100 ( Figure 1 The amplification path of the physical implementation scheme. When incorporated into a Doherty amplifier, the amplification path can correspond to either the main amplifier path or the peaking amplifier path.

[0080] Device 200 includes input pin 202 (e.g., Figure 1 Input pin 102), output pin 204 (e.g., Figure 1 Output 204), transistor die 240 (e.g., Figure 1 Transistor 140), input impedance matching circuit 210 (e.g., Figure 1 The input impedance matching circuit 110) and the output impedance matching circuit 250 (e.g., Figure 1 The output impedance matching circuit 250. Some components of the input impedance matching circuit 210 can be implemented in the IPD component 213, and some components of the output impedance matching circuit 250 can be implemented in the IPD component 255.

[0081] Input pin 202 and output pin 204 are mounted on the top surface of isolation structure 203 on opposite sides of the central opening, and thus input pin 202 and output pin 204 are raised above the top surface of flange 201 and electrically isolated from flange 201. Generally, input pin 202 and output pin 204 are oriented to allow bonding wires to be attached between input pin 202 and output pin 204 and components and elements within the central opening of isolation structure 203.

[0082] Transistor die 240 includes an integrated power FET, wherein the FET has a control terminal (e.g., a gate terminal) and two conductive terminals (e.g., a drain terminal and a source terminal). The control terminal of the FET within transistor die 240 is coupled to input pin 202 via input impedance matching circuitry 210. More specifically, power transistor die 240 includes a transistor input terminal 242 (e.g., a conductive bonding pad) electrically connected within power transistor die 240 to the control terminal (e.g., a gate terminal) of a single-stage or final-stage FET integrated within die 240. Additionally, one conductive terminal (e.g., a drain terminal) of the FET within transistor die 240 is coupled to output pin 204 via output impedance matching circuitry 250. The other conductive terminals (e.g., source terminals) of the FET within transistor die 240 are electrically coupled to flange 201 (e.g., coupled to ground) via die 240.

[0083] IPD component 213 may also include a base semiconductor substrate 282 (e.g., a silicon substrate, a silicon carbide substrate, a GaN substrate, or another type of semiconductor substrate, which may be referred to herein as an "IPD substrate") and a construction structure of alternating dielectrics 217 and patterned conductive layers. As will be discussed in more detail below, the parallel capacitor 214 of the input impedance matching circuit 210 (e.g., ...) Figure 1 The capacitor 114 is integrally formed within the IPD assembly 213 with a first end and a second end. The first end is electrically connected to a conductive bonding pad 215 on the top surface of the IPD assembly 213, and the second end is electrically connected to a conductive flange 201 (e.g., electrically connected to ground) via a through-substrate via 226 reaching a conductive layer 286 on the bottom surface of the IPD assembly 213.

[0084] For example, the input impedance matching circuit 210 may include two inductor elements 212 and 216 (e.g., Figure 1 Inductors 112, 116) and parallel capacitor 213 (e.g., Figure 1 Parallel capacitor 114). First inductor element 212 (e.g., Figure 1 The inductor element 112 can be implemented as a conductive bonding pad 215 coupled to the top surface of the input pin 202 and the IPD component 213 (e.g., corresponding to...). Figure 1 The first set of bond lines between the connection node 115). The second inductor element 216 (e.g., Figure 1 The inductor element 116 can be implemented as coupled to the bonding pad 215 (corresponding to Figure 1 The second set of bonding wires between the connection node 115 and the input terminal 242 of the transistor die 240.

[0085] Parallel capacitor 213 (e.g., Figure 1The first electrode (or end) of the parallel capacitor 214 is electrically coupled to the conductive bonding pad 215 (and thus to the bonding line 216), and the second electrode (or end) of the parallel capacitor 214 (e.g., using a conductive through-substrate via 226 extending through the semiconductor substrate) is electrically coupled to the conductive flange.

[0086] IPD component 255 may also include a base semiconductor substrate 266 (e.g., referred to herein as an "IPD substrate") and a construction structure of alternating dielectrics 257 and patterned conductive layers. As will be discussed in more detail below, the parallel capacitor 256 of the output impedance matching circuit 250 (e.g., ...) Figure 1 The capacitor 156 is integrally formed within the IPD assembly 255 with a first end and a second end. The first end is electrically connected to a conductive bonding pad 259 on the top surface of the IPD assembly 255, and the second end is electrically connected to a conductive flange 201 (connected to ground) via a through-substrate via 272 reaching a conductive layer 268 on the bottom surface of the IPD assembly 255.

[0087] First, the connection between the transistor die 240 and the output pin 204 via the output impedance matching circuit 250 will be described in more detail. More specifically, the output pin 204 is electrically coupled to a second terminal 244 of the transistor die 240 via the output impedance matching circuit 250. The second terminal 244 is then electrically coupled to the drain terminal of the FET within the transistor die 240.

[0088] For example, the output impedance matching circuit 240 may include two inductor elements 252, 254 (e.g., Figure 1 Inductors 152, 154) and parallel capacitor 256 (e.g., Figure 1 Parallel capacitor 156). First inductor element 252 (e.g., Figure 1 The inductor element 152 can be implemented as a conductive bonding pad 244 coupled to the top surface of the output pin 204 and the transistor die 240 (e.g., corresponding to the conductive bonding pad 244 on the top surface of the transistor die 240). Figure 1 The third set of bonding wires between terminals 144). The second inductor element 254 (e.g., Figure 1 The inductor element 154 can be implemented as coupled to the bonding pad 259 (corresponding to Figure 1 The fourth set of bonding wires between the connection node 159 and the bonding pad 244 of the transistor die 240.

[0089] Parallel capacitor 256 (e.g., Figure 1The first electrode (or end) of the parallel capacitor 156 is electrically coupled to the conductive bonding pad 259 (and thus to the bonding line 254), and the second electrode 262 (or end) of the parallel capacitor 256 (e.g., using a conductive through-substrate via 272 extending through the semiconductor substrate 266) is electrically coupled to the conductive flange.

[0090] Device 200 is incorporated in an air-cavity package, wherein transistor die 240, IPD assemblies 213 and 255, and various other components are located within the enclosed air cavity. Essentially, the air cavity is bounded by flange 201, isolation structure 203, and a cover (not shown) that covers and contacts isolation structure 203 and leads 202 and 204. Figure 2 In the example, the inner perimeter of the cover is indicated by the dashed box 209, while the outer perimeter will be roughly aligned with the outer perimeter of the flange 201. Alternatively, the components of device 200 can be incorporated into an overmolded package (i.e., a package in which electrical components within the active device region are encapsulated by a non-conductive molding compound, and portions of pins 202 and 240 may also be surrounded by a molding compound). In an overmolded package, isolation structures may not be included.

[0091] Due to the parallel arrangement of the two bonded wire arrays, positive magnetic coupling exists between bonded wire array 254 (which acts as parallel inductor 154) and bonded wire array 252 (which acts as output feed inductor 142) because the bonded wire arrays are very close together. This positive magnetic coupling generates positive mutual inductance. However, this positive mutual inductance poses a considerable challenge in the design of the output matching network 150.

[0092] Embodiments for reducing mutual coupling between the output matching network bond line arrays 252 and 254 will now be described. These embodiments can reduce or eliminate the positive mutual inductance between the bond line arrays 252 and 254 and significantly improve the matching network transformation.

[0093] These embodiments “separate” the bonding wire array 252 into forward and reverse bonding wire arrays. As used herein, the term “separate” as used to describe the bonding wire array means adding an additional set of bonding wires to connect one end of the parallel capacitor to ground. The forward bonding wire array connects the second end of the transistor die to the top plate of the output parallel capacitor. The reverse bonding wire array connects the bottom plate of the output parallel capacitor to the package flange or to the ground node of the transistor die.

[0094] The proposed arrangement of the split bond wire arrays electromagnetically couples to the output bond wire arrays in a manner that creates effective negative mutual inductance between them. Furthermore, when using multi-up RF transistors, this arrangement shields the output bond wire arrays from coupling (electrically and magnetically) to the parallel inductor bond wire arrays, and also shields RF signal paths coupled to adjacent paths. The split bond wire arrangement also improves impedance transformation, potentially eliminating the need for a post-bonding matching network. The split bond wire arrangement also improves isolation between bond wire arrays 216 and 254. Finally, the split bond wire arrangement eliminates the need for through-substrate vias (TSVs) in the output IPD assembly, which helps improve device reliability and reduce the complexity associated with TSV formation.

[0095] Figure 4 This is a schematic diagram of an embodiment of an RF power amplifier circuit 400 using decoupled bonded wires. In this embodiment, circuit 400 includes an input 402 (e.g., a first conductive package pin), an input impedance matching circuit 410, a transistor 440, an output impedance matching circuit 450, and an output pin 404 (e.g., a second conductive package pin). Each of the input 402 and the output 404 may be more generally referred to as an "RF input / output (I / O)".

[0096] The input impedance matching circuit 410 may be referred to as the "input circuit". Similarly, the output impedance matching circuit 450 may be referred to as the "output circuit". Although the transistor 440 and various components of the input and output impedance matching circuits 410 and 450 are shown as a single component, this is described only for ease of explanation. Those skilled in the art will understand based on the description herein that the transistor 440 and / or certain components of the input impedance matching circuit 410 and the output impedance matching circuit 450 may each be implemented as multiple components (e.g., connected in parallel or series with each other). Additionally, embodiments may include single-path devices (e.g., including a single input pin, output pin, transistor, etc.), dual-path devices (e.g., including two input pins, output pins, transistors, etc.), and / or multi-path devices (e.g., including two or more input pins, output pins, transistors, etc.). Furthermore, the number of input / output pins may differ from the number of transistors (e.g., for a given set of input / output pins, multiple transistors may operate in parallel). Therefore, the following description of the various elements of transistor 440, input impedance matching circuit 410, and output impedance matching circuit 450 is not intended to limit the scope of the invention to the embodiments shown.

[0097] Input 402 and output 404 may each include conductors configured to enable electrical coupling of circuit 400 to an external circuitry (not shown). More specifically, in this embodiment, input 402 and output 404 are physically positioned across the exterior and interior of a device package. Input impedance matching circuitry 410 is electrically coupled between input 402 and a first terminal 442 (e.g., gate terminal) of transistor 440. Similarly, output impedance matching circuitry 450 is electrically coupled between a second terminal 444 (e.g., drain terminal) of transistor 440 and output 404. A third terminal 445 (e.g., source terminal) of transistor 440 is coupled to a ground reference node.

[0098] According to an embodiment, transistor 440 is the primary active component of circuit 400. Transistor 440 includes a control terminal 442 and two conductive terminals 444 and 445, wherein the conductive terminals 444 and 445 are spatially and electrically separated by a variable conductivity channel. For example, transistor 440 may be a field-effect transistor (FET) including a gate terminal (control terminal 442), a drain terminal (first conductive terminal 444), and a source terminal (second conductive terminal 445). According to an embodiment, and using the nomenclature generally applied to FETs in a non-limiting manner, the gate terminal 442 of transistor 440 is coupled to an input impedance matching circuit 410, the drain terminal 444 of transistor 440 is coupled to an output impedance matching circuit 450, and the source terminal 445 of transistor 440 is coupled to ground (or another reference voltage). The current between the conductive terminals of transistor 440 can be modulated by varying the control signal provided to the gate terminal of transistor 440.

[0099] According to various embodiments, transistor 440 may be a silicon-based FET (e.g., a laterally diffused metal-oxide-semiconductor (LDMOS) FET). In other embodiments, transistor 440 may be a gallium-based FET (e.g., gallium arsenide, gallium phosphide, or gallium nitride) (e.g., a high electron mobility transistor (HEMT)). Transistor 440 may also use other III-V materials of other architectures (e.g., indium phosphide or indium antimonide).

[0100] As mentioned above, the input impedance matching circuit 410 is electrically coupled between the input 402 and the first terminal 442 (e.g., the gate terminal) of the transistor 440.

[0101] Input impedance matching circuit 410 is coupled between connection node 415 and control terminal 442 (e.g., gate terminal) of transistor 440. Input impedance matching circuit 410 is configured to transform (e.g., raise) the gate impedance of transistor 440 at node 402 to a higher (e.g., intermediate or higher) impedance level (e.g., in the range of about 2 ohms to about 10 ohms or higher). This is advantageous because it allows the printed circuit board level (PCB level) matching interface from the excitation stage to have an impedance that can be achieved with minimal loss and variation in high-volume manufacturing (e.g., a “user-friendly” matching interface). Input impedance matching circuit 410 includes a first series inductor element 412 (e.g., a first set of bond wires) coupled between input 402 and first node 415 (also referred to as the “connection node”). In addition to establishing an electrical connection between input 402 and node 415, the first inductor element 412 also adds reactance to the final transformed impedance provided by input impedance matching circuit 410. A series inductor element 416 (e.g., a second set of bond wires) is coupled between input 402 (or more specifically, inductor 412 or connection node 415) and control terminal 442 of transistor 440. Therefore, inductors 412 and 416 are connected in series between input 402 and control terminal 442 of transistor 440. A first terminal of parallel capacitor 414 is coupled to connection node 415, and a second terminal of parallel capacitor 414 is coupled to ground (or another reference voltage).

[0102] According to an embodiment, series inductors 412 and 416 and parallel capacitor 414 form a low-pass filter for the input matching circuit 410. The low-pass configuration allows for wideband operation at RF frequencies below the cutoff frequency of the low-pass filter.

[0103] According to an embodiment, inductor 412 may have an inductance value ranging from about 150 picohens (pH) to about 450 pH, inductor 416 may have an inductance value ranging from about 150 pH to about 450 pH, and parallel capacitor 414 may have a capacitance value ranging from about 10 pF to about 100 pF. Desiredly, parallel capacitor 414 has a relatively large capacitance (e.g., greater than about 10 pF) to provide an acceptable low RF impedance point at connection node 415. In other embodiments, some or all of the components listed above may have component values ​​smaller or larger than the ranges given above.

[0104] On the output side of circuit 400, an output impedance matching circuit 450 is coupled between the first conductive terminal 444 (e.g., the drain terminal) of transistor 440 and output 404. The output impedance matching circuit 450 is configured to match the output impedance of circuit 400 to the input impedance of external circuitry or components (not shown) that can be coupled to output 404. The output impedance matching circuit 450 can have any of a plurality of different circuit configurations, and Figure 4 Only one example is shown. More specifically, in Figure 4 In the non-limiting example shown, the output impedance matching circuit 450 includes three inductor elements 452, 454, and 458 and a parallel capacitor 456. A first inductor element 452 (e.g., a third set of bond wires) is coupled between a first conductive terminal 444 (e.g., the drain terminal) of transistor 440 and output 404. In an embodiment, a second inductor element 454 (e.g., a fourth set of bond wires) is coupled between the first conductive terminal 444 of transistor 440 and node 459, which is then coupled to a first terminal of the parallel capacitor 456 and may correspond to another RF low impedance point. In an embodiment, a third inductor element 458 (e.g., a fifth set of bond wires) is coupled between a second terminal of the parallel capacitor 456 and ground (or coupled to another reference voltage).

[0105] For example, Figure 5 It is a manifestation Figure 4 The diagram shows a top view of an embodiment of the layout of an RF amplifier device 500, an example of circuitry 400, and is used to provide portions of the amplifier and matching network in a Doherty amplifier. Additionally, two instances of the RF amplifier device 500 can be incorporated into a package to provide two amplifiers (e.g., a main amplifier (or carrier amplifier) ​​and a peaking amplifier) ​​in a Doherty amplifier. Figure 6 Including according to the example embodiments Figure 5 A cross-sectional side view along line 6-6.

[0106] In an embodiment, device 500 includes a flange 501 (or "device substrate"), the flange comprising a rigid conductive substrate having a thickness sufficient to provide structural support for various electrical components and elements of device 500. Additionally, flange 501 may serve as a heat sink for transistor die 540 and other devices mounted on flange 501. Flange 501 has a top surface and a bottom surface (in... Figure 5 Only the central portion of the top surface is visible, and the perimeter of the device 500 is basically rectangular.

[0107] Flange 501 is formed of a conductive material and can be used to provide a ground reference node for device 500. For example, various components and elements may have ends electrically coupled to flange 501, and flange 501 may be electrically coupled to system ground when device 500 is integrated into a larger power system. At least the top surface of flange 501 is formed of a layer of conductive material, and possibly all of flange 501 is formed of a bulk conductive material.

[0108] In the embodiment, the isolation structure ( Figure 6 The insulating structure 503 is attached to the top surface of the flange 501. The insulating structure 503, formed of a rigid electrically insulating material, provides electrical isolation between conductive components of the device (e.g., between pins 502, 504 and flange 501). In embodiments, the insulating structure 503 has a frame shape, comprising a substantially closed quadrilateral structure with a central opening. The insulating structure 503 may have a substantially rectangular shape, or it may have another shape (e.g., a ring, an ellipse, etc.).

[0109] A portion of the top surface of the flange 501 exposed through the opening in the isolation structure 503 is referred to herein as the “active region” of the device 500. The transistor die 540, together with integrated IPD components 513 and 555, is located within the active device region of the device 500, as will be described in more detail later. For example, the transistor die 540 and the IPD components 513 and 555 may be coupled to the top surface of the flange 501 using conductive epoxy, solder, solder bumps, sintering, and / or eutectic bonding.

[0110] Device 500 accommodates display circuit 400 ( Figure 4 The amplification path of the physical implementation scheme. When incorporated into a Doherty amplifier, the amplification path can correspond to either the main amplifier path or the peaking amplifier path.

[0111] Device 500 includes input pin 502, output pin 504, and transistor die 540 (e.g., Figure 4 Transistor 440), input impedance matching circuit 510 (e.g., Figure 4 The input impedance matching circuit 410) and the output impedance matching circuit 550 (e.g., Figure 4 Output impedance matching circuit 450).

[0112] Input pin 502 and output pin 504 are mounted on the top surface of isolation structure 503 on opposite sides of the central opening, and thus input pin 502 and output pin 504 are raised above the top surface of flange 501 and electrically isolated from flange 501. Generally, input pin 502 and output pin 504 are oriented to allow bonding wires to be attached between input pin 502 and output pin 504 and components and elements within the central opening of isolation structure 503.

[0113] Transistor die 540 includes an integrated power FET (e.g., a single-stage FET or a final-stage FET), wherein the FET has a control terminal (e.g., a gate terminal) and two conductive terminals (e.g., a drain terminal and a source terminal). The control terminal of the FET within transistor die 540 is coupled to an input impedance matching circuit 510 via transistor input terminal 542, and thus coupled to input pin 502. Additionally, one conductive terminal (e.g., the drain terminal) of the FET within transistor die 540 is coupled to an output pin 504 via an output impedance matching circuit 550. In an embodiment, the other conductive terminals (e.g., the source terminal) of the FET within transistor die 540 are electrically coupled to an flange 501 (e.g., coupled to ground) via die 540.

[0114] Some of the components of the input impedance matching circuit 510 can be implemented within the IPD component 513. Simply put, the input impedance matching circuit 510 is coupled between the input pin 502 and the control terminal of the FET within the transistor die 540. Similarly, some of the components of the output impedance matching circuit 550 can be implemented within the IPD component 555. Simply put, each output impedance matching circuit 550 is coupled between a conductive terminal (e.g., the drain terminal) of the FET within the transistor die 540 and the output pin 504.

[0115] IPD component 513 may include a base semiconductor substrate 582 (e.g., a silicon substrate, silicon carbide substrate, GaN substrate, or another type of semiconductor substrate which may be referred to herein as an "IPD substrate") and a construction of alternating dielectrics 517 and patterned conductive layers, wherein portions of the patterned conductive layers are electrically connected using conductive vias. As will be discussed in more detail below, the parallel capacitor of the input impedance matching circuit 510 is integrally formed within the IPD component 513 and may be electrically connected to conductive bonding pads 515 on the top surface of the IPD component 513, and may also be electrically connected to conductive flanges 501 using through-substrate vias 526 reaching the conductive layer 586 on the bottom surface of the IPD component 513.

[0116] First, the connection between the transistor die 540 and the input pin 502 via the input impedance matching circuit 510 will be described in more detail. More specifically, the input pin 502 is electrically coupled to the input terminal 542 of the transistor die 540 via an example of the input impedance matching circuit 510. The input terminal 542 is then electrically coupled to the control terminal (e.g., the gate terminal) of the FET within the transistor die 540.

[0117] For example, in an embodiment, the input impedance matching circuit 510 may include two inductor elements 512, 516 (e.g., Figure 1 Inductors 412, 416) and parallel capacitor 513 (e.g., Figure 1 Parallel capacitor 414). First inductor element 512 (e.g., Figure 1 The inductor element 412 can be implemented as a conductive bonding pad 515 coupled to the top surface of the input pin 502 and the IPD component 513 (e.g., corresponding to...). Figure 1 The first set of bond lines between the connection node 415). The second inductor element 516 (e.g., Figure 1 The inductor element 416 can be implemented as coupled to the bonding pad 515 (corresponding to Figure 1 The second set of bonding wires between the connection node 415 and the input terminal 542 of the transistor die 540.

[0118] According to an embodiment, parallel capacitors (e.g., Figure 4 The first electrode 518 (or end) of the parallel capacitor 414 is electrically coupled 528 to the conductive bonding pad 515 (and thus to the bonding lines 512, 516), and the second electrode 520 (or end) of the parallel capacitor (e.g., using a conductive through-substrate via 526 extending through the semiconductor substrate) is electrically coupled to a conductive flange. The parallel capacitor can be implemented as a metal-insulator-metal (MIM) capacitor (or a group of parallel-coupled MIM capacitors) integrally formed as part of the IPD assembly 513. In another embodiment, the parallel capacitor can also be implemented as a metal-oxide-semiconductor (MOS) capacitor. In an alternative embodiment, the parallel capacitor 513 can be implemented using one or more discrete capacitors coupled to the top surface of the IPD assembly 513 or using another type of capacitor.

[0119] According to an embodiment, bonding wire 512 may have an inductance value in the range of about 200 pH to about 600 pH, bonding wire 516 may have an inductance value in the range of about 200 pH to about 600 pH, and parallel capacitor 514 may have a capacitance value in the range of about 60 pF to about 200 pF. In other embodiments, some or all of the components listed above may have component values ​​smaller or larger than the ranges given above.

[0120] IPD component 555 may also include a base semiconductor substrate 566 (e.g., a silicon substrate, silicon carbide substrate, GaN substrate, or another type of semiconductor substrate, which may be referred to herein as "IPD substrate") and a construction structure of alternating dielectrics 557 and patterned conductive layers. As will be discussed in more detail below, the parallel capacitor of the output impedance matching circuit 550 is integrally formed within the IPD component 555 and may be electrically connected to conductive bonding pads 559 on the top surface of the IPD component 555, and may also be electrically connected to conductive flange 501 (e.g., electrically connected to ground) via pads 592, bonding wires 558, and pads 595.

[0121] The connection between transistor die 540 and output pin 504 via output impedance matching circuit 550 will be described in more detail. More specifically, output pin 504 is electrically coupled to a second terminal 544 of transistor die 540 via output impedance matching circuit 550. Second terminal 544 is then electrically coupled to the drain terminal of the FET within transistor die 540.

[0122] For example, in an embodiment, the output impedance matching circuit 540 may include three inductor elements 552, 554, and 558 (e.g., Figure 4 Inductors 452, 454, 458) and parallel capacitors (e.g., Figure 4 Parallel capacitor 456). First inductor element 552 (e.g., Figure 4 The inductor element 452 can be implemented as a conductive bonding pad 544 coupled to the top surface of the output pin 504 and the transistor die 540 (e.g., corresponding to...). Figure 4 The third set of bond lines between the connection node 444). The second inductor element 554 (e.g., Figure 4 The inductor element 454 can be implemented as coupled to the bonding pad 559 (corresponding to Figure 1 The fourth set of bonding wires between the connection node 459 and the second end 544 of the transistor die 540. The third inductor element 558 (e.g., Figure 4 The inductor element 458 can be implemented as coupled to the bonding pad 592 (corresponding to Figure 4 The fifth bond line between the connection node 492 and the flange 501 or ground.

[0123] According to an embodiment, the parallel capacitor 556 (e.g., Figure 1The first electrode 562 (or end) of the parallel capacitor 456 is electrically coupled to the conductive bonding pad 559 (and thus to the bonding line 554) via a via 590, and the second electrode 560 (or end) of the parallel capacitor 556 is electrically coupled to the conductive flange 501 via the pad 595, the bonding line 558, and the pad 592. The parallel capacitor 556 may be implemented as a MIM capacitor (or a set of parallel-coupled MIM capacitors) integrally formed as part of the IPD assembly 555. In another embodiment, the parallel capacitor may also be implemented as a MOS capacitor. In a more specific embodiment, the second electrode 560 of the parallel capacitor 556 is “directly connected” to the bonding pad 592, where “directly connected” means electrically connected, possibly having one or more conductive traces and / or conductive vias 570, but without intervening circuit elements (i.e., circuit elements with an inductance greater than the trace inductance, where “trace inductance” is an inductance less than about 100 pH). Because the parallel capacitor 556 and the bonding pad 592 are "directly connected," and the bonding pad 592 only has trace inductance, in this embodiment, the bonding line 558 and the parallel capacitor 556 can also be considered "directly connected." Similarly, the parallel capacitor 556, the bonding pad 559, and the bonding line 554 are "directly connected." In an alternative embodiment, the parallel capacitor 456 can be implemented using one or more discrete capacitors coupled to the top surface of the IPD assembly 555 or using another type of capacitor.

[0124] According to an embodiment, bonding wire 552 may have an inductance value in the range of about 200 pH to about 600 pH, bonding wire 554 may have an inductance value in the range of about 200 pH to about 600 pH, bonding wire 558 may have an inductance value in the range of about 100 pH to about 300 pH, and parallel capacitor 556 may have a capacitance value in the range of about 60 pF to about 200 pF. Furthermore, bonding wires 552 and 554 may have mutual inductance in the range of about 5 to about 100 pH, bonding wires 552 and 558 may have negative mutual inductance in the range of about 5 to about 150 pH, and bonding wires 554 and 558 may have negative mutual inductance in the range of about 5 to about 100 pH. In other embodiments, some or all of the components or inductors listed above may have component values ​​or inductance values ​​smaller or larger than the ranges given above.

[0125] The mutual inductances between bond wires 552, 554, and 558 can be selected based on various design choices regarding the size and location of bond wires 552, 554, and 558. Because the current flowing through bond wire 558 is in the opposite direction to the current flowing through bond wires 552 and 554, a negative mutual inductance is generated, which reduces the total mutual inductance between bond wires 552, 554, and 558. Therefore, due to... Figure 1 The potential decay caused by the mutual inductance between bond wires 152 and 154 can be reduced by using bond wire 558. Furthermore, it should be noted that bond wires 552, 554, and 558 are substantially parallel to each other.

[0126] It should also be noted that bonding wire 558 can essentially shield the bonding wires 554 and 552. For example... Figure 5 As shown, bonding wire 558 is located between bonding wire 552 and bonding wire 554 to provide this shielding. While bonding wire 558 is expected to provide the desired shielding, the number and grouping of bonding wires can differ. Figure 5 The numbers and groupings shown are as follows. For example, bond line 554 is shown as a group of bond lines (i.e., only a single bond line 554 is located between adjacent bond lines 558), but this number can be more. Similarly, bond lines 558 are also shown as a group of bond lines (i.e., only a single bond line 558 is located between adjacent bond lines 554, 512), but this number can also be more.

[0127] According to one embodiment, device 500 is incorporated in an air-cavity package, wherein transistor die 540, IPD assemblies 544 and 555, and various other components are located within the enclosed air cavity. Essentially, the air cavity is bounded by flange 501, isolation structure 503, and a cover (not shown) that covers and contacts isolation structure 503 and pins 502 and 504. Figure 5 In this example, the inner perimeter of the cover is indicated by a dashed box 509, while the outer perimeter will be aligned with the outer perimeter of the flange 501. In other embodiments, components of device 500 may be incorporated into an overmolded package (i.e., a package in which electrical components within the active device region are encapsulated by a non-conductive molding compound, and portions of pins 502 and 504 may also be surrounded by a molding compound). In an overmolded package, the isolation structure 503 may not be included.

[0128] Figure 4-6An embodiment of an RF amplifier device is illustrated, comprising input and output pins coupled to a substrate (i.e., with intervening electrical isolation), and a transistor die also coupled to the substrate between the input and output pins. Such RF amplifier devices may be particularly suitable for high-power amplification. Based on the description herein, those skilled in the art will understand that various embodiments can also be implemented using different forms of packaging or construction. For example, one or more amplification paths including embodiments of the subject matter of this invention may be coupled to a substrate such as a PCB, a leadless type package (e.g., a quad flat no-leads (QFN) package), or another type of package. In such embodiments, conductive solder pads or other input / output (I / O) structures may be used to implement the inputs and outputs of the amplification paths. Such implementations may be particularly suitable for smaller power amplification systems, such as those including relatively low-power Doherty amplifiers, where the main amplification path and peaking amplification path (including bare transistor dies, IPDs, bias circuitry, etc.), power dividers, delay and impedance inverting elements, combiners, and other components may be coupled to the substrate. It should be understood that embodiments of the subject matter of this invention are not limited to the embodiments shown.

[0129] Figure 7 It is a manifestation Figure 4 A top view of another embodiment of the layout of the RF amplifier device 700, an example of circuit 400. Regarding the construction of the transistor die 740 and how the bonding wire 558 is grounded, the device 700... Figure 5 The device 500 is different. In device 500 ( Figure 4-6 In device 700, the bonding wire 558 is grounded via a connection to flange 501. As discussed above, this can be accomplished by directly connecting the bonding wire 558 to the flange or by using connection structure 595. In device 700, the bonding wire 558 is connected to pad 797 on the top surface of transistor die 740, wherein pad 797 is electrically coupled to a conductive layer (not shown) on the bottom surface of transistor die 740 via conductive structures within transistor die 740 (e.g., vias and portions of patterned conductive layers). The bottom conductive layer is then connected (grounded) to the flange. Otherwise, devices 540 and 740 may be substantially identical.

[0130] Figure 8A top view is shown of an embodiment of an output parallel capacitor 856 that can be incorporated into an output IPD (e.g., output IPD 555) used in the aforementioned devices 500, 700. The parallel capacitor 856 includes a first plate 824 and a second plate 825 (or a first electrode and a second electrode), the first and second plates overlapping each other and separated by a dielectric. The parallel capacitor 856 includes bonding pads 892 connected to the first plate 824 using conductive vias (e.g., vias in region 822). The parallel capacitor 856 also includes bonding pads 859 connected to the second plate 825. Because the bonding pads 892, 859 are located on opposite sides of the parallel capacitor 856, when the bonding pads 829, 859 (e.g., using bonding wires 854, 858) are connected to a transistor die and connected to ground, at least one set of bonding wires connected to the parallel capacitor 856 crosses the parallel capacitor 856, as if bonding... Figure 10 and 12 describe.

[0131] Figure 9 A top view is shown of an embodiment of an output parallel capacitor 956 that can be alternatively used in the aforementioned devices 500, 700. The parallel capacitor 956 has a first plate 924 and a second plate 925. The parallel capacitor 956 includes a plurality of bonding pads 992, each of which is connected to the first plate 924 via a via (e.g., a via in zone 922). The parallel capacitor 956 also includes a plurality of bonding pads 959, each of which is connected to the second plate 925. Because the bonding pads 992, 959 are on the same side of the parallel capacitor 956, neither of the two sets of bonding wires connected to the parallel capacitor 956 (e.g., bonding wires 954, 958) needs to cross the parallel capacitor 956, as if the bonding... Figure 11 and 13 describe.

[0132] Figure 10-13 Different configurations of devices 500 and 700 using parallel capacitors 856 and 956 are shown.

[0133] Figure 10 In the output IPD (e.g., in Figure 5 In the IPD 555, a parallel capacitor 856 is used. Figure 8 A simplified side view of an embodiment of the device 500. In this embodiment, bonding wires 858 and 854 are connected to opposite sides of the parallel capacitor 856 (e.g., to bonding pads 892 and 859, respectively). In this embodiment, bonding wire 858 is grounded to flange 501 directly or via pad 595. As previously described... Figure 5 and 6As described, bonding wire 854 connects transistor die 540 to parallel capacitor 856, and bonding wire 852 connects transistor die 540 to output pin 504.

[0134] Figure 11 In the output IPD (e.g., in Figure 5 In the IPD 555, a parallel capacitor 956 is used. Figure 9 A simplified side view of an embodiment of the device 500. In this embodiment, bonding wires 958 and 954 are connected to the same side of the parallel capacitor 956 (e.g., to bonding pads 992 and 959, respectively). In this embodiment, bonding wire 558 is grounded to flange 501 directly or via pad 595. As previously described... Figure 5 and 6 As described, bonding wire 954 connects transistor die 540 to parallel capacitor 956, and bonding wire 952 connects transistor die 540 to output pin 504.

[0135] Figure 12 In the output IPD (e.g., in Figure 7 In the IPD 555, a parallel capacitor 856 is used. Figure 8 A simplified side view of an embodiment of the device 700. In this embodiment, bonding wires 558 and 554 are connected to opposite sides of the parallel capacitor 856 (e.g., to bonding pads 892 and 859, respectively). In this embodiment, bonding wire 558 is connected to the transistor die 740 (e.g., to bonding pad 797) and then grounded to the flange 501 via a conductive structure 741 in the transistor die 740. As previously described, bonding wire 854 connects the transistor die 740 to the parallel capacitor 856, and bonding wire 852 connects the transistor die 740 to the output pin 504.

[0136] Figure 13 In the output IPD (e.g., in Figure 7 In the IPD 555, a parallel capacitor 956 is used. Figure 9 A simplified side view of an embodiment of the device 700. In this embodiment, bonding wires 558 and 554 are connected to the same side of the parallel capacitor 956 (e.g., to bonding pads 992 and 959, respectively). In this embodiment, bonding wire 558 is connected to the transistor die 740 (e.g., to bonding pad 797) and then grounded to the flange 501 via a conductive structure 741 in the transistor die 740. As previously described, bonding wire 954 connects the transistor die 740 to the parallel capacitor 956, and bonding wire 952 connects the transistor die 740 to the output pin 504.

[0137] Figure 14 It is used to manufacture packaged RF power amplifier devices (e.g., Figure 5 Device 500 or Figure 7 The flowchart of a method (applied to device 700) includes embodiments of input and output impedance matching circuits (e.g., circuits 410 and 450) according to various example embodiments. In blocks 1402-1404, the method may begin by forming one or more IPD components. More specifically, in block 1402, one or more input IPDs and output IPDs (e.g., ...) may be formed. Figure 5-7 IPDs of 10-13 (e.g., 513, 555, 856, 956). According to embodiments, the input IPD (e.g., IPD 513) includes components of an input impedance matching circuit. For example, each input IPD may include one or more integrated parallel capacitors (e.g., ...). Figure 4 (Capacitor 414). According to an embodiment, the output IPD (e.g., IPD 555, 856, 956) includes components of an output impedance matching circuit. For example, each output IPD may include one or more integrated parallel capacitors (e.g., capacitor 414). Figure 4-13 The capacitors are 555, 856, and 956. In addition to forming the passive components of each IPD, forming each IPD also includes forming various conductive members (e.g., conductive layers and vias), which facilitates electrical connections between various components of each circuit. For example, forming an IPD may also include forming various accessible connection nodes on the surface of each IPD substrate. As previously discussed, connection nodes may include conductive bonding pads (e.g., Figure 4-9 The bonding pads (515, 559, 592, 859, 892, 959, 992) can accept inductive components (e.g., Figure 5-7 The attachment of bonding lines 512, 516, 552, 554, and 558 (10-13). Furthermore, in block 1404, when corresponding to various circuit elements (e.g., Figure 4 When some components of capacitors 414, 456 are implemented as discrete components (rather than integrated components), these discrete components can be coupled to conductors exposed on the surface of each IPD to form one or more IPD assemblies.

[0138] In block 1406, for the air cavity embodiment, isolation structure 503 is coupled to a device substrate (e.g., flange 401). Additionally, one or more active devices (e.g., transistor 440) and IPD components (e.g., IPD components 513, 555, 855, 9565) are coupled to a portion of the top surface of the substrate exposed through an opening in isolation structure 503. Pins (e.g., input pin 402 and output pin 404) are coupled to the top surface of isolation structure 503. For overmolded (e.g., encapsulated) device embodiments, isolation structure 503 may not be included, and the substrate and pins may form a portion of a leadframe.

[0139] In block 1408, the input pins, transistors, IPD components, and output pins are electrically coupled together. For example, as previously discussed, electrical connections can be made between the various device components and elements using bonding wires. Some of the bonding wires correspond to inductive components of the input or output matching circuitry (e.g., Figure 5-7 (10-13 bond lines 512, 516, 552, 554, 558). Finally, in block 1410, the device is capped (e.g., for air cavity encapsulation) or encapsulated (e.g., using a molding compound for overmolded encapsulation). The device can then be incorporated into a larger electrical system (e.g., a Doherty amplifier or other type of electrical system).

[0140] The above description describes a packaged radio frequency (RF) amplifier device comprising: a device substrate; an input pin coupled to the device substrate; an output pin coupled to the device substrate; a transistor die coupled to the device substrate, wherein the transistor die includes a transistor, a transistor input coupled to the input pin, and a transistor output coupled to the output pin; an output impedance matching circuit coupled to the output pin and the transistor output, wherein the output impedance matching circuit includes a first set of bonding wires coupled between the output pin and the transistor output; an output capacitor including a first terminal and a second terminal; a second set of bonding wires coupled between the transistor output and the first terminal of the output capacitor; and a third set of bonding wires coupled between the second terminal of the output capacitor and a ground reference node, wherein the third set of bonding wires is substantially parallel to the first and second sets of bonding wires.

[0141] The above description also describes a method of manufacturing an RF amplifier device, the method comprising the steps of: coupling an input pin to a device substrate; coupling an output pin to the device substrate; coupling a transistor die to the device substrate between the input and output pins, wherein the transistor die includes a transistor and a transistor input terminal; coupling an output impedance matching circuit between the output pin and the transistor output terminal, wherein the output impedance matching circuit includes a first set of bonding wires coupled between the output pin and the transistor output, an output capacitor including a first terminal and a second terminal, a second set of bonding wires coupled between the transistor output and the first terminal of the output capacitor, and a third set of bonding wires coupled between the second terminal of the output capacitor and a ground reference node, wherein the third set of bonding wires is substantially parallel to the first and second sets of bonding wires.

[0142] The above description also describes a radio frequency (RF) amplifier comprising: a transistor die having a transistor and a transistor output; an output impedance matching circuit coupled to the output pin and the transistor output, wherein the output impedance matching circuit includes a first set of bonding wires coupled between the output pin and the transistor output; an output capacitor including a first terminal and a second terminal; a second set of bonding wires coupled between the transistor output and the first terminal of the output capacitor; and a third set of bonding wires coupled between the second terminal of the output capacitor and a ground reference node, wherein the third set of bonding wires is substantially parallel to the first and second sets of bonding wires.

[0143] The foregoing specific embodiments are merely illustrative in nature and are not intended to limit the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, one should not be bound by any expressed or implied theory presented in the foregoing technical field, background art, or specific embodiments.

[0144] The connecting lines shown in the figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of the subject matter. Furthermore, certain terms may be used herein for reference only, and therefore these terms are not intended to be limiting, and unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply order or sequence.

[0145] As used herein, a “node” means any internal or external reference point, connection point, interface, signal line, conductive element, etc., where a given signal, logic level, voltage, data mode, current, or quantity exists. Furthermore, two or more nodes can be implemented using a single physical element (and although received or output at a common node, two or more signals can still be multiplexed, modulated, or otherwise distinguished).

[0146] The foregoing description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly engaged to (or directly communicates with) another element, and not necessarily mechanically. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly engaged to (or directly or indirectly connected to) another element electrically or otherwise, and not necessarily mechanically. Therefore, while the schematic diagrams shown depict an exemplary arrangement of elements, additional intervening elements, means, features, or components may be present in embodiments of the depicted subject matter.

[0147] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed description will provide a convenient guide for those skilled in the art to implement the one or more described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing this patent application.

Claims

1. A packaged RF amplifier device, characterized in that, include: device substrate; Input pins are coupled to the device substrate; The output pin is coupled to the device substrate; A transistor die coupled to the device substrate, wherein the transistor die includes a transistor, a transistor input terminal coupled to the input pin, and a transistor output terminal coupled to the output pin; An output impedance matching circuit is coupled to the output pin and the transistor output terminal, wherein the output impedance matching circuit includes... The first set of bonding wires is coupled between the output pin and the transistor output terminal. The output capacitor includes a first terminal and a second terminal. The second set of bonding wires is coupled between the transistor output terminal and the first terminal of the output capacitor, and A third set of bond wires is coupled between the second terminal of the output capacitor and the ground reference node, wherein the third set of bond wires is parallel to the first and second sets of bond wires. The first set of bonding wires, the second set of bonding wires, and the third set of bonding wires have profiles configured to increase the electromagnetic coupling between the first set of bonding wires and the third set of bonding wires, decrease the electromagnetic coupling between the first set of bonding wires and the second set of bonding wires, and decrease the electromagnetic coupling between the second set of bonding wires and the third set of bonding wires.

2. The packaged RF amplifier device according to claim 1, characterized in that, The output capacitor is an integrated passive device.

3. The packaged RF amplifier device according to claim 2, characterized in that, The first and second terminals of the output capacitor are on opposite sides of the integrated passive device.

4. The packaged RF amplifier device according to claim 2, characterized in that, The first and second terminals of the output capacitor are on the same side of the integrated passive device.

5. The packaged RF amplifier device according to claim 1, characterized in that, The bonding wires in the third group of bonding wires shield each other between the bonding wires in the first group of bonding wires and the bonding wires in the second group of bonding wires.

6. The packaged RF amplifier device according to claim 5, characterized in that, The third set of bonding wires shields the first set of bonding wires from the second set of bonding wires.

7. The packaged RF amplifier device according to claim 1, characterized in that, The grounding reference node is a flange.

8. The packaged RF amplifier device according to claim 1, characterized in that, The ground reference node is the ground pad on the transistor die.

9. A method for manufacturing an RF amplifier device, characterized in that, The method includes the following steps: Couple the input pins to the device substrate; Couple the output pin to the device substrate; A transistor die is coupled to the device substrate between the input and output pins, wherein the transistor die includes a transistor and a transistor input terminal; An output impedance matching circuit is coupled between the output pin and the transistor output terminal, wherein the output impedance matching circuit includes... The first set of bonding wires is coupled between the output pin and the transistor output terminal. The output capacitor includes a first terminal and a second terminal. The second set of bonding wires is coupled between the transistor output terminal and the first terminal of the output capacitor, and A third set of bonding wires is coupled between the second terminal of the output capacitor and the ground reference node, wherein the third set of bonding wires is parallel to the first and second sets of bonding wires. The first set of bonding wires, the second set of bonding wires, and the third set of bonding wires have profiles configured to increase the electromagnetic coupling between the first set of bonding wires and the third set of bonding wires, decrease the electromagnetic coupling between the first set of bonding wires and the second set of bonding wires, and decrease the electromagnetic coupling between the second set of bonding wires and the third set of bonding wires.

10. A radio frequency (RF) amplifier, characterized in that, include: A transistor die, which has a transistor and a transistor output terminal; An output impedance matching circuit is coupled to the output pin and the transistor output terminal, wherein the output impedance matching circuit includes... The first set of bonding wires is coupled between the output pin and the transistor output terminal. The output capacitor includes a first terminal and a second terminal. The second set of bonding wires is coupled between the transistor output terminal and the first terminal of the output capacitor, and A third set of bond wires is coupled between the second terminal of the output capacitor and the ground reference node, wherein the third set of bond wires is parallel to the first and second sets of bond wires. The first set of bonding wires, the second set of bonding wires, and the third set of bonding wires have profiles configured to increase the electromagnetic coupling between the first set of bonding wires and the third set of bonding wires, decrease the electromagnetic coupling between the first set of bonding wires and the second set of bonding wires, and decrease the electromagnetic coupling between the second set of bonding wires and the third set of bonding wires.

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