drive device

Abstract

The present application provides a kind of driving device, prevent the overcurrent detection input terminal voltage due to the current flowing in the chip peripheral ground wiring rises and thus generates the false operation of overcurrent detection circuit.In the IS terminal of overcurrent detection circuit arranged in the position far away from GND terminal and the B point of chip peripheral ground wiring (11) are provided as terminal protection circuit transistor MN1, in the CFO terminal arranged in the position further away from GND terminal and the C point of chip peripheral ground wiring (11) are provided as terminal protection circuit zener diode ZD1.In addition, the input of the acceptance threshold voltage of comparator COMP_IS and the B point of chip peripheral ground wiring (11) are provided as potential offset element transistor MN2.Between thus, when the potential of B point rises due to the overvoltage applied to CFO terminal, by making the two input terminals of comparator COMP_IS also rise, thereby preventing false operation.

Description

Technical Field

[0001] This invention relates to drive devices, and more particularly to drive devices having terminal protection circuits for overvoltage noise and overcurrent detection circuits. Background Technology

[0002] For example, a three-phase motor used in an air conditioner compressor is driven and controlled by a motor drive unit. The motor drive unit comprises a power switch that controls the power supplied to the three-phase motor, a drive circuit that drives the switching of these power switches on and off, and various protection circuits, all assembled in a single package.

[0003] Figure 4 This diagram illustrates a typical configuration of a motor drive unit. It should be noted that in the following description, the terminal names and the voltage, signal, etc., of those terminals may use the same symbols.

[0004] like Figure 4 As shown, the three-phase motor M is driven by a motor drive device consisting of an IPM (Intelligent Power Module) 100, which is controlled by a microcontroller unit (MCU) 200 built into a microcomputer.

[0005] The IPM100 has power switches Q1 to Q6. In this configuration example, the power switches Q1 to Q6 are IGBTs (Insulated Gate Bipolar Transistors), and each IGBT is connected in reverse parallel with a FWD (Free Wheeling Diode).

[0006] Power switches Q1 and Q2 are connected in series, and their two ends are connected to the positive power terminal (P terminal) and negative power terminal (N (U) terminal) of IPM100. The connection point between power switches Q1 and Q2 is connected to the U-phase terminal of the three-phase motor M via the U terminal of IPM100. Power switches Q3 and Q4 are connected in series, and their two ends are connected to the P terminal and negative power terminal (N (V) terminal) of IPM100. The connection point between power switches Q3 and Q4 is connected to the V-phase terminal of the three-phase motor M via the V terminal of IPM100. Power switches Q5 and Q6 are connected in series, and their two ends are connected to the P terminal and negative power terminal (N (W) terminal) of IPM100. The connection point between power switches Q5 and Q6 is connected to the W-phase terminal of the three-phase motor M via the W terminal of IPM100.

[0007] The gates of the high-side power switches Q1, Q3, and Q5 are connected to the output terminals of the high-voltage side control circuits HV-IC(U), HV-IC(V), and HV-IC(W). The input terminals of the high-voltage side control circuits HV-IC(U), HV-IC(V), and HV-IC(W) are connected to the HU, HV, and HW terminals of the MCU200 via the IN (HU), IN (HV), and IN (HW) terminals of the IPM100.

[0008] The gates of the low-side power switches Q2, Q4, and Q6 are connected to the UOUT, VOUT, and WOUT terminals of the low-voltage side control circuit LV-IC. The low-voltage side control circuit LV-IC has VCC, GND, TEMP, IS, CFO, VFO, UIN, VIN, and WIN terminals.

[0009] The VCC terminal of the low-voltage side control circuit LV-IC is connected to the positive terminal of power supply E1 and the positive terminal of capacitor C1 via the VCCL terminal of IPM100. The negative terminals of power supply E1 and capacitor C1 are connected to the negative power supply terminal, which is connected to the N(U), N(V), and N(W) terminals of IPM100, and the GND terminal of MCU200. The GND terminal of the low-voltage side control circuit LV-IC is connected to the negative power supply terminal and the GND terminal of MCU200 via the COM terminal of IPM100. It should be noted that the power supply E1 of the low-voltage side control circuit LV-IC is connected to a bootstrap circuit (not shown) and generates power supply voltages for the high-voltage side control circuits HV-IC(U), HV-IC(V), and HV-IC(W) based on the potentials of the N(U), N(V), and N(W) terminals of IPM100, respectively. Therefore, the high-voltage side control circuits HV-IC(U), HV-IC(V), and HV-IC(W) shift the signal level from the MCU200 to output the voltages that drive the high-side power switches Q1, Q3, and Q5.

[0010] The TEMP terminal of the low-voltage side control circuit LV-IC is the output terminal of the overheat protection circuit, and is connected to the TEMP terminal of the MCU200 via the TEMP terminal of the IPM100. The IS terminal is the input terminal of the overcurrent detection circuit that detects overcurrent in power switches Q1~Q6, and is connected to the IS terminal of the IPM100. The low-side power switches Q2, Q4, and Q6 use IGBTs with current sensing terminals. These IGBTs have a structure that shuns a certain proportion of the current flowing from the collector to an emitter different from the emitter through which the main current flows. The current from the current sensing terminals of power switches Q2, Q4, and Q6 is pooled at the VSC terminal of the IPM100 and returned to the negative power supply terminal through an externally connected current sensing resistor RIS. The VSC terminal of the IPM100 is connected to the negative power supply terminal via a series circuit of resistor Rn and capacitor Cn, and the junction of resistor Rn and capacitor Cn is connected to the IS terminal of the IPM100. Therefore, the current output from the current sensing terminals of power switches Q2, Q4, and Q6 is converted into voltage by the current sensing resistor RIS, and the converted voltage is noise-removed by resistor Rn and capacitor Cn before being input to the overcurrent detection circuit of the low-voltage side control circuit LV-IC.

[0011] The VFO terminal of the low-voltage side control circuit LV-IC is the output terminal for a fault signal indicating an abnormal state detected by the internal protection circuit, and it is connected to the VFO terminal of MCU200 via the VFO terminal of IPM100. The VFO terminals of IPM100 and MCU200 are connected to the positive terminals of power supply E2 and capacitor C2 via pull-up resistors Rp. The positive terminals of power supply E2 and capacitor C2 are also connected to the VDD terminal of MCU200. The negative terminals of power supply E2 and capacitor C2 are connected to the negative power supply terminal and the GND terminal of MCU200. When the protection circuit of the low-voltage side control circuit LV-IC is not outputting a fault signal indicating an abnormal state, a high (H) level signal is input to the VFO terminal of MCU200 due to the pull-up resistor Rp. When the protection circuit of the low-voltage side control circuit LV-IC is outputting a fault signal indicating an abnormal state, a low (L) level fault signal is input to the VFO terminal of MCU200. In addition, when the low-voltage side control circuit LV-IC outputs a low (L) level fault signal, it stops the low-side power switches Q2, Q4, and Q6.

[0012] The CFO terminal of the low-voltage side control circuit LV-IC is connected to one terminal of an externally connected capacitor Cfo via the CFO terminal of the IPM100, and the other terminal of capacitor Cfo is connected to the negative power supply terminal. This capacitor Cfo is used to set the minimum output width of the L-level fault signal. This minimum output width is set by detecting when the terminal voltage of capacitor Cfo reaches a predetermined voltage while the capacitor Cfo is being charged with a constant current. If the system recovers from the abnormal state after this minimum output width has elapsed, the low-voltage side control circuit LV-IC can again drive the low-side power switches Q2, Q4, and Q6.

[0013] The UIN, VIN, and WIN terminals of the low-voltage side control circuit LV-IC are the input terminals for the signals that control the power switches Q2, Q4, and Q6 from the MCU200. The UIN, VIN, and WIN terminals are connected to the LU, LV, and LW terminals of the MCU200 respectively via the IN (LU), IN (LV), and IN (LW) terminals of the IPM100.

[0014] Here, the VCC, TEMP, IS, CFO, VFO, UIN, VIN, and WIN terminals of the low-voltage side control circuit LV-IC are equipped with terminal protection circuits to prevent damage to the input / output terminals caused by overvoltage in the event of electrostatic discharge, lightning surges, etc. A specific example of this terminal protection circuit will be described below.

[0015] Figure 5 This is a circuit diagram illustrating an example of a terminal protection circuit for a low-voltage side control circuit. Figure 6 This is a diagram illustrating an example of the configuration on a semiconductor chip for a low-voltage side control circuit. Figure 7 This is a diagram showing the operating waveforms of the terminal protection circuit when an overvoltage is applied. It should be noted that... Figure 7 The following data is displayed from top to bottom: voltage V_CFO at CFO terminal, current Ip flowing into CFO terminal when overvoltage is applied, potential VB at point B, potential VA at point A, and overcurrent detection signal OCP.

[0016] The terminal protection circuits of the VCC, IS, VFO, UIN, VIN and WIN terminals of the low-voltage side control circuit LV-IC use MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) that connect the gate to the source, and Zener diodes are used in the terminal protection circuits of the TEMP and CFO terminals. Figure 5The circuit shown illustrates an example of the circuitry surrounding the IS and CFO terminals. Furthermore, Figure 6 An example of the configuration of the GND terminal, IS terminal, CFO terminal, VFO terminal, and UIN terminal on a semiconductor chip is shown.

[0017] exist Figure 5 In the circuit shown, the IS terminal is connected to the non-inverting input of the comparator COMP_IS via a protection resistor R1 for current limiting, and a threshold voltage VthIS is applied to the inverting input of the comparator COMP_IS. The threshold voltage VthIS is obtained by dividing the voltage Vreg generated in the low-voltage side control circuit LV-IC using voltage divider resistors Rd1 and Rd2. The comparator COMP_IS, together with the voltage divider resistors Rd1 and Rd2, constitutes an overcurrent detection circuit that outputs a level H overcurrent detection signal OCP when the current of power switches Q2, Q4, and Q6 is greater than the current equivalent to the threshold voltage VthIS.

[0018] A terminal protection circuit consisting of transistors MN1 and MP1 is provided at point A, where the protection resistor R1 is connected to the non-inverting input of the comparator COMP_IS. Transistor MN1 is an N-channel MOSFET with its drain connected to point A and its gate and source connected to point B of the chip peripheral ground wiring 11. It should be noted that the diode PD1 connected to the drain and source of transistor MN1 is a parasitic diode of transistor MN1. Transistor MP1 is a P-channel MOSFET with its drain connected to point A and its gate and source connected to the VCC terminal of the low-voltage side control circuit LV-IC. Although not shown, transistor MP1 also has a parasitic diode. Although not shown, a terminal protection circuit consisting of MOSFETs for electrostatic discharge protection is connected to the VCC terminal.

[0019] When a positive overvoltage exceeding the voltage of the VCC terminal is applied to the IS terminal, the overvoltage, after passing through the protection resistor R1, is supplied to the VCC terminal via the parasitic diode of transistor MP1, and is clamped to a predetermined voltage by the terminal protection circuit of the VCC terminal. Therefore, the voltage at point A is limited to the voltage obtained by adding the forward voltage of the parasitic diode of transistor MP1 to the clamping voltage of the terminal protection circuit of the VCC terminal.

[0020] Furthermore, when a negative overvoltage is applied to the IS terminal, a current path is formed from point B through the parasitic diode of transistor MN1 and the protection resistor R1 to the IS terminal. At this time, the voltage at point A is limited to the voltage obtained by applying the forward voltage of the parasitic diode of transistor MN1 to the potential at point B.

[0021] The CFO terminal of the low-voltage side control circuit LV-IC is connected to the cathode of Zener diode ZD1. The anode of Zener diode ZD1 is connected to point C, which is farther from the GND terminal than point B of the chip's peripheral ground wiring 11. Furthermore, the CFO terminal is connected to the output terminal of the pulse width setting circuit that sets the minimum output width of the fault signal. In the illustrated example, the pulse width setting circuit includes transistors MP11 and MP12, resistors R11 and R12, and transistor MN11. The drain and gate of transistor MP11 are connected to a constant current generation circuit (not shown), and the source of transistor MP11 is connected to the power supply line Vdd. The source of transistor MP12 is connected to the power supply line Vdd, the gate of transistor MP12 is connected to the drain and gate of transistor MP11, and the drain of transistor MP12 is connected to one terminal of resistor R11. The other terminal of resistor R11 is connected to one terminal of resistor R12, the CFO terminal voltage measurement circuit, and the drain of transistor MN11 used for discharge control. The other terminal of resistor R12 is connected to the CFO terminal.

[0022] Here, if an overvoltage is applied to the CFO terminal, the overvoltage is clamped by the breakdown voltage of the Zener diode ZD1. Therefore, the pulse width setting circuit connected to the CFO terminal will not apply a voltage higher than the breakdown voltage of the Zener diode ZD1.

[0023] The chip peripheral ground wiring 11 has a wiring resistance Rg1 between point B and the GND terminal, a wiring resistance Rg2 between point C and point B, and a wiring resistance Rg3 on the opposite side of the GND terminal relative to point C.

[0024] The chip's peripheral ground wiring is as follows: 11 Figure 6 As shown, a pad 13 for a GND terminal is formed on a portion of the semiconductor chip 12 arranged along the outer periphery of the low-voltage side control circuit LV-IC. Inside the outer periphery ground wiring 11 arranged along the upper edge of the figure, pads 14 for a TEMP terminal, 15 for an IS terminal, 16 for a CFO terminal, 17 for a VFO terminal, and 18 for a UIN terminal are also arranged.

[0025] A Zener diode serving as a terminal protection circuit, connected to the output terminal (TEMP terminal) of the overheat protection circuit, is formed in the protection circuit region 14a under the pad 14 of the TEMP terminal. Similarly, a Zener diode ZD1 serving as a terminal protection circuit, connected to the CFO terminal, is formed in the protection circuit region 16a under the pad 16 of the CFO terminal, and a transistor serving as a terminal protection circuit, connected to the UIN terminal, is formed in a protection circuit region 18a of the pad 18 of the UIN terminal.

[0026] Transistors MN1 and MP1, serving as terminal protection circuits connected to the IS terminal of the overcurrent detection circuit, are formed in the protection circuit region 15a. Inside the protection circuit region 15a of the semiconductor chip 12, a threshold voltage generation circuit region 15b is disposed to generate the threshold voltage VthIS for the overcurrent detection circuit. Voltage divider resistors Rd1 and Rd2 are formed in the threshold voltage generation circuit region 15b. One terminal of voltage divider resistor Rd1 is connected to the voltage Vreg line, and one terminal of voltage divider resistor Rd2 is connected to the chip ground wiring 11a extending from the pad 13. The threshold voltage VthIS is output from the other terminal of voltage divider resistors Rd1 and Rd2.

[0027] The chip peripheral ground wiring 11 has a point B near the transistor MN1 that is connected to the source of the transistor MN1, and a point C near the pad 16 that is connected to the anode of the Zener diode ZD1.

[0028] Based on the above-described overcurrent detection circuit, looking at the chip's outer peripheral ground wiring 11 from the pad 13 of the GND terminal, there is a point C connected to the anode of the Zener diode ZD1 of the terminal protection circuit, located further away than point B, which is connected to the source of the transistor MN1 in the terminal protection circuit. Therefore, if an overvoltage is applied to the pad 16 of the CFO terminal (in... Figure 7 In the case where the width Tw is a pulse-shaped overvoltage noise of 1 microsecond (μs), a current Ip flows through the Zener diode ZD1, and this current Ip flows through the chip peripheral ground wiring 11 to the pad 13 of the GND terminal.

[0029] At this time, due to the large current Ip flowing through the wiring resistance Rg1 between point B and the pad 13 of the GND terminal, the potential VB at point B rises. If the potential VB at point B becomes higher than the forward voltage of the parasitic diode of transistor MN1, the parasitic diode of transistor MN1 conducts, and current flows backward from point B of the outer peripheral ground wiring 11 to point A, which is connected to the drain of transistor MN1, causing the potential VA at point A to rise. The threshold voltage VthIS for the overcurrent detection circuit is generated based on the potential of the inner ground wiring 11a, which is different from the outer peripheral ground wiring 11, and is not affected by the potential rise at point B; therefore, it remains at the same value. Therefore, if the potential VA at point A exceeds the threshold voltage VthIS, the comparator COMP_IS outputs an H-level overcurrent detection signal OCP. If the comparator COMP_IS outputs an H-level overcurrent detection signal OCP, this output is self-held, and the low-voltage side control circuit LV-IC forcibly shuts down all its outputs; therefore, as an overcurrent detection circuit, a malfunction occurs.

[0030] Here, if the overcurrent detection signal OCP is temporarily output, the transistor MN11 of the pulse width setting circuit is turned off, but the transistors MP11 and MP12 of the current mirror circuit remain on, so the capacitor Cfo connected to the CFO terminal begins to charge, and the voltage V_CFO at the CFO terminal rises.

[0031] Therefore, in an overcurrent detection circuit, when the voltage at the overcurrent detection input terminal rises due to the intrusion of overvoltage noise, in order to prevent the overcurrent detection circuit from malfunctioning, the threshold voltage VthIS is sometimes changed simultaneously (for example, see Patent Document 1).

[0032] Existing technical documents

[0033] Patent documents

[0034] Patent Document 1: Japanese Patent Application Publication No. 2013-062721 Summary of the Invention

[0035] Technical issues

[0036] However, since the technology described in Patent Document 1 is configured such that the threshold of the comparator for detecting overcurrent varies according to the average load current, the AC variation of the load current, and the magnitude of the power supply voltage, there is a problem that it cannot keep up with transient interference such as noise.

[0037] The present invention was made in view of this, and its purpose is to provide a drive device to prevent the overcurrent detection circuit from malfunctioning due to the voltage of the overcurrent detection input terminal rising because of a large current flowing through the ground wiring on the outer periphery of the chip.

[0038] Technical solution

[0039] In order to solve the above-mentioned problems, one embodiment of the present invention provides a driving device comprising: a chip peripheral ground wiring connected to a GND terminal, i.e., a first pad, in a semiconductor chip; and an overcurrent detection circuit having an input terminal, i.e., a second pad, for receiving an overcurrent detection signal, a threshold voltage generation circuit for generating a threshold voltage, a comparator for comparing the overcurrent detection signal with the threshold voltage, and a first input protection element connected between the input terminal and a first position on the chip peripheral ground wiring. The overcurrent detection circuit of the drive device includes a potential offset element connected between the terminal of the comparator receiving the threshold voltage and the first position of the chip peripheral ground wiring. The potential offset element offsets the threshold voltage applied to the comparator according to the potential of the first position. The first input protection element and the potential offset element are N-channel MOSFETs with their gate and source connected to the first position of the chip peripheral ground wiring. The drain of the first input protection element is connected to the third position, and the drain of the potential offset element is connected to the inverting input terminal of the comparator. The third position is located on the wiring that connects the protection resistor to the non-inverting input terminal of the comparator. The inverting input terminal of the comparator is connected to the threshold voltage generation circuit.

[0040] Technical effect

[0041] The driving device described above has the following advantages: even if the potential of the first position of the chip's outer peripheral ground wiring rises due to the application of overvoltage to other terminals, the comparator will not malfunction due to the application of overvoltage because both input terminals of the comparator are affected by the same potential rise. Attached Figure Description

[0042] Figure 1 This is a circuit diagram illustrating an example of a terminal protection circuit having a low-voltage side control circuit according to an embodiment of the present invention.

[0043] Figure 2 This is a diagram showing an example of the configuration on a semiconductor chip for a low-voltage side control circuit.

[0044] Figure 3 This is a diagram showing the operating waveform of the terminal protection circuit when an overvoltage is applied.

[0045] Figure 4 This is a diagram showing an example of the configuration of a typical motor drive device.

[0046] Figure 5 This is a circuit diagram illustrating an example of a terminal protection circuit for a low-voltage side control circuit.

[0047] Figure 6 This is a diagram showing an example of the configuration on a semiconductor chip for a low-voltage side control circuit.

[0048] Figure 7 This is a diagram showing the operating waveform of the terminal protection circuit when an overvoltage is applied.

[0049] Symbol Explanation

[0050] 11: Chip peripheral grounding wiring

[0051] 11a: Internal grounding wiring of the chip

[0052] 12: Semiconductor chips

[0053] 13, 14: Padding

[0054] 14a: Protection Circuit Area

[0055] 15: Padding

[0056] 15a: Protection Circuit Area

[0057] 15b: Threshold voltage generation circuit area

[0058] 16: Padding

[0059] 16a: Protection Circuit Area

[0060] 17, 18: Padding

[0061] 18a: Protection Circuit Area

[0062] 19: Control Circuit Area

[0063] COMP_IS: Comparator

[0064] MN1, MN2, MP1, MN11, MP11, MP12: Transistors

[0065] PD1, PD2: Diodes

[0066] R1: Protection resistor

[0067] R11, R12: Resistors

[0068] Rd1, Rd2: Voltage divider resistors

[0069] Rg1, Rg2, Rg3: Wiring resistance

[0070] ZD1: Zener diode Detailed Implementation

[0071] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings, taking as an example an overcurrent detection circuit applied to a low-voltage side control circuit having a pad located away from the GND terminal along the ground wiring on the outer periphery of the chip. It should be noted that in the following description, the description of the low-voltage side control circuit and the IPM including the low-voltage side control circuit will refer to... Figure 4 and for use in illustrating prior art Figure 5 as well as Figure 6 The same constituent elements shown in the diagram are described using the same symbols.

[0072] Figure 1 This is a circuit diagram illustrating an example of a terminal protection circuit having a low-voltage side control circuit according to an embodiment of the present invention. Figure 2 This is a diagram illustrating an example of the configuration on a semiconductor chip for a low-voltage side control circuit. Figure 3 This is a diagram showing the operating waveforms of the terminal protection circuit when an overvoltage is applied. It should be noted that... Figure 3 The following data is shown from top to bottom: the voltage V_CFO at the CFO terminal, the current Ip flowing into the CFO terminal when an overvoltage is applied, the potential VB at point B, the potential VA at point A, and the overcurrent detection signal OCP.

[0073] exist Figure 1 The image shows a portion of the overcurrent detection circuit with an IS terminal and the pulse width setting circuit with a CFO terminal, which are part of the low-voltage side control circuit LV-IC. Furthermore, in... Figure 2 The diagram shows the arrangement of pad 13 (first pad) for the GND terminal, pad 15 (second pad) for the IS terminal, and pad 16 (third pad) for the CFO terminal in this order along the outer periphery ground wiring 11 of the semiconductor chip 12 of the low voltage side control circuit LV-IC.

[0074] like Figure 1 As shown, the overcurrent detection circuit includes an IS terminal, a protection resistor R1 for current limiting, a transistor MN1 constituting a first input protection element, a transistor MP1 constituting a second input protection element, a comparator COMP_IS, voltage divider resistors Rd1 and Rd2 for generating a threshold voltage, and a transistor MN2 constituting a potential offset element. The IS terminal of the overcurrent detection circuit is connected to the non-inverting input of the comparator COMP_IS via the protection resistor R1 for current limiting, and a threshold voltage VthIS is applied to the inverting input of the comparator COMP_IS. The threshold voltage VthIS is generated by a threshold voltage generation circuit having voltage divider resistors Rd1 and Rd2. Here, one terminal of voltage divider resistor Rd1 is connected to the line of the voltage Vreg generated in the low-voltage side control circuit LV-IC, and the other terminal of voltage divider resistor Rd1 is connected to one terminal of voltage divider resistor Rd2. The other terminal of voltage divider resistor Rd2 is connected to the GND terminal via an internal ground wiring 11a, which is different from the external ground wiring 11 of the chip. Therefore, the threshold voltage VthIS is generated by dividing the voltage Vreg using voltage divider resistors Rd1 and Rd2.

[0075] A terminal protection circuit with transistors MN1 and MP1 is provided at point A on the wiring connecting the protection resistor R1 to the non-inverting input of the comparator COMP_IS. Transistor MN1 is an N-channel MOSFET with its drain connected to point A and its gate and source connected to point B (position 1) on pad 13 (first pad) in the outer peripheral ground wiring 11, away from the GND terminal. It should be noted that the diode PD1 connected to the drain and source of transistor MN1 is a parasitic diode of transistor MN1. Transistor MP1 is a P-channel MOSFET with its drain connected to point A and its gate and source connected to the power line connected to the VCC terminal of the low-voltage side control circuit LV-IC. Although not shown, transistor MP1 also has a parasitic diode.

[0076] The inverting input of the comparator COMP_IS, to which a threshold voltage VthIS is applied, is also connected to a potential offset element consisting of a transistor MN2, which is an N-channel MOSFET. The drain of transistor MN2 is connected to the inverting input of comparator COMP_IS, and the gate and source of transistor MN2 are connected to point B of the chip peripheral ground wiring 11, which is connected to the gate and source of transistor MN1 in the terminal protection circuit. Diode PD2, connected to the drain and source of transistor MN2, is a parasitic diode of transistor MN2. Therefore, the threshold voltage VthIS applied to the inverting input of comparator COMP_IS is offset according to the potential at point B of the chip peripheral ground wiring 11. It should be noted that transistors MN1 and MN2 use transistors with the same structure and characteristics.

[0077] On the other hand, the CFO terminal connected to the capacitor Cfo is connected to the cathode of the Zener diode ZD1, which constitutes the third input protection element. The anode of the Zener diode ZD1 is connected to point C, which is further away from the GND terminal (the second position) than point B of the chip peripheral ground wiring 11.

[0078] The CFO terminal is also connected to the output of at least transistors MP11 and MP12, resistors R11 and R12, a CFO terminal voltage measurement circuit, and a pulse width setting circuit for transistor MN11. Transistors MP11 and MP12 have their sources connected to the power supply Vdd line, and the gate and drain of transistor MP11 are connected to the gate of transistor MP12 to form a current mirror circuit for constant current charging of capacitor Cfo. The drain of transistor MP12 is connected to one terminal of resistor R11, the other terminal of resistor R11 is connected to one terminal of resistor R12, the CFO terminal voltage measurement circuit, and the drain of transistor MN11 for discharge control, and the other terminal of resistor R12 is connected to the CFO terminal. The source of transistor MN11 is connected to ground.

[0079] like Figure 2 As shown, the chip peripheral grounding wiring 11 is disposed on the outer periphery of the semiconductor chip 12 of the low-voltage side control circuit LV-IC. On the left side of the figure, a pad 13 with a GND terminal is formed adjacent to the chip peripheral grounding wiring 11. In the configuration example shown, control circuit area 19, protection circuit area 14a, protection circuit area 15a, threshold voltage generation circuit area 15b, protection circuit area 16a, and protection circuit area 18a are disposed inside the chip peripheral grounding wiring 11.

[0080] In protection circuit region 14a, a pad 14 with a TEMP terminal is formed at the top, and a Zener diode serving as a terminal protection circuit is formed at the bottom. In protection circuit region 15a, a pad 15 with an IS terminal, transistors MN1 and MP1 serving as terminal protection circuits, and transistor MN2 serving as a potential offset element are formed at the top. In threshold voltage generation circuit region 15b, voltage divider resistors Rd1 and Rd2 constituting a threshold voltage generation circuit are formed. In protection circuit region 16a, a pad 16 with a CFO terminal is formed at the top, and a Zener diode ZD1 serving as a terminal protection circuit is formed at the bottom. In protection circuit region 18a, a pad 18 with a UIN terminal and a transistor serving as a terminal protection circuit (not shown) are formed at the top.

[0081] Since the chip peripheral ground wiring 11 is disposed on the outer periphery of the semiconductor chip 12, point B, which is connected to the gate and source of transistors MN1 and MN2, is located away from the GND terminal on pad 13. Therefore, a wiring resistance Rg1 exists between pad 13 and point B at the GND terminal of the chip peripheral ground wiring 11. Furthermore, the anode of the Zener diode ZD1 formed in the protection circuit region 16a is connected to point C, which is farther from point B when viewed from pad 13 at the GND terminal. Therefore, a wiring resistance Rg2 exists between point B and point C of the chip peripheral ground wiring 11. It should be noted that... Figure 1 In the diagram, the chip peripheral ground wiring 11, which is farther from point C than point C, is shown as wiring resistor Rg3, viewed from the pad 13 of the GND terminal.

[0082] In the low-voltage side control circuit LV-IC configured above, for example, assuming that a pressure is applied to the pad 16 at the CFO terminal as shown above... Figure 3The overvoltage noise is illustrated. In the illustrated example, the overvoltage noise is set as a pulsed voltage V_CFO with a width Tw of 1 μs. If such an overvoltage is applied to the CFO terminal, and this overvoltage is higher than the breakdown voltage of the Zener diode ZD1, the current Ip flows through the Zener diode ZD1 and the wiring resistors Rg2 and Rg1 of the chip peripheral ground wiring 11 to the pad 13 of the GND terminal. At this time, a voltage drop caused by the current Ip is generated in the wiring resistor Rg1, causing the potential VB at point B of the chip peripheral ground wiring 11 to rise. If the potential VB at point B exceeds the voltage (e.g., 0.7V) obtained by applying the forward voltage of the parasitic diode PD1 of transistor MN1 to the threshold voltage VthIS (0.5 volts (V) in the illustrated example) (1.2V), the potential VA at point A rises to above 0.5V. At this point, since the parasitic diodes of transistor MN2, namely diode PD2 and diode PD1, are also conducting, the threshold voltage VthIS (=0.5V) also rises above 0.5V. It should be noted that by setting the voltage divider resistors Rd1 and Rd2, which generate the threshold voltage VthIS, to high resistance values ​​of tens of kilohms (kΩ), the current flowing through diode PD2 to the voltage divider resistors Rd1 and Rd2 is very small; therefore, the threshold voltage VthIS itself does not change significantly.

[0083] Thus, if an overvoltage is applied to the CFO terminal, causing the potential VB at point B to rise, both inputs of the comparator COMP_IS will rise to above 0.5V. At this time, since point A is connected to the IS terminal via the protection resistor R1, its voltage rise is delayed compared to the voltage rise at the input terminal with the applied threshold voltage VthIS due to the capacitance of the terminal and / or the capacitance of the externally connected RC filter (resistor Rn, capacitor Cn). Therefore, because the voltage at the input terminal with the applied threshold voltage VthIS is higher than the potential VA at point A, the comparator COMP_IS will not falsely detect the overcurrent and will not output an overcurrent detection signal OCP at level H.

[0084] Furthermore, when an overvoltage is applied to the CFO terminal, if the potential VB at point B of the chip's peripheral ground wiring 11 is less than 1.2V, although the threshold voltage VthIS remains unchanged, the potential VA at point A only rises to less than 0.5V. Therefore, since the potential VA at point A will not become higher than the threshold voltage VthIS, the comparator COMP_IS will not malfunction.

[0085] According to the overcurrent detection circuit equipped with a potential offset element consisting of transistor MN2, when the potential VB at point B of the chip peripheral ground wiring 11 rises and the potential VA at point A of the IS terminal rises compared to the threshold voltage VthIS, the same effect is applied to the threshold voltage VthIS. Therefore, false detection of overcurrent can be prevented when an overvoltage such as the rise of the potential VB at point B of the chip peripheral ground wiring 11 is applied, and the overvoltage noise tolerance of the drive device can be improved.

[0086] Furthermore, since the chip peripheral grounding wiring 11 does not require increasing its width and thickness to reduce wiring resistance, it can suppress the reduction of the wiring area by narrowing the width, and thus reduce chip cost.

[0087] In the above embodiment, since the terminal protection circuit as the CFO terminal can use a Zener diode buried under the pad instead of an input protection resistor that limits the input current, the component area of ​​the terminal protection circuit can be reduced and the chip cost can be lowered.

[0088] Furthermore, while it is preferable to position terminals that handle signals with small detection voltages, such as the IS terminal, as close as possible to the GND terminal, the limitations of terminal placement can be mitigated by incorporating a potential offset element.

[0089] It should be noted that in this embodiment, the potential shifting element is constituted by an N-channel transistor MN2. However, the potential shifting element is not limited to an N-channel transistor MN2, and can also be constituted by a diode or Zener diode with its anode connected to point B on the chip's peripheral ground wiring 11. In this case, in order to match the characteristics of the potential shifting element with those of the element located between points A and B, it is preferable that transistor MN1 is also constituted by a diode or Zener diode.

Claims

1. A driving device, characterized in that, have: The chip's peripheral ground wiring is connected to the first pad, which serves as the GND terminal in the semiconductor chip; and An overcurrent detection circuit includes a second pad serving as an input terminal for receiving an overcurrent detection signal, a threshold voltage generation circuit for generating a threshold voltage, a comparator for comparing the overcurrent detection signal with the threshold voltage, and a first input protection element connected between the input terminal and a first position on the chip's peripheral ground wiring. The overcurrent detection circuit includes a potential offset element connected between the terminal of the comparator that receives the threshold voltage and the first position of the chip's peripheral ground wiring, and offsetting the threshold voltage applied to the comparator according to the potential of the first position. The first input protection element and the potential offset element are N-channel MOSFETs with their gate and source connected to the first location of the chip's peripheral ground wiring. The drain of the first input protection element is connected to the third position, and the drain of the potential offset element is connected to the inverting input of the comparator. The third position is located on the wiring that connects the protection resistor to the non-inverting input of the comparator. The inverting input of the comparator is connected to the threshold voltage generation circuit.

2. The driving device according to claim 1, characterized in that, The overcurrent detection circuit has a second input protection element between the terminal of the comparator that receives the overcurrent detection signal and the power supply.

3. The driving device according to claim 2, characterized in that, The second input protection element is a P-channel MOSFET with its gate and source connected to the power supply and its drain connected to the third location.

4. The driving device according to claim 1, characterized in that, The drive device includes a third input protection element connected between a third pad and a second position of the chip peripheral ground wiring. The third pad is positioned further away from the first pad than the second pad, and the second position of the chip peripheral ground wiring is positioned further away from the first pad than the first position.

5. The driving device according to claim 4, characterized in that, The third input protection element is a Zener diode whose anode is connected to the second position of the chip's outer peripheral ground wiring and whose cathode is connected to the capacitor.

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