Provides information to the host system about the elasticity status of the memory subsystem's controller memory buffers

Abstract

An indication of a capacity of a CMB elastic buffer and an indication of a throughput of one or more memory components associated with the CMB elastic buffer may be received. An amount of time for data at the CMB elastic buffer to be transferred to the one or more memory components may be determined based on the capacity of the CMB elastic buffer and the throughput of the one or more memory components. Write data may be transferred from a host system to the CMB elastic buffer based on the determined amount of time for data at the CMB elastic buffer to be transferred to the one or more memory components.

Description

Technical Field

[0001] The present disclosure relates generally to memory subsystems, and more particularly, to providing information of a controller memory buffer (CMB) elasticity status of an elastic buffer in a memory subsystem to a host system. Background Art

[0002] The memory subsystem may be a storage system, such as a solid state drive (SSD) or a hard disk drive (HDD). The memory subsystem may be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is shown.

[0005] Figure 2 is a flow chart of an example method for transferring write data based on information of a CMB elastic buffer according to some embodiments.

[0006] Figure 3 A CMB elastic buffer according to some embodiments of the present disclosure is shown.

[0007] Figure 4 is a flow chart of an example method of providing information of a CMB elastic buffer according to some embodiments of the present disclosure.

[0008] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0009] Aspects of the present disclosure relate to providing information of a CMB elastic buffer of a memory subsystem to a host system. A memory subsystem is also referred to as a "memory device" hereinafter. An example of a memory subsystem is a storage device coupled to a central processing unit (CPU) through a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module coupled to a CPU via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), non-volatile dual in-line memory modules (NVDIMMs), and the like. A memory subsystem may be a hybrid memory / storage subsystem. Typically, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem, and may request to retrieve data from the memory subsystem.

[0010] In a conventional memory subsystem, a host system may provide a write operation to store data at the memory subsystem. The write operation may be transmitted from the host system to a buffer memory of the memory subsystem. For example, the buffer memory may store data for multiple write operations to be stored at a memory component of the memory subsystem. The memory subsystem may then retrieve data from the buffer memory and transmit the retrieved data to be stored at the memory component. For example, the memory subsystem may retrieve a portion of the accumulated write operations from the buffer memory and may transmit the corresponding write data to be stored in the memory component.

[0011] A conventional memory subsystem may receive a write operation from a host system via a first interface and may transmit the write operation from a buffer memory to a memory component via a second interface. For example, a host system may transmit a write operation to a memory subsystem via a peripheral component interconnect express (PCIe) interface for storage at a buffer memory. The memory subsystem may then transmit the write data from the buffer memory to the memory component via a different second interface, such as a non-volatile memory express (NVMe) interface. Thus, a differential interface may be used to receive data from a host system and store the data at one or more memory components.

[0012] If the interface of the host system for transmitting write operations to the memory subsystem is faster than the interface of the memory subsystem for transmitting write data to the memory component, the accumulation of write operations (issued by the host system) at the memory subsystem may exceed the ability of the memory subsystem to transmit and store the write data at the memory component of the memory subsystem. For example, the host system may transmit the write operation to the memory subsystem through the PCIe interface at a faster rate than the rate at which the memory subsystem stores the write data of the write operation at the memory component using the NVMe interface. Therefore, over time, the buffer memory of the memory subsystem may receive more write operations than the write operations that the memory subsystem can write at the memory component. Subsequently, if the buffer memory becomes full and there is no further capacity to store the write data (i.e., data from the write operation), the interface (e.g., PCIe interface) between the host system and the memory subsystem may become congested. When the write operation from the host system can no longer be stored in the buffer memory of the memory subsystem due to the buffer memory being full of previously received write data, the PCIe interface may be considered congested. Due to interface congestion, other buffers or memories of the host system are then required to store the write operations to be issued by the host system. For a memory that is slower than the host and is 2 to 3 times larger than the maximum transaction layer packet (TLP) size of the PCI interface that the PCIe interface can absorb before an acknowledgement is issued, the host system may attempt repeated memory write retries through the PCIe interface. These repeated retries significantly reduce the transfer efficiency of the host system burst transfers that are 2 to 3 times larger than the maximum TLP size.

[0013] Aspects of the present disclosure address the above and other deficiencies by providing information of a CMB elastic buffer of a memory subsystem to a host system. The CMB elastic buffer may be a buffer or a memory component contained in a memory subsystem. The CMB elastic buffer may be external to a controller of the memory subsystem and may be directly accessed by the host system. For example, the host system may access certain data of the CMB elastic buffer without requesting the data from the controller of the memory subsystem. In addition, the CMB elastic buffer may store write operations from the host system that have been transmitted over a PCIe interface. The stored write operations may then be executed from the CMB elastic buffer to store the data at the memory component by retrieving the data from the CMB elastic buffer and transmitting the data from the CMB elastic buffer to the memory component via an NVMe interface.

[0014] The memory subsystem may disclose or provide one or more characteristics or information of the CMB elastic buffer to the host system. The host system may then use the one or more characteristics of the provided CMB elastic buffer to determine when to transmit subsequent write operations through the PCIe interface between the host system and the memory subsystem. For example, the one or more characteristics may specify the size or capacity of the CMB elastic buffer and the write throughput of the CMB storage area. The size or capacity may specify the number of write operations or the amount of write data that can be stored at the CMB elastic buffer. The write throughput of the CMB storage area may specify the number of write operations or the amount of write data that can be transmitted from the CMB elastic buffer to store data at the CMB storage area component within a specific time period. For example, the write throughput may specify the amount of write data or the number of write operations that can be transmitted through the NVMe interface within a defined time period (i.e., the bandwidth of the NVMe interface).

[0015] The size or capacity of the CMB elastic buffer and the write throughput of the CMB storage area component can be provided or disclosed to the host system. For example, the characteristics of the CMB elastic buffer and the CMB storage area component can be stored at a memory element (i.e., a register) that is directly accessible to the host system. Subsequently, the host system can calculate or determine the amount of time required for a write operation to be retrieved from the CMB elastic buffer and stored at the CMB storage area component. For example, the amount of time determined by the host system can specify the amount of time required for a set of write operations to be stored in the CMB elastic buffer and completely deleted from the CMB elastic buffer after being submitted for storage at the CMB storage area component of the memory subsystem (e.g., a burst of write operations from the host system via a PCIe interface). Therefore, the host system can receive information about the CMB elastic state and can determine the amount of time for a write operation to be submitted and stored at the memory component via the NVMe interface.

[0016] The host system may utilize the amount of time to determine when to issue the next set of write operations to the memory subsystem via the PCIe interface. For example, the host system may transmit the write operations to the memory subsystem via the PCIe interface based on the amount of time determined for the write operations to be transmitted from the CMB elastic buffer to the memory component via the NVMe interface. Therefore, since the host system may issue write operations to the memory subsystem based on the rate at which other write operations are removed from the CMB elastic buffer, the available capacity of the CMB elastic buffer may store the write data to be issued by the host system. As a result, congestion of the PCIe interface may be prevented because the host system will not issue write operations if the CMB elastic buffer does not have available capacity to store the write operations.

[0017] Advantages of the present disclosure include, but are not limited to, preventing congestion at an interface (e.g., PCIe) between a host system and a memory subsystem. Prevention of congestion can improve the overall performance of the memory subsystem. For example, if the capacity of the CMB elastic buffer is 256KB, and the CMB storage throughput is 2GB / s, the host system can write up to 64x 4KB transfers, wait for a period of time (e.g., 256KB divided by 2GB / s = 125ms), and then poll the memory subsystem to determine whether the write data from the host system has been committed to the CMB. If so, the host system can write another array of write data.

[0018] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is shown. The memory subsystem 110 may include media, such as memory components 112A to 112N. The memory components 112A to 112N may be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. In general, the computing environment 100 may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0019] The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110, so that the host system 120 may read data from the memory subsystem 110 or write data to the memory subsystem. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0020] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND type flash memory. Each of memory components 112A to 112N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more data bits (e.g., data blocks) used by the host system 120. Although non-volatile memory components such as NAND type flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), a cross-point array of non-volatile memory cells, or other storage class memory (SCM). The cross-point array of non-volatile memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform write-in-place operations, where non-volatile memory cells may be programmed without pre-erasing the non-volatile memory cells. Furthermore, the memory cells of memory components 112A to 112N may be grouped into memory pages or data blocks, which may refer to cells of a memory component used to store data.

[0021] The memory system controller 115 (hereinafter referred to as the "controller") can communicate with the memory components 112A to 112N to perform operations, such as reading data, writing data, or erasing data at the memory components 112A to 112N, and other such operations. The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110 (including handling communications between the memory subsystem 110 and the host system 120). In some embodiments, the local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the controller 115, but may rely on external control (e.g., external control provided by an external host or by a processor or controller separate from the memory subsystem).

[0022] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory components 112A to 112N. The controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory components 112A to 112N, and convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0023] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a fast cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory components 112A to 112N.

[0024] The memory subsystem 110 includes a CMB 114 and a CMB elastic buffer component 113, which can provide information of the CMB elastic buffer to the host system 120. In some embodiments, the controller 115 includes at least a portion of the CMB elastic buffer component 113. For example, the controller 115 can include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the CMB elastic buffer component 113 is part of the host system 120, an application or an operating system, or is external to the controller 115. For example, the CMB elastic buffer component 113 can be a memory component coupled between the host system 120 and the controller 115 within the memory subsystem 110.

[0025] The CMB elastic buffer component 113 may provide information of the CMB elastic buffer to the host system 120. The information may specify the capacity of the CMB elastic buffer used by the CMB and the write throughput of the CMB storage area. As used herein, the CMB storage area may refer to one or more memory components used to store data present at the CMB elastic buffer. For example, the memory components 112A to 112N may be memory components of the CMB storage area. In some embodiments, the memory components 112A to 112N may be dynamic random access memory (DRAM) or storage class memory (SCM). The host system 120 may further include a write transmitter component 121, which may receive information and determine the amount of time to transmit multiple groups of write operations to the memory subsystem 110. Further details on the operation of the CMB elastic buffer component 113 and the write transmitter component 121 are described below.

[0026] Figure 2 2 is a flow chart of an example method 200 for writing data based on information transmission of a CMB elastic buffer according to some embodiments. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1The write transmitter component 121 of the embodiment is executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0027] like Figure 2 As shown, at operation 210, the processing logic receives an indication of the capacity of the CMB elastic buffer. At operation 220, the processing logic receives an indication of the throughput of the CMB storage area. The throughput of the CMB storage area can be the throughput of one or more memory components of the CMB storage area. The indication can be received when the host system is about to store data at the memory subsystem. For example, the host system can issue a write operation to store data at the memory subsystem. The host system can be coupled to the memory subsystem via a PCIe interface. The host system can retrieve the capacity and throughput indication of the CMB elastic state from one or more memory elements (e.g., registers) of the CMB elastic buffer. For example, the host system can directly access (e.g., without using a controller) a memory element that stores the capacity and throughput indication of the CMB elastic state. In some embodiments, the indication can be received when the host system initially detects the memory subsystem via a PCIe interface. The indication can be received via a PCI interface.

[0028] At operation 230, processing logic determines an amount of time for data at the CMB elastic buffer to be transferred from the CMB elastic buffer based on the capacity and the throughput. In some embodiments, the amount of time may be an unload timeout calculation that informs the host system of the reserve capacity of the CMB elastic buffer. For example, the host system may calculate an amount of time to transfer data and remove data from the CMB elastic buffer based on a combination of the CMB elastic buffer capacity and the CMB storage area throughput. The determined amount of time may be the capacity of the CMB elastic buffer divided by the throughput of the CMB storage area. In some embodiments, the host system may issue a write operation through a PCIe interface based on previous write data transferred to the CMB elastic buffer, the previous write data being removed from the CMB elastic buffer and submitted for storage in one or more CMB storage area components.

[0029] In some embodiments, the host system may transmit or issue an initial number of write operations based on the capacity of the CMB elastic buffer. For example, the number of write operations initially issued or transmitted by the host system may satisfy or fill the capacity of the CMB elastic buffer. For example, the amount of write data of the initial number of write operations may fill the capacity of the CMB elastic buffer. When the write data is committed by the memory subsystem, the write data initially transmitted or issued by the host system may be removed from the CMB elastic buffer. When the write data has been retrieved or removed from the CMB elastic buffer and is to be or is being written or refreshed to the CMB storage area component of the memory subsystem, the write data may be considered committed.

[0030] At operation 240, processing logic transmits write data to the CMB elastic buffer based on the determined amount of time. After the determined amount of time has passed, the host system may issue or transmit a write operation to the CMB elastic buffer. For example, the host system may issue or transmit a write operation after the determined amount of time has passed since a previous write operation was issued or transmitted to the CMB elastic buffer. Thus, a first group (i.e., a burst) of write operations may be issued or transmitted from the host system. Then, after the determined amount of time has passed, the host system may issue or transmit a second group (i.e., another burst) of write operations. Thus, the host system may periodically transmit the next group of write operations when the determined amount of time has passed.

[0031] In some embodiments, the host system may perform a polling operation on the CMB elastic buffer after a determined amount of time has passed, and may issue a subsequent set of write operations based on the results of the polling operation. For example, the polling operation may be a retrieval of data or a status indicator stored at a specific memory element (e.g., a register) of the CMB elastic buffer. The specific register may store a status indicator of a previous set of write data transmitted from the host system to the memory subsystem (e.g., via a PCIe interface). The status indicator may identify whether a previous set of write data (i.e., a previous burst) from a write operation has been submitted and stored in the memory component via an interface (e.g., an NVMe interface) between the CMB elastic buffer and the memory component. In some embodiments, the status indicator may further indicate whether the write data has been stored without error and is persistent (e.g., stored at the memory component). If the status indicator identifies that the write data of the previous set of write operations has been submitted, the host system may continue to transmit the next set of write operations to the memory subsystem via the PCIe interface. Otherwise, if the status indicator identifies that the previous set of write operations has not been submitted, the host system may wait for the next set of write operations to be transmitted via the PCIe interface. For example, the host system can pause or stop transmitting write operations for a threshold amount of time until the next polling operation of a particular register is performed. The polling operation can be used to ensure that the write data previously transmitted by the host system has been successfully stored at the memory component before the host system transmits subsequent write data.

[0032] Figure 3 FIG. 3 shows a CMB elastic buffer 300 according to some embodiments of the present disclosure. In some embodiments, the CMB elastic buffer 300 may correspond to Figure 1 The CMB elastic buffer component 113 of the controller 115.

[0033] like Figure 3 As shown, the CMB elastic buffer 300 can store write data 301. For example, the host system can transmit the write data 301 to the CMB elastic buffer 300 of the memory subsystem via the first interface 310 (e.g., a PCIe interface). When the host system transmits or issues a write operation through the first interface 310, the CMB elastic buffer 300 can store the write data 301. The write data 301 stored at the CMB elastic buffer 300 can be removed and transmitted through the second interface 311 (e.g., an NVMe interface) to be stored at one or more memory components of the memory subsystem. For example, when the corresponding write operation is submitted or transmitted through the second interface 311, the write data 301 can be removed from the CMB elastic buffer 300.

[0034] The CMB elastic buffer 300 may include additional memory elements 320 and 330. The memory elements 320 and 330 may be part of the CMB elastic buffer 300, or may be additional registers or other such memory components coupled to the CMB elastic buffer 300. The memory element 320 may store an indication of the capacity of the CMB elastic buffer 300, and the memory element 330 may store an indication of the throughput of write data 301 from the CMB elastic buffer 300 to the CMB storage area component through the second interface 311.

[0035] In some embodiments, memory element 320 and memory element 330 may store predefined or specified values ​​of the CMB elastic buffer capacity and the throughput of CMB storage area component 300. For example, the predefined or specified values ​​may be programmed or stored at memory elements 320 and 330 when the memory subsystem is manufactured. Memory elements 320 and 330 may be read-only registers. In some embodiments, the memory subsystem may store values ​​at memory elements 320 and 330. For example, the memory subsystem may detect the capacity and throughput of CMB elastic buffer 300, and may store the detected values ​​at memory elements 320 and 330. In some embodiments, if the memory subsystem detects that the capacity or throughput of CMB elastic buffer 300 has changed, the memory subsystem may update the values ​​to new values. For example, if a portion of CMB storage area component 300 can no longer store write data, or if the throughput via second interface 311 changes, the values ​​may be updated. Memory elements 320 and 330 may be accessed by a host system without requesting the data stored at memory elements 320 and 330 from a controller of the memory subsystem. For example, memory elements 320 and 33 may be directly accessible by a host system.

[0036] Figure 4 4 is a flow chart of an example method 400 for providing information of a CMB elastic buffer according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The CMB elastic buffer component 113 is executed. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0037] like Figure 4 As shown, at operation 410, processing logic provides an indication of the capacity of the CMB elastic buffer to the host system. For example, a register or other such memory element may be accessible by the host system. The register or memory element may store a value indicating the capacity of the CMB elastic buffer. The capacity may indicate the maximum number of write operations or the maximum amount of write data that can be stored at the CMB elastic buffer at a particular time. At operation 420, processing logic provides an indication of the throughput of one or more CMB storage area components to the host system. For example, the same or another register or memory element may be made accessible and may store a value indicating the throughput of the memory component of the CMB storage area.

[0038] At operation 430, processing logic receives data from a host system via a first interface based on the throughput of one or more CMB storage area components and the capacity of the CMB elastic buffer. The capacity and throughput may indicate a CMB elastic state. For example, write data to be stored at a CMB elastic buffer may be received from a PCIe interface at a rate based on the capacity and throughput of the CMB elastic state. In some embodiments, the rate may be the amount of time that write data stored at a CMB elastic buffer at full capacity may be fully transmitted and removed from the CMB elastic buffer when the write data is committed at the memory component. Data received from a host system via a first interface may be stored at the CMB elastic buffer. At operation 440, processing logic transmits data from a CMB elastic buffer via a second interface based on the throughput of one or more CMB storage area components. For example, a certain amount of write data may be transmitted at a rate defined by the throughput.

[0039] At operation 450, the processing logic stores the transmitted data at one or more CMB storage area components. For example, the write data transmitted from the CMB elastic buffer can be stored at a memory component of the memory subsystem. The write data can be stored in the memory component after being transmitted through the second interface.

[0040] Thus, the CMB elastic buffer can store write data received from the host system via the first interface, and can transfer the stored write data to one or more memory components via the second interface. The rate at which data is transferred via the first interface can exceed the rate at which data is transferred via the second interface. For example, a memory component utilizing the second interface can utilize a greater amount of time to store data than the host system can transfer data via the first interface. Characteristics of the CMB elastic state (e.g., capacity and throughput) can be provided to the host system to control when the host system transfers subsequent write data to the CMB elastic buffer.

[0041] Figure 5An example machine of a computer system 500 is shown in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 A host system (eg, a memory subsystem 110) of Figure 1 host system 120) or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0042] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, a digital or non-digital circuit, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be performed by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0043] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0044] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 502 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 that communicates through a network 520.

[0045] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, with the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0046] In one embodiment, instructions 526 include instructions for implementing a method corresponding to a write transmitter component or a CMB elastic buffer component (eg, Figure 1 The machine-readable storage medium 524 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more methods of the present disclosure. The term "computer-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0047] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. In this document, and generally, an algorithm is conceived to be a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0048] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0049] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including a floppy disk, an optical disk, a CD-ROM, and a magnetic optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic or optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0050] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0051] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0052] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method of operating a memory system, the method comprising: receiving, by a processing device of the host system, from a controller memory buffer CMB elastic buffer, an indication of a capacity of the CMB elastic buffer; receiving, by the processing device, from the CMB elasticity buffer an indication of a throughput of one or more memory components associated with the CMB elasticity buffer; determining, by the processing device, an amount of time for data at the CMB elasticity buffer to be transferred to the one or more memory components based on the capacity of the CMB elasticity buffer and the throughput of the one or more memory components; as well as Write data is transferred from the host system to the CMB elastic buffer based on the amount of time for data at the CMB elastic buffer to be transferred to the one or more memory components.

2. The method of claim 1 , wherein the transferring of the write data from the host system to the CMB elastic buffer is performed via a first interface, and the transferring of the data at the CMB elastic buffer to the one or more memory components is performed via a second interface different from the first interface.

3. The method of claim 2, wherein the first interface is a Peripheral Component Interconnect Express (PCIe) interface or a Non-Volatile Memory Express (NVMe) interface coupling the host system with a memory subsystem including the CMB elastic buffer and the one or more memory components, and the second interface is a memory bus interface coupling the CMB elastic buffer with the one or more memory components.

4. The method of claim 2, wherein the first interface is associated with a higher throughput than the throughput of the one or more memory components based on the second interface.

5. The method of claim 1 , wherein transferring the write data from the host system to the CMB elastic buffer based on the amount of time comprises: The write data is transferred from the host system to the CMB elastic buffer after the amount of time has elapsed since a previous write data was transferred from the host system to the CMB elastic buffer.

6. The method of claim 1 , wherein transferring the write data from the host system to the CMB elastic buffer based on the amount of time comprises: A polling operation is performed to identify a status of previous write data that has been transferred from the host system to the CMB elastic buffer after the amount of time has elapsed since the previous write data was transferred from the host system to the CMB elastic buffer, wherein subsequent write data is transferred from the host system to the CMB elastic buffer in response to the status indicating that the previous write data has been transferred to the one or more memory components.

7. The method of claim 1 , wherein receiving the indication of the capacity and the indication of the throughput of the one or more memory components comprises: The indication of the capacity and the indication of the throughput are retrieved from one or more memory elements associated with a CMB storage area of ​​the CMB elastic buffer.

8. A memory system comprising: Memory components; a controller storage buffer, a CMB elastic buffer, coupled to a host system via a first interface and coupled to the memory component via a second interface, wherein the CMB elastic buffer is associated with one or more memory elements that store an indication of a capacity of the CMB elastic buffer and an indication of a throughput of a CMB storage region corresponding to the memory component, wherein the one or more memory elements are accessed by the host system via the first interface; A processing device operatively coupled to the memory component to perform the following operations: receiving data from the host system through the first interface based on the capacity of the CMB elastic buffer and the throughput of the CMB storage area; storing the data in the CMB elastic buffer; as well as Based on the throughput of the CMB storage area, the data is transferred from the CMB elastic buffer through the second interface to be stored at the memory component of the CMB storage area.

9. The memory system of claim 8, wherein the first interface is a Peripheral Component Interconnect Express (PCIe) interface, and wherein the second interface is a Non-Volatile Memory Express (NVMe) interface.

10. The memory system of claim 8, wherein the first interface is associated with a higher throughput than the throughput of the CMB elastic buffer through the first interface.

11. The memory system of claim 8, wherein the one or more memory elements correspond to one or more read-only registers accessible to the host system through the first interface.

12. The memory system according to claim 8, wherein the processing device further performs the following operations: In response to transferring the data from the CMB elastic buffer through the second interface, updating a status of the data, wherein the status indicates whether the data has been removed from the CMB elastic buffer and is to be stored at the memory component.

13. The memory system of claim 8, wherein the capacity of the CMB elastic buffer corresponds to an amount of write data from the host system that can be stored at the CMB elastic buffer.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device of a host system, cause the processing device to perform operations comprising: receiving, from a controller memory buffer CMB elastic buffer, an indication of a capacity of the CMB elastic buffer; receiving, from the CMB elasticity buffer, an indication of a throughput of one or more memory components associated with the CMB elasticity buffer; determining an amount of time for data at the CMB elasticity buffer to be transferred to the one or more memory components based on the capacity of the CMB elasticity buffer and the throughput of the one or more memory components; as well as Write data is transferred from the host system to the CMB elastic buffer based on the amount of time for data at the CMB elastic buffer to be transferred to the one or more memory components.

15. The non-transitory computer-readable storage medium of claim 14, wherein the transferring of the write data from the host system to the CMB elastic buffer is performed via a first interface, and the transferring of the data at the CMB elastic buffer to the one or more memory components is performed via a second interface different from the first interface.

16. The non-transitory computer-readable storage medium of claim 15, wherein the first interface is a Peripheral Component Interconnect Express (PCIe) interface coupling the host system with a memory subsystem including the CMB elastic buffer and the one or more memory components, and the second interface is a Non-Volatile Memory Express (NVMe) interface coupling the CMB elastic buffer with the one or more memory components.

17. The non-transitory computer-readable storage medium of claim 15, wherein the first interface is associated with a higher throughput than the throughput of the one or more memory components based on the second interface.

18. The non-transitory computer-readable storage medium of claim 14, wherein to transfer the write data from the host system to the CMB elastic buffer based on the amount of time, the operations further comprise: The write data is transferred from the host system to the CMB elastic buffer after the amount of time has elapsed since a previous write data was transferred from the host system to the CMB elastic buffer.

19. The non-transitory computer-readable storage medium of claim 14, wherein to transfer the write data from the host system to the CMB elastic buffer based on the amount of time, the operations further comprise: A polling operation is performed to identify a status of previous write data that has been transferred from the host system to the CMB elastic buffer after the amount of time has elapsed since the previous write data was transferred from the host system to the CMB elastic buffer, wherein subsequent write data is transferred from the host system to the CMB elastic buffer in response to the status indicating that the previous write data has been transferred to the one or more memory components.

20. The non-transitory computer-readable storage medium of claim 14, wherein to receive the indication of the capacity and the indication of the throughput of the one or more memory components, the operations further comprise: The indication of the capacity and the indication of the throughput are retrieved from one or more memory elements associated with a CMB storage area of ​​the CMB elastic buffer.

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