Method and apparatus for error correction of differential triangle set product convolutional codes

Abstract

Methods, devices, systems, architectures and interfaces for encoding / decoding QD-DTS-PrCC are provided. The decoding method comprises: determining the number k of input bits included in a first transmission of a data stream TS and a first bit of the input bits included in the first transmission in the data stream; determining a number of coded bit blocks (EBBs), each of the EBBs comprising any number of data blocks of a previously transmitted transport segment (TS) of the data stream, each of the data blocks having k TS bits; selecting the number of EBBs for encoding the transmitted QD‑DTS‑PrCC component codeword (QDCC) according to a DTS indexing method for indexing a plurality of EBBs; generating a QD‑DTS‑PrCC component codeword (QDCC) including a TS, a virtual segment (VS) and a c parity bits of the QDCC, wherein the dimension of the QD‑DTS‑PrCC is at least 2; and extracting the calculated TS of the QDCC to an output EBB.

Description

Technical Field

[0001] The present invention relates to the field of communications, and more particularly to methods, devices, systems, architectures and interfaces for communications in advanced or next generation wireless communication systems, including communications using new radio and / or new radio (NR) access technologies and communication systems. Background Art

[0002] Designing error correction codes (e.g., product codes, multiplication convolutional codes, etc.) for ultra-high-speed communications can be challenging due to requirements including: high data rates (e.g., greater than 500 Gb / s, and in some cases, greater than 400 Gb / s), low latency, redundancy, low power consumption, large coding gain, etc. Therefore, it is urgent to provide error correction codes that can address the above requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In the accompanying drawings, like reference numerals denote like elements, wherein:

[0004] Figure 1A is a system diagram illustrating an exemplary communication system in which one or more disclosed embodiments may be implemented;

[0005] Figure 1B is a diagram showing that according to an embodiment, Figure 1A A system diagram of an exemplary wireless transmit / receive unit (WTRU) for use within a communication system is shown;

[0006] Figure 1C is a diagram showing that according to an embodiment, Figure 1A A system diagram of an exemplary radio access network (RAN) and an exemplary core network (CN) used within the communication system shown;

[0007] Figure 1D is a diagram showing that according to an embodiment, Figure 1A A system diagram of another exemplary RAN and another exemplary CN used within the communication system shown;

[0008] Figure 2 is a diagram showing a communication system including QD-DTS-PrCC according to an embodiment;

[0009] Figure 3 is a diagram showing a QD-DTS-PrCC encoder according to an embodiment;

[0010] Figure 4 is a diagram showing an encoding stream according to an embodiment;

[0011] Figure 5 is a diagram showing a codeword format of a component code according to an embodiment;

[0012] Fig. 6A and 6B is a diagram showing bit control according to an embodiment;

[0013] Figure 7 is a diagram showing a codeword according to an embodiment;

[0014] Figure 8 is a diagram showing a method of encoding QD-DTS-PrCC according to an embodiment;

[0015] Fig. 9 is a diagram showing an index of a QD-DTS-PrCC according to an embodiment; and

[0016] Fig.10 and Fig.11 is a diagram showing simulation results of bit error rate (BER) performance of 3D-DTS-PrCC according to an embodiment. DETAILED DESCRIPTION

[0017] Figure 1A 1 is a diagram showing an exemplary communication system 100 in which one or more disclosed embodiments may be implemented. The communication system 100 may be a multiple access system that provides content such as voice, data, video, messaging, broadcast, etc. to multiple wireless users. The communication system 100 may enable multiple wireless users to access such content by sharing system resources including wireless bandwidth. For example, the communication system 100 may use one or more channel access methods such as code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), single carrier FDMA (SC-FDMA), zero tail unique word DFT-spread OFDM (ZT UW DTS-s OFDM), unique word OFDM (UW-OFDM), resource block filtered OFDM, and filter bank multi-carrier (FBMC), etc.

[0018] like Figure 1AAs shown, the communication system 100 may include wireless transmit / receive units (WTRUs) 102a, 102b, 102c, 102d, RAN 104 / 113, CN 106 / 115, public switched telephone network (PSTN) 108, Internet 110, and other networks 112, although it should be appreciated that the disclosed embodiments contemplate any number of WTRUs, base stations, networks, and / or network components. Each of the WTRUs 102a, 102b, 102c, 102d may be any type of device configured to operate and / or communicate in a wireless environment. By way of example, any of the WTRUs 102a, 102b, 102c, 102d may be referred to as a “station” and / or “STA”, which may be configured to transmit and / or receive wireless signals, and may include a user equipment (UE), a mobile station, a fixed or mobile subscriber unit, a subscription-based unit, a pager, a cellular phone, a personal digital assistant (PDA), a smart phone, a laptop, a netbook, a personal computer, a wireless sensor, a hotspot or Mi-Fi device, an Internet of Things (IoT) device, a watch or other wearable device, a head-mounted display (HMD), a vehicle, a drone, medical devices and applications (e.g., remote surgery), industrial devices and applications (e.g., robots and / or other wireless devices working in an industrial and / or automated process chain environment), consumer electronic devices, and devices working on a commercial and / or industrial wireless network, etc. Any of the WTRUs 102a, 102b, 102c, 102d may be interchangeably referred to as a UE.

[0019] The communication system 100 may also include a base station 114a and / or a base station 114b. Each of the base stations 114a, 114b may be any type of device configured to facilitate access to one or more communication networks (e.g., CN 106 / 115, Internet 110, and / or other networks 112) by wirelessly interfacing with at least one of the WTRUs 102a, 102b, 102c, 102d. For example, the base stations 114a, 114b may be a base transceiver station (BTS), a Node B, an eNode B, a Home Node B, a Home eNode B, a gNB, an NR Node B, a site controller, an access point (AP), a wireless router, and the like. Although each of the base stations 114a, 114b is depicted as a single component, it should be appreciated that the base stations 114a, 114b may include any number of interconnected base stations and / or network components.

[0020] The base station 114a may be part of the RAN 104 / 113, and the RAN may also include other base stations and / or network components (not shown), such as a base station controller (BSC), a radio network controller (RNC), a relay node, and the like. The base station 114a and / or the base station 114b may be configured to transmit and / or receive wireless signals on one or more carrier frequencies called cells (not shown). These frequencies may be in a licensed spectrum, an unlicensed spectrum, or a combination of licensed and unlicensed spectrum. A cell may provide wireless service coverage for a specific geographic area that is relatively fixed or may change over time. A cell may be further divided into cell sectors. For example, a cell associated with the base station 114a may be divided into three sectors. Thus, in one embodiment, the base station 114a may include three transceivers, that is, each transceiver corresponds to a sector of the cell. In an embodiment, the base station 114a may use multiple-input multiple-output (MIMO) technology and may use multiple transceivers for each sector of the cell. For example, by using beamforming, signals may be transmitted and / or received in a desired spatial direction.

[0021] The base stations 114a, 114b may communicate with one or more of the WTRUs 102a, 102b, 102c, 102d over an air interface 116, which may be any suitable wireless communication link (e.g., radio frequency (RF), microwave, centimeter wave, millimeter wave, infrared (IR), ultraviolet (UV), visible light, etc.). The air interface 116 may be established using any suitable radio access technology (RAT).

[0022] More specifically, as described above, the communication system 100 may be a multiple access system and may use one or more channel access schemes, such as CDMA, TDMA, FDMA, OFDMA, and SC-FDMA, among others. For example, the base station 114a in the RAN 104 / 113 and the WTRUs 102a, 102b, 102c may implement a radio technology such as Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access (UTRA), which may use Wideband CDMA (WCDMA) to establish the air interface 115 / 116 / 117. WCDMA may include communication protocols such as High Speed ​​Packet Access (HSPA) and / or Evolved HSPA (HSPA+). HSPA may include High Speed ​​Downlink (DL) Packet Access (HSDPA) and / or High Speed ​​UL Packet Access (HSUPA).

[0023] In an embodiment, the base station 114a and the WTRUs 102a, 102b, 102c may implement a radio technology such as Evolved UMTS Terrestrial Radio Access (E-UTRA), which may establish the air interface 116 using Long Term Evolution (LTE) and / or Advanced LTE (LTE-A) and / or Advanced LTE Pro (LTE-A Pro).

[0024] In an embodiment, the base station 114a and the WTRUs 102a, 102b, 102c may implement a radio technology that may use new radio (NR) to establish the air interface 116, such as NR radio access.

[0025] In an embodiment, the base station 114a and the WTRUs 102a, 102b, 102c may implement multiple radio access technologies. For example, the base station 114a and the WTRUs 102a, 102b, 102c may jointly implement LTE radio access and NR radio access (e.g., using dual connectivity (DC) principles). Thus, the air interface used by the WTRUs 102a, 102b, 102c may be characterized by multiple types of radio access technologies and / or transmissions sent to / from multiple types of base stations (e.g., eNBs and gNBs).

[0026] In other embodiments, the base station 114a and the WTRUs 102a, 102b, 102c may implement radio technologies such as IEEE 802.11 (i.e., Wireless Fidelity (WiFi)), IEEE 802.16 (Worldwide Interoperability for Microwave Access (WiMAX)), CDMA2000, CDMA2000 1X, CDMA2000EV-DO, Interim Standard 2000 (IS-2000), Interim Standard 95 (IS-95), Interim Standard 856 (IS-856), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), and GSM EDGE (GERAN), among others.

[0027] Figure 1AThe base station 114b in the example may be, for example, a wireless router, a Home NodeB, a Home eNodeB, or an access point, and may use any appropriate RAT to facilitate wireless connectivity in a local area, such as a business location, a residence, a vehicle, a campus, an industrial facility, an air corridor (e.g., for use by drones), a road, and the like. In one embodiment, the base station 114b and the WTRUs 102c, 102d may establish a wireless local area network (WLAN) by implementing a radio technology such as IEEE 802.11. In an embodiment, the base station 114b and the WTRUs 102c, 102d may establish a wireless personal area network (WPAN) by implementing a radio technology such as IEEE 802.15. In yet another embodiment, the base station 114b and the WTRUs 102c, 102d may establish a picocell or a femtocell by using a cellular-based RAT (e.g., WCDMA, CDMA2000, GSM, LTE, LTE-A, LTE-A Pro, NR, etc.). As Figure 1A As shown, the base station 114b may be directly connected to the Internet 110. Thus, the base station 114b does not need to access the Internet 110 via the CN 106 / 115.

[0028] The RAN 104 / 113 may be in communication with the CN 106 / 115, which may be any type of network configured to provide voice, data, applications, and / or Voice over Internet Protocol (VoIP) services to one or more of the WTRUs 102a, 102b, 102c, 102d. The data may have different quality of service (QoS) requirements, such as different throughput requirements, latency requirements, fault tolerance requirements, reliability requirements, data throughput requirements, mobility requirements, etc. The CN 106 / 115 may provide call control, billing services, mobile location-based services, prepaid calls, Internet connectivity, video distribution, etc., and / or may perform advanced security functions such as user authentication. Although in Figure 1A Although not shown, it will be appreciated that the RAN 104 / 113 and / or the CN 106 / 115 may be in direct or indirect communication with other RANs that employ the same RAT or a different RAT as the RAN 104 / 113. For example, in addition to being connected to the RAN 104 / 113 employing NR radio technology, the CN 106 / 115 may also be in communication with another RAN (not shown) employing GSM, UMTS, CDMA 2000, WiMAX, E-UTRA, or WiFi radio technology.

[0029] The CN 106 / 115 may also act as a gateway for the WTRUs 102a, 102b, 102c, 102d to access the PSTN 108, the Internet 110, and / or other networks 112. The PSTN 108 may include a circuit-switched telephone network that provides plain old telephone service (POTS). The Internet 110 may include a global system of interconnected computer network devices that use common communication protocols (e.g., TCP, User Datagram Protocol (UDP), and / or IP in the Transmission Control Protocol / Internet Protocol (TCP / IP) Internet Protocol Suite). The networks 112 may include wired or wireless communication networks owned and / or operated by other service providers. For example, the networks 112 may include another CN connected to one or more RANs, where the one or more RANs may use the same RAT or a different RAT as the RAN 104 / 113.

[0030] Some or all of the WTRUs 102a, 102b, 102c, 102d in the communication system 100 may include multi-mode capabilities (e.g., the WTRUs 102a, 102b, 102c, 102d may include multiple transceivers for communicating with different wireless networks over different wireless links). Figure 1A The illustrated WTRU 102c may be configured to communicate with the base station 114a, which may employ a cellular-based radio technology, and with the base station 114b, which may employ an IEEE 802 radio technology.

[0031] Figure 1B is a system diagram showing an exemplary WTRU 102. Figure 1B As shown, the WTRU 102 may include a processor 118, a transceiver 120, a transmit / receive element 122, a speaker / microphone 124, a numeric keypad 126, a display / touchpad 128, a non-removable memory 130, a removable memory 132, a power source 134, a global positioning system (GPS) chipset 136, and / or other peripherals 138. It should be appreciated that the WTRU 102 may include any sub-combination of the foregoing elements while remaining consistent with an embodiment.

[0032] The processor 118 may be a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), a state machine, and the like. The processor 118 may perform signal coding, data processing, power control, input / output processing, and / or any other functionality that enables the WTRU 102 to operate in a wireless environment. The processor 118 may be coupled to the transceiver 120, which may be coupled to the transmit / receive element 122. Although Figure 1B The processor 118 and the transceiver 120 are depicted as separate components, however it should be appreciated that the processor 118 and the transceiver 120 may also be integrated together in an electronic package or chip.

[0033] The transmit / receive component 122 may be configured to transmit or receive signals to or from a base station (e.g., base station 114a) via the air interface 116. For example, in one embodiment, the transmit / receive component 122 may be an antenna configured to transmit and / or receive RF signals. As an example, in another embodiment, the transmit / receive component 122 may be an emitter / detector configured to transmit and / or receive IR, UV, or visible light signals. In yet another embodiment, the transmit / receive component 122 may be configured to transmit and / or receive RF and light signals. It should be appreciated that the transmit / receive component 122 may be configured to transmit and / or receive any combination of wireless signals.

[0034] Although in Figure 1B 102 as a single component, but the WTRU 102 may include any number of transmit / receive components 122. More specifically, the WTRU 102 may employ MIMO technology. Thus, in one embodiment, the WTRU 102 may include two or more transmit / receive components 122 (e.g., multiple antennas) for transmitting and receiving wireless signals over the air interface 116.

[0035] The transceiver 120 may be configured to modulate signals to be transmitted by the transmit / receive component 122 and to demodulate signals received by the transmit / receive component 122. As described above, the WTRU 102 may have multi-mode capabilities. Thus, the transceiver 120 may include multiple transceivers that allow the WTRU 102 to communicate via multiple RATs (e.g., NR and IEEE 802.11).

[0036] The processor 118 of the WTRU 102 may be coupled to a speaker / microphone 124, a keypad 126, and / or a display / touchpad 128 (e.g., a liquid crystal display (LCD) display unit or an organic light emitting diode (OLED) display unit), and may receive user input data from these components. The processor 118 may also output user data to the speaker / microphone 124, the keypad 126, and / or the display / touchpad 128. In addition, the processor 118 may access information from and store information in any suitable memory such as a non-removable memory 130 and / or a removable memory 132. The non-removable memory 130 may include a random access memory (RAM), a read-only memory (ROM), a hard disk, or any other type of memory storage device. The removable memory 132 may include a subscriber identity module (SIM) card, a memory stick, a secure digital (SD) memory card, and the like. In other embodiments, the processor 118 may access information from, and store data in, memory that is not physically located on the WTRU 102, such as, for example, on a server or a home computer (not shown).

[0037] The processor 118 may receive power from the power source 134, and may be configured to distribute and / or control power for use by other components in the WTRU 102. The power source 134 may be any suitable device for powering the WTRU 102. For example, the power source 134 may include one or more dry cell batteries (e.g., nickel-cadmium (Ni-Cd), nickel-zinc (Ni-Zn), nickel-metal hydride (NiMH), lithium-ion (Li-ion), etc.), solar cells, fuel cells, and the like.

[0038] The processor 118 may also be coupled to the GPS chipset 136, which may be configured to provide location information (e.g., longitude and latitude) related to the current location of the WTRU 102. In addition to or in lieu of the information from the GPS chipset 136, the WTRU 102 may receive location information from a base station (e.g., base stations 114a, 114b) via the air interface 116 and / or determine its location based on the timing of signals received from two or more nearby base stations. It should be appreciated that the WTRU 102 may acquire location information via any suitable positioning method while remaining consistent with an embodiment.

[0039] The processor 118 may also be coupled to other peripheral devices 138, wherein the peripheral devices may include one or more software and / or hardware modules that provide additional features, functions, and / or wired or wireless connectivity. For example, the peripheral devices 138 may include an accelerometer, an electronic compass, a satellite transceiver, a digital camera (for photos and / or video), a universal serial bus (USB) port, a vibration device, a television transceiver, a hands-free headset, Modules, frequency modulation (FM) radio units, digital music players, media players, video game console modules, Internet browsers, virtual reality and / or augmented reality (VR / AR) devices, and activity trackers, etc. The peripheral device 138 may include one or more sensors, which may be one or more of the following: gyroscopes, accelerometers, Hall effect sensors, magnetometers, orientation sensors, proximity sensors, temperature sensors, time sensors, geographic location sensors, altimeters, light sensors, touch sensors, magnetometers, barometers, gesture sensors, biometric sensors, and / or humidity sensors, etc.

[0040] The WTRU 102 may include a full-duplex radio in which the reception or transmission of some or all signals (e.g., associated with specific subframes for UL (e.g., for transmission) and downlink (e.g., for reception)) may be concurrent and / or simultaneous for the radio. A full-duplex radio may include an interference management unit that reduces and / or substantially eliminates self-interference by means of hardware (e.g., chokes) or by signal processing by a processor (e.g., a separate processor (not shown) or by the processor 118). In an embodiment, the WTRU 102 may include a half-duplex radio that transmits and receives some or all signals (e.g., associated with specific subframes for UL (e.g., for transmission) or downlink (e.g., for reception)).

[0041] Figure 1C 1 is a system diagram showing the RAN 104 and the CN 106 according to an embodiment. As described above, the RAN 104 may communicate with the WTRUs 102a, 102b, 102c using an E-UTRA radio technology over the air interface 116. The RAN 104 may also be in communication with the CN 106.

[0042] The RAN 104 may include eNode-Bs 160a, 160b, 160c, however it will be appreciated that the RAN 104 may include any number of eNode-Bs while remaining consistent with an embodiment. The eNode-Bs 160a, 160b, 160c may each include one or more transceivers for communicating with the WTRUs 102a, 102b, 102c over the air interface 116. In one embodiment, the eNode-Bs 160a, 160b, 160c may implement MIMO technology. Thus, for example, the eNode-B 160a may use multiple antennas to transmit wireless signals to, and / or receive wireless signals from, the WTRU 102a.

[0043] Each of the eNodeBs 160a, 160b, 160c may be associated with a particular cell (not shown) and may be configured to handle radio resource management decisions, handover decisions, user scheduling in the UL and / or DL, etc. Figure 1C As shown, the eNode-Bs 160a, 160b, 160c may communicate with each other via an X2 interface.

[0044] Figure 1C The illustrated CN 106 may include a mobility management entity (MME) 162, a serving gateway (SGW) 164, and a packet data network (PDN) gateway (or PGW) 166. Although each of the aforementioned components are described as being part of the CN 106, it should be appreciated that any of these components may be owned and / or operated by an entity other than the CN operator.

[0045] The MME 162 may be connected to each of the eNode-Bs 160a, 160b, 160c in the RAN 104 via an S1 interface and may serve as a control node. For example, the MME 162 may be responsible for authenticating users of the WTRUs 102a, 102b, 102c, performing bearer activation / deactivation processing, selecting a particular serving gateway during an initial attach procedure for the WTRUs 102a, 102b, 102c, and the like. The MME 162 may provide a control plane function for switching between the RAN 104 and other RANs (not shown) that employ other radio technologies, such as GSM and / or WCDMA.

[0046] The SGW 164 may be connected to each of the eNode-Bs 160a, 160b, 160c in the RAN 104 via an S1 interface. The SGW 164 may generally route and forward user data packets to / from the WTRUs 102a, 102b, 102c. The SGW 164 may also perform other functions, such as anchoring the user plane during an inter-eNB handover, triggering paging processing when DL data is available for the WTRUs 102a, 102b, 102c, and managing and storing the contexts of the WTRUs 102a, 102b, 102c, and the like.

[0047] The SGW 164 may be connected to the PGW 146, which may provide the WTRUs 102a, 102b, 102c with access to packet-switched networks, such as the Internet 110, to facilitate communications between the WTRUs 102a, 102b, 102c and IP-enabled devices.

[0048] The CN 106 may facilitate communications with other networks. For example, the CN 106 may provide the WTRUs 102a, 102b, 102c with access to circuit-switched networks, such as the PSTN 108, to facilitate communications between the WTRUs 102a, 102b, 102c and traditional land-line communications devices. For example, the CN 106 may include or communicate with an IP gateway, such as an IP Multimedia Subsystem (IMS) server, and the IP gateway may serve as an interface between the CN 106 and the PSTN 108. In addition, the CN 106 may provide the WTRUs 102a, 102b, 102c with access to other networks 112, which may include other wired and / or wireless networks owned and / or operated by other service providers.

[0049] Although in Figures 1A-1D While the WTRU is described as a wireless terminal, it should be appreciated that in certain typical embodiments, such a terminal may use a (eg, temporary or permanent) wired communication interface with a communication network.

[0050] In a typical embodiment, the other network 112 may be a WLAN.

[0051] A WLAN using an infrastructure basic service set (BSS) mode may have an access point (AP) for the BSS and one or more stations (STAs) associated with the AP. The AP may access or be connected to a distributed system (DS) or other types of wired / wireless networks that send traffic into and / or out of the BSS. Traffic originating from outside the BSS and destined for the STA may arrive through the AP and be delivered to the STA. Traffic originating from the STA and destined for a destination outside the BSS may be sent to the AP for delivery to the corresponding destination. Traffic between STAs within the BSS may be sent through the AP, for example, when the source STA may send traffic to the AP and the AP may deliver traffic to the destination STA. Traffic between STAs within the BSS may be considered and / or referred to as point-to-point traffic. The point-to-point traffic may be sent between the source and destination STAs (e.g., directly therebetween) using a direct link setup (DLS). In certain typical embodiments, the DLS may use 802.11e DLS or 802.11z channelized DLS (TDLS)). For example, a WLAN using an independent BSS (IBSS) mode does not have an AP, and STAs (e.g., all STAs) within or using the IBSS can communicate directly with each other. Here, the IBSS communication mode may sometimes be referred to as an "ad-hoc" communication mode.

[0052] When using the 802.11ac infrastructure mode of operation or a similar mode of operation, the AP may transmit a beacon on a fixed channel (e.g., a primary channel). The primary channel may have a fixed width (e.g., a bandwidth of 20 MHz) or a width that is dynamically set via signaling. The primary channel may be a working channel of the BSS and may be used by STAs to establish a connection with the AP. In certain typical embodiments, carrier sense multiple access (CSMA / CA) with collision avoidance (e.g., in an 802.11 system) may be implemented. For CSMA / CA, STAs (e.g., each STA) including the AP may sense the primary channel. If a particular STA senses / detects and / or determines that the primary channel is busy, the particular STA may back off. In a specified BSS, one STA (e.g., only one station) transmits at any given time.

[0053] A high throughput (HT) STA may communicate using a 40 MHz wide channel (eg, by combining a 20 MHz wide primary channel with a 20 MHz wide adjacent or non-adjacent channel to form a 40 MHz wide channel).

[0054] Very high throughput (VHT) STA can support channels with widths of 20MHz, 40MHz, 80MHz and / or 160MHz. 40MHz and / or 80MHz channels can be formed by combining continuous 20MHz channels. A 160MHz channel can be formed by combining 8 continuous 20MHz channels or by combining two discontinuous 80MHz channels (this combination can be referred to as an 80+80 configuration). For the 80+80 configuration, after channel coding, the data can be passed and passed through a fragment parser, which can separate the data into two streams. Inverse Fast Fourier Transform (IFFT) processing and time domain processing can be performed separately on each stream. The stream can be mapped on two 80MHz channels, and the data can be transmitted by the STA performing the transmission. At the receiver of the STA performing the reception, the above operations for the 80+80 configuration can be reversed, and the combined data can be sent to the medium access control (MAC).

[0055] 802.11af and 802.11ah support working modes below 1 GHz. Compared with 802.11n and 802.11ac, the channel working bandwidth and carrier used in 802.11af and 802.11ah are reduced. 802.11af supports 5MHz, 10MHz and 20MHz bandwidths in the TV White Space (TVWS) spectrum, and 802.11ah supports 1MHz, 2MHz, 4MHz, 8MHz and 16MHz bandwidths using non-TVWS spectrum. According to a typical embodiment, 802.11ah can support instrument type control / machine type communication (e.g., MTC devices in macro coverage areas). MTC devices can have certain capabilities, such as limited capabilities including support (e.g., only support) certain and / or limited bandwidths. MTC devices can include a battery, and the battery life of the battery is higher than a threshold (e.g., for maintaining a very long battery life).

[0056] For WLAN systems that can support multiple channels and channel bandwidths (e.g., 802.11n, 802.11ac, 802.11af, and 802.11ah), these systems include channels that can be designated as primary channels. The bandwidth of the primary channel can be equal to the maximum common operating bandwidth supported by all STAs in the BSS. The bandwidth of the primary channel can be set and / or limited by a certain STA, where the STA originates from all STAs operating in the BSS that supports the minimum bandwidth operating mode. In the example of 802.11ah, even if the AP and other STAs in the BSS support 2MHz, 4MHz, 8MHz, 16MHz and / or other channel bandwidth operating modes, for STAs (e.g., MTC-type devices) that support (e.g., only support) 1MHz mode, the width of the primary channel can be 1MHz. Carrier sensing and / or network allocation vector (NAV) settings can depend on the state of the primary channel. If the primary channel is busy (eg, because a STA (which only supports 1 MHz operating mode) is transmitting to the AP), then the entire available frequency band may be considered busy even though most of the available frequency band remains idle and available for use.

[0057] In the United States, the available frequency band for 802.11ah is 902MHz to 928MHz. In South Korea, the available frequency band is 917.5MHz to 923.5MHz. In Japan, the available frequency band is 916.5MHz to 927.5MHz. Depending on the country code, the total bandwidth available for 802.11ah is 6MHz to 26MHz.

[0058] Figure 1D 1 is a system diagram showing the RAN 113 and the CN 115 according to an embodiment. As described above, the RAN 113 may communicate with the WTRUs 102a, 102b, 102c using NR radio technology over the air interface 116. The RAN 113 may also communicate with the CN 115.

[0059] The RAN 113 may include gNBs 180a, 180b, 180c, though it will be appreciated that the RAN 113 may include any number of gNBs while remaining consistent with an embodiment. The gNBs 180a, 180b, 180c may each include one or more transceivers to communicate with the WTRUs 102a, 102b, 102c over the air interface 116. In one embodiment, the gNBs 180a, 180b, 180c may implement MIMO technology. For example, the gNBs 180a, 180b may use beamforming processing to transmit and / or receive signals to and / or from the gNBs 180a, 180b, 180c. Thus, for example, the gNB 180a may use multiple antennas to transmit wireless signals to the WTRU 102a and receive wireless signals from the WTRU 102a. In an embodiment, the gNBs 180a, 180b, 180c may implement carrier aggregation technology. For example, gNB 180a may transmit multiple component carriers to WTRU 102a (not shown). A subset of these component carriers may be on an unlicensed spectrum, while the remaining component carriers may be on a licensed spectrum. In an embodiment, gNBs 180a, 180b, 180c may implement coordinated multi-point (CoMP) technology. For example, WTRU 102a may receive coordinated transmissions from gNB 180a and gNB 180b (and / or gNB 180c).

[0060] The WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c using transmissions associated with a scalable digital configuration. For example, the OFDM symbol spacing and / or OFDM subcarrier spacing may be different for different transmissions, different cells, and / or different portions of the radio transmission spectrum. The WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c using subframes or transmission time intervals (TTIs) of different or scalable lengths (e.g., containing different numbers of OFDM symbols and / or lasting different absolute time lengths).

[0061] The gNBs 180a, 180b, 180c may be configured to communicate with the WTRUs 102a, 102b, 102c in a standalone configuration and / or a non-standalone configuration. In a standalone configuration, the WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c without accessing other RANs (e.g., the eNodeBs 160a, 160b, 160c). In a standalone configuration, the WTRUs 102a, 102b, 102c may use one or more of the gNBs 180a, 180b, 180c as mobility anchors. In a standalone configuration, the WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c using signals in an unlicensed band. In a non-standalone configuration, the WTRU 102a, 102b, 102c may communicate / connect to the gNB 180a, 180b, 180c while communicating / connecting to another RAN (e.g., the eNode-B 160a, 160b, 160c). For example, the WTRU 102a, 102b, 102c may communicate with one or more gNBs 180a, 180b, 180c and one or more eNode-Bs 160a, 160b, 160c in a substantially simultaneous manner by implementing the DC principle. In a non-standalone configuration, the eNode-B 160a, 160b, 160c may act as a mobility anchor for the WTRU 102a, 102b, 102c, and the gNB 180a, 180b, 180c may provide additional coverage and / or throughput to serve the WTRU 102a, 102b, 102c.

[0062] Each of the gNBs 180a, 180b, 180c may be associated with a particular cell (not shown) and may be configured to handle radio resource management decisions, handover decisions, user scheduling in UL and / or DL, support network slicing, dual connectivity, implement interworking between NR and E-UTRA, route user plane data to a user plane function (UPF) 184a, 184b, and route control plane information to an access and mobility management function (AMF) 182a, 182b, and the like. Figure 1D As shown, gNBs 180a, 180b, and 180c can communicate with each other through the Xn interface.

[0063] Figure 1DThe CN 115 shown may include at least one AMF 182a, 182b, at least one UPF 184a, 184b, at least one session management function (SMF) 183a, 183b, and may include a data network (DN) 185a, 185b. Although each of the aforementioned components is described as part of the CN 115, it should be understood that any of these components may be owned and / or operated by an entity other than the CN operator.

[0064] The AMF 182a, 182b may be connected to one or more of the gNBs 180a, 180b, 180c in the RAN 113 via the N2 interface and may act as a control node. For example, the AMF 182a, 182b may be responsible for authenticating users of the WTRU 102a, 102b, 102c, supporting network slicing (e.g., handling different PDU sessions with different requirements), selecting a specific SMF 183a, 183b, managing registration areas, terminating NAS signaling, and mobility management, etc. The AMF 182a, 182b may use network slicing processing to customize the CN support provided to the WTRU 102a, 102b, 102c based on the type of service being used by the WTRU 102a, 102b, 102c. As an example, different network slices may be established for different use cases, such as services relying on Ultra Reliable Low Latency (URLLC) access, services relying on enhanced massive mobile broadband (eMBB) access, and / or services for machine type communication (MTC) access, etc. The AMF 182 may provide a control plane function for switching between the RAN 113 and other RANs (not shown) using other radio technologies (e.g., LTE, LTE-A, LTE-A Pro, and / or non-3GPP access technologies such as WiFi).

[0065] The SMF 183a, 183b may be connected to the AMF 182a, 182b in the CN 115 via the N11 interface. The SMF 183a, 183b may also be connected to the UPF 184a, 184b in the CN 115 via the N4 interface. The SMF 183a, 183b may select and control the UPF 184a, 184b, and may configure traffic routing through the UPF 184a, 184b. The SMF 183a, 183b may perform other functions, such as managing and allocating UE IP addresses, managing PDU sessions, controlling policy enforcement and QoS, and providing downlink data notification, etc. The PDU session type may be IP-based, non-IP-based, Ethernet-based, etc.

[0066] The UPF 184a, 184b can be connected to one or more of the gNBs 180a, 180b, 180c in the RAN 113 via the N3 interface, which can provide the WTRUs 102a, 102b, 102c with access to packet-switched networks (e.g., the Internet 110) to facilitate communication between the WTRUs 102a, 102b, 102c and IP-enabled devices. The UPF 184a, 184b can perform other functions such as routing and forwarding packets, implementing user plane policies, supporting multi-host PDU sessions, processing user plane QoS, buffering downlink packets, and providing mobility anchor processing, etc.

[0067] The CN 115 may facilitate communications with other networks. For example, the CN 115 may include or may communicate with an IP gateway (e.g., an IP Multimedia Subsystem (IMS) server) that acts as an interface between the CN 115 and the PSTN 108. In addition, the CN 115 may provide the WTRUs 102a, 102b, 102c with access to other networks 112, which may include other wired and / or wireless networks owned and / or operated by other service providers. In one embodiment, the WTRUs 102a, 102b, 102c may be connected to the local data network (DN) 185a, 185b via an N3 interface connected to the UPF 184a, 184b and an N6 interface between the UPF 184a, 184b and the DN 185a, 185b and through the UPF 184a, 184b.

[0068] In view of Figures 1A-1D and about Figures 1A-1D In accordance with the corresponding description of the present invention, one or more or all functions described herein in comparison with one or more of the following may be performed by one or more simulation devices (not shown): WTRU 102a-d, base station 114a-b, eNodeB 160a-c, MME 162, SGW 164, PGW 166, gNB 180a-c, AMF 182a-b, UPF 184a-b, SMF 183a-b, DN185ab and / or one or more other devices described herein. These simulation devices may be one or more devices configured to simulate one or more or all functions described herein. For example, these simulation devices may be used to test other devices and / or simulate network and / or WTRU functions.

[0069] The simulation device can be designed to implement one or more tests about other devices in a laboratory environment and / or an operator network environment. For example, the one or more simulation devices can perform one or more or all functions while being implemented and / or deployed as part of a wired and / or wireless communication network in whole or in part to test other devices inside the communication network. The one or more simulation devices can perform one or more or all functions while being temporarily implemented / deployed as part of a wired and / or wireless communication network. The simulation device can be directly coupled to other devices to perform the test, and / or can use over-the-air wireless communication to perform the test.

[0070] One or more simulation devices can perform one or more functions, including all functions, while not being implemented / deployed as part of a wired and / or wireless communication network. For example, the simulation device can be used in a test lab and / or a test scenario of a wired and / or wireless communication network that is not deployed (e.g., tested) to implement tests on one or more components. The one or more simulation devices can be test devices. The simulation device can transmit and / or receive data using direct RF coupling and / or wireless communication with the aid of RF circuits (e.g., which can include one or more antennas). DETAILED DESCRIPTION

[0072] Product Convolutional Code

[0073] A convolutional code, which may be referred to and / or considered to be a type of product code, may be applied to (e.g., used, considered, etc. for) situations where very high-speed applications are used. For example, a new class of quasi-product codes (i.e., codes similar and / or analogous to product codes) has been proposed, such as Bose, Chaudhuri, and Hocquenghem (BCH) codes. These quasi-product codes may provide high coding gain, low decoding complexity, and high throughput.

[0074] Convolutional codes can be associated with code types or categories, such as two-dimensional staircase codes, continuously interleaved codes, and weaving codes, which can be used in the case of ultra-high-speed communications. Both staircase codes and continuously interleaved codes can use component block codes.

[0075] The minimum distance of the ladder code is equal to the product of the minimum distances of the component codes. The ladder code can provide better performance than many other continuously interleaved codes. The ladder code is used independently or, for example, in the case of the International Telecommunication Union (ITU) standard for ultra-high throughput systems, is used as an outer code for concatenated soft-decision forward error correction (FEC).

[0076] Continuously interleaved codes with hard-decision iterative decoding (e.g., BCH codes) can provide performance close to the capacity of binary symmetric channels. However, given the introduction of staircase codes, for example, because staircase codes have (e.g., generally, as a rule, etc.) better performance, practical and theoretical interest in such codes is decreasing.

[0077] As described above, a class of product convolutional codes includes weaving codes, which may also be referred to as weaving block codes, and which may be classified as two-dimensional class product codes. Weaving block codes may not achieve good bit error rate (BER) performance, and therefore, they may not be better than (e.g., compete with) staircase codes. For example, a weaving block code with a 6.25% overhead may provide a coding gain that is less than that of a staircase code and may have an error-floor.

[0078] Multidimensional block product codes (also referred to as Q-dimensional block product codes) have not generated as much practical and theoretical interest as 2-dimensional block product codes. As an example of why there is a lack of interest, in the case of conventional Q-dimensional block product codes, their code length n_c^Q grows exponentially with the increase of the dimension Q of the code, where n_c is the length of the component block code. There are investigations into low-rate (e.g., turbo) product codes with short component codes or single parity check codes. However, such short component codes or single parity check codes significantly limit the application areas of such low-rate (e.g., turbo) product codes and their coding gain. That is, for example, in order to provide appropriate coding gain in the case of small redundancy typical of ultra-high-speed systems, component codes of a certain length, such as 256 to 1000, should be used. However, the length of the multidimensional block product code is prohibitive for implementation in this case. In addition, multidimensional multi-product convolutional codes are not well represented or discussed in the field of channel coding.

[0079] With respect to developing (e.g., future, new, unconventional) FEC techniques, there is a need to develop error correction codes that can achieve high throughput (e.g., >500 Gbps, and / or >400 Gbps) given several different use case constraints including decoding complexity, power consumption, latency, and / or (e.g., appropriate) error correction performance. However, product and / or product-like convolutional codes (e.g., staircase codes, continuously interleaved codes, and weaving codes) have drawbacks, and these drawbacks may limit the applicability of such codes in practical telecommunication use cases, particularly in wireless systems.

[0080] For example, these disadvantages may include: (1) the minimum distance of the two-dimensional code is equal to the product of the minimum distances of the component codes; in the case of component codes with small minimum distances, the resulting minimum distance of the two-dimensional multiplication convolutional code may be insufficient to provide appropriate coding gain and the required error floor, and this constrains the use of two-dimensional codes with component codes with small minimum spacing; (2) ladder codes have high decoding complexity and power consumption, which may be prohibited for high-throughput systems; and (3) ladder codes provide limited code rate flexibility. The decoding delay of ladder codes may limit the use of ladder codes when there is a maximum allowed delay, and may limit the throughput of FEC. That is, ladder codes may include a large number of component block codes. For example, the implementation of iterative decoding of such a large number of component codes may require (e.g., require) a large number of component code decoders in proportion, resulting in prohibited decoding delays. Any decoding complexity or power consumption of ladder codes may be prohibited in the case of high-throughput systems because ladder codes may use (e.g., require, require, etc.) a large number of decoders for component block codes.

[0081] The complexity of the component code decoder can be a (e.g., dominant) factor in the (e.g., overall) decoding complexity. In addition, the power consumption of iterative decoding of staircase codes and the large number of complex (i.e., complicated) component code decoders may be prohibitive for high-throughput systems. In addition, as described above, staircase codes provide limited code rate flexibility. For example, in the case of a high-throughput system, an option (e.g., features, capabilities, flexibility, operational capabilities, parameters, etc.) for selecting a code rate may be required. In this case, encoding and decoding schemes with (e.g., supporting high) code rate flexibility can be (e.g., preferably) used, especially in the case of changing use cases of interest and in view of adapting to changes in the channel environment. However, staircase codes do not have or have limited ability (e.g., opportunity) to change the minimum distance, length, and rate of the code because, as a rule, they are generally significantly limited by the design constraints of these categories / types of codes. Q-Dimensional Difference Triangle Set (Difference Triangle Set) Product Convolutional Code

[0082] According to an embodiment, there may be a Q-dimensional differential triangle set (QD-DTS)-convolutional convolutional code (PrCC), which may be a (e.g., new) category and / or (e.g., new) type of convolutional convolutional code. According to an embodiment, QD-DTS-PrCC may (e.g., significantly) reduce decoding complexity and / or latency compared to other types of convolutional convolutional codes. According to various embodiments, QD-DTS-PrCC may provide pre-service and / or improved error correction performance. In addition, according to an embodiment, QD-DTS-PrCC may allow higher throughput and / or less decoding complexity for use cases of interest and associated constraints.

[0083] Encoder structure

[0084] Figure 2 is a diagram showing a communication system including QD-DTS-PrCC according to an embodiment.

[0085] refer to Figure 2 , the communication system 200 may include a data source 201 that provides data to be encoded. For example, an encoder 202 that provides and / or performs QD-DTS-PrCC encoding may encode the data and form an encoded stream (e.g., of the encoded data). The encoded stream may be sent by a transmitter 203 on a communication channel 204. A receiver 205 receives the stream via the channel, where the stream may generally (i.e., typically) be corrupted by noise and other sources (e.g., interference) in the communication channel 204. A decoder 206 that may provide QD-DTS-PrCC decoding decodes the received stream to recover the transmitted data and provides the data to a data pool 207.

[0086] Figure 3 is a diagram showing a QD-DTS-PrCC encoder according to an embodiment; and Figure 4 is a diagram showing an encoding stream according to an embodiment.

[0087] According to an embodiment, the QD-DTS-PrCC may be encoded by an encoder (eg, a systematic recursive convolutional encoder). Figure 3 , there may be an encoder 300 (eg, a universal encoder) for QD-DTS-PrCC, where k TS and n TS They represent the L of the component block code in QD-DTS-PrCC respectively. cw The encoder 300 may include any number L of data (eg, information) and coded bits at the input and output of each encoder 301. cw The encoder 301, the mapper 302 and the memory 303. The number of input data K and the number of output coded bits N of the QD-DTS-PrCC encoder can be calculated according to Formula 1 and Formula 2 respectively:

[0088] K=L cw k TS ……………[Formula 1]

[0089] N=L cw n TS ……………[Formula 2]

[0090] According to an embodiment, the system (n c ,k c ) block codes can be used as component codes of QD-DTS-PrCC, where n cand k c are the length and dimension of the component block code, respectively. According to an embodiment, it may be desirable (eg, preferred, required, etc.) to specify a certain integer n. TS , n c =2·n TS , where the integer n TS represents any one of the dimension of the code Q and the length of the transport segment (TS). According to an embodiment, the code rate R of the component block c It can be determined according to Formula 3:

[0091]

[0092] According to an embodiment, the number of parity bits r in each component codeword may be determined according to Formula 4. c :

[0093]

[0094] According to an embodiment, any and / or all solutions, embodiments and / or features disclosed herein for a class of QD-DTS (e.g., new, unconventional, etc.) multiplication convolutional codes (e.g., QD-DTS-PrCC) may be applied to any of binary and non-binary system component block codes.

[0095] refer to Figure 4 , the encoded bit stream can be Figure 3 At the output of encoder 300 (e.g., output by, stored at, available at, etc.). According to various embodiments, a block of bits of length N output by (e.g., at the output of) a QD-DTS-PrCC encoder such as encoder 300 may be a coded bit block (EBB). Hereinafter, EBBs may be interchangeably referred to as layers, such that the figures, disclosure, examples, etc. may be interchangeably referred to as EBBs and layers). According to an embodiment, each EBB may be composed of L cw Transport Segments (TS). Figure 4 And in the present disclosure, the same number (eg, index) is shown and referenced to indicate a TS in each layer and a component codeword used to generate the TS.

[0096] According to an embodiment, there may be a relationship between consecutive blocks (e.g., groups, units, sets, etc.) of K input data bits from a streaming data source and an output stream of EBBs. According to an embodiment, a QD-DTS-PrCC may be characterized (e.g., completely) by a relationship between consecutive blocks of K input data bits from a streaming data source and an output stream of EBBs. According to an embodiment, a memory of an encoder (e.g., of a QD-DTS-PrCC) may store, for example, m consecutive previously encoded EBBs to be used during an encoding process, where m is the maximal degree of a generator polynomial of the QD-DTS-PrCC. According to an embodiment, the m previously encoded EBBs stored in the memory may be initialized to a reference state, such as a known reference state of an encoder-decoder pair. For example, the m EBBs stored in the memory of the encoder may be initialized to an all-zero state.

[0097] According to an embodiment, a rule may (e.g., be used to) define a QD-DTS-PrCC. According to an embodiment, a mapper may map the QD-DTS-PrCC according to the rule defining the QD-DTS-PrCC. For example, such as Figure 3 The QD-DTS-PrCC mapper of the mapper 302 can fill (or in other words, map) bits of a previously encoded EBB stored in the encoder's memory into (e.g., appropriate, corresponding) bit positions of the codeword of the component code in the currently encoded EBB according to specific rules defining the QD-DTS-PrCC.

[0098] Figure 5 is a diagram showing a codeword format of a component code according to an embodiment.

[0099] refer to Figure 5 , the codeword of the component code can have n c bit length and can have r c parity bits. According to an embodiment, a codeword may have at least Q segments, which include a transmission segment (TS) 501 and a virtual segment (VS) 502. According to an embodiment, TS 501 and VS 502 (eg, of a codeword) may have the same length, for example, each having a length Where Q represents the dimension of QD-DTS-PrCC. According to an embodiment, TS 501 may be composed of (e.g., by mapping) The data bits and the use of k corresponding to (eg, component codewords) c =(n c -r c ) bit calculation r cAccording to various embodiments, the filling of TS 501 (e.g., mapping to the TS) may be performed (e.g., completed, executed, etc.) according to the encoding process of the component codes. According to an embodiment, VS 502 may not be sent (e.g., in the communication channel). According to an embodiment, the bits of VS 502 may be used for (e.g., only for) the r of TS. c Generation of parity bits.

[0100] According to an embodiment, the format of the codeword of the component code can define the code rate R of the QD-DTS-PrCC. According to an embodiment, the length N of the TS TS The code rate R of QD-DTS-PrCC can be calculated according to formulas 5A and 5B:

[0101]

[0102] According to an embodiment, the bit rate of the component code can (eg, by definition) be a positive number, and the code rate R c Can meet the conditions

[0103] According to an embodiment, bits from m previously encoded EBBs (e.g., EBBs of TSs stored in a memory of an encoder) may be mapped (e.g., used) by a mapper to fill (e.g., create) a VS of the codeword of the component code, e.g., as Figure 5 As shown. That is, according to an embodiment, each VS of a codeword of a component code may be filled with bits of a TS stored in a memory of a QD-DTS-PrCC encoder (e.g., by mapping to the VS). According to an embodiment, the TS of the codeword and the (Q-1) VSs may each represent a (e.g., specific) dimension of a QD-DTS-PrCC.

[0104] According to an embodiment, any features, operations, characteristics, methods, and elements of any of the codeword formats of the encoders, decoders, and component codes disclosed herein may be applied to and / or used for codes, such as any of continuous interleaved codes, staircase codes, and differential triangular set product convolutional codes. However, according to an embodiment, in the case where Q>2, and QD-DTS-PrCC may constitute a broad category of codes, QD-DTS-PrCC is multidimensional. That is, according to an embodiment, such codes (e.g., QD-DTS-PrCC) may be designed (e.g., specifically) according to their mappers and the memory of the encoder (e.g., its organization). According to an embodiment, the difference between such codes may be defined (e.g., indicated) by the number of EBBs stored in the memory of the encoder, and may also be defined by the rules of the mapper, which define which bit of which codeword should be selected from and which bit of which previously encoded EBB stored in the memory of the encoder when creating the VS of the codeword of the component code. According to an embodiment, the organization of the memory of the mapper and encoder may define the distance property of any of the code, complexity and latency of the encoding.

[0105] According to an embodiment, the component code encoder may encode (e.g., by mapping) the data intended for transmission into the EBB of the TS as an output of, for example, a (e.g., overall) QD-DTS-PrCC encoder. According to an embodiment, a rule for bit mapping (e.g., mapping, padding) may be used to generate the VS of the component codeword. That is, according to various embodiments, the QD-DTS-PrCC may encode the EBBs of the data stream (e.g., certain EBBs, each EBB, etc.) according to a rule. For example, in the case where the encoder of the component code encodes the k TS Data bits and (Q-1)n of previously encoded TS TS In the case where each TS is generated by encoding bits (which can be used to fill the VS of the code), this can be done using rules for bit mapping (e.g., filling) of the VS for generating component codewords. According to an embodiment, the rules for mapping (e.g., filling, creating, etc.) the VS bits of (e.g., each) codeword of a component code can (e.g., completely) define the QD-DTS-PrCC. That is, the rules describing how the mapper fills and / or creates the VS bits of the codewords of the component code can (e.g., completely) define the QD-DTS-PrCC.

[0106] According to an embodiment, the bit mapping rules may be as discussed below (e.g., as defined, as described, as provided, etc.). According to an embodiment, the QD-DTS-PrCC may be defined by a bit mapping of the VS (e.g., defined by establishing requirements for the bit mapping). According to an embodiment, the QD-DTS-PrCC may be constructed (e.g., constructed, designed, configured, etc.) such that each bit of the QD-DTS PrCC is protected by Q codewords of a component code, e.g., Fig. 6A According to the embodiment, considering Fig. 6A and 6B The bit control of the Q-dimensional product code shown in , can (e.g., should) provide orthogonality between the codewords that control the component codes of each bit. According to an embodiment, this orthogonality can be a (e.g., natural) property of a canonical block product code, where the orthogonality follows directly from the geometric construction of such a code. In the case of a convolutional code, some design rules can (e.g., should) be provided to provide (e.g., ensure) such orthogonality.

[0107] According to an embodiment, the rules (e.g., a complete set of rules) for designing QD-DTS-PrCC may be as given in Table 1. According to an embodiment, Fig. 6A As shown, each bit can be controlled by a Q orthogonal codeword, and the Q orthogonal codeword can be any of a two-dimensional code and a three-dimensional code. Figure 6B As shown, an improperly designed 3D code may be used for bit control. According to an embodiment, each marked bit may be controlled by Q non-orthogonal codewords, such as a length of n c =10 and d c =2 component single parity check code, for example, Figure 6B According to an embodiment, such a cascade may result in (eg, only) a min =3 code.

[0108] According to an embodiment, the rules for defining QD-DTS-PrCC may be as shown in Table 1.

[0109]

[0110] Table 1

[0111] According to an embodiment, for example, since the Q-layers of the TS involved in the control are indexed according to the Q-differential triangle set (DTS), the above-discussed (e.g., proposed, new, non-traditional, etc.) class of convolutional codes may be referred to as QD-DTS-PrCC. According to an embodiment, since (e.g., each) EBB (e.g., layer) may be composed of L cw TS, and L cw =n TS, a minimum number (L l,min =(Q-1)) of previously coded EBB to fill the VS of the current coding layer.

[0112] According to an embodiment, K may be determined according to (eg, by following, from, etc.) a rule l,min According to an embodiment, L l,min It can be determined according to the above rules, for example, that each bit of the (Q-1) VSs of the codeword of the component code can be (for example, only) filled with one bit of the previous TS belonging to one layer, and there cannot be more than one bit filled by the corresponding TS in the VS of the codeword. cw =n TS In the case of, rules 1-4 shown in Table 1 can ensure that each bit of any TS of the QD-DTS-PrCC can be protected (e.g., exactly) by Q codewords representing the component code of the Q dimension of the QD-DTS-PrCC. That is, according to an embodiment, each bit can be protected once as a bit of the component code of the TS (first dimension) and protected (Q-1) times as a bit of the VS of the component code of the remaining (Q-1) EBB parts.

[0113] Figure 7 is a diagram illustrating code words according to an embodiment.

[0114] refer to Figure 7 , shows an example of a codeword for a quasi-productive convolutional code, where the component individual parity check codes may be of length n c =4, and d c =2, the number of EBBs of the TS stored in the encoder memory can be L l,min =2. According to an embodiment, for example, in Figure 7 In this case, such a cascade can only produce min =3. According to an embodiment, in the case where rules 1-4 are satisfied, this may result in (e.g., generate) a convolutional code having a minimum distance smaller than the minimum distance of the true product convolutional code. For example, Figure 7 This incorrectly designed code is shown in Figure 6B The situation shown in Figure 7 The ordering in the EBB codewords is shown.

[0115] According to an embodiment, given that Figure 6B and 7, the orthogonality of canonical product codes can be (e.g., considered to be) equivalent to the general property of Q-dimensional codes, which can occur, for example, in the following cases: (1) a set of Q-codewords controls the same bit; and (2) the other bits of all these codewords are controlled by one codeword (e.g., only by the one codeword) of the set of Q-codewords. According to an embodiment, rules 5 and 6 from Table 1 can be (e.g., considered to be) restrictions on code design, for example, to provide (e.g., guarantee) orthogonality of the codewords of the component codes. For example, rule 5 can be considered to be a restriction on the EBB index, and rule 6 can be considered to be a restriction on the selection of the codeword index for a given layer.

[0116] According to an embodiment, the VS may be generated based on the difference between the EBB indices. For example, to provide orthogonality of the EBBs of the Q-dimensional multiplication convolutional code, the difference in the EBB indices of the TS (e.g., stored in the encoder memory) may be used to select the EBB for generating (e.g., filling) the VS of the currently encoded EBB. Figure 6B and 7 , there may be the following cases where the difference between the EBB indices {0, -1, -2} of the codes is:

[0117] d 0,1 =)0-(-1))=1

[0118] d 0,2 =(0-(-2))=2

[0119] d 1,2 =((-1)-(-2))=1

[0120] In this case, the code difference d 0,1 and d 1,2 Equal, or in other words, d 0,1 =d 1,2 =1. According to the embodiment, Figure 7 In the case of: (1) the TS of CW1 can be used to generate VS in CW2 and CW3; and (2) the TS of CW2 can be used to generate VS in CW3. That is, CW1 fills the VS of CW2, and CW2 and CW1 simultaneously fill the VS of CW3.

[0121] Figure 8 is a diagram illustrating a method of encoding QD-DTS-PrCC according to an embodiment.

[0122] According to the embodiment, for example, referring to Figure 8 , the differences between the indices of the EBBs may be different integers (e.g., integers having different and / or corresponding values). Figure 8, the differences between the indices {0, -1, -3} of the EBBs of the TSs used to generate the currently encoded EBB of the VS are different integers:

[0123] d 0,1 =(0-(-1))=1

[0124] d 0,3 =(0-(-3))=3

[0125] d 1,3 =((-1)-(-3))=2

[0126] In this case, bits of the TS segments of CW1 and CW2 may be used (e.g., jointly) to generate (e.g., simultaneously fill) the VS of CW3. However, CW1 may not be used to generate the VS of CW2, e.g., because the differences between these g-indexes may be different integers. According to an embodiment, EBBs having different (e.g., respective) differences in the EBB indices may result in a VS with d min = 4 convolutional code (for example, can be used to generate a code with d min =4 convolutional code). According to an embodiment, there may be three EBBs (e.g., the required number) in the encoder memory. For example, referring to Figure 8 , the encoder memory may (eg, need to have) three EBBs, which is greater than L l,min =2.

[0127] According to an embodiment, L for constituting (eg, filling) the VS of the current coded EBB l,min The EBBs may (e.g., should) have (e.g., different) differences between their indices. According to an embodiment, having different differences between the indices may (e.g., help) avoid selecting EBB indices that destroy the orthogonality of the codewords of the component codes. According to an embodiment, the L of the VS populating the current coding layer may be used, for example, based on a differential triangle set. l,min The indices of the layers are used to satisfy the orthogonality requirement.

[0128] According to an embodiment, Q-Difference Triangle Set (-DTS) may be a set of integers {a j |0≤Q}, so that all differences {a j -a j’ |0≤j'≤j} are all different, where 0=a1 <a2<…<a J-1. According to an embodiment, a differential triangle set may be used in the FEC design, and the Q-DTS may also be referred to as a Golomb scale. According to an embodiment, (e.g., some) Q-DTS are shown in Table 2A, where m is and / or represents a maximum integer of (e.g., a specific) Q-DTS. According to various embodiments, the maximum integer m of the DTS may define the number of EBBs of the TS stored in the QD-DTS-PrCC encoder memory, and may be consistent with the maximum degree of the generator polynomial of the QD-DTS-PrCC. The present disclosure is not limited to the various sets shown in Tables 2A and 2B, and any suitable and / or similar differential triangle set (DTS) may be used according to an embodiment. Another set of useful DTSs is given in Table 2B. These DTSs are designed to reduce the effects of intermodulation interference. This Q-DTS{0≤a0 <a1<…<a Q-1} is constructed to have all 3 items and All have different characteristics (e.g., requirements). The DTS of Table 2B can be longer than the DTS of Table 2A, which can result in an increase in the constraint length of the code and the total coding delay. However, such a Q-DTS shows better performance in iterative decoding of QD-DTS-PrCC (e.g., to some extent).

[0129] Q Q-DTS m 2 {0,1} 1 3 {0,1,3} 3 3 {0,1,4} 4 3 {0,1,8} 8 4 {0,1,4,6} 6 5 {0,1,4,9,11} 11

[0130] Table 2A

[0131] Q Q-DTS m 2 {0,1} 1 3 {0,1,4} 4 4 {0,1,8,11} 11 5 {0,1,7,16,27} 27 6 {0,14,18,45,51,56} 56

[0132] Table 2B

[0133] Fig. 9 is a diagram showing an index of a QD-DTS-PrCC according to an embodiment.

[0134] refer to Fig. 9 , the EBB index of QD-DTS-PrCC can be used for four integer-valued DTSs, that is, QD-DTS-PrCC can be defined by Q-DTS with Q=4, which can be expressed as 4-DTS of {0, 1, 4, 6}. According to various embodiments, Fig. 9 A QD-DTS-PrCC encoder with 6 EBBs stored in memory is shown, or in other words, the number m=6 is the number of EBBs stored in memory. According to various embodiments, a 4-DTS of {0, 1, 4, 6} may be used to index the L of the VS that populates (e.g., is mapped to) the currently encoded EBB l,min=Q=4 EBBs. According to various embodiments, the symbol “-” (e.g., a negative sign or a subtract sign) may represent a previously encoded EBB stored in the memory of the QD-DTS-PrCC encoder, e.g., relative to the current EBB with index 0, e.g., with a given index “layerp pos -0". According to an embodiment, (eg, only) the EBB with index "layer" in the QD-DTS-PrCC memory is stored. pos -1", "layerp pos -4"layer pos -6" bits of the previously encoded EBB TS can be used to encode the TS with index "layer pos -0". According to an embodiment, VSs of different dimensions of a given codeword may be filled with (e.g., only) bits of specific different dimensions.

[0135] According to various embodiments, the use of DTS to index layers (e.g., EBBs) may be a necessary and sufficient condition for the orthogonality of the codewords of DTS-PrCC and 2D-DTS-PrCC (where 2D-DTS-PrCC may be considered a special case of DTS-PrCC). According to an embodiment, in the case of higher dimensions, such as Q≥3, the use of Q-DTS may be a necessary condition for orthogonality, but not a sufficient condition. According to an embodiment, Rule 6 of Table 1 may result in the following requirement being met: two codewords in the Q-codeword set control one (e.g., and only one) bit of one (e.g., and only one) codeword from another EBB. According to an embodiment, (e.g., even) in the case of EBB orthogonality, for example, due to the use of Q-DTS, an appropriate codeword (e.g., satisfying Rule 6) may be selected for indexing in each layer of the TS stored in the memory of the encoder.

[0136] According to an embodiment, the encoding and decoding of each bit of the QD-DTS-PrCC may be described using any of the following: (1) the position (e.g., index) of the EBB relative to other EBBs stored in memory, (2) the component codeword number in the layer, and (3) the bit index in the codeword of the layer. According to various embodiments, such a description may be sufficient for a (e.g., exact) representation of each bit at any of the input and output of the encoder of the QD-DTS-PrCC, and may be sufficient for a (e.g., exact) representation of their relationship (e.g., association), for example, as defined by the memory of the encoder.

[0137] According to an embodiment, and as described herein, each bit position may be given in the form of any number of coordinates that define the position (e.g., exact position) of the corresponding bit of any component codeword of a particular EBB. According to an embodiment, the coordinates may have (e.g., may be provided, identified, described, etc. in accordance with) the following format: EBB (e.g., layer) position, codeword position, bit position. According to an embodiment, the coordinates (layer 1) of each bit in the VS currently encoding the EBB are given in the form of any number of coordinates that define the position (e.g., exact position) of the corresponding bit of any component codeword of a particular EBB. According to an embodiment, the coordinates (e.g., layer 2) of each bit in the VS currently encoding the EBB are given in the form of (e.g., exact position) of any component codeword of a particular EBB. According to an embodiment, the coordinates (e.g., layer 3) of each bit in the VS currently encoding the EBB are given in the form of pos ,cw pos ,bit pos ) (which may be referred to as a triple coordinate) may be defined by any of the following indices: (1) layer pos : Index of the EBB currently encoded; (2) cw pos :EBBlayer pos (For example, with index layer pos The index of the currently encoded component codeword (e.g., the codeword of the component code) in the EBB of the bit; and (3) bit pos : The currently encoded component codeword cw in EBB pos The index of the bit in the VS (n TS ≤bit pos <n c ).

[0138] According to an embodiment, triple coordinates (layer pos ,cw pos ,bit pos ) can be used to identify (eg, calculate) a triplet of coordinates (layer' ) of bits in a TS of a (eg, already) encoded EBB stored in a memory of a QD-DTS-PrCC encoder. pos ,cw' pos ,bit' pos According to an embodiment, the identified bits may be used to fill (eg, may be mapped to) a datagram having an index cw pos The bit position of one of the (Q-1) VSs of the VS of the codeword of the codeword of the QD-DTS-PrCC is shown in Table 3 according to an embodiment. According to the requirements set forth in Table 1 and the aforementioned "coordinate" notation, a variation of the general bit mapping of the VS of the component codewords of the QD-DTS-PrCC with odd codewords in the EBB is constructed, where the operator " / " can, for example, represent rounding down, for example, 3 / 2=1; and the operator "x%y" can represent the remainder, for example, 5%3=2. According to an embodiment, the bit mapping can follow the EBB index and the bit numbering of the component codeword, for example, as Figure 4 and 5 According to an embodiment, Table 3 shows a method for having components (n c ,k c) Variants of the generic VS bit mapping of 3D-DTS-PrCC for odd codewords in systematic block codes and EBB.

[0139]

[0140] Table 3

[0141] According to an embodiment, any of the hardware and / or software implementations, operations, methods, features, etc. of QD-DTS-PrCC encoding and / or decoding may be based on the bit mapping described in Table 3. According to an embodiment, the index bit' defined by Q-DTS pos and cw′ pos The variation of can be non-unique. For example, the index bit′ pos and cw′ pos Variations of may be non-unique, even when constructed according to the requirements given in Table 1. According to an embodiment, there may be a selection (eg, selection) of index bit ' pos and cw′ pos According to an embodiment, the variants shown in Table 3 may be selected (eg, picked) for use with any number L of component codes in the EBB, for example, due to and / or based on their versatility. cw Code word.

[0142] The constraint length of QD-DTS-PrCC can be referred to as N A , and may be a parameter (eg, a useful parameter) for comparison of convolutional codes. According to an embodiment, the constraint length N A It can be determined according to formula 7:

[0143]

[0144] Where m represents the maximum degree of the generator polynomial of QD-DTS-PrCC. According to an embodiment, for example, referring to Fig. 9 , the maximum degree m of the generator polynomial of the QD-DTS-PrCC may be consistent with the maximum integer m that can define the Q-DTS of the QD-DTS-PrCC. The upper limit of the maximum degree m of the generator polynomial of the QD-DTS-PrCC may be consistent with (e.g., other) upper limits. According to an embodiment, the upper limit of the maximum degree m of the generator polynomial of the QD-DTS-PrCC may be consistent with the upper limit of the maximum integer that defines the Q-DTS of the QD-DTS-PrCC, as shown in Formula 8:

[0145]

[0146] According to an embodiment, in the case where the Q-DTS specifying the QD-DTS-PrCC has the smallest maximum integer m among all DTSs having Q elements, the QD-DTS-PrCC defined by the Q-DTS may have a minimum value N A According to various embodiments, as discussed herein, (e.g., all) parameters of the QD-DTS-PrCC may be used (e.g., necessary and / or sufficient) to implement any of the encoders and decoders of the QD-DTS-PrCC identified and / or discussed herein.

[0147] The design of QD-DTS-PrCC is described below according to an embodiment. That is, according to an embodiment, there may be a three-dimensional (3D) DTS-PrCC in which the component (255, 237) system double extended binary BCH code (e.g., each code may be represented by (n, k), where n may be the size of the encoded bit stream and k may be the size of the input bit stream) has d min =6. According to an embodiment, the length of TS may be determined as

[0148] According to an embodiment, L cw can be selected so that the EBB of 3D-DTS-PrCC has L cw =N TS = 85 TS. According to an embodiment, Formula 2 (see above) provides the code rate of the 3D-DTS-PrCC:

[0149]

[0150] According to an embodiment, in the case of designing the above-mentioned 3D-DTS-PrCC, 3D-DTS {0, 1, 4} may be selected (e.g., picked) from the Q-DTS shown in Table 4 as the Q-DTS defining the 3D-DTS-PrCC. According to an embodiment, for example, the VS bit mapping of the designed code may be performed as shown in Table 4 to be implemented according to the variation given in Table 4, which shows the VS bit mapping of the 3D-DTS-PrCC and the component (255, 237) systematic block code according to an embodiment.

[0151]

[0152] Table 4

[0153] According to an embodiment, the QD-DTS-PrCC designed as described above may have a confinement length given as follows:

[0154]

[0155] Decoder structure

[0156] According to various embodiments, QD-DTS-PrCC can be a convolutional code, and a series of (e.g., various) decoding strategies with different complexities and delays can be allowed (e.g., permitted, applied to, etc.). Convolutional convolutional codes (e.g., all known convolutional convolutional codes) can use iterative decoding. In the case of high throughput systems (e.g., throughput ≥ 400Gb / s), iterative decoding with hard decision syndrome decoding of component codes can be used for step codes, continuously interleaved codes, and weaving codes. In the case of iterative soft decision decoding of convolutional codes, known methods for decoding parallel concatenated codes can be applied.

[0157] According to an embodiment, in the case of decoding QD-DTS-PrCC, an iterative decoding algorithm may be used. According to various embodiments, for example, in a manner similar to a staircase code, QD-DTS-PrCC may be iteratively decoded over a window of L received EBBs (e.g., the received EBBs may correspond to transmitted EBBs including any of channel noise and interference). According to an embodiment, there may be a decoding window with L=10 received EBBs, and the QD-DTS-PrCC EBB received from the channel at time i may be represented as Y TS,i According to an embodiment, at the (eg, very) beginning of decoding, Y TS,i , i = 0, 1, ..., (m-1), which may also be referred to as an all-zero EBB, where m represents the maximum integer defining the DTS of the QD-DTS-PrCC, and {Y Ts,m ,…,Y TS,10} is the first (10-(m-1)) EBBs first received from the channel. According to an embodiment, in the decoding window, for each i∈{m,…,10}, the decoder can use the continuously received EBBs (Y TS,i ,Y TS,i+1 ,…,Y TS,i+m ) to reconstruct the codeword of the component code, which can be based on Figure 5 The word format shown and the bit mapping that satisfies the rules provided in Table 1, for example.

[0158] According to an embodiment, at each decoding iteration, the decoder may proceed from i=m by decoding each component code used in constructing EBBi (e.g., by using a hard decision decoder appropriate for that component code). According to an embodiment, the received EBBY may be decoded. TS,O -Y TS,DTS[u],u=0,1,…,(Q-1) for correction (e.g., update), where DTS[u] may be an array of indices of the layers involved in the control of these bits. For example, correction and / or update may be performed because each bit may be involved in (e.g., used for) Q component codewords. According to an embodiment, (e.g., corresponding) correction and / or update may be performed with (e.g., for all) Y TS,0 -Y TS,DTS[u] According to an embodiment, reconstruction and decoding of the component codewords may continue (e.g., process) one EBB after another (e.g., from one EBB to the next EBB) until the end of the window is reached at i=10. According to an embodiment, at the end of a decoding iteration, the decoding window may output Y tS,m EBB, and can obtain (e.g., the latest) received block Y TS,11 According to an embodiment, the decoding process may continue indefinitely as the decoding window slides over each newly received EBB.

[0159] According to an embodiment, it may be beneficial to repeat the above (e.g., previously described) decoding process, and it may be useful to use modified decoding. According to an embodiment, such repeated and / or modified decoding may result in improved performance due to, for example, a reduction in error propagation caused by the following miscorrections: (1) correcting only t-1 errors for the t-error correction component code of the least reliable layer (e.g., the least reliable layer is the layer received from the channel); and (2) increasing the reliability of subsequent layers.

[0160] Performance Results

[0161] Fig.10 and Fig.11 3D-DTS-PrCC is a diagram showing simulation results of bit error rate (BER) performance according to an embodiment. Fig.10 , showing a rate with R = 0.935 and d min =6(t=2)component (1023,1001) BCH code 3D-DTS-PrCC performance. Fig.11 , showing a rate with R = 0.937 and d min = 8 (t = 3) component (1020,990) BCH code performance of two-dimensional DTS-PrCC.

[0162] According to an embodiment, the double extension (n c ,k c ) The binary BCH code may be a component code of the considered 3D-DTS-PrCC. According to an embodiment, with non-extended parameters Double expansion (n c ,kc ) Binary BCH codes can be used as component codes, where m bch can be the field spreading degree, and t can represent the number of correctable errors. According to an embodiment, the parameters of the double spreading code are shown in Table 5, where and expenses

[0163]

[0164] Table 5

[0165] According to an embodiment, the mapper of 3D-DTS-PrCC may be constructed according to a rule, for example, according to Table 5. According to an embodiment, a channel model with additive white Gaussian noise (AWGN) and binary phase shift keying (BPSK) modulation may be assumed, and all BER performance curves may be simulated according to the condition that the number of decoding errors is not less than 100. According to an embodiment, Fig.10 The output BER of 5.58dB given in is based on 36 output errors.

[0166] According to an embodiment, Fig.10 shows that the min =6(t=2)(1023,1001) The rate of 3D-DTS-PrCC of BCH code is R=0.935. According to the embodiment, considering the comparison Fig.10 According to simulation results of the 3D-DTS-PrCC defined by DTS:{0,1,4}, the 3D-DTS-PrCC can provide approximately (e.g., almost, nearly) the same performance as the 3D-DTS-PrCC of the similar (e.g., same) rate 3D-DTS-PrCC in one EBB, where the decoder of the component BCH code with t=4 is more complex (e.g., much more complex) and the number of encoders / decoders is larger (e.g., much larger). According to an embodiment, given that Fig.10 and 11 , it can be seen that 3DTS-PrCC provides (eg, to some extent) better performance than the more complex DTS-PrCC with component codes of t=3.

[0167] Comparison of QD-DTS-PrCC with product codes, staircase codes and LDPC codes

[0168] In the following, QD-DTS-PrCC (e.g., as described above and / or according to embodiments herein) may be compared to product codes (e.g., product block codes), staircase codes, and LDPC codes, e.g., where the binary component codes have the same n c and k cAnd in the case of comparing a QD-DTS-PrCC (e.g., a QD-DTS-PrCC as described above according to an embodiment) with a product block code (e.g., a canonical, multidimensional, conventional, etc. product block code), the length N of the Q-dimensional product code can be determined according to Formula 10 pc :

[0169] N pc =n c Q ……………………[Formula 10]

[0170] where, in this case, the number of information bits K pc =k c Q =(n c -r c ) Q Furthermore, in this case, the code rate R of the Q-dimensional product code pc It can be determined according to formula 11:

[0171]

[0172] According to an embodiment, such a lower bound may follow a Bernoulli number of the form Bernoulli )Inequality: (1-x) Q :(1-x) Q ≥1-Qx, where integer Q ≥ 0 and real number 0 <x<1。

[0173] will be represented as The code rate of QD-DTS-PrCC and the code rate of the two-dimensional product code R pc By comparison, it is clear that the code rate of the product code can be (e.g., slightly) greater than the code rate of QD-DTS-PrCC. At (e.g., typical) code rates above R>0.8 (e.g., which may be the code rate of interest for ultra-high-speed systems) together with (e.g., typical) length n c = 200-2000, the difference (eg, in terms of code rate) may be negligible.

[0174] According to an embodiment, The constraint length N of QD-DTS-PrCC A According to the public

[0175] Formula 12 is used to determine:

[0176]

[0177] By comparing the constraint length N of QD-DTS-PrCC A and the length N of the Q-dimensional product codepc , it is clear that the constraint length of QD-DTS-PrCC is smaller (e.g., much smaller) than the length (e.g., half the size) of a Q-dimensional product code having (e.g., approximately) the same code rate, for example, as shown in Formula 13:

[0178]

[0179] According to an embodiment, there may be a case where the number of component codes of 3D-DTGS-PrCC is given (eg, selected) as And DTS is 3-DTS{0, 1, 3}, for example, it defines the maximum degree m of the generator polynomial of 3D-DTS-PrCC = 3. In this case, according to an embodiment, the constraint length of 3D-DTS-PrCC can be shown as formula 14:

[0180]

[0181] In this case, the relationship is generated by comparing the constraint length of the 3D-DTS-PrCC with the length of the Q-dimensional product code In this case, by comparing the length of the product code with the same component code as the QD-DTS-PrCC, the QD-DTS-PrCC can have a constraint length n less than the product code. c According to an embodiment, Table 6 may provide a numerical comparison for the case of component double-extended component BCH codes.

[0182] According to an embodiment, as shown in Table 6, even in the case of a three-dimensional code, the 3D-DTS-PrCC may have a constraint length that is 1000 times shorter (e.g., approximately, greater than, etc.) than the length of the canonical 3D product code. In this case, the ratio It may reflect that the length of the multidimensional product code may be exponentially larger than N of QD-DTS-PrCC (eg, the proposed class of codes). A .

[0183]

[0184] Table 6

[0185] It is apparent (e.g., obvious) from the above that multidimensional canonical product codes are not practical, e.g., due to their (e.g., impractical, huge, etc.) code lengths. Such large code lengths may be the reason why multidimensional canonical product codes are not used in telecommunication systems (e.g., except for low-rate variants based on very short component codes or a single parity-check code).

[0186] In the case of comparing QD-DTS-PrCC to ladder codes, the ladder code can be (e.g., considered to be) a special case of DTS-PrCC defined by 2-DTS{0,1}. As described above, the BER performance of (a) 3D-DTS-PrCC with component BCH codes with t=2 and (b) ladder codes with more powerful component codes with t=4 are almost the same over the simulated BER range. Thus, when comparing QD-DTS-PrCC to ladder codes, QD-DTS-PrCC has the advantage of providing any of the following advantages: less decoding complexity and less encoding complexity.

[0187] Table 7 provides a comparison of staircase coding and 3D-DTS-PrCC in the case of iterative decoding (eg, as described above).

[0188]

[0189] Table 7

[0190] As is apparent in Table 7, the ladder code and the 3D-DTS-PrCC code may have similar code rates, but the ladder code is longer (e.g., much longer) and its constraint length NA is almost twice that of the 3D-DTS-PrCC. Fig.11 , the BER performance of the two codes may be (e.g., almost) identical. However, depending on an embodiment, for QD-DTS-PrCC, any of the following may be smaller (e.g., half the size) than for the ladder code: (1) the number of encoders for the component codes; (2) the number of coset constructors; and (3) the number of decoders for the component codes of the QD-DTS-PrCC. Furthermore, all decoders for the component codes with t=2 for 3D-DTS-PrCC may have much smaller decoding complexity than decoders for the component codes with t=4 for the ladder code. The encoding and / or decoding delay of the ladder code may be defined by the number of bits in the EBB of the encoder and / or decoder of the ladder code.

[0191] When decoding starts and the QD-DTS-PrCC encoder and decoder are initialized to the all-zero state, the latency of encoding and / or decoding of the staircase code and QD-DTS-PrCC can be expressed as:

[0192] DecLat = (number of iterations) * (number of decoders in the layer) * (length of the transmitted segment)

[0193] DncLat = (number of encoders in the layer) * (length of the transmitted segment)

[0194] In this case, the delays of the codes as shown in Table 7 can be compared, and the coding delays of the step code and DTS-PrCC of the considered example can be given by:

[0195] DecLat SC =n it ·L cw ·n TS =8·748·748=4476032

[0196] DecLat DTS =n it ·L cw ·n TS =10·341·341=1162810

[0197] EncLat SC =L cw ·n TS =748·748=559504

[0198] EncLat DTS =L cw ·n TS =341·341=116281

[0199] In this case, the comparison of delays enables the encoding and / or decoding delay of 3D DTS-PrCC to be four times smaller than that of a ladder code with similar same code rate.

[0200] The comparison of the delay estimate of the ladder code with the delay estimate of the QD-DTS-PrCC defined by different Q-DTS can be obtained similarly as described above. However, for such comparison, the performance of the specific QD-DTS-PrCC can (e.g., should) be analyzed (e.g., investigated, determined, etc.) in order to obtain the n required for such comparison. it . According to an embodiment, QD-DTS-PrCC of different constraint lengths may be constructed based on any of the following: (1) selecting an appropriate and / or longer set of difference triangles; and (2) selecting a different dimension Q. For staircase codes, this flexibility does not exist. According to an embodiment, QD-DTS-PrCC may be more flexible (e.g., much more flexible) than staircase codes, e.g., due to (e.g., the possibility of) changing the constraint length of the QD-DTS-PrCC by selecting a (e.g., specific, appropriate, etc.) set of differences.

[0201] In the case of comparing QD-DTS-PrCC (e.g., QD-DTS-PrCC according to the above-described embodiments) with LDPC codes, LDPC codes may provide the (e.g., most) powerful class of error correction codes with (e.g., highly) parallel decoding. However, in the case of ultra-high throughput systems with data rates above 400 Gb / s, LDPC codes may not have (e.g., retain) such advantages over FEC techniques, since it is known that the main advantages of LDPC codes are evident in the lower data rate domain (e.g., <50 Gb / s).

[0202] In the case of ultra-high throughput systems, there may be (e.g., a specific set of typical, etc.) requirements, namely, that FEC: (1) should not have a BER ≤ 10 -15 The invention relates to a method for implementing an LDPC code with a code rate R ≥ 0.8, wherein the code rate R ≥ 0.8 should have a minimum error floor; (2) should have a code rate R ≤ 0.8; (3) should have a high coding gain; and (4) should have a small power consumption and complexity. Results of hardware implementations of LDPC codes with a code rate R ≥ 0.8 have been implemented and / or reported. However, implementation results of LDPC codes with a code rate smaller than R ≤ 0.8 and a better coding gain may not be available, for example, due to a lack of (e.g., good) implementable LDPC solutions that meet the FEC requirements.

[0203] According to an embodiment, a method for encoding QD-DTS-PrCC may include performing any of the following: (1) (e.g., first) determining a minimum number of previously encoded bit blocks (EBBs) to be used when generating newly encoded codewords and transmitted segments that are (compose) part of these codewords, wherein the EBBs may define all transmitted segments (TS) at a given transmission instance; (2) selecting (e.g., specific) EBBs from the encoder memory (e.g., based on an indexing method (e.g., a differential triangle set) (e.g., based on the minimum number); (3) determining (e.g., component) codeword segments represented as virtual segments (VS) using the selected (e.g., specific) EBBs based on a given set of bit and / or symbol mappings based on rules; and (4) obtaining newly encoded (e.g., component) codewords and TSs using input data / source bitstream and the determined VS.

[0204] According to an embodiment, a method for determining VS based on a set of bit / symbol mapping rules for encoding QD-DTS-PrCC may be such that any of the following: (1) a transmission segment (TS) in a (e.g., given, specific, one, etc.) EBB may not be used to construct a VS of the same EBB; (2) each bit and / or symbol of a (e.g., arbitrary) TS in a (e.g., given, etc.) EBB may be used to construct (e.g., only one) VS of a component codeword in other EBBs; and (3) (e.g., only one) bit and / or symbol of a (e.g., arbitrary) TS may be used in the construction of a VS of a (e.g., given) component codeword.

[0205] According to an embodiment, there may be a method for determining a bitmap having components (n c ,k c ) VS method of QD-DTS-PrCC of system block code: (1) bit' pos =bit pos -n Ts ; (2) cw' pos =9cw pos +bit′ pos / (J-1))%L cw ; and (3) layer' pos =layer pos -dts[bit' pos %(J-1)+1], where the coordinates (layer pos ,cw pos ,bit pos ) can represent each bit in the VS of the current coded EBB, and (layer' pos ,cw' pos ,bit' pos ) may represent each bit in the VS of the previously encoded EBB stored in the encoder memory.

[0206] According to an embodiment, a method of encoding a QD-DTS-PrCC may include: selecting an alternating component code for encoding consecutive EBBs; wherein the component code (n c ,n c -r c,1 ), and the component code (n c ,n c -r c,2 ). In addition, according to an embodiment, future encoding operations may follow such an order.

[0207] in conclusion

[0208] Although the features and elements are described above in specific combinations, it will be understood by those skilled in the art that each feature or element may be used alone or in any combination with other features and elements. In addition, the methods described herein may be implemented in a computer program, software, or firmware embedded in a computer-readable medium and executed by a computer or processor. Examples of non-transitory computer-readable media include, but are not limited to, read-only memory (ROM), random access memory (RAM), registers, buffer memory, semiconductor storage devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM discs and digital versatile discs (DVDs). A processor associated with the software may be used to implement a radio frequency transceiver used in a UE, WTRU, terminal, base station, RNC, or any host computer.

[0209] In addition, in the above embodiments, reference is made to processing platforms, computing systems, controllers, and other devices including processors (including constraint servers and assembly points / servers). These devices may include at least one central processing unit ("CPU") and memory. According to the practice of those skilled in the art of computer programming, references to symbolic descriptions of actions and operations or instructions may be performed by various CPUs and memories. These actions and operations or instructions may be referred to as being "executed," "computer executed," or "CPU executed."

[0210] Those skilled in the art will appreciate that the operations or instructions described by the actions and symbols include the manipulation of electrical signals by the CPU. The electrical system representation can identify data bits, which cause the electrical signals to be transformed or restored and the maintenance of the storage location of the data bits in the storage system to thereby reconfigure or otherwise change the operation of the CPU and other processing of the signal. The storage location of the data bits is maintained to have specific electrical, magnetic, optical or organic properties corresponding to or representing the data bits. It should be understood that the representative embodiments are not limited to the above-mentioned platforms or CPUs and other platforms and CPUs can support the provided methods.

[0211] The data bits may also be maintained on a computer-readable medium, including a magnetic disk, an optical disk, and any other volatile (e.g., random access memory ("RAM")) or non-volatile (e.g., read-only memory ("ROM")) CPU-readable mass storage system. The computer-readable medium may include cooperating or interconnected computer-readable media that reside exclusively on a processor system or distributed among multiple interconnected processing systems that may be local or remote to the processing system. It is understood that the exemplary embodiments are not limited to the above-mentioned memories and that other platforms and memories may support the described methods.

[0212] In the illustrated embodiment, any of the operations, processes, etc. described herein may be implemented as computer-readable instructions stored on a computer-readable medium. The computer-readable instructions may be executed by a processor of a mobile unit, a network element, and / or any other computing device.

[0213] There is a slight distinction between hardware and software implementations of systems. The use of hardware or software is generally (e.g., but not always, as the choice between hardware and software can be important in certain environments) a design choice that considers a trade-off between cost and efficiency. There can be various tools (e.g., hardware, software, and / or firmware) that affect the processes and / or systems and / or other technologies described herein, and the preferred tools can change with the context of the deployed processes and / or systems and / or other technologies. For example, if the implementer determines that speed and accuracy are most important, the implementer may choose to use primarily hardware and / or firmware tools. If flexibility is most important, the implementer may choose to use primarily software implementation. Alternatively, the implementer may choose some combination of hardware, software, and / or firmware.

[0214] The above detailed description has presented various embodiments of the device and / or process through the use of block diagrams, flow charts and / or examples. To the extent that these block diagrams, flow charts and / or examples include one or more functions and / or operations, those skilled in the art will understand that each function and / or operation within these block diagrams, flow charts or examples can be implemented separately and / or together by a wide range of hardware, software or firmware or substantially any combination thereof. Suitable processors include, for example, general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), application-specific standard products (ASSPs); field-programmable gate array (FPGA) circuits, any other type of integrated circuit (IC) and / or state machines.

[0215] Although features and elements are provided above in specific combinations, it is understood by those skilled in the art that each feature or element can be used alone or in any combination with other features and elements. The present disclosure is not limited to the specific embodiments described in this application, which are intended to be examples of various aspects. Many modifications and variations can be made without departing from its essence and scope, which are known to those skilled in the art. The elements, actions or instructions used in the description of this application should not be understood as being key or necessary to the present invention unless explicitly stated. In addition to these methods and devices listed herein, those skilled in the art can also know functionally equivalent methods and devices within the scope of the present disclosure based on the above description. These modifications and variations should also fall within the scope of the appended claims. The present disclosure is limited only by the appended claims, including the full scope of their equivalents. It should be understood that the present disclosure is not limited to a specific method or system.

[0216] It should also be understood that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. As used herein, when the term "user equipment" and its abbreviation "UE" are referred to herein, it can mean (i) a wireless transmit and / or receive unit (WTRU), such as described below; (ii) any of a plurality of embodiments of a WTRU, such as described below; (iii) a device with wireless capabilities and / or wired capabilities (e.g., tetherable via a mobile phone) configured with some or all of the structure and functionality of a WTRU, such as described below; (iii) a device with wireless capabilities and / or wired capabilities that is configured with less than all of the structure and functionality of a WTRU, such as described below; or (iv) the like. Details of an example WTRU, which can represent any UE described herein.

[0217] In certain representative embodiments, some parts of the subject matter described herein may be implemented via application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), and / or other integrated formats. However, those skilled in the art will appreciate that some aspects of the embodiments disclosed herein, in whole or in part, may equally be implemented by integrated circuits, as one or more computer programs running on one or more computers (e.g., one or more programs running on one or more computer systems), one or more programs running on one or more processors (e.g., one or more programs running on one or more microprocessors), firmware, or substantially any combination of these, and that designing circuits and / or writing codes for the software and / or firmware according to the present disclosure is known to those skilled in the art. In addition, those skilled in the art will appreciate that the mechanisms of the subject matter described herein may be distributed as program products in various forms, and that the exemplary embodiments of the subject matter described herein are applicable, regardless of the specific type of signal-bearing medium used to actually perform the distribution. Examples of signal-bearing media include, but are not limited to, the following: recordable media, such as floppy disks, hard disks, CDs, DVDs, digital tapes, computer memories, etc., and transmission media, such as digital and / or analog communication media (e.g., optical cables, waveguides, wired communication links, wireless communication links, etc.).

[0218] The subject matter described here sometimes shows different components, which are contained in or connected to different other components. It can be understood that these depicted architectures are only examples, and many other architectures that implement the same function in practice can be implemented. Conceptually, any arrangement of components that implement the same function more effectively "associated" can implement the desired function. Therefore, any two components combined here to implement a specific function can be regarded as "associated" to each other to implement the desired function, regardless of the architecture or intermediate components. Similarly, any two components associated can also be regarded as "operationally connected" or "operationally coupled" to implement the desired function, and any two components that can be associated in this way can also be regarded as "operationally couplable" to each other to implement the desired function. Specific examples of operational coupling include but are not limited to physically pairable and / or physically interactive components and / or wirelessly interactive and / or wirelessly interactive components and / or logically interactive and / or logically interactive components.

[0219] With respect to the use of substantially any plural and / or singular terms herein, those skilled in the art may translate from the plural to the singular and / or from the singular to the plural as is appropriate to the context and / or application. For purposes of clarity, various singular / plural permutations may be expressly set forth herein.

[0220] Those skilled in the art will appreciate that the terms used herein in general and in the claims in particular (e.g., the body of the claims) are generally "open" terms (e.g., the term "including" should be understood as "including but not limited to", the term "having" should be understood as "having at least", the term "including" should be understood as "including but not limited to", etc.). Those skilled in the art will also appreciate that if a claim is to describe a specific number, it will be explicitly described in the claim, and there is no such meaning in the absence of such description. For example, if only one item is to be indicated, the term "single" or similar language may be used. To aid understanding, the following claims and / or the description herein may include the use of the leading phrases "at least one" or "one or more" to introduce a claim description. However, the use of these phrases should not be understood to imply that a claim description introduced by the indefinite article "a" will limit any particular claim containing such introduced claim description to an embodiment containing only one such description, even if the same claim includes the leading phrases "one or more" or "at least one" and an indefinite article (e.g., "a") (e.g., "a" should be understood to mean "at least one" or "one or more"). The same is true for the use of definite articles used to introduce claim descriptions. In addition, even if a specific number of claims described in the introduction is explicitly described, it can be understood by those skilled in the art that such description should be understood to mean at least the number described (for example, the description of "two descriptions" alone without other modifiers means at least two descriptions, or two or more descriptions). In addition, in these examples where a convention similar to "at least one of A, B, and C, etc." is used, generally speaking, such a convention is a convention understood by those skilled in the art (for example, "the system has at least one of A, B, and C" can include but is not limited to the system having only A, only B, only C, A and B, A and C, B and C, and / or A, B and C, etc.). In these examples where a convention similar to "at least one of A, B, or C, etc." is used, generally speaking, such a convention is a convention understood by those skilled in the art (for example, "the system has at least one of A, B, or C" can include but is not limited to the system having only A, only B, only C, A and B, A and C, B and C, and / or A, B and C, etc.). Those skilled in the art will also appreciate that substantially any separated word and / or phrase representing two or more alternatives, whether in the specification, claims or drawings, should be understood to include the possibility of including one of the two items, any one or both items. For example, the phrase "A or B" is understood to include the possibility of "A" or "B" or "A" and "B". In addition, the term "arbitrary" used herein followed by multiple items and / or multiple items listed is intended to include "arbitrary", "arbitrary combination", "arbitrary multiple" and / or "any combination of multiple" of the multiple items and / or multiple items, either alone or in combination with other items and / or other items.Furthermore, the terms "set" or "group" as used herein are intended to include any number of items, including zero. Furthermore, the term "number" as used herein is intended to include any number, including zero.

[0221] In addition, if features or aspects of the disclosure are described in terms of Markush groups, those skilled in the art will recognize that the disclosure is also described in terms of any individual member or subgroup of members of the Markush group.

[0222] Those skilled in the art will appreciate that, for any and all purposes, such as to provide a written description, all ranges disclosed herein also include any and all possible sub-ranges and combinations of sub-ranges thereof. Any listed range can be easily understood to be sufficient to describe and implement the same range that is divided into at least equal halves, three parts, four parts, five parts, ten parts, etc. As a non-limiting example, each range described here can be easily divided into the lower third, the middle third, and the upper third, etc. Those skilled in the art can also understand that all languages ​​such as "up to", "at least", "greater than", "less than", etc. include the described numbers and can be divided into the above-mentioned sub-ranges accordingly. Finally, those skilled in the art can appreciate that the range includes each individual member. Therefore, for example, a group and / or set with 1-3 cells refers to a group / set with 1, 2, or 3 cells. Similarly, a group / set with 1-5 cells refers to a group / set with 1, 2, 3, 4, or 5 cells, etc.

[0223] Furthermore, the claims should not be read as limited to the order or elements provided unless described to that effect. Furthermore, the use of the term "means for..." in any claim is intended to invoke 35 U.S.C. § 112, 6 or means-plus-function claim format, any claim without the term “means for…” does not have such an intent.

[0224] A processor in association with software may be used to implement a radio frequency transceiver for use in a wireless transmit / receive unit (WTRU), user equipment (UE), terminal, base station, mobility management entity (MME) or evolved packet core (EPC), or any host computer. The WTRU may incorporate modules implemented in hardware and / or software, including software defined radio (SDR), and other components such as a camera, a video camera module, a video phone, an intercom phone, a vibration device, a speaker, a microphone, a television transceiver, a hands-free headset, a keyboard, module, a frequency modulation (FM) radio unit, a near field communication (NFC) module, a liquid crystal display (LCD) display unit, an organic light emitting diode (OLED) display unit, a digital music player, a media player, a video game console module, an Internet browser and / or any wireless local area network (WLAN) or ultra-wideband (UWB) module.

[0225] Although the invention is described in terms of a communication system, it is understood that the system can be implemented in software on a microprocessor / general purpose computer (not shown). In some embodiments, one or more of the functions of the various components can be implemented in software controlling a general purpose computer.

[0226] Furthermore, while the invention has been shown and described with reference to particular embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the range of equivalents of the claims and without departing from the invention.

Claims

1. A method performed by a wireless transmit receive unit WTRU including a Q-dimensional QD-differential triangular set DTS-product convolutional code-PrCC encoder for encoding a QD-DTS-PrCC of an output data stream, the method comprising: determining a number of input bits received by each of a number of component encoders of the QD-DTS-PrCC encoder; determining a number of available coded bit blocks EBBs of the QD-DTS-PrCC encoder, each of the available EBBs comprising a set of previously transmitted transport segments TS of the output data stream, wherein each of the previously transmitted TSs has the same bit length; selecting a number of EBBs from the available EBBs according to a DTS indexing method, wherein the number of selected EBBs is Q-1, and Q is an integer value indicating the dimension of the QD-DTS-PrCC, and wherein Q is greater than or equal to 2; According to the selected EBB, a QD-DTS-PrCC component codeword QCC is generated, the QCC comprising: (1) a new TS, (2) a number of virtual segments VS equal to the number of the selected EBBs, and (3) a number of parity check bits; generating an output data stream comprising at least the new TS included in the QCC, wherein the new TS is extracted from the QCC; and The output data stream is transmitted.

2. A method for encoding a convolutional code PrCC performed by a wireless transmit receive unit WTRU, the method comprising: determining a plurality of input bits for each of a plurality of component encoders of a PrCC encoder; determining a plurality of coded bit blocks EBB of the PrCC encoder, each respective EBB comprising a set of previously transmitted first transmitted segments TS; generating a component codeword using Q-1 EBBs of the plurality of EBBs, wherein Q is an integer value greater than or equal to 2, and the component codeword includes: (1) a second TS, (2) a number of virtual segments VS based on the number of the Q-1 EBBs, and (3) a plurality of parity check bits; and An output data stream is transmitted, the output data stream comprising information indicative of at least the second TS extracted from the component codewords.

3. The method according to claim 2, wherein: The PrCC encoder is a Q-dimensional QD-Differential Triangle Set DTS-PrCC encoder.

4. The method according to claim 2, wherein: Each of the previously transmitted first TSs has the same bit length.

5. The method according to claim 2, wherein: The component codeword is a Q-dimensional QD-differential triangle set DTS-PrCC component codeword.

6. The method according to claim 2, further comprising: The plurality of parity bits are generated using a number of VSs equal to the number of the Q-1 EBBs.

7. The method according to claim 2, further comprising: The set of TSs is determined using the Q-1 EBBs of the plurality of EBBs.

8. The method according to claim 2, further comprising: Based on the mapping of the indexes of the plurality of EBBs, the Q-1 VSs are determined.

9. The method according to claim 2, wherein: The second TS includes information indicating the plurality of input bits and the parity bits.

10. The method according to claim 2, further comprising: The parity check bits are generated based on the lengths and dimensions of the component codes of the PrCC encoder.

11. A wireless transmit receive unit WTRU, the WTRU comprising: A processor and a transceiver configured to: determining a plurality of input bits for each of a plurality of component encoders of a product convolutional code PrCC encoder, determining a plurality of coded bit blocks EBB of said PrCC encoder, each respective EBB comprising a set of previously transmitted first transmitted segments TS, generating a component codeword using Q-1 EBBs of the plurality of EBBs, wherein Q is an integer value greater than or equal to 2, and the component codeword includes: (1) a second TS, (2) a number of virtual segments VS based on the number of the Q-1 EBBs, and (3) a plurality of parity check bits, and An output data stream is transmitted, the output data stream comprising information indicative of at least the second TS extracted from the component codewords.

12. The WTRU of claim 11, wherein the PrCC encoder is a Q-dimensional QD-Differential Triangular Set (DTS-PrCC) encoder.

13. The WTRU of claim 11, wherein each of the previously transmitted first TSs has a same bit length.

14. The WTRU of claim 11, wherein the component codeword is a Q-dimensional QD-Differential Triangular Set (DTS-PrCC) component codeword.

15. The WTRU of claim 11 , wherein the processor and the transceiver are configured to: The plurality of parity bits are generated using a number of VSs equal to the number of the Q-1 EBBs.

16. The WTRU of claim 11 , wherein the processor and the transceiver are configured to: The set of TSs is determined using the Q-1 EBBs of the plurality of EBBs.

17. The WTRU of claim 11 wherein the processor and the transceiver are configured to: Based on the mapping of the indexes of the plurality of EBBs, the Q-1 VSs are determined.

18. The WTRU of claim 11, wherein the second TS includes information indicating the plurality of input bits and the parity bits.

19. The WTRU of claim 11 wherein the processor and the transceiver are configured to: The parity check bits are generated based on the lengths and dimensions of the component codes of the PrCC encoder.

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