Semiconductor Structure and Method for Manufacturing the Same

Abstract

The present disclosure relates to a semiconductor structure and a method of manufacturing the same. A method includes: depositing a dummy gate dielectric layer over a semiconductor region; depositing a dummy gate electrode layer; and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of the dummy gate electrode. The method further includes forming a protective layer on sidewalls of the upper portion of the dummy gate electrode and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. Then, a third etching process is performed using the protective layer as an etching mask to etch the lower portion of the dummy gate electrode. The dummy gate electrode is tapered by the third etching process. The protective layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures and methods of manufacturing the same. Background Art

[0002] Technological advances in integrated circuit (IC) materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generations. During the evolution of ICs, the functional density (e.g., the number of interconnect devices per chip area) generally increases while the geometric dimensions decrease. This scaling process typically provides benefits by increasing production efficiency and reducing associated costs.

[0003] This scaling also increases the complexity of processing and manufacturing ICs, and to achieve these advances, similar developments in IC processing and manufacturing are needed. For example, fin field-effect transistors (FinFETs) have been introduced to replace planar transistors. The structure of FinFETs and methods of manufacturing FinFETs are under development.

[0004] The formation of FinFETs generally includes forming a dummy gate stack and replacing the dummy gate stack with a replacement gate stack. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a method of manufacturing a semiconductor structure is provided, including: depositing a dummy gate dielectric layer over a semiconductor region; depositing a dummy gate electrode layer over the dummy gate dielectric layer; performing a first etching process, wherein an upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode; forming a protective layer on sidewalls of the upper portion of the dummy gate electrode; performing a second etching process, wherein a lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode; performing a third etching process using the protective layer as an etching mask to etch the lower portion of the dummy gate electrode, wherein the dummy gate electrode is tapered by the third etching process; removing the protective layer; and replacing the dummy gate electrode with a replacement gate electrode.

[0006] According to another embodiment of the present disclosure, a semiconductor structure is provided, including: a protruding semiconductor fin; a first gate stack on the protruding semiconductor fin, wherein the first gate stack includes a first sidewall, the first sidewall including: a first lower straight portion having a first tilt angle; and a first upper straight portion having a second tilt angle greater than the first tilt angle; and a first gate spacer in contact with both the first lower straight portion and the first upper straight portion of the first gate stack.

[0007] According to another embodiment of the present disclosure, a semiconductor structure is provided, including: a semiconductor fin; a gate dielectric on the semiconductor fin; a gate electrode on the gate dielectric, wherein the gate electrode includes: an upper portion having a first sidewall; and a lower portion below the upper portion and joined to the upper portion, wherein the lower portion has a second sidewall joined to the first sidewall, and wherein the first sidewall is more upright than the second sidewall, and there is a sudden change in the inclination angles of the first sidewall and the second sidewall; and gate spacers in contact with the first sidewall and the second sidewall. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0009] Figures 1 - 4 , Figure 5A , Figure 5B , Figure 6 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figures 7 - 10 and Figure 11A are perspective views and / or cross-sectional views of intermediate stages of forming a fin field-effect transistor (FinFET) according to some embodiments.

[0010] Figure 6F , Figure 6G , Figure 6H and Figure 6I are cross-sectional views of intermediate stages of forming a dummy gate electrode having more than one narrowing portion according to some embodiments of the present disclosure.

[0011] Figure 11B - 1 , Figure 11B - 2 and Figure 11B - 3 illustrate the height of the transition level of the sidewall of a replacement gate relative to the fin top according to some embodiments.

[0012] Figures 12 - 15 is a cross-sectional view of an intermediate stage of forming a replacement gate having two transition regions according to some embodiments.

[0013] Figures 16 - 23 is a cross-sectional view of an intermediate stage of forming a replacement gate having a transition region formed for a selected sidewall of a selected replacement gate according to some embodiments.

[0014] Figure 24Illustrates a process flow for forming a FinFET according to some embodiments. Detailed Description

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on top of a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, spatially relative terms (e.g., "below", "beneath", "lower", "above", "upper", etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (one or more) element or (one or more) feature. These spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0017] According to some embodiments, a fin field-effect transistor (FinFET) having a replacement gate (the bottom end of the replacement gate is narrower than the top end) is provided. According to some embodiments, the formation of the dummy gate stack is controlled such that the bottom end of the dummy gate stack is narrower than the corresponding top end, and thus it is easier to form the replacement gate subsequently, and the performance of the FinFET is improved. The embodiments discussed herein will provide examples to enable the manufacture or use of the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of the different embodiments. Throughout the various views and illustrative embodiments, like reference numerals are used to indicate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0018] Figures 1 - 4 , Figure 5A , Figure 5B , Figure 6 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figures 7 - 10 and Figure 11Ais a perspective view and / or a cross-sectional view of an intermediate stage of forming a fin field-effect transistor (FinFET) according to some embodiments of the present disclosure. Figure 24 The corresponding processes are also schematically reflected in the process flow shown.

[0019] In Figure 1 a substrate 20 is provided. The substrate 20 can be a semiconductor substrate (e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc.), which can be doped (e.g., using p-type or n-type dopants) or undoped. The semiconductor substrate 20 can be a part of a wafer 10 (e.g., a silicon wafer). Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, e.g., multi-layer or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate 20 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0020] Further referring to Figure 1 a well region 22 is formed in the substrate 20. The corresponding process is shown as process 202 in process flow 200 shown in Figure 24 According to other embodiments of the present disclosure, the well region 22 is a p-type well region formed by implanting a p-type impurity (which can be boron, indium, etc.) into the substrate 20. According to some embodiments of the present disclosure, the well region 22 is an n-type well region formed by implanting an n-type impurity (which can be phosphorus, arsenic, antimony, etc.) into the substrate 20. The resulting well region 22 can extend to the top surface of the substrate 20. The n-type or p-type impurity concentration can be equal to or less than 10 18 cm -3 e.g., in the range between about 10 17 cm -3 and about 10 18 cm -3

[0021] Referring to Figure 2 an isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is optionally referred to as a shallow trench isolation (STI) region. The corresponding process is shown as Figure 24 ​Process 204 in the process flow 200 shown in the figure. The portion of the substrate 20 between adjacent STI regions 24 is referred to as the semiconductor strip 26. To form the STI regions 24, a pad oxide layer 27 and a hard mask layer (not shown) are formed on the semiconductor substrate 20, and then patterned. The pad oxide layer 27 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 27 is formed in a thermal oxidation process, in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 27 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer. The pad oxide layer 27 may also serve as an etch stop layer for etching the hard mask layer. According to some embodiments of the present disclosure, the hard mask layer is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer is formed by thermal nitridation of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer, and then patterned. Then, the patterned photoresist is used as an etch mask to pattern the hard mask layer to form a hard mask 29 as shown in Figure 2 shown.

[0022] Next, the patterned hard mask layer is used as an etch mask to etch the pad oxide layer 27 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with a (one or more) dielectric material. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to remove the excess portion of the dielectric material, and the remaining portion of the (one or more) dielectric materials is the STI region 24. The STI region 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc. formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI region 24 may also include a dielectric material located above the liner oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, etc. According to some embodiments, the dielectric material located above the liner dielectric may include silicon oxide.

[0023] The top surface of the hard mask 29 and the top surface of the STI region 24 can be substantially flush with each other. The semiconductor strip 26 is located between adjacent STI regions 24. According to some embodiments of the present disclosure, the semiconductor strip 26 is part of the original substrate 20, and thus the material of the semiconductor strip 26 is the same as the material of the substrate 20. In an alternative embodiment of the present disclosure, the semiconductor strip 26 is a replacement strip formed by etching the portion of the substrate 20 located between the STI regions 24 to form a groove, and performing epitaxy to regrow another semiconductor material in the groove. Thus, the semiconductor strip 26 is formed of a semiconductor material different from the semiconductor material of the substrate 20. According to some embodiments, the semiconductor strip 26 is formed of silicon germanium, silicon carbide, or a group III-V compound semiconductor material.

[0024] Reference Figure 3 , the STI region 24 is recessed. Thus, the top of the semiconductor strip 26 protrudes above the top surface 24A of the remaining portion of the STI region 24 to form a protruding fin 26'. The corresponding process is shown as Figure 24 Process 206 in the process flow 200 shown in. A dry etching process can be used to perform the etching, where, for example, HF3 and NH3 are used as etching gases. During the etching process, a plasma can be generated. Argon can also be included. According to an alternative embodiment of the present disclosure, a wet etching process is used to perform the recessing of the STI region 24. The etching chemical can include, for example, HF.

[0025] In the above embodiments, the fins can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the fins, including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with, for example, pitches smaller than those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer or mandrel can then be used to pattern the fins.

[0026] Figure 4 The formation of a dummy gate stack 34 according to some embodiments is shown, where the dummy gate stack 34 includes a dummy dielectric layer 28, a dummy gate electrode layer 30, and a hard mask 32. The corresponding process is shown as Figure 24Process 208 in process flow 200 shown in [].Dummy dielectric layer 28 is formed on sidewalls and top surfaces of protruding fins 26'.According to some embodiments of the present disclosure,a conformal deposition process is used to form dummy dielectric layer 28,which may include atomic layer deposition (ALD),chemical vapor deposition (CVD),etc.The material of dielectric layer 28 may include silicon oxide,silicon nitride,silicon carbonitride,etc.According to alternative embodiments,the formation of dielectric layer 28 includes (e.g.,using a thermal oxidation process) oxidizing surface portions of protruding fins 26'.The resulting dielectric layer 28 includes an oxide formed on exposed surfaces of protruding fins 26' (but not on top surfaces of STI regions 24).The formation of dielectric layer 28 may or may not include a deposition process.Dashed lines are used to indicate that some portions of dielectric layer 28 located on top of STI region 24 may or may not be formed,depending on the formation process.

[0027] Dummy gate electrode layer 30 is deposited on dielectric layer 28.Dummy gate electrode layer 30 may be formed of or include polysilicon or amorphous silicon,and other materials may also be used.The formation process may include a deposition process followed by a planarization process.Then,hard mask layer 32 is deposited on dummy gate electrode layer 30.Hard mask layer 32 may be formed of or include silicon nitride,silicon oxide,silicon oxy - carbo - nitride,or multiple layers thereof.

[0028] Next,with reference to Figure 5A ,hard mask layer 32 is patterned (e.g.,by etching using a patterned photoresist (not shown) as an etch mask),thereby forming hard mask strip 32'.The corresponding process is shown as Figure 24 process 210 in process flow 200 shown in []. Figure 5B shows a reference vertical cross - section 5B - 5B as shown in Figure 5A .In Figure 5A , Figure 5B and subsequent figures,the level of top surface 26T of protruding fin 26' is shown.Similarly,dummy gate dielectric layer 28 is formed of or includes a dielectric material,which may or may not be the same material as that of STI region 24.Therefore,dummy gate dielectric layer 28 is shown in Figure 5B ,but may not be shown separately in subsequent figures.Therefore,the top surface portion of STI region 24 shown in subsequent figures may be considered as dummy gate dielectric layer 28.

[0029] In a subsequent process, the dummy gate electrode layer 30 and the optional dummy gate dielectric layer 28 are patterned, where the hard mask strip 32' is used as an etch mask. Thereby, a dummy gate electrode 30' is formed, as Figure 6 shown. The dummy gate stack 34' may have a lower portion (also referred to as a narrowed portion) that is narrower and more tapered compared to the upper portion, and details of the dummy gate electrode 30' are as Figure 6E shown.

[0030] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D and Figure 6E illustrate intermediate stages of patterning the dummy gate electrode layer 30 according to some embodiments. Referring to Figure 6A , a first etch process 36 (which is an anisotropic etch process) is performed using the hard mask 32' as an etch mask. According to some embodiments, the process gas includes both an etch gas and a byproduct generating gas. The etch gas may include Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, or a combination thereof. The byproduct generating gas may include nitrogen (N2), oxygen (O2), SO2, CO2, CO, or a combination thereof. Other gases (e.g., Ar, He, Ne, etc.) may also be added to the process gas. According to some embodiments of the present disclosure, the etch process is performed using a source power in the range between about 10 watts and about 3000 watts. The bias power may be higher than about 200 watts and may be in the range between about 10 watts and about 3000 watts. The pressure of the process gas may be in the range between about 1 mTorr and about 800 mTorr. The flow rate of the process gas may be in the range between about 1 sccm and about 5000 sccm.

[0031] In the etch process 36, the surface layer of the formed dummy gate electrode 30' reacts with the byproduct generating gas to form a byproduct layer 38, which includes a portion on the sidewalls of the newly formed portion of the dummy gate electrode 30'. The corresponding process is shown as Figure 24 process 212 in the process flow 200 shown in. The byproduct layer 38 may be formed on the surface of the hard mask 32' (or may not be formed on the surface of the hard mask 32', as Figure 6F shown), depending on the composition of the hard mask 32'. Depending on the process gas, the byproduct layer 38 may include Si w O x N y C z 、SiBr a Cl b O cAnd so on. To generate the byproduct layer 38 and to make the byproduct layer 38 thick enough to serve as an etch mask in subsequent processes, more byproduct-generating gas is introduced. For example, the ratio of the flow rate of the byproduct-generating gas to the flow rate of the etch gas can be higher than about 40 and can be in the range between about 1 and about 1000. As the etching process 36 proceeds, the byproduct layer 38 extends downward, as Figure 6B shown. The thickness T1 of the byproduct layer 38 can be in the range between about and about . In the etching process 36, the plasma is turned on. The temperature of the corresponding wafer can be in the range between about 0 °C and about 150 °C.

[0032] According to some embodiments, after the etching process 36, the etch gas is stopped and the byproduct-generating gas continues to increase the thickness of the byproduct layer 38. The corresponding byproduct-generating gas can include N2, O2, SO2, CO2, CO, SiCl4, etc., or a combination thereof. In this process, the plasma can be turned on. The corresponding process is called a byproduct-thickening process. According to some embodiments, the byproduct-thickening process is performed in-situ (in the same process chamber) with the etching process 36 and the subsequent etching process 40 ( Figure 6C ), and there is no vacuum break between these processes. According to alternative embodiments, the byproduct-thickening process is performed ex-situ with processes 36 and 40, and there is a vacuum break between these processes. The ex-situ byproduct-thickening process can be performed using N2, O2, SO2, CO2, CO, etc., or a combination thereof as the process gas.

[0033] According to alternative embodiments, the byproduct-thickening process is performed using a chemical solution, which can include ozone and / or CO2 dissolved in deionized water, where the wafer 10 is immersed in the chemical solution to form the byproduct layer 38.

[0034] According to yet another alternative embodiment, in the etching process 36, the process gas includes the etch gas and does not include the byproduct-generating gas. Therefore, in the etching process 36, no byproduct layer is generated. The byproduct layer 38 is generated by the byproduct-thickening process, which can include the in-situ, ex-situ, or wet process as described above. According to some embodiments, in the in-situ, ex-situ, or wet process, the byproduct layer 38 is also formed on the exposed horizontal surface of the unetched portion of the dummy gate electrode layer 30, similar to as Figure 6GThe protective layer 38' shown. According to other embodiments, in some in-situ or non-in-situ processes, the by-product layer 38 is formed (or thickened) on the sidewalls, rather than being formed (or thickened) on the horizontal surface of the unetched portion of the dummy gate electrode layer 30.

[0035] Reference Figure 6C , after performing the first etching process 36, a second anisotropic etching process 40 is performed to further etch the dummy gate electrode layer 30 until the etching passes through the dummy gate electrode layer 30 to generate a dummy gate electrode 30'. The corresponding process is shown as Figure 24 Process 214 in the process flow 200 shown in. In the etching process 40, the plasma is turned on. The dummy gate dielectric layer 28 can then be patterned, or may not be patterned at this time. The second etching process 40 is performed using an etching gas, which may include Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, or a combination thereof. According to some embodiments, the process gas does not contain any by-product generating gas, which may include N2, O2, SO2, CO2, CO, etc. According to alternative embodiments, the process gas includes one or more by-product generating gases. However, compared with the etching process 36, the flow rate of the by-product generating gas is reduced. If the flow rates of the by-product generating gas in the etching processes 36 and 40 are respectively represented as BPFR 36 and BPFR 40 , then the ratio BPFR 40 / BPFR 36 can be less than about 0.2 or 0.1, and can be in the range between about 0 and 0.2 or 0.1. On the other hand, the flow rates of the etching gases in the etching processes 36 and 40 can be equal to each other, or can be different from each other. Therefore, basically no new by-product layer is generated in the etching process 40, or although a by-product layer 38 is generated through the etching process 40, the thickness T2 of the newly generated by-product layer 38 is less than the thickness T1. For example, in Figure 6C , the dashed line is used to show the by-product layer 38 generated in the etching process 40, and the by-product layer 38 has a thickness T2. According to some embodiments, the ratio T2 / T1 is less than about 0.2 or 0.1, and can be in the range between 0 and 0.2 or 0.1.

[0036] Figure 6CSeveral embodiments are shown, in which several possible positions of the bottom end 38BE of the by-product layer 38 are shown. Also shown is the level of the top surface 26T of the protruding fin 26'. In various embodiments, the bottom end 38BE can be higher than the top surface 26T of the protruding fin 26', flush with the top surface 26T of the protruding fin 26', or lower than the top surface 26T of the protruding fin 26'. For example, the bottom end 38BE of the by-product layer 38 can be higher by a height difference D1 compared to the fin top surface 26T, and the height difference D1 can be in the range between 0 nm and about 50 nm. The bottom end 38BE of the by-product layer 38 can be lower by a height difference D2 compared to the fin top surface 26T, and the height difference D2 can be in the range between 0 nm and about 100 nm.

[0037] Reference Figure 6D , after forming the dummy gate electrode 30', an etching process 42 is performed, which is also referred to as the reshaping process of the dummy gate electrode 30'. The corresponding process is shown as Figure 24 Process 216 in the process flow 200 shown in. According to some embodiments, the etching process 42 is performed using a process gas capable of etching the dummy gate electrode 30', and the process gas can be selected from Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, or a combination thereof. The process gas can be free of by-product generating gases (e.g., N2, O2, SO2, CO2, CO, etc.), or can include a small amount of by-product generating gases to adjust the etching process. Thus, no by-product layer is generated. The etching process 42 can be performed using a source power in the range between about 10 watts and about 3000 watts. The pressure of the process gas can be in the range between about 1 mTorr and about 800 mTorr. The flow rate of the process gas can be in the range between about 1 sccm and about 5000 sccm. Compared to the bias power used in processes 36 and 40, the bias power is reduced such that, in addition to the anisotropic effect, the etching process 42 also has some isotropic effects. The bias power can be less than about 40% of the bias power used in the etching processes 36 and 40, and can be in the range between about 5% and about 80%. According to some embodiments, the bias power used in the etching process 42 can be lower than about 100 watts, and can be in the range between about 10 watts and about 3000 watts.

[0038] According to some embodiments, as a result of the etching process 42, the dummy gate electrode 30' is shaped, and the resulting structure is shown in Figure 6D Thus, a dummy gate stack 34' is formed, and the dummy gate stack 34' can include the patterned dummy gate dielectric 28' ( Figure 7)(when it is patterned), or does not include the dummy gate dielectric 28’ (when it is not patterned). In the etching process 42, the by-product layer 38 partially protects the lower portion 30A’ of the dummy gate electrode 30’, which is below the bottom end 38BE of the by-product layer 38. Therefore, the by-product layer 38 is alternatively referred to as a protective layer. Since the etching process 42 also has an isotropic effect, there is also lateral etching on the lower portion 30A’ of the dummy gate electrode 30’. The upper portion of the lower portion 30A’ is more protected, and the lateral etching is less significant. The lower portion of the lower portion 30A’ is less protected, and the lateral etching is more significant. As a result, the lower portion 30A’ is tapered. Throughout the specification, the lower portion 30A’ is also referred to as a narrowed portion.

[0039] According to some embodiments, the lower portion 30A’ has inclined and straight sidewalls. The top width W2 is greater than the bottom width W3. According to some embodiments, the difference (W2 - W3) is greater than about The height H1 of the lower portion 30A’ can be greater than about The inclination angle θ1 of the sidewall of the lower portion 30A’ is less than 90 degrees, and can be less than about 88 degrees, or within the range of about 80 degrees and about 88 degrees.

[0040] The upper portion 30B’ has sidewalls that can be straight and more vertical compared to the lower portion, where the inclination angle θ2 is greater than θ1. According to some embodiments, the inclination angle θ2 is equal to or less than 90 degrees. The difference (θ2 - θ1) is greater than about 2 degrees, about 5 degrees or about 10 degrees, and can be within the range of about 1 degree and about 30 degrees. The height H2 of the upper portion 30B’ can be greater than about 40 nm, and can be within the range of about 10 nm to about 200 nm.

[0041] After the etching process 42, for example, the by-product layer 38 is removed in the etching process. The corresponding process is shown as Figure 24 process 218 in the process flow 200 shown in Figure 6E The resulting structure is shown in Figure 7 Next, as shown in Figure 24 a gate spacer 46 is formed on the sidewalls of the dummy gate stack 34’. The corresponding process is shown as

[0042] Then an etching process is performed. The portions of the protruding fins 26’ that are not covered by the dummy gate stack 34’ and the gate spacer 46 are etched, resulting in Figure 8 the structure shown inFigure 24 Process 222 in the process flow 200 shown in Figure 24 . The etching process can be anisotropic, so that the portions of the protruding fin 26' directly under the dummy gate stack 34' and the gate spacer 46 are protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 can be lower than the top surface 24A of the STI region 24. Accordingly, a groove 50 is formed. The groove 50 includes some portions on opposite sides of the dummy gate stack 34', and some portions between the remaining portions of the protruding fin 26'.

[0043] Next, an epitaxial region (source / drain region) 54 is formed by selectively growing a semiconductor material (by epitaxy) in the groove 50, resulting in Figure 9 the structure shown in Figure 9 . The corresponding process is shown as Figure 24 Process 224 in the process flow 200 shown in Figure 24 . Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type impurities or n-type impurities can be in-situ doped during the epitaxial process. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 54 includes a group III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or a multi-layer thereof. After filling the groove 50 with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and facets can be formed. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. Voids (air gaps) 56 may be generated.

[0044] After the epitaxial process, the epitaxial region 54 can be further implanted with p-type or n-type impurities to form the source region and the drain region, which are also denoted by the reference numeral 54. According to an alternative embodiment of the present disclosure, when the epitaxial region 54 is in-situ doped with p-type impurities or n-type impurities during epitaxy, the implantation step is skipped.

[0045] Figure 10 A perspective view of the structure after forming the contact etch stop layer (CESL) 58 and the interlayer dielectric (ILD) 60 is shown. The corresponding process is shown as Figure 24Process 226 in the process flow 200 shown. The CESL 58 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD 60 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. The ILD 60 can be formed of an oxygen-containing dielectric material, which can be a silicon oxide-based material, such as tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process, such as a CMP process or a mechanical polishing process, can be performed to make the top surfaces of the ILD 60, the dummy gate stack 34', and the gate spacers 46 flush with each other.

[0046] Then, the dummy gate stack 34' is removed. The portion of the dummy gate dielectric layer located on the protruding fin 26' is also removed to expose the protruding fin 26'. A replacement gate stack 66 and a self-aligned hard mask 68 are formed in the resulting trench. In Figure 11A the resulting structure is shown. The corresponding process is shown as Figure 24 process 228 in the process flow 200 shown. The gate stack 66 includes a gate dielectric 62 and a gate electrode 64. The gate dielectric 62 can include an interface layer (IL) (not shown) and a high-k dielectric layer. The IL is formed on the exposed surface of the protruding fin 26' and can include an oxide layer (e.g., a silicon oxide layer), which is formed by thermal oxidation, chemical oxidation process, or deposition process of the protruding fin 26'. The high-k dielectric layer includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc.

[0047] Further referring to Figure 11A the gate electrode 64 is formed on the gate dielectric 62. The gate electrode 64 can include a stacked layer, which can include a diffusion barrier layer (cap layer), and one or more work function layers located above the diffusion barrier layer. The diffusion barrier layer can be formed of titanium nitride, which can (or can not) be doped with silicon, titanium silicon nitride, etc. The work function layer determines the work function of the gate electrode and includes at least one layer, or multiple layers formed of different materials. The gate electrode 64 can also include a metal fill region, which can be formed of cobalt, tungsten, their alloys, or other metals or metal alloys, or include cobalt, tungsten, their alloys, or other metals or metal alloys.

[0048] Next, a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed so that the top surface of the gate stack 66 is coplanar with the top surface of the ILD 60. In a subsequent process, the gate stack 66 is etched back to obtain a recess formed between the opposing gate spacers 46. Next, a hard mask 80 is formed over the replacement gate stack 66. According to some embodiments of the present disclosure, the formation of the hard mask 80 includes a deposition process for forming a blanket dielectric material and a planarization process for removing the excess dielectric material located over the gate spacers 46 and the ILD 60. The hard mask 80 can be formed of, for example, silicon nitride or other similar dielectric materials. Thus, the FinFET 81 is formed.

[0049] Figure 11B - 1 , Figure 11B - 2 and Figure 11B - 3 show cross-sectional views of a replacement gate stack 66 according to some embodiments, where these cross-sectional views are obtained from Figure 11A reference cross-section 11B-11B in. The positions of the top surface 26T and the bottom end 26B of the protruding fin 26' are also marked, and the protruding fin 26' will extend between 26T and 26B, but the protruding fin 26' is not shown as it lies in a plane different from the plane shown. The lower portion 66A' of the replacement gate stack 66 replaces Figure 6D the lower portion 30A' of the dummy gate stack 30' in, and thus has the same profile as Figure 6D the lower portion 30A' of the dummy gate stack 30' in. As a result, the lower portion 30A' is tapered. Throughout the specification, the lower portion 66A' is also referred to as the narrowing portion. The upper portion 66B' of the replacement gate stack 66 replaces Figure 6D the upper portion 30B' of the dummy gate stack 30' in, and thus has the same profile as Figure 6D the upper portion 30B' of the dummy gate stack 30' in. Thus, the tilt angles θ1 and θ2 are the same as those discussed with reference to Figure 6D and the detailed details are not repeated here. In addition, the sidewall profile of the replacement gate stack 66 will follow Figure 6D the sidewall profile of the dummy gate stack 30' in.

[0050] Figure 11B - 1 shows an embodiment in which the joining level 82 of the lower portion 66A' and the corresponding upper portion 66B' is higher than the top surface 26T of the protruding fin 26'. Figure 11B - 2 shows an embodiment in which the joining level 82 is flush with the top surface 26T of the protruding fin 26'. Figure 11B - 3 shows an embodiment in which the joining level 82 is lower than the top surface 26T of the protruding fin 26'. The adjustment of the joining level 82 can include adjusting when to proceed from process 36 ( Figure 6B)Transition to Process 40( Figure 6C );Adjust the pressure, power, gas flow rate, and etch time of the etch processes 36 and 40. For example, increasing the pressure and power of the etch process can help form a thick enough by-product layer on the sidewalls of the lower portion of the dummy gate electrode 30’, and thus can help achieve Figure 11B - 3 in the embodiments. It should also be understood that since the high-k dielectric layer of the gate dielectric 62 can be conformal, the tilt angle of the gate stack 66 discussed above can also be equal to the tilt angle of the sidewalls of the corresponding portions of the gate electrode 64.

[0051] According to some embodiments, two directly adjacent replacement gate stacks 66 can have their bonding levels 82 different from each other. For example, one of the two directly adjacent replacement gate stacks 66 can adopt an embodiment as shown in Figure 11B - 1 、 Figure 11B - 2 and Figure 11B - 3 one of them, while the other of the two directly adjacent replacement gate stacks 66 can adopt a different embodiment as shown in Figure 11B - 1 、 Figure 11B - 2 and Figure 11B - 3 one of them.

[0052] Figure 6F 、 Figure 6G 、 Figure 6H and Figure 6I show the formation of the dummy gate stack 34’ according to alternative embodiments. Unless otherwise specified, the materials and formation processes of the components in these embodiments (and the embodiments in Figures 12 - 23 ) are substantially the same as those of the same components (represented by the same reference numerals) in the foregoing embodiments (shown by Figures 1 - 4 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D and Figure 6E ). Therefore, the details of the formation processes and materials of the components shown in Figure 6F 、 Figure 6G 、 Figure 6H and Figure 6I as well as Figures 12 - 23 can be found in the discussion of the foregoing embodiments.

[0053] The initial process is the same as that shown in Figures 1 - 4 、 Figure 5A and Figure 5B . Next, referring to Figure 6F , perform the etch process 40 (also denoted as 40A). The process details are the same as those referred to in Figure 6CThe process details are the same as those discussed for the etching process 40 in [reference]. Thus, the dummy gate electrode layer 30 is etched and no by-product layer is formed. Refer to [reference]. Figure 6G , for example, use ALD, CVD, PEALD, PECVD, etc. to deposit the protective layer 38'. The material of the protective layer 38' may include SiN, SiON, SiCON, SiC, SiOC, SiO2, etc. The thickness of the protective layer 38' can be in the range of about and about between. Next, refer to [reference]. Figure 6H , perform another etching process 40 (also denoted as 40B), which is carried out using process conditions that are substantially the same as those discussed in [reference]. Figure 6C Thus, the dummy gate electrode layer 30 is etched through to form the dummy gate electrode 30'.

[0054] Figure 6I shows an etching process 42 for shaping the profile of the dummy gate electrode 30'. The process details can be found in [reference] and will not be repeated here. The profile of the dummy gate electrode 30' can also be found in the discussion of [reference]. Then, the protective layer 38' is removed by etching. The remaining processes for forming the FinFET 81 are shown in Figure 6D [reference], Figure 6D [reference], Figures 7 - 11A [reference], Figure 11B - 1 [reference], Figure 11B - 2 [reference], Figure 11B - 3 and [reference].

[0055] As shown in Figure 6D and Figure 6I , the dummy gate electrode 30' has a narrowed portion 30A' and a transition region where the lower portion starts to narrow downwards. According to an alternative embodiment, the dummy gate electrode can have more than one (e.g., two, three, four, or more) narrowed portions. Figures 12 to 15 shows the process for forming a dummy gate electrode 34' having two narrowed portions, where the sidewalls of the lower part are more inclined compared to the corresponding upper part. The process can start from the structure shown in Figure 6D and the corresponding structure is as shown in Figure 12 . Accordingly, Figure 12 the formation of the structure shown can include a first etching process 36 ( Figure 6A and Figure 6B ), a second etching process 40 ( Figure 6C ), and a third etching process 42 ( Figure 6D ).

[0056] Next, refer to [reference]. Figure 13 , perform another etching process 36 (denoted as 36B). The process can be referred to in Figure 6A andFigure 6B Find the details of the etching process 36, and the process gas includes an etching gas and a by-product generating gas. Since the etching is anisotropic, the lower portion 30A' is not actually etched. At the same time, the by-product layer 38 extends downward onto the inclined sidewalls of the dummy gate electrode 30'. According to some embodiments, the position of the bottom end of the by-product layer 38 is determined by adjusting the corresponding process. For example, the pressure of the process gas is adjusted to be neither too high nor too low. If the pressure is too high, the by-product layer 38 extends downward too much and may even form a conformal layer on the entire surface of the dummy gate electrode 30'. If the pressure is too low, the by-product layer 38 cannot extend downward the required distance. According to some embodiments, the pressure is in the range between about 1 mTorr and about 800 mTorr. Similarly, too high a source power may cause the by-product layer 38 to extend downward too much, and too low a source power may cause the by-product layer 38 to extend downward insufficiently. According to some embodiments, the source power is in the range between about 10 watts and about 3000 watts. The bias power is lower than the bias power used in both the etching processes 36 and 40 in order to have both anisotropic and isotropic effects in the etching process. According to some embodiments, the bias power is in the range between about 10 watts and about 3000 watts. In addition, N2 is more reactive than O2, and more N2 can cause the by-product layer 38 to extend more. According to some embodiments, compared with Figure 6A and Figure 6B the etching process 36 in Figure 13 as shown in

[0057] Figure 14 Another etching process 42 (denoted as 42C) is shown. The process conditions can be substantially the same as those in Figure 6D In place of Figure 6D the bias power used in the process 42 shown in

[0058] Figure 15 A replacement gate stack 66 is shown, which replaces Figure 14Dummy gate stack 34' therein. The resulting replacement gate stack 66 has the same profile as the dummy gate stack 34' and has the tilt angles θ1, θ2, and θ3 as discussed with reference to Figure 14 The possible level of the top surface 26T of the protruding fin 26' is also shown.

[0059] Figures 16 - 23 A process for selectively shaping the dummy gate stack 34' according to some embodiments is shown. Similarly, details of the processes and materials of these embodiments can be found in similar processes and materials as discussed in the previous embodiments. Referring to Figure 16 , the STI region 24 is formed to extend into the substrate 20. The gate dielectric layer 28, the gate electrode layer 30, and the hard mask 32' are formed. The formation process is substantially the same as that shown in Figures 1 - 4 , Figure 5A and Figure 5B and will not be repeated here. Similarly, since a cross-sectional view in Figure 16 is obtained across the STI region 24 and both the gate dielectric layer 28 and the STI region 24 are dielectric, the gate dielectric layer 28 is not shown separately in the subsequent figures.

[0060] Figure 17 An etching process 36 is shown, and details of the etching process 36 can be found with reference to Figure 6A and Figure 6B Thus, a by-product layer 38 is formed. Next, referring to Figure 18 , an etching process 40 is performed to etch through the gate electrode layer 30 and form the dummy gate electrode 30'. Details of the etching processes 36 and 40 can be found in the foregoing embodiments. No new by-product layer is formed by the etching process 40, or the by-product layer (if formed) is very thin, similar to that shown in Figure 6C Similarly, the bottom end of the by-product layer 38 can be higher than, flush with, or lower than the top surface 26T of the protruding fin 26' (the possible levels are shown).

[0061] Figure 19 The formation of an etching mask 84 (which can be a photoresist) according to some embodiments is shown. The etching mask 84 partially or completely protects some of the dummy gate electrodes 30' and leaves some other dummy gate electrodes 30' uncovered. Next, referring to Figure 20 , an etching process 42 is performed. Details of the etching process 42 can be found in the foregoing embodiments. The sidewalls of the dummy gate electrodes 30' exposed to the etching gas are shaped. The profile of the shaped sidewalls can be substantially the same as that of the shaped sidewalls shown in Figure 6D and can be referred to Figure 6DDetails can be found in the discussion. The other sidewalls of the dummy gate electrode 30' protected by the etch mask 84 are not shaped. Additionally, an example is shown where the right sidewall of the rightmost dummy gate electrode 30' is not shaped because the distance of the sidewall is close enough to the etch mask that the etch gas cannot reach the sidewall. Throughout the specification, the shaped (and thus more inclined) sidewalls are denoted as 30SL (where SL stands for "slanted"), and the unshaped (and thus more straight) sidewalls are denoted as 30ST (ST stands for "straight"). Similarly, letters "A", "B", "C", "D", etc. are added to identify the respective sidewalls. Refer to Figure 22 and Figure 23 the profile of the dummy gate electrode 30' is discussed.

[0062] Next, the etch mask 84 is removed, and Figure 21 the resulting structure is shown. Then, the by-product layer 38 is removed, and Figure 22 the resulting structure is shown. Figures 7 - 10 、 Figure 11A 、 Figure 11B - 1 、 Figure 11B - 2 and Figure 11B - 3 show the remaining processes for forming a FinFET (which is similar to FinFET 81). Figure 23 shows the corresponding replacement gate stack 66 (which replaces the dummy gate stack 34').

[0063] Figure 22 and Figure 23 show profiles such as the inclined edges of the dummy gate electrode 30' and the replacement gate stack 66 and the inclined angles θ1 and θ2. Some sidewalls of the dummy gate electrode 30' and the replacement gate stack 66 have lower parts that are more inclined compared to the corresponding upper parts. For example, the lower sidewall portions 30SLA, 30SLB, 30SLC, and 30SLD are more inclined than the corresponding upper parts of the respective sidewalls. On the other hand, some other lower parts 30STA, 30STB, 30STC, and 30STD and their corresponding upper parts form continuous straight sidewalls. Additionally, the dummy gate electrode 30' (and the corresponding replacement gate electrode) (e.g., the second dummy gate electrode 30' counted from the right side of Figure 22 can have one inclined lower sidewall while the opposite sidewall is straight and less inclined. Some dummy gate electrodes 30' can have sidewalls where both lower parts are more inclined than the upper part, and some other dummy gate electrodes 30' can have sidewalls where both lower parts have the same inclined angle as the corresponding upper part.

[0064] Furthermore, Figure 15 the embodiments in Figures 16 - 23In the embodiments, each of the inclined sidewalls 30SLA, 30SLB, 30SLC, and 30SLD can have more than one (e.g., between about 2 and about 10) straight and inclined portions, where each lower portion is straight and becomes more inclined compared to the corresponding upper portion.

[0065] According to some embodiments, the distance S1 between some fins is less than the distance S2. For example, the ratio S2 / S1 is greater than about 2.0. The dummy gate electrode 30' having the distance S1 is referred to as being in a pattern-dense region, and the dummy gate electrode 30' having the distance S2 is referred to as being in a pattern-iso region. The sidewall profiles of the dummy gate and replacement gate may be affected by whether the corresponding FinFET is in a pattern-dense region or a pattern-iso region, and such sidewall profiles may be undesirable. According to some embodiments of the present disclosure, by forming an etch mask 84 in a selected region, the sidewall profile of the dummy gate electrode 30' is controllable and not determined by whether the corresponding dummy gate electrode 30' is in a pattern-dense region or a pattern-iso region, and can be adjusted individually by the etch mask 84.

[0066] As Figure 23 The embodiments shown can be used to meet both performance requirements and reliability requirements. For example, for a dummy gate electrode with a narrowed lower portion, the corresponding transistor has better performance. However, the dummy gate electrodes of these transistors are prone to collapse. On the other hand, FinFETs with straight dummy gate electrodes are not prone to collapse, but the resulting FinFETs may not perform as well as those with a narrowed lower portion. By adopting the embodiments as Figures 16 - 23 shown, FinFETs with higher performance requirements can adopt inclined sidewalls, while other FinFETs can adopt straight sidewalls to have a better yield.

[0067] Embodiments of the present disclosure have some advantageous features. By etching the dummy gate electrode to have a tapered lower portion, the performance of the resulting FinFET is improved, and the saturation current is increased. By selectively forming inclined sidewalls for selected dummy gate electrodes, the requirements for improving performance and reliability are balanced.

[0068] According to some embodiments of the present disclosure, a method includes: depositing a dummy gate dielectric layer over a semiconductor region; depositing a dummy gate electrode layer over the dummy gate dielectric layer; performing a first etching process, wherein an upper portion of the dummy gate electrode layer is etched to form an upper portion of the dummy gate electrode; forming a protective layer on sidewalls of the upper portion of the dummy gate electrode; performing a second etching process, wherein a lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode; performing a third etching process using the protective layer as an etching mask to etch the lower portion of the dummy gate electrode, wherein the dummy gate electrode is tapered by the third etching process; removing the protective layer; and replacing the dummy gate electrode with a replacement gate electrode. In an embodiment, the protective layer is formed simultaneously when the first etching process is performed. In an embodiment, the first etching process is performed using a process gas including an etching gas and a by-product generating gas. In an embodiment, the method further includes: forming an additional etching mask to cover an additional dummy gate electrode after the second etching process and before the third etching process; and removing the additional etching mask after the third etching process. In an embodiment, the protective layer is a by-product layer generated by the first etching process, and the protective layer includes silicon and oxygen atoms. In an embodiment, the by-product layer further contains bromine and chlorine. In an embodiment, the first etching process and the second etching process are anisotropic, and the third etching process has both anisotropic and isotropic effects. In an embodiment, the first etching process and the second etching process are performed using a first bias power, and the third etching process is performed using a second bias power lower than the first bias power. In an embodiment, removing the protective layer is achieved by etching.

[0069] According to some embodiments of the present disclosure, a structure includes: a protruding semiconductor fin; a first gate stack on the protruding semiconductor fin, wherein the first gate stack includes a first sidewall, and the first sidewall includes: a first lower straight portion having a first tilt angle; and a first upper straight portion having a second tilt angle greater than the first tilt angle; and a first gate spacer in contact with both the first lower straight portion and the first upper straight portion of the first gate stack. In an embodiment, the first gate stack further includes a second sidewall opposite to the first sidewall, and wherein the second sidewall includes: a second lower straight portion having the first tilt angle; and a second upper straight portion having the second tilt angle. In an embodiment, the first gate stack further includes a second sidewall opposite to the first sidewall, and wherein the entirety of the second sidewall is substantially straight. In an embodiment, the structure further includes a second gate stack, and the second gate stack includes a third sidewall, and wherein the entirety of the third sidewall is substantially straight. In an embodiment, the first sidewall of the first gate stack further includes: a bottom straight portion below and joined to the first lower straight portion, and the bottom straight portion has a third tilt angle less than the first tilt angle. In an embodiment, the difference between the second tilt angle and the first tilt angle is greater than about 5 degrees.

[0070] According to some embodiments of the present disclosure, a structure includes: a semiconductor fin; a gate dielectric on the semiconductor fin; a gate electrode over the gate dielectric, wherein the gate electrode includes: an upper portion having a first sidewall; a lower portion below and joined to the upper portion, and the lower portion has a second sidewall joined to the first sidewall, and wherein the first sidewall is more upright than the second sidewall, and there is a sudden change in the tilt angles of the first sidewall and the second sidewall; and a gate spacer in contact with the first sidewall and the second sidewall. In an embodiment, the gate electrode further includes a bottom below and joined to the lower portion, and the bottom has a third sidewall joined to the second sidewall, and wherein the third sidewall is more tilted than the second sidewall, and there is a sudden change in the tilt angles of the second sidewall and the third sidewall. In an embodiment, the upper portion further includes a third sidewall opposite to the first sidewall, and the lower portion further includes a fourth sidewall opposite to the second sidewall, and wherein there is a sudden change in the tilt angles of the third sidewall and the fourth sidewall. In an embodiment, the upper portion further includes a third sidewall opposite to the first sidewall, and the lower portion further includes a fourth sidewall opposite to the second sidewall, and wherein the third sidewall and the fourth sidewall are part of the same continuous and straight sidewall. In an embodiment, the gate electrode includes a metal, and the gate dielectric includes a high-k dielectric material.

[0071] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0072] Example 1. A method of manufacturing a semiconductor structure, comprising: depositing a dummy gate dielectric layer over a semiconductor region; depositing a dummy gate electrode layer over the dummy gate dielectric layer; performing a first etching process, wherein an upper portion of the dummy gate electrode layer is etched to form an upper portion of the dummy gate electrode; forming a protective layer on sidewalls of the upper portion of the dummy gate electrode; performing a second etching process, wherein a lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode; using the protective layer as an etching mask to perform a third etching process to etch the lower portion of the dummy gate electrode, wherein the dummy gate electrode is tapered by the third etching process; removing the protective layer; and replacing the dummy gate electrode with a replacement gate electrode.

[0073] Example 2. The method according to Example 1, wherein the protective layer is formed simultaneously when the first etching process is performed.

[0074] Example 3. The method according to Example 2, wherein the first etching process is performed using a process gas comprising an etching gas and a by-product generating gas.

[0075] Example 4. The method according to Example 1, further comprising: forming an additional etching mask to cover an additional dummy gate electrode after the second etching process and before the third etching process; and removing the additional etching mask after the third etching process.

[0076] Example 5. The method according to Example 1, wherein the protective layer is a by-product layer generated by the first etching process, and the protective layer comprises silicon and oxygen atoms.

[0077] Example 6. The method according to Example 5, wherein the by-product layer further comprises bromine and chlorine.

[0078] Example 7. The method according to Example 1, wherein the first etching process and the second etching process are anisotropic, and the third etching process has both anisotropic and isotropic effects.

[0079] Example 8. The method according to Example 1, wherein the first etching process and the second etching process are performed using a first bias power, and the third etching process is performed using a second bias power lower than the first bias power.

[0080] Example 9. The method according to Example 1, wherein the removal of the protective layer is achieved by etching.

[0081] Example 10. A semiconductor structure, comprising: a protruding semiconductor fin; a first gate stack on the protruding semiconductor fin, wherein the first gate stack includes a first sidewall, and the first sidewall includes: a first lower straight portion having a first tilt angle; and a first upper straight portion having a second tilt angle greater than the first tilt angle; and a first gate spacer in contact with both the first lower straight portion and the first upper straight portion of the first gate stack.

[0082] Example 11. The semiconductor structure according to Example 10, wherein the first gate stack further includes a second sidewall opposite to the first sidewall, and wherein the second sidewall includes: a second lower straight portion having the first tilt angle; and a second upper straight portion having the second tilt angle.

[0083] Example 12. The semiconductor structure according to Example 10, wherein the first gate stack further includes a second sidewall opposite to the first sidewall, and wherein the entirety of the second sidewall is straight.

[0084] Example 13. The semiconductor structure according to Example 10, further comprising a second gate stack, the second gate stack including a third sidewall, and wherein the entirety of the third sidewall is straight.

[0085] Example 14. The semiconductor structure according to Example 10, wherein the first sidewall of the first gate stack further includes: a bottom straight portion below and joined to the first lower straight portion, wherein the bottom straight portion has a third tilt angle smaller than the first tilt angle.

[0086] Example 15. The semiconductor structure according to Example 10, wherein the difference between the second tilt angle and the first tilt angle is greater than 5 degrees.

[0087] Example 16. A semiconductor structure includes: a semiconductor fin; a gate dielectric on the semiconductor fin; a gate electrode over the gate dielectric, wherein the gate electrode includes: an upper portion having a first sidewall; and a lower portion below the upper portion and joined to the upper portion, wherein the lower portion has a second sidewall joined to the first sidewall, and wherein the first sidewall is more upright than the second sidewall and there is a sudden change in the inclination angles of the first sidewall and the second sidewall; and a gate spacer in contact with the first sidewall and the second sidewall.

[0088] Example 17. The semiconductor structure according to Example 16, wherein the gate electrode further includes a bottom portion below the lower portion and joined to the lower portion, wherein the bottom portion has a third sidewall joined to the second sidewall, and wherein the third sidewall is more inclined than the second sidewall and there is a sudden change in the inclination angles of the second sidewall and the third sidewall.

[0089] Example 18. The semiconductor structure according to Example 16, wherein the upper portion further includes a third sidewall opposite to the first sidewall, and the lower portion further includes a fourth sidewall opposite to the second sidewall, and wherein there is a sudden change in the inclination angles of the third sidewall and the fourth sidewall.

[0090] Example 19. The semiconductor structure according to Example 16, wherein the upper portion further includes a third sidewall opposite to the first sidewall, and the lower portion further includes a fourth sidewall opposite to the second sidewall, and wherein the third sidewall and the fourth sidewall are parts of the same continuous and straight sidewall.

[0091] Example 20. The semiconductor structure according to Example 16, wherein the gate electrode includes a metal and the gate dielectric includes a high-k dielectric material.

Claims

1. A method of manufacturing a semiconductor structure, comprising: Deposit a dummy gate dielectric layer over the semiconductor region; Deposit a dummy gate electrode layer over the dummy gate dielectric layer; Perform a first etching process, wherein an upper portion of the dummy gate electrode layer is etched to form an upper portion of the dummy gate electrode; Form a protective layer on sidewalls of the upper portion of the dummy gate electrode; Perform a second etching process, wherein a lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode; After the second etching process, form an additional etching mask to cover an additional dummy gate electrode; After forming the additional etching mask, use the protective layer as an etching mask to perform a third etching process to etch the lower portion of the dummy gate electrode, wherein the dummy gate electrode becomes tapered through the third etching process; After the third etching process, remove the additional etching mask; Remove the protective layer; and Replace the dummy gate electrode with a replacement gate electrode.

2. The method according to claim 1, wherein, The protective layer is formed simultaneously when the first etching process is performed.

3. The method according to claim 2, wherein, The first etching process is performed using a process gas including an etching gas and a by-product generating gas.

4. The method according to claim 1, wherein, The protective layer is a by-product layer generated by the first etching process, and the protective layer includes silicon and oxygen atoms.

5. The method according to claim 4, wherein, The by-product layer further includes bromine and chlorine.

6. The method according to claim 1, wherein, The first etching process and the second etching process are anisotropic, and the third etching process has both anisotropic and isotropic effects.

7. The method according to claim 1, wherein, The first etching process and the second etching process are performed using a first bias power, and the third etching process is performed using a second bias power lower than the first bias power.

8. The method according to claim 1, wherein, Removing the protective layer is achieved by etching.

9. A semiconductor structure, comprising: A protruding semiconductor fin; A first gate stack on the protruding semiconductor fin, wherein the first gate stack includes a first sidewall, and the first sidewall includes: A first lower straight portion having a first tilt angle; and A first upper straight portion having a second tilt angle greater than the first tilt angle; and a first gate spacer in contact with both the first lower straight portion and the first upper straight portion of the first gate stack, wherein the first sidewall of the first gate stack further includes: A bottom straight portion below and joined to the first lower straight portion, wherein the bottom straight portion has a third tilt angle less than the first tilt angle.

10. The semiconductor structure according to claim 9, wherein, The first gate stack further includes a second sidewall opposite to the first sidewall, and wherein the second sidewall includes: A second lower straight portion having the first tilt angle; and A second upper straight portion having the second tilt angle.

11. The semiconductor structure according to claim 9, wherein, The first gate stack further includes a second sidewall opposite to the first sidewall, and wherein the entirety of the second sidewall is straight.

12. The semiconductor structure according to claim 9, further comprising a second gate stack, the second gate stack comprising a third sidewall, and wherein, The entirety of the third sidewall is straight.

13. The semiconductor structure according to claim 9, wherein, The difference between the second tilt angle and the first tilt angle is greater than 5 degrees.

14. A semiconductor structure, comprising: A semiconductor fin; A gate dielectric on the semiconductor fin; A gate electrode on the gate dielectric, wherein the gate electrode includes: An upper portion having a first sidewall; and A lower part, below the upper part and joined to the upper part, wherein the lower part has a second sidewall joined to the first sidewall, and wherein the first sidewall is more upright than the second sidewall, and there is a sudden change in the inclination angles of the first sidewall and the second sidewall; and A gate spacer, in contact with the first sidewall and the second sidewall, wherein the gate electrode further includes a bottom, below the lower part and joined to the lower part, wherein the bottom has a third sidewall joined to the second sidewall, and wherein the third sidewall is more inclined than the second sidewall, and there is a sudden change in the inclination angles of the second sidewall and the third sidewall.

15. The semiconductor structure according to claim 14, wherein, The upper part further includes a fourth sidewall opposite to the first sidewall, and the lower part further includes a fifth sidewall opposite to the second sidewall, and wherein there is a sudden change in the inclination angles of the fourth sidewall and the fifth sidewall.

16. The semiconductor structure according to claim 14, wherein, The upper part further includes a fourth sidewall opposite to the first sidewall, and the lower part further includes a fifth sidewall opposite to the second sidewall, and wherein the fourth sidewall and the fifth sidewall are parts of the same continuous and straight sidewall.

17. The semiconductor structure according to claim 14, wherein, The gate electrode includes a metal, and the gate dielectric includes a high-k dielectric material.

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