Display substrate, display device

Abstract

The present invention provides a display substrate and a display device, relating to the technical field of displays. To solve the problem that the transient large current entering the fan-out line from the driving chip is likely to damage the via hole between the fan-out line and the signal line, resulting in the vertical dark line defect in the display panel. The display substrate includes: a display area and a peripheral area surrounding the display area, and the peripheral area includes a fan-out area; the display substrate further includes: a plurality of first signal lines, a plurality of fan-out lines, and a plurality of first electrostatic protection circuits, the first signal lines extend from the display area to the peripheral area; the fan-out lines are located in the fan-out area; the fan-out lines are coupled to the corresponding first signal lines; the plurality of fan-out lines include a plurality of target fan-out lines, and the target fan-out lines are arranged in a different layer from the first signal lines to which they are coupled; the first electrostatic protection circuits are located in the fan-out area, and the first electrostatic protection circuits are coupled to the corresponding fan-out lines for releasing the static electricity on the fan-out lines. The display substrate provided by the present invention is used to form a display device.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular, to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, display products are increasingly developing towards narrow bezels. To meet the development requirements of narrow bezels, the width of the fan-out region in the display panel becomes narrower, and the fan-out lines in the fan-out region layout adopt an alternating layout of a gate metal layer and a source-drain metal layer for the fan-out lines. When the data lines are made of a source-drain metal layer, when the fan-out lines made of a gate metal layer are coupled to the corresponding data lines, via holes and conductive bridging portions are required, that is, the conductive bridging portions are respectively coupled to the corresponding fan-out lines and data lines through the via holes.

[0003] Although the above structure is beneficial to the development of narrow bezels of the display panel, after a large current enters the fan-out lines from the driving chip of the display panel, it first passes through the via holes in the fan-out region. Such a transient large current is extremely likely to damage the via holes, resulting in vertical dark line defects in the display panel. Summary of the Invention

[0004] The purpose of the present invention is to provide a display substrate and a display device, which are used to solve the problem that the transient large current entering the fan-out lines from the driving chip is likely to damage the via holes between the fan-out lines and the signal lines, resulting in vertical dark line defects in the display panel.

[0005] To achieve the above purpose, the present invention provides the following technical solutions:

[0006] A first aspect of the present invention provides a display substrate, including: a display area and a peripheral area surrounding the display area, the peripheral area including a fan-out area; the display substrate further includes:

[0007] A plurality of first signal lines, the first signal lines extending from the display area to the peripheral area;

[0008] A plurality of fan-out lines, the fan-out lines being located in the fan-out area; the fan-out lines are coupled to the corresponding first signal lines; the plurality of fan-out lines include a plurality of target fan-out lines, and the target fan-out lines are arranged in a different layer from the first signal lines to which they are coupled;

[0009] A plurality of first electrostatic protection circuits, the first electrostatic protection circuits being located in the fan-out area, the first electrostatic protection circuits being coupled to the corresponding fan-out lines, and being used to release static electricity on the fan-out lines.

[0010] Optionally, the display substrate further includes:

[0011] A plurality of conductive connection portions, the conductive connection portions being respectively coupled to the corresponding target fan-out lines and the corresponding first signal lines; a positive projection of the first electrostatic protection circuit on the substrate of the display substrate is located on a side of a positive projection of the conductive connection portion on the substrate away from the display area.

[0012] Optionally, the display substrate further includes a common signal line; the first electrostatic protection circuit includes:

[0013] A first transistor, a gate of the first transistor is coupled to the common signal line, a first pole of the first transistor is coupled to the corresponding fan-out line, and a second pole of the first transistor is coupled to the common signal line;

[0014] A second transistor, a gate of the second transistor is coupled to the corresponding fan-out line, a first pole of the second transistor is coupled to the corresponding fan-out line, and a second pole of the second transistor is coupled to the common signal line.

[0015] Optionally, the display substrate further includes:

[0016] A bonding area, the fan-out area is located between the display area and the bonding area;

[0017] A plurality of second electrostatic protection circuits, the second electrostatic protection circuits are coupled to the corresponding fan-out lines, and the second electrostatic protection circuits are located between the first electrostatic protection circuit and the bonding area for releasing static electricity on the fan-out lines.

[0018] Optionally, the second electrostatic protection circuit includes: at least one third transistor, the at least one third transistor is arranged along an extending direction of a fan-out line corresponding to the second electrostatic protection circuit, and a gate, a first pole, and a second pole of the third transistor are all coupled to the corresponding fan-out line.

[0019] Optionally, the second electrostatic protection circuit includes: a plurality of third transistors, and along a direction from the fan-out area to the bonding area, channel width-to-length ratios of the plurality of third transistors gradually decrease.

[0020] Optionally, the display substrate further includes: a plurality of sub-pixels, the plurality of sub-pixels are located in the display area, and the sub-pixels include driving transistors; channel width-to-length ratios of the plurality of third transistors are smaller than channel width-to-length ratios of the driving transistors.

[0021] Optionally, the display substrate includes a gate metal layer and a source-drain metal layer, the target fan-out line is provided on the same layer and made of the same material as the gate metal layer, non-target fan-out lines among the plurality of fan-out lines are provided on the same layer and made of the same material as the source-drain metal layer, and the non-target fan-out lines and the corresponding first signal lines form an integral structure.

[0022] Optionally, the display substrate further includes:

[0023] A plurality of third electrostatic protection circuits located between the display area and the fan-out area, and the third electrostatic protection circuits are coupled to the corresponding first signal lines for releasing static electricity on the first signal lines.

[0024] Optionally, the display substrate further includes:

[0025] A plurality of virtual transistor groups, each virtual transistor group including at least one virtual transistor, the at least one virtual transistor being arranged along the extension direction of the first signal line corresponding to the virtual transistor group, and a first pole of the virtual transistor being coupled to the first signal line; a gate of the virtual transistor and a second pole of the virtual transistor are both floating.

[0026] The virtual transistor groups are multiplexed as the third electrostatic protection circuits.

[0027] Optionally, the virtual transistor group includes a plurality of virtual transistors, and along the direction from the display area to the fan-out area, the channel width-to-length ratios of the plurality of virtual transistors gradually decrease.

[0028] Optionally, the display substrate further includes:

[0029] A plurality of sub-pixels located in the display area, each sub-pixel including a driving transistor, and the channel width-to-length ratio of the driving transistor is greater than that of a part of the virtual transistors and less than that of another part of the virtual transistors.

[0030] Based on the above technical solution of the display substrate, a second aspect of the present invention provides a display device including the above display substrate.

[0031] Optionally, the display device further includes a counter substrate and a liquid crystal layer, the counter substrate being disposed opposite to the display substrate, and the liquid crystal layer being located between the display substrate and the counter substrate.

[0032] In the technical solution provided by the present invention, a first electrostatic protection circuit is arranged in the fan-out area, and the first electrostatic protection circuit is coupled to the corresponding fan-out line. In this way, when a large-current static electricity enters the fan-out line from the driving chip, it first passes through the first electrostatic protection circuit, then passes through the position where the fan-out line is coupled to the first signal line, and then enters the first signal line. Therefore, in the technical solution provided by the present invention, when the large-current static electricity passes through the first electrostatic protection circuit, the first electrostatic protection circuit can release the large-current static electricity, avoiding the transient large current from damaging the coupling point between the fan-out line and the first signal line, thereby avoiding the vertical dark line defect in the display device when the display substrate is applied to the display device. Moreover, the first electrostatic protection circuit releases the large-current static electricity, and also avoids the large current directly damaging several rows of driving transistors near the peripheral area in the display area, thereby avoiding the defect of bright and dark spots formed by some sub-pixels due to the short circuit of the source and drain electrodes of the driving transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present invention and form a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0034] Figure 1 Schematic diagram of the first electrostatic protection circuit of the display substrate provided by the embodiment of the present invention;

[0035] Figure 2 is Figure 1 Cross-sectional view along the A1A2 direction in;

[0036] Figure 3 Schematic diagram of the new electrostatic protection circuit of the display substrate provided by the embodiment of the present invention;

[0037] Figure 4 is Figure 3 Cross-sectional view along the B1B2 direction in;

[0038] Figure 5 is Figure 3 Cross-sectional view along the C1C2 direction in;

[0039] Figure 6 Schematic diagram of the third electrostatic protection circuit of the display substrate provided by the embodiment of the present invention;

[0040] Figure 7 is Figure 6 Cross-sectional view along the D1D2 direction in. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] In order to further illustrate the display substrate and the display device provided by the embodiments of the present invention, the following will be described in detail with reference to the accompanying drawings of the specification.

[0042] At present, organic light-emitting diodes (OLEDs) and thin-film transistor-liquid crystal devices (TFT-LCDs) are both developing towards narrow bezels in order to improve the display effect and screen-to-body ratio.

[0043] Since the COG (chip on glass) method is less costly than the COF packaging method, it is widely used in display panels. In a display panel using the COG method, the driving chip (Source IC) is directly bonded to the array substrate in the display panel. The data signal provided by the driving chip can be transmitted to the data line through the fan-out line. During the data signal transmission process, after entering the data line from the fan-out line, it passes through the ESD (electro-static discharge) static ring and the Dummy area in sequence, and finally enters the display area.

[0044] At the same time, since the bezel where the display panel bonding area is located becomes narrower, the wiring of the fan-out lines will be more dense. In order to layout more fan-out lines in the limited layout space, a method of alternately laying out the fan-out lines with the gate metal layer and the source-drain metal layer is considered. When the data line is made of the source-drain metal layer, when the fan-out line made of the gate metal layer is coupled to the corresponding data line, via holes and conductive bridging parts are required, that is, the conductive bridging parts are respectively coupled to the corresponding fan-out line and data line through the via holes.

[0045] In addition, since the driving chip bonding area needs to be connected to the driving chip, a conductive bridging part is also required for connection. The driving chip bonding area is located in the pad area of the display panel. During the production process of the display panel, such as in the module section, ESD situations may occur due to equipment or human factors during the processes of polarizer lamination and driving chip bonding. The generated static electricity enters the fan-out line through the conductive bridging part on the surface of the bonding area and leads to the display area. Moreover, before the array substrate and the color filter substrate are aligned, a large amount of static electricity is also generated during the TFT-LCD rubbing process. The conductive bridging part in the bonding area is the outermost film layer and there is no film layer for isolating static electricity to protect it. Therefore, static electricity can be introduced into the display area during the related support processes of the display panel, thereby damaging and burning the via holes, resulting in vertical dark lines in the display panel or damaging the first few driving thin film transistors in the display area, causing bright and dark spot defects. In addition, during the process of assembling the whole machine at the client side, there may also be a situation where a large ESD current enters the display panel from the driving chip and causes damage.

[0046] An ESD static ring is set in the display panel, which can eliminate the influence of ESD. However, in order to prevent large leakage currents from occurring when the thin-film transistors (TFTs) in the ESD static ring are operating normally (the signal lines are often connected to the Com traces through the ESD unit), resulting in signal loss or crosstalk, the TFT channel length L is often relatively large. The relatively large channel length design leads to a relatively large impedance of the TFT, so the ability to resist transient ESD large currents is relatively weak. Often, the transfer holes in the display panel and the TFTs in the display area become the weak points that are first broken down by the ESD large current. The order of the ease of breakdown of the three is: the TFT in the display area ≈ the transfer holes in the fan-out area < the ESD static ring.

[0047] It can be seen that after the large current enters the fan-out line from the driving chip, it first passes through the transfer holes in the fan-out area, and there is no protection for the transfer holes before that. The transient large current is very likely to damage the transfer holes, resulting in vertical dark line defects in the display panel. In addition, part of the large current enters the display area through the transfer holes. Except for the ESD static ring (whose effect is not significant enough), there is no effective protection measure either. For the case where the fan-out line and the data line without the transfer hole form an integrated structure, the large current will directly damage several rows of driving transistors in the display area near the peripheral area, causing the source and drain to be short-circuited, and making some sub-pixels form bright and dark spot defects.

[0048] Please refer to Figure 1 and Figure 2 , an embodiment of the present invention provides a display substrate, including: a display area and a peripheral area surrounding the display area, the peripheral area including a fan-out area 21; the display substrate further includes:

[0049] Multiple first signal lines 30, the first signal lines 30 extending from the display area 10 to the peripheral area;

[0050] Multiple fan-out lines 31, the fan-out lines 31 being located in the fan-out area 21; the fan-out lines 31 are coupled to the corresponding first signal lines 30; the multiple fan-out lines 31 include multiple target fan-out lines 310, and the target fan-out lines 310 are arranged in a different layer from the first signal lines 30 to which they are coupled;

[0051] Multiple first electrostatic protection circuits 40, the first electrostatic protection circuits 40 being located in the fan-out area 21, the first electrostatic protection circuits 40 being coupled to the corresponding fan-out lines 31 for releasing the static electricity on the fan-out lines 31.

[0052] Exemplarily, the display area includes a rectangular display area, the peripheral area surrounds the display area, and the peripheral area includes an upper border area, a lower border area, a left border area, and a right border area. The lower border area includes a fan-out area 21 and a bonding area. The fan-out area 21 is provided with fan-out lines 31, and the bonding area is provided with a driving chip.

[0053] Exemplarily, the first signal line 30 includes a data line or other signal lines. The first signal line 30 includes a portion located in the display area and a portion located in the peripheral area.

[0054] Exemplarily, at least a portion of the fan-out lines 31 is located in the fan-out area 21. The plurality of fan-out lines 31 correspond to the plurality of first signal lines 30 one by one, and the fan-out lines 31 are respectively coupled to corresponding pins of the first signal lines 30 and the driving chip. The fan-out lines 31 can transmit the signals provided by the driving chip to the first signal lines 30.

[0055] Exemplarily, the plurality of fan-out lines 31 includes a plurality of target fan-out lines 310 and a plurality of non-target fan-out lines 311. The target fan-out lines 310 are disposed on a different layer from the first signal lines 30, and the non-target fan-out lines 311 are disposed on the same layer and made of the same material as the first signal lines 30.

[0056] Exemplarily, the plurality of first electrostatic protection circuits 40 correspond to the plurality of fan-out lines 31 one by one. The first electrostatic protection circuit 40 is coupled to the corresponding fan-out line 31 for releasing the static electricity on the corresponding fan-out line 31.

[0057] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present invention, the first electrostatic protection circuit 40 is disposed in the fan-out area 21, and the first electrostatic protection circuit 40 is coupled to the corresponding fan-out line 31. In this way, when a large current of static electricity enters the fan-out line 31 from the driving chip, it first passes through the first electrostatic protection circuit 40, then passes through the position where the fan-out line 31 is coupled to the first signal line 30, and then enters the first signal line 30. Therefore, in the display substrate provided by the embodiment of the present invention, when the large current of static electricity passes through the first electrostatic protection circuit 40, the first electrostatic protection circuit 40 can release the large current of static electricity, avoiding the transient large current from damaging the coupling point between the fan-out line 31 and the first signal line 30, thereby avoiding the occurrence of vertical dark line defects in the display device when the display substrate is applied to the display device. Moreover, the first electrostatic protection circuit 40 releases the large current of static electricity, which also avoids the large current directly damaging several rows of driving transistors near the peripheral area in the display area 10, thereby avoiding the formation of bright and dark point defects in some sub-pixels due to the short circuit between the source and drain electrodes of the driving transistors.

[0058] Please refer to Figure 1 and Figure 2 , in some embodiments, the display substrate further includes:

[0059] A plurality of conductive connection portions 50, each of the conductive connection portions 50 being coupled to a corresponding target fan-out line 310 and a corresponding first signal line 30; a positive projection of the first electrostatic protection circuit 40 on the substrate 70 of the display substrate is located on a side of a positive projection of the conductive connection portion 50 on the substrate 70 away from the display area 10.

[0060] Exemplarily, the display substrate further includes a plurality of sub-pixels arranged in an array, the sub-pixels including a pixel electrode and a common electrode arranged in a stacked manner, and the common electrode is located between the substrate 70 and the pixel electrode. Exemplarily, the common electrode is made of a first indium tin oxide layer, and the pixel electrode is made of a second indium tin oxide layer. Exemplarily, a plurality of slits are provided on the pixel electrode.

[0061] Exemplarily, the conductive connection portion 50 is made of a second indium tin oxide layer.

[0062] Exemplarily, the plurality of conductive connection portions 50 correspond one-to-one to a plurality of target fan-out lines 310 included in the plurality of fan-out lines 31, and correspond one-to-one to a plurality of the first signal lines 30 corresponding to the plurality of target fan-out lines 310. A positive projection of the conductive connection portion 50 on the substrate 70 at least partially overlaps a positive projection of the corresponding target fan-out line 310 on the substrate 70, and the conductive connection portion 50 and the corresponding target fan-out line 310 are coupled through at least one first via hole 541 at the overlapping portion. A positive projection of the conductive connection portion 50 on the substrate 70 at least partially overlaps a positive projection of the corresponding first signal line 30 on the substrate 70, and the conductive connection portion 50 and the corresponding first signal line 30 are coupled through at least one second via hole 542 at the overlapping portion.

[0063] With the above setting that the positive projection of the first electrostatic protection circuit 40 on the substrate 70 is located on a side of the positive projection of the conductive connection portion 50 on the substrate 70 away from the display area 10, when a large-current static electricity passes through the first electrostatic protection circuit 40, the first electrostatic protection circuit 40 can release the large-current static electricity, avoiding the transient large current from damaging the first via hole 541 and the second via hole 542, and thus avoiding the occurrence of vertical dark line defects in the display device when the display substrate is applied to the display device.

[0064] As Figure 1 and Figure 2 shown, in some embodiments, the display substrate further includes a common signal line 51; the first electrostatic protection circuit 40 includes:

[0065] A first transistor T1, wherein a gate T1-g of the first transistor T1 is coupled to the common signal line 51, a first pole T1-1 of the first transistor T1 is coupled to the corresponding fan-out line 31, and a second pole T1-2 of the first transistor T1 is coupled to the common signal line 51;

[0066] A second transistor T2, wherein a gate T2-g of the second transistor T2 is coupled to the corresponding fan-out line 31, a first pole T2-1 of the second transistor T2 is coupled to the corresponding fan-out line 31, and a second pole T2-2 of the second transistor T2 is coupled to the common signal line 51.

[0067] It should be noted that Figure 1 and Figure 2 also schematically shows an active layer T1-3 of the first transistor and an active layer T2-3 of the second transistor.

[0068] Exemplarily, the common signal line 51 is loaded with the same common signal as the common electrode.

[0069] Exemplarily, a positive projection of the channel of the first transistor T1 on the substrate 70 is located between the display area 10 and a positive projection of the channel of the second transistor T2 on the substrate 70.

[0070] Exemplarily, when static electricity with a large current passes through the first electrostatic protection circuit 40, the second transistor T2 turns on first, and the static electricity is released to the common signal line 51. If the current of the static electricity is large enough, after passing through the first transistor T1 and being released, there is still part of the static electricity transmitted to the first transistor T1, and this part of the static electricity can be released to the common signal line 51 through the first transistor T1.

[0071] Exemplarily, in the first electrostatic protection circuit 40 corresponding to the target fan-out line 310, the first pole T1-1 of the first transistor T1 can be coupled to the corresponding target fan-out line 310 through a first jumper pattern 551, and the second electrode of the first transistor T1 can be coupled to the common signal line 51 through a second jumper pattern 552; the first pole T2-1 of the second transistor T2 is coupled to the corresponding target fan-out line 310 through a third jumper pattern 553, and the second pole T2-2 of the second transistor T2 is coupled to the common signal line 51 through the second jumper pattern 552. The gate T2-g of the second transistor T2 and the corresponding target fan-out line 310 form an integral structure.

[0072] Exemplarily, in the first electrostatic protection circuit 40 corresponding to the non-target fan-out line 311, the first pole T1-1 of the first transistor T1 can be integrally formed with the corresponding non-target fan-out line 311, and the second electrode of the first transistor T1 can be coupled to the common signal line 51 through the fourth jumper pattern 554; the first pole T2-1 of the second transistor T2 is integrally formed with the corresponding non-target fan-out line 311, and the second pole T2-2 of the second transistor T2 is coupled to the common signal line 51 through the fourth jumper pattern 554. The gate T2-g of the second transistor T2 is coupled to the first pole T2-1 of the second transistor T2 through the fifth jumper pattern 555.

[0073] Exemplarily, the common signal line 51 includes alternately arranged first common patterns and second common patterns, and adjacent first common patterns and second common patterns are coupled. The first common pattern is provided on the same layer and made of the same material as the target fan-out line 310, and the orthographic projection of the first common pattern on the substrate 70 does not overlap with the orthographic projection of the target fan-out line 310 on the substrate 70. The second common pattern is made of the second indium tin oxide layer, and the orthographic projection of the second common pattern on the substrate 70 partially overlaps with the orthographic projection of the target fan-out line 310 on the substrate 70. The second common pattern can span the target fan-out line 310 to electrically connect the first common patterns located on both sides of the target fan-out line 310.

[0074] Setting the first electrostatic protection circuit 40 to the above structure realizes that the first electrostatic protection circuit 40 has a simple structure while ensuring good electrostatic protection effect, which is beneficial to reducing the layout difficulty of the first electrostatic protection circuit 40.

[0075] As Figures 3 to 5 shown, in some embodiments, the display substrate further includes:

[0076] A bonding area, and the fan-out area 21 is located between the display area 10 and the bonding area;

[0077] A plurality of second electrostatic protection circuits 41, the second electrostatic protection circuits 41 are coupled to the corresponding fan-out lines 31, and the second electrostatic protection circuits 41 are located between the first electrostatic protection circuit 40 and the bonding area for releasing static electricity on the fan-out lines 31.

[0078] Exemplarily, the orthographic projection of the second electrostatic protection circuit 41 on the substrate 70 is located between the orthographic projection of the first electrostatic protection circuit 40 on the substrate 70 and the orthographic projection of the bonding area on the substrate 70.

[0079] The second electrostatic protection circuit 41 is disposed between the first electrostatic protection circuit 40 and the bonding region, so that the second electrostatic protection circuit 41 can be combined with the first electrostatic protection circuit 40 to form a new type of ESD electrostatic ring unit. This new type of ESD electrostatic ring unit can not only release the static electricity accumulated in the screen but also withstand transient large currents.

[0080] As Figures 3 to 5 shown, in some embodiments, the second electrostatic protection circuit 41 includes: at least one third transistor T3. The at least one third transistor T3 is arranged along the extending direction of the fan-out line 31 corresponding to the second electrostatic protection circuit 41. The gate T3-g, the first pole T3-1, and the second pole T3-2 of the third transistor T3 are all coupled to the corresponding fan-out line 31.

[0081] It should be noted that Figures 3 to 5 also shows the active layer T3-3 of the third transistor T3.

[0082] Exemplarily, in the third transistor T3 coupled to the non-target fan-out line 311, the gate T3-g of the third transistor T3 is coupled to the second pole T3-2 of the third transistor T3 through a sixth jumper pattern 556, and the first pole T3-1 of the third transistor T3 is integrally formed with the non-target fan-out line 311.

[0083] Exemplarily, in the third transistor T3 coupled to the target fan-out line 310, the gate T3-g of the third transistor T3 is coupled to the second pole T3-2 of the third transistor T3 through a seventh jumper pattern 557, and the first pole T3-1 of the third transistor T3 is coupled to the target fan-out line 310 through an eighth jumper pattern 558.

[0084] When electrostatic discharge is performed through the third transistor T3, the third transistor T3 will be electrostatically broken down.

[0085] Setting the second electrostatic protection circuit 41 to include at least one third transistor T3 enables the second electrostatic protection circuit 41 to have a simple structure while ensuring good electrostatic protection effect, so that the second electrostatic protection circuit 41 does not occupy too much space in the fan-out area 21, which is beneficial to reducing the layout difficulty of the second electrostatic protection circuit 41.

[0086] As Figures 3 to 5 shown, in some embodiments, the second electrostatic protection circuit 41 includes: a plurality of third transistors T3. Along the direction from the fan-out area 21 to the bonding region, the channel width-to-length ratios of the plurality of third transistors T3 gradually decrease.

[0087] Exemplarily, among the multiple third transistors T3, the channel width-to-length ratios of at least two third transistors T3 are different.

[0088] The above-described second electrostatic protection circuit 41 includes multiple third transistors T3, such that the multiple third transistors T3 can serve as sacrificial points that are first broken down by a large-current electrostatic signal flowing in from the bonding region, thereby realizing the protection of other functional structures on the side of the third transistors T3 facing the display region 10.

[0089] The above-described channel width-to-length ratios of the multiple third transistors T3 gradually decrease, such that the difficulty levels of the multiple third transistors T3 in resisting electrostatic breakdown are distributed in a stepped manner, and can better correspond to large currents of different electrostatic levels, enabling the second electrostatic protection circuit 41 to handle a larger electrostatic range.

[0090] As Figure 6 and Figure 7 shown, in some embodiments, the display substrate further includes: multiple sub-pixels, the multiple sub-pixels are located in the display region 10, and the sub-pixel includes a driving transistor DTFT; the channel width-to-length ratios of the multiple third transistors T3 are smaller than the channel width-to-length ratio of the driving transistor DTFT.

[0091] Exemplarily, the sub-pixel further includes a pixel electrode, the output electrode of the driving transistor DTFT is coupled to the pixel electrode, the gate of the driving transistor DTFT is coupled to a corresponding scanning line, the input electrode of the driving transistor DTFT is coupled to a corresponding data line, and the driving transistor DTFT is turned on under the control of a scanning signal provided by the corresponding scanning line, and transmits a data signal provided by the corresponding data line to the pixel electrode.

[0092] The above-described channel width-to-length ratios of the multiple third transistors T3 are smaller than the channel width-to-length ratio of the driving transistor DTFT, such that the difficulty level of the multiple third transistors T3 being broken down is smaller than the difficulty level of the driving transistor DTFT being broken down. Since current always chooses to move along a path with lower impedance, the third transistors T3 will induce a large current to first break down themselves, and most of the energy will be consumed during the electrostatic discharge process, such that the remaining energy of the large-current electrostatic after being released through the third transistors T3 is not sufficient to damage the via hole 54 and the driving transistor DTFT.

[0093] In some embodiments, the display substrate includes a gate metal layer and a source-drain metal layer. The target fan-out line 310 is provided on the same layer and made of the same material as the gate metal layer, the non-target fan-out lines 311 among the multiple fan-out lines 31 are provided on the same layer and made of the same material as the source-drain metal layer, and the non-target fan-out lines 311 and the corresponding first signal lines 30 form an integral structure.

[0094] The target fan-out line 310 is provided on the same layer and made of the same material as the gate metal layer, so that the target fan-out line 310 and the gate metal layer can be formed in the same patterning process, which is beneficial to simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0095] The non-target fan-out lines 311 among the plurality of fan-out lines 31 are provided on the same layer and made of the same material as the source-drain metal layer, so that the non-target fan-out lines 311 among the plurality of fan-out lines 31 and the source-drain metal layer can be formed in the same patterning process, which is beneficial to simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0096] The non-target fan-out line 311 and the corresponding first signal line 30 are formed into an integral structure, which is beneficial to improving the electrical connection reliability between the non-target fan-out line 311 and the first signal line 30.

[0097] As Figure 6 and Figure 7 shown, in some embodiments, the display substrate further includes:

[0098] A plurality of third electrostatic protection circuits 42, the third electrostatic protection circuits 42 are located between the display area 10 and the fan-out area 21, and the third electrostatic protection circuits 42 are coupled to the corresponding first signal lines 30 for releasing static electricity on the first signal lines 30.

[0099] Exemplarily, the plurality of third electrostatic protection circuits 42 correspond to the plurality of first signal lines 30 one by one, and the third electrostatic protection circuits 42 are coupled to the corresponding first signal lines 30.

[0100] Setting the third electrostatic protection circuit 42 to be coupled to the corresponding first signal line 30 enables the third electrostatic protection circuit 42 to release the large-current static electricity before it enters the display area 10, thereby avoiding the large-current static electricity from directly damaging several rows of driving transistors in the display area 10 near the peripheral area and causing a source-drain short circuit, and avoiding the formation of bright and dark spot defects in the sub-pixels of the display substrate.

[0101] As Figure 6 and Figure 7 shown, in some embodiments, the display substrate further includes:

[0102] A plurality of virtual transistor groups, the virtual transistor groups including at least one virtual transistor DUTFT, the at least one virtual transistor DUTFT being arranged along the extending direction of a corresponding first signal line 30 of the virtual transistor group, a first pole DUTFT-1 of the virtual transistor DUTFT being coupled to the first signal line 30; a gate DUTFT-g and a second pole DUTFT-2 of the virtual transistor DUTFT being both floating; the virtual transistor group being multiplexed as the third electrostatic protection circuit 42.

[0103] It should be noted that Figure 6 and Figure 7 schematically shows an active layer DUTFT-3 of the virtual transistor DUTFT. Figure 7 schematically shows a common electrode layer 52, which is made of indium tin oxide.

[0104] Exemplarily, the plurality of virtual transistor groups are arranged in a DUMMY area 23 of the display substrate, and the DUMMY area 23 is located between the fan-out area 21 and the display area 10.

[0105] Exemplarily, the virtual transistor group includes a plurality of the virtual transistors DUTFT, and the plurality of the virtual transistors DUTFT are arranged along the extending direction of a corresponding first signal line 30 of the virtual transistor group. Exemplarily, the virtual transistor group includes four of the virtual transistors DUTFT.

[0106] Exemplarily, the virtual transistor DUTFT includes a complete gate, source, and drain, and can absorb ESD charges to form source-drain breakdown. Exemplarily, the virtual transistor DUTFT has the same structure as the driving transistor. Exemplarily, the virtual transistor DUTFT has the same structure as the third transistor T3. Exemplarily, the structure of the virtual transistor group is the same as the structure of the first electrostatic protection circuit 40.

[0107] After static electricity enters the DUMMY area 23 from the fan-out area 21, the energy will be greatly attenuated after being absorbed by a plurality of virtual transistors DUTFT, thereby protecting the driving transistors in the display area 10.

[0108] In some embodiments, the virtual transistor group includes a plurality of virtual transistors DUTFT, and along the direction from the display area 10 to the fan-out area 21, the channel width-to-length ratios of the plurality of virtual transistors DUTFT gradually decrease.

[0109] Exemplarily, the channel width-to-length ratio of the virtual transistor DUTFT includes 17μm / 2.3μm.

[0110] Exemplarily, the area of the active layer of the virtual transistor DUTFT is 17.35 * 15.55 μm 2 .

[0111] By setting the channel width-to-length ratios of the plurality of virtual transistors DUTFT to gradually decrease, such that the ease of electrostatic breakdown of the plurality of virtual transistors DUTFT is distributed in a stepped manner, it is possible to better correspond to large currents of different electrostatic levels.

[0112] In some embodiments, the display substrate further includes:

[0113] A plurality of sub-pixels, the plurality of sub-pixels being located in the display area 10, the sub-pixel including a driving transistor, the channel width-to-length ratio of the driving transistor being greater than the channel width-to-length ratios of a part of the plurality of virtual transistors DUTFT and less than the channel width-to-length ratios of another part of the plurality of virtual transistors DUTFT.

[0114] Since the breakdown voltage of the TFT is proportional to the length L of the channel and has no correlation with the width W of the channel, when the virtual transistor DUTFT in the DUMMY area 23 adopts a design with a gradually changing channel length, within the scope of the exposure process capabilities, with the channel length of the driving transistor as the center point, a hierarchical setting of the channel lengths of a plurality of virtual transistors DUTFT can be adopted. Exemplarily, the channel length range of the virtual transistor DUTFT can be distributed within the range of 1 μm to 4 μm. Considering that the existence of the virtual transistor DUTFT is a point for inducing ESD release, a stepped distribution design with the channel lengths of the plurality of virtual transistors DUTFT being 1 μm, 1 μm, 3 μm, and 4 μm in sequence can be set to respectively correspond to different levels of electrostatic magnitudes. Exemplarily, the channel length of the driving transistor is 2.3 μm. Exemplarily, the channel length of the transistor in the first electrostatic protection circuit 40 is 12 μm.

[0115] In the display substrate provided by the above embodiments, based on the alternate wiring design in the narrow border fan-out area 21, by adding transistors with different breakdown vulnerability degrees as breakdown sacrifice points at the via holes 54 in the fan-out area 21 and the front end of the driving transistors in the display area 10, and by setting the first electrostatic protection circuit 40 in the fan-out area 21, the ability to prevent static large currents in the fan-out area 21 and the display area 10 is effectively enhanced, the incidence of vertical lines and bright and dark spots is reduced, the product quality is improved, and the margin of the process is increased.

[0116] It should be noted that the film layer preparation process flows of all the virtual transistors DUTFT and the new electrostatic ring design are the same, and are the same as the preparation processes of existing products. Therefore, the present invention does not require an additional mask process, and by changing the design on the basis of the existing process, the ability to prevent static large currents in the fan-out area 21 and the display area 10 can be enhanced, and the production cost will not be increased additionally.

[0117] It should be noted that the manufacturing process flow includes, in sequence: fabricating a gate metal layer, fabricating a gate insulating layer GI, fabricating an active layer, fabricating a source / drain metal layer, fabricating a passivation layer PVX, and fabricating an indium tin oxide layer. The gate metal layer is used to fabricate the gate of the transistor and a part of the common signal line 51. The active layer can form the channel of the transistor. The source / drain metal layer is used to form the source and drain of the transistor. The passivation layer PVX is used to protect the underlying film layer covered thereby. The indium tin oxide layer is used to fabricate the conductive connection portion 50 and another part of the common signal line 51.

[0118] An embodiment of the present invention further provides a display device, including the display substrate provided in the above embodiment.

[0119] In the display substrate provided in the above embodiment, a first electrostatic protection circuit 40 is disposed in the fan-out region 21, and the first electrostatic protection circuit 40 is coupled to the corresponding fan-out line 31. In this way, when a large-current static electricity enters the fan-out line 31 from the driving chip, it first passes through the first electrostatic protection circuit 40, then passes through the position where the fan-out line 31 is coupled to the first signal line 30, and then enters the first signal line 30. Therefore, in the display substrate provided in the above embodiment, when the large-current static electricity passes through the first electrostatic protection circuit 40, the first electrostatic protection circuit 40 can release the large-current static electricity, avoiding the transient large current from damaging the coupling point of the fan-out line 31 and the first signal line 30, thereby avoiding the occurrence of vertical dark line defects when the display substrate is applied to the display device. Moreover, the first electrostatic protection circuit 40 releasing the large-current static electricity also avoids the large current directly damaging several rows of driving transistors in the vicinity of the peripheral region in the display area 10, thereby avoiding the formation of bright and dark dot defects in some sub-pixels due to the short circuit of the source and drain of the driving transistors.

[0120] When the display device provided in the embodiment of the present invention includes the above display substrate, it also has the above beneficial effects, which will not be elaborated here.

[0121] It should be noted that the display device may be: any product or component with a display function such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc. Among them, the display device further includes a flexible circuit board, a printed circuit board, a backplane, etc.

[0122] In some embodiments, the display device further includes a counter substrate 60 and a liquid crystal layer. The counter substrate 60 is disposed opposite to the display substrate, and the liquid crystal layer is located between the display substrate and the counter substrate 60.

[0123] Exemplarily, the counter substrate 60 includes a color filter substrate. A black matrix BM is disposed on the counter substrate 60.

[0124] It should be noted that the "same layer" in the embodiments of the present invention may refer to the film layers on the same structural layer. Or for example, the film layers in the same layer may be the film layers formed by the same film-forming process for forming a specific pattern, and then the layer structure formed by patterning the film layer by using the same mask through a single patterning process. According to the different specific patterns, the single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0125] In the method embodiments of the present invention, the sequence numbers of the steps cannot be used to limit the order of the steps. For those of ordinary skill in the art, without creative efforts, the changes in the order of the steps are also within the protection scope of the present invention.

[0126] It should be noted that the embodiments in this specification are all described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, they are described relatively simply, and the relevant parts can be referred to the partial description of the product embodiments.

[0127] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should have the ordinary meaning understood by those of ordinary skill in the art to which the present invention belongs. The "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected", "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0128] It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there may be intermediate elements.

[0129] In the description of the above embodiments, the specific features, structures, materials or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0130] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims described above.

Claims

1. A display substrate, characterized in that, it includes: a display area and a peripheral area surrounding the display area, the peripheral area including a fan-out area; the display substrate further includes: a plurality of first signal lines, the first signal lines extending from the display area to the peripheral area; a plurality of fan-out lines, the fan-out lines being located in the fan-out area; the fan-out lines are coupled to the corresponding first signal lines; the plurality of fan-out lines include a plurality of target fan-out lines, and the target fan-out lines are arranged in a different layer from the first signal lines to which they are coupled; a plurality of first electrostatic protection circuits, the first electrostatic protection circuits being located in the fan-out area, and the first electrostatic protection circuits being coupled to the corresponding fan-out lines for releasing static electricity on the fan-out lines; the display substrate further includes a common signal line; the first electrostatic protection circuit includes: a first transistor, the gate of the first transistor being coupled to the common signal line, the first pole of the first transistor being coupled to the corresponding fan-out line, and the second pole of the first transistor being coupled to the common signal line; a second transistor, the gate of the second transistor being coupled to the corresponding fan-out line, the first pole of the second transistor being coupled to the corresponding fan-out line, and the second pole of the second transistor being coupled to the common signal line; the display substrate further includes: a bonding area, the fan-out area being located between the display area and the bonding area; a plurality of second electrostatic protection circuits, the second electrostatic protection circuits being coupled to the corresponding fan-out lines, and the second electrostatic protection circuits being located between the first electrostatic protection circuits and the bonding area for releasing static electricity on the fan-out lines; the second electrostatic protection circuit includes: at least one third transistor, the at least one third transistor being arranged along the extending direction of the fan-out line corresponding to the second electrostatic protection circuit, and the gate, first pole and second pole of the third transistor being all coupled to the corresponding fan-out line.

2. The display substrate according to claim 1, characterized in that, the display substrate further includes: a plurality of conductive connection parts, the conductive connection parts being respectively coupled to the corresponding target fan-out lines and the corresponding first signal lines; the orthographic projection of the first electrostatic protection circuit on the substrate of the display substrate is located on the side of the orthographic projection of the conductive connection part on the substrate away from the display area.

3. The display substrate according to claim 1, characterized in that, the second electrostatic protection circuit includes: a plurality of third transistors, and along the direction from the fan-out area to the bonding area, the channel width-to-length ratios of the plurality of third transistors gradually decrease.

4. The display substrate according to claim 3, characterized in that, the display substrate further includes: a plurality of sub-pixels, the plurality of sub-pixels being located in the display area, and the sub-pixels including driving transistors; the channel width-to-length ratios of the plurality of third transistors are smaller than the channel width-to-length ratios of the driving transistors.

5. The display substrate according to claim 1, characterized in that, The display substrate includes a gate metal layer and a source-drain metal layer. The target fan-out line is provided on the same layer and made of the same material as the gate metal layer. Among the multiple fan-out lines, the non-target fan-out lines are provided on the same layer and made of the same material as the source-drain metal layer. The non-target fan-out line and the corresponding first signal line form an integrated structure.

6. The display substrate according to claim 1, wherein, the display substrate further includes: a plurality of third electrostatic protection circuits, which are located between the display area and the fan-out area, and the third electrostatic protection circuits are coupled to the corresponding first signal lines for releasing static electricity on the first signal lines.

7. The display substrate according to claim 6, wherein, the display substrate further includes: a plurality of virtual transistor groups, each virtual transistor group includes at least one virtual transistor, and the at least one virtual transistor is arranged along the extending direction of the first signal line corresponding to the virtual transistor group. The first pole of the virtual transistor is coupled to the first signal line; the gate of the virtual transistor and the second pole of the virtual transistor are both floating; the virtual transistor group is multiplexed as the third electrostatic protection circuit.

8. The display substrate according to claim 7, wherein, the virtual transistor group includes a plurality of virtual transistors, and along the direction from the display area to the fan-out area, the channel width-to-length ratios of the plurality of virtual transistors gradually decrease.

9. The display substrate according to claim 8, wherein, the display substrate further includes: a plurality of sub-pixels, which are located in the display area, and each sub-pixel includes a driving transistor. The channel width-to-length ratio of the driving transistor is greater than that of a part of the virtual transistors and less than that of another part of the virtual transistors.

10. A display device, wherein, it includes the display substrate according to any one of claims 1 to 9.

11. The display device according to claim 10, wherein, the display device further includes a counter substrate and a liquid crystal layer. The counter substrate is disposed opposite to the display substrate, and the liquid crystal layer is located between the display substrate and the counter substrate.

Images