Semiconductor package structure and method of forming the same

Abstract

The application relates to a semiconductor packaging structure and a forming method thereof. The semiconductor packaging structure is characterized by comprising: an interposer having an upper surface; a redistribution line (RDL) located on the upper surface of the interposer; a silicon optical chip located on the RDL; a first die laterally offset from the silicon optical chip and having an upward active surface, and the first die is embedded in a cavity below the upper surface of the interposer, wherein the active surface of the first die is electrically connected with the silicon optical chip through the RDL.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and more particularly, to a semiconductor package structure and a forming method thereof. BACKGROUND

[0002] In recent years, the development of big data and artificial intelligence has become a trend, and improving the data transmission rate of electronic devices has become a development focus. Silicon photonics is a technology that can effectively improve data transmission efficiency. The current silicon photonics mainly uses an interposer as a connection medium for various functional chips, that is, various functional chips are dispersed on the upper surface of the interposer, and then connected to the bottom substrate through the TSV structure in the interposer for signal transmission. However, all the chips arranged on the upper surface of the interposer not only occupy a large area, but also limit the number of connectable functional chips due to the miniaturization process, and cannot effectively achieve the effect of server on chip. SUMMARY

[0003] In view of the above problems in the related art, the present application provides a semiconductor package structure and a forming method thereof.

[0004] Embodiments of the present application provide a semiconductor package structure, comprising: an interposer having an upper surface; a redistribution line (RDL) located on the upper surface of the interposer; a silicon photonics chip located on the redistribution line; a first die laterally offset from the silicon photonics chip and having an upward active surface, and the first die is embedded in a cavity below the upper surface of the interposer, wherein the active surface of the first die is electrically connected to the silicon photonics chip through the redistribution line.

[0005] In some embodiments, the first die further has a non-active surface arranged opposite to the active surface, wherein the non-active surface is attached to the cavity of the interposer through a die attach film (DAF).

[0006] In some embodiments, the width of the cavity is greater than the width of the first die.

[0007] In some embodiments, the width of the cavity is greater than the width of the first die by 2 / 3 of the size of the bump metal.

[0008] In some embodiments, the semiconductor package structure further comprises: a fan-out package arranged above the redistribution line and the first die, the fan-out package comprising a plurality of stacked layers of dies; wherein a second die in the lowermost layer of the plurality of stacked layers of dies is arranged opposite to and electrically connected to the first die.

[0009] In some embodiments, the multiple-tiered die of the fan-out package further includes a third die above the second die, and the fan-out package further has redistribution lines electrically connected to the third die and conductive pillars extending vertically within the fan-out package, wherein the third die is electrically connected to the silicon photonic chip through the redistribution lines and the conductive pillars within the fan-out package and through through-silicon vias (TSVs) through the interposer.

[0010] In some embodiments, the third die includes a plurality of third dies stacked.

[0011] In some embodiments, the second die includes a fast-access memory die and the third die includes a non-fast-access memory die.

[0012] In some embodiments, the fan-out package is electrically connected to the interposer through bump metals.

[0013] In some embodiments, the first die includes a processor die and a cache die.

[0014] Embodiments of the present disclosure further provide a method of forming a semiconductor package structure, including: forming an interposer having a cavity recessed from an upper surface of the interposer; forming a first die within the cavity with an active surface facing upward; forming redistribution lines (RDLs) above the upper surface of the interposer and a silicon photonic chip laterally offset from the cavity above the RDLs such that the first die is electrically connected to the silicon photonic chip through the RDLs.

[0015] In some embodiments, the method further includes: forming a second die in a lowermost tier of a fan-out package above the RDLs and the first die, the second die being disposed opposite to the first die and electrically connected to the first die.

[0016] In some embodiments, the method further includes: forming a third die above the second die and forming redistribution lines electrically connected to the third die and conductive pillars extending vertically within the fan-out package, wherein the third die is electrically connected to the silicon photonic chip through the redistribution lines and the conductive pillars within the fan-out package and through through-silicon vias through the interposer.

[0017] In some embodiments, the first die further has a non-active surface disposed opposite to the active surface, wherein forming the first die within the cavity includes: attaching the non-active surface of the first die within the cavity through a die attach film (DAF).

[0018] In some embodiments, the method further includes, before forming the interposer having the cavity, forming solder bumps on a lower surface of the interposer; and, after forming the third die, joining a substrate to the solder bumps.

[0019] In some embodiments, the third die includes a plurality of third dies stacked.

[0020] In some embodiments, the width of the cavity is formed to be greater than the width of the first die and 2 / 3 of a bump metal size.

[0021] In some embodiments, the second die comprises a fast access memory die and the third die comprises a non-fast access memory die.

[0022] In some embodiments, after forming the first die, further comprising: forming a bump metal on the upper surface of the interposer and on the active surface of the first die, the fan-out package being electrically connected to the interposer by the bump metal.

[0023] In some embodiments, the first die comprises a processor die and a cache die. BRIEF DESCRIPTION OF DRAWINGS

[0024] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that the various components are not necessarily drawn to scale. Indeed, the dimensions of the various components can be arbitrarily increased or decreased for the sake of discussion. It should be understood that the detailed description is but one implementation, and is not intended to limit the scope of the application. Rather, the claims should be accorded the full scope consistent with the claims, while the detailed description serves merely as a preferred embodiment of the claimed application.

[0025] Figure 1 is a schematic diagram of a semiconductor package structure according to an embodiment of the application.

[0026] Figure 2 is a schematic diagram of a semiconductor package structure according to another embodiment of the application.

[0027] Figures 3A to 3J is a schematic diagram of various stages of a method of forming a semiconductor package structure according to an embodiment of the application. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Various elements of the embodiments disclosed below can be used alone or in combination with other elements, in various embodiments. It is intended that the application covers all such embodiments, and their equivalents. For example, the following disclosure provides various examples of forming a first component over or on a second component. These examples can include embodiments in which the first component and the second component are in direct contact, as well as embodiments in which additional components are formed between the first component and the second component such that the first component and the second component can not be in direct contact. Moreover, the application can be repeated with variations and permutations of the various examples. Such repetitions are not to be regarded as repetitions of the same or similar subject matter, but rather, such repetitions are to be regarded as repetitions of the same or similar elements in different examples. Moreover, the application is intended to cover all such embodiments, and their equivalents. For example, the following disclosure provides various examples of forming a first component over or on a second component. These examples can include embodiments in which the first component and the second component are in direct contact, as well as embodiments in which additional components are formed between the first component and the second component such that the first component and the second component can not be in direct contact. Moreover, the application can be repeated with variations and permutations of the various examples. Such repetitions are not to be regarded as repetitions of the same or similar subject matter, but rather, such repetitions are to be regarded as repetitions of the same or similar elements in different examples. Moreover, the application is intended to cover all such embodiments, and their equivalents.

[0029] Figure 1 is a schematic diagram of a semiconductor package structure according to an embodiment of the application. As Figure 1As shown, the semiconductor structure includes an interposer 110. A redistribution layer (RDL) 112 is on an upper surface of the interposer 110. A silicon photonic chip 121 is disposed on and electrically connected to the redistribution layer 112. A first die 122 is embedded in a cavity 114 under the upper surface of the interposer 110 laterally offset from the silicon photonic chip 121, i.e., the silicon photonic chip 121 and the first die 122 do not overlap in a vertical direction. An active surface of the first die 122 faces upward and has electrical connections 123 such as solder balls on the active surface. The first die 122 can be electrically connected to the silicon photonic chip 121 via the redistribution layer 112 through the electrical connections 123 on the active surface of the first die 122.

[0030] In some embodiments, the first die 122 includes computing chips related to the silicon photonic chip 121: a processor die and a cache die. The processor die and the cache die are embedded in the cavity 114 of the interposer 110 and can communicate with the silicon photonic chip 121 quickly through the redistribution layer 112 on the interposer 110.

[0031] The first die 122 also has a non-active surface disposed opposite the active surface, where the non-active surface is attached to the cavity 114 of the interposer 110 by a die attach film (DAF). A width W1 of the cavity 114 can be greater than a width W2 of the first die 122. In one embodiment, the width W1 of the cavity 114 can be greater than the width W2 of the first die 122 by 2 / 3 of a bump metal size.

[0032] Still referring to Figure 1 The semiconductor package structure also includes a fan-out package 100 disposed above the redistribution layer 112 and the first die 122. In some embodiments, the fan-out package 100 can be electrically connected to the interposer 110 by bump metals 124. The fan-out package 100 includes stacked multiple dies. A second die 125 is disposed in a lowermost one of the multiple dies, which is disposed opposite and electrically connected to the first die 122 embedded in the interposer 110.

[0033] In some embodiments, the second die 125 includes a fast access memory die (e.g., a memory die). The fast access memory is interfaced with the computing chips (the processor die and the cache die) in an up-down manner, which effectively shortens the signal transmission distance between the silicon photonic chip, the processor die, and the fast access memory die, and speeds up the signal transmission and access.

[0034] Figure 2is a schematic diagram of a semiconductor package structure according to another embodiment of the present application. In this embodiment, the multiple tiers of dies of the fan-out package 100' further include a third die 126 above the second die 125, and the fan-out package 100' further has redistribution lines 132 electrically connected to the third die 126 and conductive pillars 133 extending vertically within the fan-out package 100'. The third die 126 is electrically connected to the silicon photonic chip 121 through the redistribution lines 132 and the conductive pillars 133 within the fan-out package 100' and the through-silicon vias (TSVs) 111 through the interposer 110. The third die 126 can include multiple third dies 126 stacked on top of each other. The third die 126 includes remaining non-quick access memory dies (e.g., SSD and HDD). The third die 126 can be stacked on top of each other through a fan-out structure including redistribution lines and conductive pillars, and then interfaced with the interposer 110 on top and bottom. Since the information of the third die 126 does not need to be accessed quickly, the third die 126 can communicate with the silicon photonic chip 121 through the through-silicon vias 111 of the interposer 110 and the substrate 10 below the interposer 110.

[0035] Figures 3A to 3J is a schematic diagram of various stages of a method of forming a semiconductor package structure according to an embodiment of the present application. The method begins with Figure 3A , providing an interposer 110 having through-silicon vias 111 therein, one end of the through-silicon vias 111 being exposed from an upper surface of the interposer 110. In Figure 3A , bump metals 123 are formed on the exposed through-silicon vias 111. Figure 3B

[0036] Next, in Figure 3C , a first carrier is bonded over the bump metals 123, and the resulting structure is inverted. In Figure 3D , the interposer 110 is ground to expose the other end of the through-silicon vias 111. Electrical connections 129, such as C4 bumps, are formed over the surface of the interposer 110. Then, a second carrier 202 is bonded over the electrical connections 129, and the resulting structure is inverted again and the first carrier 201 is removed, as in Figure 3E .

[0037] In Figure 3F , the surface of the interposer 110 is recessed to form cavities 114 between the through-silicon vias 111. In the illustrated embodiment, the number of cavities 114 is two. In Figure 3G ​In this process, the active surface of the first die 122 is formed within the cavity 114 with the active surface facing upwards. The non-active surface of the first die 122 can be attached to the cavity 114 via a die-attach film (DAF) 128. A redistribution line 112 is formed on the surface of the interposer 110, and the silicon photonic chip 121 is laterally offset from the cavity 114 and formed above the redistribution line 112, so that the first die 122 is electrically connected to the silicon photonic chip 121 through the redistribution line 112.

[0038] Then, as Figure 3H A fan-out package 100 is formed above the redistribution line 112 and the first die 122. In this embodiment, the fan-out package 100 includes four dies 125 and 126. The die 125 in the lowest layer of the fan-out package 100 is formed above the redistribution line 112 and the first die 122, and is disposed opposite to and electrically connected to the first die 122. In another embodiment, the fan-out package may also be as follows: Figure 2 The fan-out package 100' shown.

[0039] exist Figure 3I In the process, the second carrier 202 is removed, and the resulting structure is inverted and placed on the tape 302. Then, the substrate 140 is joined by the electrical connector 129, and the resulting structure is inverted as follows. Figure 3J .

[0040] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor package structure, comprising: Comprising: an interposer having an upper surface; a redistribution line (RDL) on the upper surface of the interposer and extending laterally along the upper surface of the interposer; a silicon optical chip on the RDL, wherein bump metals are directly connected on the RDL and under the silicon optical chip to electrically connect the silicon optical chip with the RDL; a first die laterally offset from the silicon optical chip and having an active surface facing upward, and the first die is embedded in a cavity under the upper surface of the interposer, wherein the active surface of the first die is electrically connected with the silicon optical chip through the RDL; a fan-out package disposed over the RDL and the first die, the fan-out package comprising a plurality of stacked dies, wherein the plurality of stacked dies comprises a second die in a lowermost layer and a third die spaced above the second die, the second die in the plurality of stacked dies is laterally spaced from the silicon optical chip on the RDL and disposed opposite to the first die and electrically connected with the first die, the third die in the plurality of stacked dies is electrically connected with the silicon optical chip through redistribution lines within the fan-out package and conductive pillars extending vertically within the fan-out package and throughs (TSVs) through the interposer.

2. The semiconductor package structure of claim 1, wherein, the first die further has a non-active surface disposed opposite to the active surface, wherein the non-active surface is attached within the cavity of the interposer through a die attach film (DAF).

3. The semiconductor package structure of claim 1, wherein: a width of the cavity is greater than a width of the first die.

4. The semiconductor package structure of claim 3, wherein: the width of the cavity is greater than the width of the first die by 2 / 3 of a size of the bump metals.

5. The semiconductor package structure of claim 1, wherein, the third die comprises a plurality of the third dies stacked.

6. The semiconductor package structure of claim 1, wherein, the second die comprises a fast access memory die and the third die comprises a non-fast access memory die.

7. The semiconductor package structure of claim 1, wherein, the fan-out package is electrically connected with the interposer through bump metals.

8. The semiconductor package structure of claim 1, wherein, the first die comprises a processor die and a cache die.

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