Memory device and method for manufacturing the same

Abstract

An embodiment of the present invention provides a memory device and a method for manufacturing the same. The memory device includes a first split-gate memory cell, and the first split-gate memory cell includes a first memory stack located above a substrate. The first memory stack includes a first floating gate and a first control gate located above the first floating gate. The split-gate memory cell further includes a first select gate adjacent to the first floating gate and the first control gate, and a contact etch stop layer located above a part of the top surface of the first select gate. The contact etch stop layer can narrow the drain contact via during an etching process. By narrowing the drain contact via, the density of the split-gate memory cell can be increased.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth in the past few decades. In the process of IC evolution, the functional density (i.e., the number of interconnect devices per chip area) has generally increased, while the geometric size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased.

[0003] Ultra-fast flash technology enables designers to create cost-effective and high-performance programmable system-on-chip (SOC) solutions by using split-gate flash memory cells. The aggressive scaling of the third-generation embedded super-flash memory (ESF3) enables the design of flash memories with high storage array density. Summary of the Invention

[0004] Embodiments of the present invention provide a memory device, which includes a first split-gate memory cell. The first split-gate memory cell includes a first memory stack, a first select gate, and a first contact etch stop layer. The first memory stack is located above a substrate and includes a first floating gate and a first control gate located above the first floating gate. The first select gate is adjacent to the first floating gate and the first control gate. The first contact etch stop layer is located above a part of the top surface of the first select gate.

[0005] Embodiments of the present invention provide a memory device, which includes a first split-gate memory cell, a second split-gate memory cell, and a drain contact. The first split-gate memory cell is located on a substrate. The second split-gate memory cell is located on the substrate. The drain contact is located between the first split-gate memory cell and the second split-gate memory cell and is electrically connected to a drain region located in the substrate. Wherein the drain contact has a profile discontinuity at a contact etch stop layer located above the first split-gate memory cell and the second split-gate memory cell, wherein the drain contact has a first part located above the contact etch stop layer and a second part located below the contact etch stop layer, and the first part is wider than the second part.

[0006] An embodiment of the present invention provides a method of manufacturing a memory device, including: forming at least two split-gate memory cells on a substrate, each of the at least two split-gate memory cells including: a pair of memory stacks including a floating gate and a control gate located above the floating gate; a common source located between the pair of memory stacks; an erase gate located above the common source; and a select gate adjacent to each of the pair of memory stacks, the select gate being located opposite to the erase gate; and a dielectric layer located between the at least two split-gate memory cells; patterning a hard mask layer above the at least two split-gate memory cells to form a contact etch stop layer above the select gate; forming an interlayer dielectric layer above the at least two split-gate memory cells; and anisotropically etching the interlayer dielectric layer and the dielectric layer located between the at least two split-gate memory cells such that when the interlayer dielectric layer located above the at least two split-gate memory cells and the dielectric layer located between the at least two split-gate memory cells are removed, the contact etch stop layer causes the drain contact via to narrow. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or reduced.

[0008] Figure 1 is a vertical cross-sectional view of a split-gate flash memory cell according to some embodiments.

[0009] Figure 2 is a vertical cross-sectional view showing a step of forming isolation features in a method of manufacturing a semiconductor device according to some embodiments.

[0010] Figure 3 is a vertical cross-sectional view showing a step of forming a tunneling dielectric layer and a floating gate layer in a method of manufacturing a semiconductor device according to some embodiments.

[0011] Figure 4 is a vertical cross-sectional view showing a step of forming a blocking dielectric layer, a control gate layer, and a hard mask layer in a method of manufacturing a semiconductor device according to some embodiments.

[0012] Figure 5 is a vertical cross-sectional view showing a step of patterning a control gate in a method of manufacturing a semiconductor device according to some embodiments.

[0013] Figure 6 is a vertical cross-sectional view showing a step of forming sidewalls on a control gate in a method of manufacturing a semiconductor device according to some embodiments.

[0014] Figure 7 is a vertical cross-sectional view showing the step of patterning a floating gate in a method for manufacturing a semiconductor device according to some embodiments.

[0015] Figure 8 is a vertical cross-sectional view showing the step of forming an inter-gate dielectric layer in a method for manufacturing a semiconductor device according to some embodiments.

[0016] Figure 9 is a vertical cross-sectional view showing the step of forming a common source in a method for manufacturing a semiconductor device according to some embodiments.

[0017] Figure 10 is a vertical cross-sectional view showing the step of forming a select gate dielectric layer in a method for manufacturing a semiconductor device according to some embodiments.

[0018] Figure 11 is a vertical cross-sectional view showing the step of forming a conductive layer in a method for manufacturing a semiconductor device according to some embodiments.

[0019] Figure 12 is a vertical cross-sectional view showing the step of patterning the conductive layer to form an erase gate in a method for manufacturing a semiconductor device according to some embodiments.

[0020] Figure 13 is a vertical cross-sectional view showing the step of depositing a hard mask in a method for manufacturing a semiconductor device according to some embodiments.

[0021] Figure 14 is a vertical cross-sectional view showing the step of forming a select gate in a method for manufacturing a semiconductor device according to some embodiments.

[0022] Figure 15 is a vertical cross-sectional view showing the step of forming a main sidewall spacer in a method for manufacturing a semiconductor device according to some embodiments.

[0023] Figure 16 is a vertical cross-sectional view showing the step of forming a drain region in a method for manufacturing a semiconductor device according to some embodiments.

[0024] Figure 17 is a vertical cross-sectional view showing the steps of forming a contact etch stop layer and depositing and patterning an oxide layer over a storage region in a method for manufacturing a semiconductor device according to some embodiments.

[0025] Figure 18Is a vertical cross-sectional view showing the step of depositing an oxide hard mask over a storage region in a method for manufacturing a semiconductor device according to some embodiments.

[0026] Figure 19 Is Figure 18 A close-up of a vertical cross-sectional view of a storage region, which shows the step of depositing and patterning photoresist in a method for manufacturing a semiconductor device according to some embodiments.

[0027] Figure 20 Is Figure 18 A close-up of a vertical cross-sectional view of a storage region, which shows the step of patterning an oxide hard mask layer using the Figure 19 Patterning photoresist shown in a method for manufacturing a semiconductor device according to some embodiments.

[0028] Figure 21 Is a vertical cross-sectional view showing the step of patterning a hard mask layer using a patterned oxide hard mask layer.

[0029] Figure 22 Is a vertical cross-sectional view showing the steps of depositing a protective layer over the storage region and removing a tunneling dielectric layer, a floating gate layer, a blocking dielectric layer, a control gate layer, and a hard mask layer from a peripheral region in a method for manufacturing a semiconductor device according to some embodiments.

[0030] Figure 23 Is a vertical cross-sectional view showing the steps of forming a gate dielectric layer, a gate electrode layer, and a hard mask layer in a method for manufacturing a semiconductor device according to some embodiments.

[0031] Figure 24 Is a vertical cross-sectional view showing the step of patterning a gate electrode in a method for manufacturing a semiconductor device according to some embodiments.

[0032] Figure 25 Is a vertical cross-sectional view showing the step of forming a sealing layer over a gate stack in a method for manufacturing a semiconductor device according to some embodiments.

[0033] Figure 26 Is a vertical cross-sectional view showing the step of forming spacers in a method for manufacturing a semiconductor device according to some embodiments.

[0034] Figure 27 Is a vertical cross-sectional view showing the step of forming source / drain regions in a method for manufacturing a semiconductor device according to some embodiments.

[0035] Figure 28 Is a vertical cross-sectional view showing the step of planarizing a peripheral region of a substrate in a method for manufacturing a semiconductor device according to some embodiments.

[0036] Figure 29 is a vertical cross-sectional view showing the step of forming a contact in a method for manufacturing a semiconductor device according to some embodiments.

[0037] Figure 30 is Figure 29 a close-up of a portion of the vertical cross-sectional view of.

[0038] Figure 31 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments. Detailed Description

[0039] The following disclosure provides a number of different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0040] Furthermore, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0041] Figure 1A vertical cross-sectional view showing an ESF3 memory cell (MC1 and MC2), also known as a "third-generation SuperFlash" memory cell, according to some embodiments. For example, the ESF3 memory cell MC1 includes a pair of symmetric split-gate memory cells SGMC1, SGMC2, and each of the split-gate memory cells SGMC1, SGMC2 includes a source region CS, a drain region DR, and a channel region CR disposed between the source region CS and the drain region DR. In the ESF3 architecture, the source region CS of each of the split-gate memory cells SGMC1, SGMC2 can be a common source region CS shared with its adjacent cell. Each split-gate memory cell (e.g., SGMC1 and SGMC2) can have its own drain region DR. Those of ordinary skill in the art will understand that the source region CS can also be a designated drain region DR. Thus, in other embodiments, adjacent split-gate memory cells can also share a common drain region DR.

[0042] Within each of the split-gate cells SGMC1, SGMC2, a floating gate FG can be disposed above the channel region CR of the split-gate cells SGMC1, SGMC2. In addition, a control gate CG can be disposed above the floating gate FG. A select gate SG can be disposed on one side of the floating gate FG and the control gate CG (e.g., between the individual source region CS / drain region DR of the ESF3 memory cell MC and the sidewalls of the floating gate FG and / or the control gate CG). An erase gate EG can be disposed above the common source / drain region CS between the split-gate cell SGMC1 and the split-gate cell SGMC2. At least one of the split-gate cells SGMC1, SGMC2 can be configured to store a variable charge level on its floating gate FG, where the level of this charge corresponds to the data state stored in the cell split-gate cells SGMC1, SGMC2 and can be stored in a non-volatile manner such that the stored charge / data persists without power.

[0043] Typical flash memory cells use a floating gate FG to store a bit by the presence or absence of charge. If the floating gate FG is uncharged (i.e., neutral), then the device operates almost like a normal MOSFET. For example, a positive charge in the control gate CG creates a channel CR in the p-type substrate, and the channel CR carries current from the source region CS to the drain region DR. However, if the floating gate FG is negatively charged, then this charge shields the channel region CR from the control gate CG somewhat and prevents a channel from forming between the source CS and the drain DR. The threshold voltage V th is the voltage applied to the control gate CG at which the transistor becomes conductive. The presence or absence of charge results in a more positive threshold voltage Vth or more negative threshold voltages V th . Referring to flash memory terminology, programming (placing electrons into the floating gate FG) refers to writing a 0, and erasing (removing charge from the floating gate FG) refers to resetting the flash memory content to 1; or in other words: a programmed cell stores logic 0, and an erased (also referred to as flash) split gate memory cell SGMC1, SGMC2 stores logic 1.

[0044] Embodiments of the present disclosure relate to flash memory storage structures having self-aligned contacts and methods of manufacturing these flash memory storage structures. Specifically, in a self-alignment process, a hard mask may be used in the fabrication of split gate memory cells SGMC1, split gate memory cells SGMC2 to form a contact etch stop layer. The presence of the contact etch stop layer may reduce the width of the drain contact via (and ultimately the width of the drain contact) formed between split gate memory cells SGMC1 and split gate memory cells SGMC2 by a selective etch process. Compared to split gate memory cells of an EFS3 memory cell formed without using a self-alignment process and a contact etch stop layer, by using a self-alignment process to fabricate the drain contact, an EFS3 memory device may be fabricated in which paired split gate memory cells SGMC1, split gate memory cells SGMC2 of an EFS3 memory cell MC1 may be formed closer to adjacent paired split gate memory cells SGMC1, split gate memory cells SGMC2. Thus, the EFS3 memory device disclosed herein may operate faster than a conventionally formed EFS3 memory device because carriers travel a shorter distance to and within EFS3 memory cells MC1, EFS3 memory cells MC2. Additionally, the disclosed embodiments of the EFS3 memory device may be made smaller than a conventionally formed EFS3 memory device because the disclosed embodiments of EFS3 memory cells MC1, EFS3 memory cells MC2 may be formed closer to each other. Further, better alignment of the self-alignment process may result in more reliable split gate memory cells SGMC1, split gate memory cells SGMC2 than memory cells fabricated without a self-alignment process.

[0045] Figures 2 to 26 are vertical cross-sectional views of different stages of a method 100 for manufacturing a semiconductor device according to some embodiments. It should be understood that additional steps may be implemented before, during, or after method 100, and for other embodiments of method 100, some of the described steps may be replaced or removed.

[0046] See Figure 2, a substrate 210 can be provided. In some embodiments, the substrate 210 can be, for example, a bulk silicon substrate, a germanium substrate, a substrate of a compound substrate, or other suitable substrates. The substrate 210 can include an epitaxial layer overlying a bulk semiconductor, a silicon-germanium layer overlying bulk silicon, a silicon layer overlying bulk silicon-germanium, or a semiconductor-on-insulator (SOI) structure. The substrate 210 can include a storage region 212 and a peripheral region 214. The peripheral region 214 can be arranged such that it surrounds the storage region 212.

[0047] The substrate 210 may include isolation features (e.g., shallow trench isolation structures) IF1 and IF2 formed in the substrate 210. The shallow trench isolation structures IF1 and IF2 may be formed in an upper portion of the substrate 210. For example, a photoresist layer may be coated and patterned over the top surface of the substrate 210, and the pattern in the photoresist layer may be transferred to the upper portion of the substrate 210 by using an anisotropic etching process to form shallow trenches having a depth in the range of 50 nanometers to 500 nanometers through the top surface of the substrate 210. If a positive photoresist is used, the portion of the photoresist to be removed may be developed by exposure to UV light. If a negative photoresist is used, the portion of the photoresist that is to act as a mask may be developed by exposure to UV light. In both cases, the trenches may be etched, for example, by wet etching, after the photoresist is patterned. The photoresist layer may then be removed, for example, by ashing. A dielectric material may be deposited in the shallow trenches, and a planarization process (e.g., a chemical mechanical polishing (CMP) process) may be used to remove the excess portion of the dielectric from above a horizontal plane including the top surface of the substrate 210. The remaining portion of the dielectric material filling the shallow trenches includes the shallow trench isolation structures IF1 and IF2. In some embodiments, the dielectric material may include an oxide and / or other dielectric materials. Optionally, a liner oxide (not shown) may be formed in the trenches. In some embodiments, the liner oxide may be a thermal oxide. In some other embodiments, an in-situ steam generation (ISSG) method may be used to form the liner oxide. In still some other embodiments, a selective area chemical vapor deposition (SACVD) or other CVD method may be used to form the liner oxide. Chemical mechanical polishing (CMP) may then be performed to make the top surface of the dielectric material substantially flush with the top surface of the substrate 210, thereby forming a plurality of isolation features IF1 and IF2 in the trenches. The formation of the liner oxide may reduce the electric field and thus improve the performance of semiconductor devices that may be subsequently formed on the substrate 210. It should be noted that although the figure shows a single isolation feature IF1, embodiments within the scope of the present disclosure may include a plurality of isolation features IF1.

[0048] See Figure 3 , a tunneling layer 220 may be formed over the substrate 210 and the isolation features IF1 and IF2. A floating gate layer 230 may be formed over the tunneling layer 220. The tunneling layer 220 may include, for example: a dielectric material (e.g., silicon dioxide (SiO 2 ), silicon nitride (Si 3 N4 )), silicon oxynitride (SiON)), high-k materials, other non-conductive materials, or combinations thereof. Other suitable dielectric materials are also contemplated within the scope of the present disclosure. The tunneling layer 220 can be deposited using thermal oxidation, ozone oxidation, other suitable processes, or combinations thereof. The floating gate layer 230 can include polysilicon. The floating gate layer 230 can include polysilicon deposited by, for example, low pressure CVD (LPCVD) methods, CVD methods, and PVD sputtering methods using suitable silicon source materials. In some embodiments, the floating gate layer 230 can be ion implanted. In other embodiments, the floating gate layer 230 can include metals, metal alloys, single crystal silicon, or combinations thereof. In an embodiment, the polysilicon layer can be conformally formed over the tunneling layer 220, and then a CMP process can be performed to remove a portion of the polysilicon layer such that the remaining portion of the polysilicon layer (i.e., the floating gate layer 230) can be planarized.

[0049] See Figure 4 , a blocking layer 240, a control gate layer 250, and a hard mask layer 260 can be formed over the substrate 210, the tunneling layer 220, and the floating gate layer 230. The blocking layer 240 can be conformally formed over the floating gate layer 230. In some embodiments, the blocking layer 240 and the tunneling layer 220 can be formed of the same material. In other embodiments, the blocking layer 240 and the tunneling layer 220 can be formed of different materials. That is, the blocking layer 240 can include, for example, a dielectric material (such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON)), high-k materials, other non-conductive materials, or combinations thereof. Other suitable dielectric materials are also within the scope of the present disclosure. Chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), ozone oxidation, other suitable processes, or combinations thereof can be used to form the blocking layer 240, the control gate layer 250, and the hard mask layer 260, respectively.

[0050] The control gate layer 250 can be conformally formed over the blocking layer 240. The control gate layer 250 can include polysilicon. In some embodiments, the control gate layer 250 can be ion implanted. In some other embodiments, the control gate layer 250 can be made of metals, metal alloys, single crystal silicon, or combinations thereof. In some embodiments, the control gate layer 250 can be thicker than the floating gate layer 230.

[0051] The hard mask layer 260 can be conformally formed over the control gate layer 250. In some embodiments, as Figure 4As shown, the hard mask layer 260 may include a stacked layer of a silicon nitride (SiN) layer 260A, a silicon oxide (SiO 2 ) layer 260B, and a silicon nitride (SiN) layer 260C, or other suitable materials. In other embodiments (not shown), the hard mask layer 260 may be formed as a single layer. The single layer of the hard mask layer 260 may include SiN. However, other suitable materials are also within the scope of the present disclosure.

[0052] Referring to Figure 5 , a photoresist (not shown) may be coated and patterned over the top surface of the hard mask layer 260, and the pattern in the photoresist layer may be transferred to the hard mask layer 260, the control gate layer 250, and the blocking layer 240 by using an anisotropic etching process. Subsequently, the photoresist layer may be removed, for example, by ashing. Patterning and etching the hard mask layer 260, the control gate layer 250, and the blocking layer 240 may form storage stacks MS1-MS4 within the storage region 212 of the substrate 210 and form a layer stack over the peripheral region 214. In the Figure 5 embodiment shown, the storage stacks MS1-MS4 may each include a blocking layer 240, a patterned control gate layer 250 that may subsequently form a control gate CG, and a hard mask layer 260. As mentioned above and as Figure 5 shown, the hard mask layer 260 may include a stacked layer of a silicon nitride (SiN) layer 260A, a silicon oxide (SiO 2 ) layer 260B, and a silicon nitride (SiN) layer 260C, or other suitable materials.

[0053] Referring to Figure 6 , at least one dielectric material (such as silicon nitride and / or silicon oxide) may be conformally deposited over the storage stack structure (MS1-MS4). The at least one dielectric material may be anisotropically etched (such as by a reactive ion etching process) to remove the horizontal portions. Each remaining vertical portion that laterally surrounds the corresponding storage stack structure (MS1 to MS4) includes a sidewall spacer 270 that includes at least one dielectric material. Although only a single sidewall spacer 270 of the storage stack structure (MS1-MS4) is shown, in the embodiments expressly covered herein, multiple sidewall spacers are formed over the storage stack structure (MS1-MS4) by sequentially depositing and anisotropically etching multiple dielectric materials.

[0054] Referring to Figure 7, the tunneling layer 220 and the floating gate layer 230 may be patterned such that the memory stacks MS1-MS4 include the patterned floating gate layer 230 forming the floating gate FG and the patterned tunneling layer 220. Thus, at this time in the manufacturing process, each of the memory stacks MS1 to MS4 may include the patterned tunneling layer 220, the floating gate FG, the patterned blocking layer 240, the control gate CG, and the patterned hard mask layer 260.

[0055] See Figure 8 , an inter-gate dielectric layer 280 may be formed over the sidewalls of the memory stacks MS1 to MS4 in a similar manner as described above with respect to the sidewall spacers 270. As Figure 8 shown, the inter-gate dielectric layer 280 may be formed on the sidewall spacers 270 and on the sidewalls of the floating gate FG and the patterned tunneling layer 220. In some embodiments, the inter-gate dielectric layer 280 may include an oxide, a combination of oxide, nitride, and oxide (ONO), and / or other dielectric materials. In some embodiments, forming the inter-gate dielectric layer 280 includes, for example, depositing a blanket layer of dielectric material over the substrate 210 and then performing an etching process to remove the horizontal portions of the blanket layer, and the remaining vertical portions of the blanket layer may serve as the inter-gate dielectric layer 280.

[0056] See Figure 9 , a common source region CS may be formed in the exposed portions of the substrate 210 between the memory stack MS1 and the memory stack MS2 and between the memory stack MS3 and the memory stack MS4. In an embodiment, ions may be implanted into the exposed portions of the substrate 210 to form the common source region CS. The memory stacks MS1 and MS2 may share the common source region CS. Additionally, the memory stacks MS3 and MS4 may share the common source region CS. As mentioned above, one of ordinary skill in the art will recognize that although the common source region CS is shown formed between the memory stack MS1 and the memory stack MS2 (or between the memory stack MS3 and the memory stack MS4) in the figures, the common source region may also serve as a common drain region DR. A common source dielectric layer CSD may be formed over the common source region CS. The common source dielectric layer CSD may be made of silicon oxide. The common source dielectric layer CSD may be formed over the source region CS using, for example, oxidation, CVD, other suitable deposition, or similar processes. In some embodiments, forming the common source dielectric layer CSD (such as oxidation or deposition) includes depositing a dielectric material layer and etching those portions of the dielectric material layer that are not located between the memory stack MS1 and the memory stack MS2 or between the memory stack MS3 and the memory stack MS4, such that the remaining portions of the dielectric layer form the common source dielectric layer CSD located over the common source region CS.

[0057] See Figure 10 , a select gate dielectric layer 300 can be formed adjacent to the memory stacks MS1-MS4 and between the memory stacks MS1 to MS4. The select gate dielectric layer 300 can be an oxide layer or other suitable dielectric layer. For example, the select gate dielectric layer 300 can include silicon oxide, silicon nitride, silicon oxynitride, other non-conductive materials, or combinations thereof. The thickness of the select gate dielectric layer 300 can be in the range of about 5 angstroms to about 500 angstroms to provide suitable electrical isolation between the substrate 210 and the select gate to be formed subsequently. In some embodiments, a thermal oxidation process can be performed such that the portion of the substrate 210 not covered by the memory stacks MS1-MS4 (i.e., the surface of the substrate 210 located between the pairs of memory stacks MS1, MS2 and memory stacks MS3, MS4) and the common source dielectric layer CSD can be oxidized to form the select gate dielectric layer 300. The select gate dielectric layer 300 can be deposited by any suitable method, such as by CVD, plasma-enhanced chemical vapor deposition (PECVD), LPCVD, or other suitable processes.

[0058] See Figure 11 , a conductive layer 310 can be formed over the entire substrate 210 and Figure 11 the structure of. In some embodiments, the conductive layer 310 can be made of polysilicon, other suitable conductive materials, or combinations thereof. For example, the conductive layer 310 can include doped polysilicon or doped amorphous silicon. The conductive layer 310 can be formed by CVD, plasma-enhanced chemical vapor deposition (PECVD), LPCVD, or other suitable processes.

[0059] See Figure 12 , the conductive layer 310 can be etched to remove the excess conductive material of the conductive layer 310 from the regions between the pairs of memory stacks (such as MS1, MS2 and MS3, MS4) and the regions adjacent to the memory stacks MS1-MS4, thereby forming an erase gate EG above the common source region CS between the memory stacks MS1 and MS2 and between the memory stacks MS3 and MS4. Additionally, the material of the etched conductive layer 310 between the pairs of memory stacks MS1, MS2 and the pairs of memory stacks MS3, MS4 can be patterned as discussed below to form a select gate SG at the sides of the memory stacks MS1-MS4 opposite to the erase gate EG.

[0060] See Figure 13, a hard mask layer 320 can be conformally deposited over the etched conductive layer 310 and the memory stacks MS1-MS4. The hard mask layer 320 protects the erase gate EG during subsequent etching steps. The hard mask layer 320 can also be used to pattern the select gate SG, as discussed in more detail below. Additionally, the hard mask layer 320 can be patterned to form a contact etch stop layer 320e in subsequent operations. As discussed in more detail below, the contact etch stop layer 320e can allow the drain / source contact 400 to be narrowed, which ultimately allows for an increase in the density of memory cells on the device. The hard mask layer can be formed by any suitable method such as CVD, plasma enhanced chemical vapor deposition (PECVD), or LPCVD.

[0061] See Figure 14 , a chemical mechanical polishing (CMP) process can be performed to remove the excess portion of the hard mask layer 320 over the memory stacks MS1-MS4. For example, the hard mask layer 320 can be polished down to the top height of the hard mask layer 260 over the memory stacks MS1-MS4. A photoresist (not shown) can be deposited on the top surface of the memory stacks MS1-MS4 and patterned, and an etching process can be performed using the patterned photoresist as a mask such that trenches 211, for example, 20 nanometers to 40 nanometers wide, can be formed in the conductive layer 310 and the hard mask layer 320 below the photoresist between the paired memory stacks MS1, memory stack MS2 and the paired memory stacks MS3, memory stack MS4. In an embodiment, the etching can continue until the top surface of the substrate 210 is reached. In this way, the hard mask layer 320, the conductive layer 310, and the select gate dielectric layer 300 can be removed downward until the top surface of the substrate 210 is exposed, thereby forming the trench 211 between the adjacent paired memory stacks M2, memory stack M3. Additionally, in this way, the select gate SG can be formed on the opposite side of the memory stacks MS1-MS4 from the erase gate EG along the inter-gate dielectric layer 280.

[0062] See Figure 15 , a main sidewall spacer MSW can be formed on the sidewalls of the select gate SG and on the sidewalls of the remaining portion of the hard mask layer 320 above the select gate SG. In an embodiment, the main sidewall spacer MSW comprises silicon nitride. However, other suitable materials are also contemplated within the scope of the present disclosure. In an embodiment, the main sidewall spacer MSW includes silicon nitride and can be formed by any suitable method such as CVD, plasma enhanced chemical vapor deposition (PECVD), or LPCVD.

[0063] See Figure 16, a drain region DR can be formed in the exposed portion of the substrate 210 between the main sidewall spacers MSW. The drain region DR can be formed by a self-aligned ion implantation process or by depositing a thin layer of metal (such as Ti, Ni, W) and heating to react the metal with the substrate to form a metal silicide. The formation of the drain region DR defines the outer boundaries of the split-gate memory cell SGMC1 and the split-gate memory cell SGMC2.

[0064] See Figure 17 , after forming the self-aligned drain region DR, a contact etch stop layer CESL can be conformally deposited on the sidewalls of the main sidewall spacers MSW. The contact etch stop layer CESL can have a thickness in the range of 35 angstroms to 75 angstroms. In an embodiment, a dielectric layer 390 can be formed to fill any open gaps between adjacent pairs of memory stacks M1 - M4. That is, a dielectric material can be deposited on the contact etch stop layer CESL. In an embodiment, a CMP process can be performed to remove the patterned hard mask layer 260 within each memory stack M1 - M4 and reduce the thickness of the hard mask layer 320 formed adjacent to the memory stacks M1 - M4. In an embodiment, the CMP process can be performed such that the resulting hard mask layer 320 above the select gate SG can be in the range of 250 angstroms to 400 angstroms.

[0065] See Figure 18 , an oxide hard mask layer 502 can be deposited above the memory region 212 of the substrate 210. The oxide hard mask layer 502 can be made of any suitable oxide (such as silicon oxide).

[0066] See Figure 19 , a close-up 540 of the memory region 212 is shown, where a photoresist layer 504 is deposited above the oxide hard mask layer 502. The photoresist layer 504 can be patterned to expose selected portions of the oxide hard mask layer 502.

[0067] See Figure 20 , the patterned photoresist layer 504 can be used to pattern the oxide hard mask layer 502 such that the oxide hard mask layer 502 has the same pattern as the patterned photoresist layer 504. As Figure 20 can be seen, after patterning the oxide hard mask layer 502, a first portion 320a of the hard mask layer 320 above the select gate SG is exposed, while the second portion of the hard mask layer 320 is still covered by the patterned oxide hard mask layer 502. In an embodiment, patterning the patterned oxide hard mask layer 502 can be such that the hard mask layer 320 above the erase gate EG is completely exposed.

[0068] See Figure 21, the patterned oxide hard mask layer 502 can be used as a mask to pattern the hard mask layer 320, i.e., to remove the exposed first portion 320a of the hard mask layer 320 to form the contact etch stop layer 320e. Subsequently, the patterned oxide hard mask layer 502 can be removed. The removal of the oxide hard mask layer 502 can be accomplished, for example, using a CMP process. In an embodiment, the portion of the hard mask layer 320 adjacent to the main sidewall MSW (i.e., the contact etch stop layer 320e) is not removed. In an embodiment, a metal (such as Co, Ni, Ti, Ta, W, or an alloy thereof) layer can be deposited over the exposed surfaces of the polysilicon erase gate EG and the select gate SG. The wafer can then be annealed at a temperature in the range of 750 °C to 1000 °C for 1 hour to 2 hours, or laser annealed for a few microseconds to a few seconds depending on the power of the laser, to form the silicide contact region 396 on top of the erase gate EG and the select gate SG. Additionally, the oxide hard mask layer 502 can be removed, for example, using a CMP process.

[0069] See Figure 22 , a protective layer PL2 can be deposited within the memory region 212. The protective layer PL2 can protect the memory region 212 of the substrate 210, and logic devices can then be formed in the peripheral region 214 of the substrate, as discussed in more detail below. See also Figure 18 , the tunneling layer 220, the floating gate layer 230, the blocking layer 240, the control gate layer 250, and the hard mask layer 260 can be removed from the substrate 210 while the second protective layer PL2 protects the memory region 212 of the substrate 210. The tunneling layer 220, the floating gate layer 230, the blocking layer 240, the control gate layer 250, and the hard mask layer 260 can be removed in a series of etching steps (e.g., by a series of wet etching steps).

[0070] See Figure 23, a gate dielectric layer 330, a gate electrode layer 340, and a hard mask layer 350 can be conformally deposited over the storage region 212 and the peripheral region 214. In this document, one or more processes (e.g., one or more lithography processes and etching processes) can be initially performed to remove any protrusions of the isolation features IF1 and IF2, such that a flat surface is created in the peripheral region 214. Subsequently, the gate dielectric layer 330, the gate electrode layer 340, and the hard mask layer 350 can be formed over the substrate 210 in sequence. The gate dielectric layer 330 can be made of a suitable high-k material, other non-conductive materials, or a combination thereof. Examples of high-k materials include but are not limited to: hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium oxide-aluminum (HfO 2 -Al 2 O 3 ) or other applicable dielectric materials. The gate electrode layer 340 can be made of a conductive material (e.g., a polysilicon layer). The hard mask layer 350 can be made of silicon nitride or other suitable materials. Optionally, a planarization process can be performed on the surface of the substrate 210 before forming the gate dielectric layer 330, the gate electrode layer 340, and the hard mask layer 350.

[0071] In some embodiments, the gate dielectric layer 330 can be thicker in the regions where high-voltage devices can be formed and thinner in the regions where low-voltage devices can be formed. Thus, the selected gate dielectric layer 300 can have a thick region and a thin region that is thinner than the thick region. Accordingly, the gate dielectric layer 330 can have a thick region and a thin region that is thinner than the thick region. Exemplary methods for achieving different thicknesses can include conformally depositing the gate dielectric layer 330, masking a first region of the gate dielectric layer 330 while leaving a second region of the gate dielectric layer unmasked, and thinning (e.g., etching) the second region of the gate dielectric layer 330. Consequently, the resulting second region is thinner than the first region.

[0072] See Figure 24, the gate dielectric layer 330, the gate electrode layer 340, and the hard mask layer 350 may be patterned to form gate stack GS1, gate stack GS2, and gate stack GS3. In an embodiment, the gate stack GS1 may be a dummy gate stack located above the exposed first isolation feature IF1. The second gate stack GS2 may be a high-voltage storage stack. The third gate stack GS3 may be a logic storage stack formed above the peripheral region 214. The patterning may be performed by any suitable lithography process and etching process.

[0073] See Figure 25 , a seal layer 382 may be formed on the opposing sidewalls of the dummy storage stack GS1, the high-voltage storage stack GS2, and the logic storage stack GS3. For example, a dielectric seal layer may be conformally formed above the structures in the Figure 21 peripheral region 214 of, and an etching process (e.g., an anisotropic etching process) may be performed to remove the horizontal portions of the dielectric seal layer. The vertical portions of the remaining dielectric seal layer are left to form the seal layer 382. The seal layer 382 may be made of silicon nitride or other suitable materials. Other suitable materials are also contemplated within the scope of the present disclosure.

[0074] See Figure 26 , sidewall spacers 369 may be formed on the seal layer 382 on the sidewalls of the gate stacks GS1 to GS3. The sidewall spacers 369 may be formed of a dielectric material (e.g., silicon nitride, silicon oxide) and / or other dielectric materials or combinations thereof. The sidewall spacers 369 may be made by any suitable method such as CVD, plasma enhanced chemical vapor deposition (PECVD), or LPCVD. For example, a dielectric spacer layer may be conformally formed above the Figure 22 structures of, and an etching process (e.g., an anisotropic etching process) may be performed to remove the horizontal portions of the dielectric spacer layer and retain the vertical portions of the dielectric spacer layer to form the sidewall spacers 369.

[0075] See Figure 27 , source / drain regions SD1 and source / drain regions SD2 may be formed in the peripheral region 214 of the substrate 210. The source / drain regions SD1 and source / drain regions SD2 may be made by ion implantation processes or by forming silicides with the exposed portions of the substrate 210.

[0076] See Figure 28 , a planarization process (e.g., CMP) may be selectively performed to remove the hard mask layer 350. Optionally, the planarization process may expose the top surfaces of the gate stacks GS1 to GS3.

[0077] See Figure 29, the second protective layer PL2 can be removed from the storage region 212 of the substrate 210, and the interlayer dielectric layer 401 and the interlayer dielectric layer 402 can be formed over the entire surface of the substrate 210. A drain or source (drain / source) contact 400 can be formed in the storage region 212 of the substrate 210, and source / drain contacts C1 to C4 can be formed in the peripheral portion of the substrate 210. The drain / source contact 400 and the source / drain contacts C1 to C4 can be formed by anisotropically etching vias in the interlayer dielectric layer 401 and the interlayer dielectric layer 402 and filling the vias with a conductive material (such as polysilicon or a metal (such as Ni, Ti, W, Cu, Al, or an alloy thereof)). In an embodiment, the interlayer dielectric layer 401, the interlayer dielectric layer 402, and the dielectric layer 390 between adjacent pairs of storage stacks M1 - M4 can be made of an oxide, while the contact etch stop layer 320e can be made of silicon nitride. Thus, the anisotropic etching used to form the vias can be selected to etch the oxide selectively with respect to the nitride. Therefore, when the dielectric layer 390 is removed, the contact etch stop layer 320e will cause the vias to narrow. In this way, the drain / source contact 400 can be self - aligned with the drain / source region DR while being narrower than the drain / source contact formed without self - aligning the drain / source contact 400 with the drain / source region DR using the contact etch stop layer 320e. In this way, the first split - gate memory cell SGMC1 and the second split - gate memory cell SGMC2 can be closer to each other than in the case where the drain / source contacts are not self - aligned.

[0078] See Figure 30 , presenting Figure 29 a close - up of. As Figure 30 can be seen, the drain / source contact 400 includes a first wide portion 404 located above the contact etch stop layer 320e and a second narrow portion 405 located adjacent to and below the contact etch stop layer 320e. That is, the drain / source contact 400 made using a self - alignment process results in a drain / source contact 400 having a profile discontinuity at the contact etch stop layer 320e. Above the contact etch stop layer 320e, the drain / source contact 400 includes a first portion 404, and below the contact etch stop layer 320e, the drain / source contact 400 includes a second portion 405. Thus, the drain contact can have a profile discontinuity at the contact etch stop layer 320e located above the first split - gate memory cell and the second split - gate memory cell (SGMC1 and SGMC2), where the drain / source contact 400 can have a first portion 404 above the etch stop layer and a second portion 405 below the contact etch stop layer 320e, and the first portion 404 is wider than the second portion 405.

[0079] As Figure 30 shown, the contact etch stop layer 320e and the contact etch stop layer (CESL) formed on the main sidewall spacer MSW narrow the width of the etched via hole. The width of the via hole narrowed using the contact etch stop layer 320e and the contact etch stop layer (CESL) narrows the width of the via hole and the subsequent drain / source contact 400 to W1. Conversely, the drain contact via hole and the subsequent drain contact 400N formed without the contact etch stop layer 320e and the contact etch stop layer CESL can be formed to have a width W2.

[0080] Figure 31 is a process flow diagram of a method 100 for manufacturing an EFS3 memory device at different stages according to some embodiments. Referring to Figure 31 , method 100 begins at operation 102 where at least two separate gate memory cells SGMC1, SGMC2 are formed on substrate 210. Method 100 then proceeds to operation 104 where a hard mask layer 320 can be patterned to subsequently form a contact etch stop layer 320e. Next, method 100 proceeds to operation 106 where an interlayer dielectric layer 401, an interlayer dielectric layer 402 can be formed over substrate 210. Referring to Figure 31 , method 100 proceeds to operation 108 where an etching process can be performed to form a via hole to expose the drain region DR and the source / drain regions SD1 and SD2. In an embodiment, the etching process includes anisotropically etching the interlayer dielectric layer 401, the interlayer dielectric layer 402, and the dielectric layer 390 located between at least two separate gate memory cells SGMC1, separate gate memory cell SGMC2 such that when removing the interlayer dielectric layer 401 over the two separate gate memory cells SGMC1, SGMC2 and the dielectric layer 390 located between at least two separate gate memory cells SGMC1, SGMC2, the contact etch stop layer 320e causes the drain contact via hole to narrow.

[0081] Embodiments of the present disclosure relate to flash memory storage structures having self-aligned drain contacts and methods of fabricating such structures. Specifically, in a self-alignment process, a hard mask may be used to form a contact etch stop layer in the fabrication of split gate memory cells SGMC1 and split gate memory cells SGMC2. The presence of the contact etch stop layer may reduce the width of the drain contact via (and ultimately the width of the drain contact) between the split gate memory cells SGMC1 and the split gate memory cells SGMC2 formed by a selective etch process. Compared to the split gate memory cells of an EFS3 memory cell formed without using a self-alignment process and a contact etch stop layer, by using a self-alignment process to fabricate the drain contact, the paired split gate memory cells SGMC1 and SGMC2 of the EFS3 memory cell MC1 in the fabricated EFS3 memory device can be made closer to adjacent paired split gate memory cells SGMC1 and SGMC2. Thus, the EFS3 memory device disclosed herein can operate faster than an EFS3 memory device formed by a conventional method because the distance that carriers travel to and within the EFS3 memory cells MC1 and EFS3 memory cells MC2 is shorter. Additionally, the disclosed embodiments of the EFS3 memory device can be made smaller because the disclosed embodiments of the EFS3 memory cells MC1 and memory cells MC2 can be formed closer to each other. Further, better alignment of the self-alignment process can result in more reliable split gate memory cells SGMC1 and split gate memory cells SGMC2 than memory cells fabricated without using a self-alignment process.

[0082] An embodiment relates to a memory device that includes a first split gate memory cell SGMC1 having a first memory stack MS located above a substrate 210. The first memory stack MS includes a first floating gate FG and a first control gate CG located above the first floating gate FG. The first split gate memory cell SGMC1 also has a first select gate SG located adjacent to the first floating gate FG and the first control gate CG, and a contact etch stop layer 320e located above a portion of the top surface of the first select gate SG.

[0083] In the above memory device, it further includes: a second memory stack, a second select gate, and a second contact etch stop layer. The second memory stack is located above the substrate, and the second memory stack includes a second floating gate and a second control gate located above the first floating gate. The second select gate is adjacent to the second floating gate and the second control gate. The second contact etch stop layer is located above a portion of the top surface of the second select gate.

[0084] In the above-mentioned memory device, a first erase gate is further included, which is located between the first memory stack and the second memory stack.

[0085] In the above-mentioned memory device, a common source is further included, which is located below the first erase gate.

[0086] In the above-mentioned memory device, the following are further included: a second split-gate memory cell, including: a third memory stack located above a substrate, the third memory stack including a third floating gate and a third control gate located above the first floating gate; and a third select gate adjacent to the third floating gate and the third control gate; and a third contact etch stop layer located above a part of the top surface of the third select gate; and a fourth memory stack located above the substrate, the fourth memory stack including a fourth floating gate and a fourth control gate located above the fourth floating gate; and a fourth select gate adjacent to the fourth floating gate and the second control gate; and a fourth contact etch stop layer located above a part of the top surface of the fourth select gate; a second erase gate located between the third memory stack and the fourth memory stack; and a drain region located between the second memory stack and the third memory stack.

[0087] In the above-mentioned memory device, a self-aligned drain contact in contact with the drain region is further included.

[0088] In the above-mentioned memory device, the drain contact has a profile discontinuity at each of the second contact etch stop layer and the third contact etch stop layer located above the second select gate and the third select gate. The drain contact has a first part and a second part. The first part is located above the second contact etch stop layer and the third contact etch stop layer located above the second select gate and the third select gate, and the second part is located below the second contact etch stop layer and the third contact etch stop layer located above the second select gate and the third select gate, and the first part is wider than the second part.

[0089] In the above-mentioned memory device, the drain region includes implanted ions.

[0090] In the above-mentioned memory device, the drain region includes self-aligned silicide.

[0091] Another embodiment relates to a memory device, the memory device comprising: a first split-gate memory cell SGMC1 located on a substrate 210; a second split-gate memory cell SGMC2 located on the substrate 210; and a drain / source contact 400 located between the first split-gate memory cell SGMC1 and the second split-gate memory cell SGMC2 and electrically connected to a drain / source region DR in the substrate 210. The drain / source contact 400 has a profile discontinuity at a contact etch stop layer 320e located above the first split-gate memory cell SGMC1 and the second split-gate memory cell SGMC2, wherein the drain / source contact 400 has a first portion located above the contact etch stop layer 320e and a second portion located below the contact etch stop layer 320e, and the first portion is wider than the second portion.

[0092] In the above memory device, wherein the second portion of the drain contact has a constant diameter perpendicular to the surface of the substrate.

[0093] In the above memory device, wherein the drain region is self-aligned.

[0094] In the above memory device, wherein the substrate is a silicon-on-insulator substrate.

[0095] In the above memory device, further comprising logic transistors located in a peripheral region of the substrate.

[0096] Another embodiment relates to a method of manufacturing a memory device, the method including the operation of forming at least two separate gate memory cells (e.g., SGMC1, SGMC2) on a substrate 210. Each of the at least two separate gate memory cells (e.g., SGMC1, SGMC2) includes: a pair of memory stacks (e.g., MS1, MS2), the pair of memory stacks including a floating gate FG and a control gate CG located above the floating gate FG; a common source CS located between the pair of memory stacks (e.g., MS1, MS2); an erase gate EG located above the common source CS; a select gate SG adjacent to each of the memory stacks (e.g., MS1, MS2), the select gate SG being located opposite to the erase gate EG; and a dielectric layer located between the at least two separate gate memory cells (e.g., SGMC1, SGMC2). The method of manufacturing a memory device further includes the operation of patterning a hard mask layer 320 above the at least two separate gate memory cells (e.g., SGMC1, SGMC2) to form a contact etch stop layer 320e above the select gate SG. The method further includes the operation of forming an interlayer dielectric layer 401 and an interlayer dielectric layer 402 above the at least two separate gate memory cells (e.g., SGMC1, SGMC2). The method of manufacturing a memory device further includes the following operation: anisotropically etching the interlayer dielectric layer 402 and the dielectric layer 390 located between the at least two separate gate memory cells (e.g., SGMC1, SGMC2) such that when the interlayer dielectric layer 402 located above the at least two separate gate memory cells (e.g., SGMC1, SGMC2) and the dielectric layer 390 located between the at least two separate gate memory cells (e.g., SGMC1, SGMC2) are removable, the contact etch stop layer 320e causes the drain contact via to narrow.

[0097] In the above method of manufacturing a memory device, it further includes depositing a conductive material in the drain contact via to form a drain contact, the drain contact being in electrical contact with a drain region in the substrate located between the at least two separate gate memory cells.

[0098] In the above method of manufacturing a memory device, wherein the drain contact has a profile discontinuity, wherein a diameter of a lower portion of the drain contact is smaller than a diameter of an upper portion of the drain contact.

[0099] In the above method of manufacturing a memory device, it further includes forming a self-aligned drain region between the at least two separate gate memory cells using the hard mask layer to self-align the drain region.

[0100] In the above method of manufacturing a memory device, wherein the self-aligned drain region is formed by implanting ions into the substrate by ion implantation using the hard mask layer as a mask.

[0101] In the method of manufacturing a memory device described above, wherein the self-aligned drain region is formed by depositing a metal in a region between the at least two split-gate memory cells and reacting the metal with the substrate, wherein the substrate comprises silicon.

[0102] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: A first split-gate memory cell, comprising: A first memory stack located above a substrate, the first memory stack comprising: A first floating gate; and A first control gate located above the first floating gate; A first select gate adjacent to the first floating gate and the first control gate; A first contact etch stop layer located above a portion of the top surface of the first select gate; A main sidewall spacer laterally contacting the first select gate and the first contact etch stop layer; A first drain region adjacent to the first memory stack; and A first self-aligned drain region contact longitudinally extending to the first drain region and laterally contacting the first select gate and the first contact etch stop layer via the main sidewall spacer, and having a profile discontinuity at the first contact etch stop layer.

2. The memory device according to claim 1, further comprising: A second memory stack located above the substrate, the second memory stack comprising: A second floating gate; and A second control gate located above the first floating gate; A second select gate adjacent to the second floating gate and the second control gate; and A second contact etch stop layer located above a portion of the top surface of the second select gate.

3. The memory device according to claim 2, further comprising a first erase gate located between the first memory stack and the second memory stack.

4. The memory device according to claim 3, further comprising a common source located below the first erase gate.

5. The memory device according to claim 4, further comprising: A second split-gate memory cell, comprising: A third memory stack located above the substrate, the third memory stack comprising: A third floating gate; and A third control gate located above the third floating gate; A third select gate adjacent to the third floating gate and the third control gate; A third contact etch stop layer located above a portion of the top surface of the third select gate; A fourth memory stack located above the substrate, the fourth memory stack comprising: A fourth floating gate; and A fourth control gate located above the fourth floating gate; A fourth select gate adjacent to the fourth floating gate and the second control gate; A fourth contact etch stop layer located above a portion of the top surface of the fourth select gate; and A second erase gate located between the third memory stack and the fourth memory stack; and A second drain region located between the second memory stack and the third memory stack.

6. The memory device according to claim 5, further comprising a second self-aligned drain contact contacting the second drain region.

7. The memory device according to claim 6, wherein the first contact etch stop layer, the second contact etch stop layer, the third contact etch stop layer, and the fourth contact etch stop layer each comprise silicon nitride.

8. The memory device according to claim 6, further comprising: A third drain region, adjacent to the fourth memory stack; and a third self-aligned drain contact, in contact with the third drain region.

9. The memory device according to claim 8, further comprising logic transistors located in a peripheral region of the substrate.

10. The memory device according to claim 6, wherein the second drain region comprises implanted ions.

11. The memory device according to claim 6, wherein the second drain region comprises self-aligned silicide.

12. A memory device comprising a first split-gate memory cell, comprising: a first memory stack; a first select gate, adjacent to the first memory stack; a first contact etch stop layer, located above the first select gate; and a first main sidewall spacer, laterally contacting the first select gate and the first contact etch stop layer; a second split-gate memory cell, comprising: a second memory stack; a second select gate, adjacent to the second memory stack; a second contact etch stop layer, located above the second select gate; and a second main sidewall spacer, laterally contacting the second select gate and the second contact etch stop layer; and a drain region, located between the first memory stack and the second memory stack; and a self-aligned drain contact, longitudinally extending to contact the drain region and laterally contacting the first select gate and the first contact etch stop layer via the first main sidewall spacer, and laterally contacting the second select gate and the second contact etch stop layer via the second main sidewall spacer, wherein the self-aligned drain contact has a profile discontinuity at each of the first contact etch stop layer and the second contact etch stop layer located above the first select gate and the second select gate, and wherein the self-aligned drain contact has a first portion and a second portion, the first portion being located above the first contact etch stop layer and the second contact etch stop layer located above the first select gate and the second select gate, the second portion being located below the first contact etch stop layer and the second contact etch stop layer located above the first select gate and the second select gate, and the first portion being wider than the second portion.

13. The memory device according to claim 12, wherein a sidewall of the second portion of the self-aligned drain contact is perpendicular to a top surface of the drain region.

14. The memory device according to claim 13, wherein the first portion of the self-aligned drain contact has a varying diameter, the varying diameter being wider at a top surface of the first portion of the self-aligned drain contact.

15. A memory device, comprising: a first split-gate memory cell, located on a substrate; a second split-gate memory cell, located on the substrate; A drain contact, located between the first split-gate memory cell and the second split-gate memory cell and electrically connected to a drain region in the substrate, wherein the drain contact has a profile discontinuity at a contact etch stop layer located above the first split-gate memory cell and the second split-gate memory cell, wherein the drain contact has a first portion above the contact etch stop layer and a second portion below the contact etch stop layer, and the first portion is wider than the second portion; and a main sidewall spacer, laterally spacing the second portion of the drain contact from the contact etch stop layer.

16. The memory device according to claim 15, wherein the second portion of the drain contact has a constant diameter perpendicular to the surface of the substrate.

17. The memory device according to claim 16, wherein the drain region is self-aligned.

18. The memory device according to claim 15, wherein the substrate is a silicon-on-insulator substrate.

19. The memory device according to claim 15, further comprising logic transistors in a peripheral region of the substrate.

20. The memory device according to claim 15, wherein the contact etch stop layer comprises silicon nitride.

21. A method of manufacturing a memory device, comprising: forming at least two split-gate memory cells on a substrate, each of the at least two split-gate memory cells comprising: a pair of memory stacks, comprising a floating gate and a control gate located above the floating gate; a common source, located between the pair of memory stacks; an erase gate, located above the common source; and a select gate, adjacent to each of the pair of memory stacks, the select gate being located opposite to the erase gate; and a dielectric layer, located between the at least two split-gate memory cells; patterning a hard mask layer above the at least two split-gate memory cells to form a contact etch stop layer above the select gate; forming an interlayer dielectric layer above the at least two split-gate memory cells; and anisotropically etching the interlayer dielectric layer and the dielectric layer located between the at least two split-gate memory cells such that when the interlayer dielectric layer above the at least two split-gate memory cells and the dielectric layer located between the at least two split-gate memory cells are removed, the contact etch stop layer causes the drain contact via to narrow.

22. The method of manufacturing a memory device according to claim 21, further comprising depositing a conductive material in the drain contact via to form a drain contact that electrically contacts a drain region in the substrate located between the at least two split-gate memory cells.

23. The method of manufacturing a memory device according to claim 22, wherein the drain contact has a profile discontinuity, wherein the diameter of the lower portion of the drain contact is smaller than the diameter of the upper portion of the drain contact.

24. The method of manufacturing a memory device according to claim 21 further comprises forming a self-aligned drain region between the at least two separate gate memory cells using the hard mask layer to be self-aligned with the drain region.

25. The method of manufacturing a memory device according to claim 24, wherein the self-aligned drain region is formed by implanting ions into the substrate by ion implantation using the hard mask layer as a mask.

26. The method of manufacturing a memory device according to claim 24, wherein the self-aligned drain region is formed by depositing a metal in a region between the at least two separate gate memory cells and reacting the metal with the substrate, wherein the substrate comprises silicon.

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