Clock generator and display device including the same

Abstract

Disclosed are a clock generator and a display device including the clock generator, the display device including: a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals with different phases based on the on-clock signal and the off-clock signal when the enable signal has a first voltage level, wherein when the enable signal has a second voltage level different from the first voltage level, the clock generator inserts a common pulse into each of the plurality of clock signals based on the common signal; and a gate driver configured to generate a gate signal based on the plurality of clock signals and sequentially provide the gate signals to the gate lines.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0006811 filed on January 17, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure generally relates to a clock generator and a display device including the clock generator. Background Art

[0003] Each pixel of the display device may emit light at a brightness corresponding to a data signal input through a data line, and the display device may display a frame image through a combination of light emitted from the pixels.

[0004] When a display device displays a moving image, a blurred afterimage is viewed because the previous image and the current image overlap each other. In order to prevent a phenomenon in which an afterimage is viewed (e.g., a motion blur phenomenon), a technology for displaying a black image between frames of a moving image (or a black frame insertion technology) has been developed.

[0005] The display device may generate a plurality of clock signals having different phases by using a level shifter (or a clock generator), and the gate driver may generate a scan signal by using the clock signals.

[0006] As the resolution and / or driving frequency of the display device increases, multiple level shifters that generate a larger number of clock signals (or clock signals to which the black frame insertion technique is applied) may be used. As the number of level shifters increases, the number of input signals and related components (e.g., control signals, lines for transmitting control signals, and / or input terminals) for individually driving the level shifters increases. Summary of the invention

[0007] Example embodiments of the present disclosure provide a clock generator and a display device which can reduce the number of input signals for clock generation and signal lines and / or input terminals related thereto.

[0008] According to one or more example embodiments of the present disclosure, there is provided a display device, comprising: a display unit including a gate line and a pixel electrically coupled to the gate line; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals with different phases based on the on-clock signal and the off-clock signal when the enable signal has a first voltage level, wherein when the enable signal has a second voltage level different from the first voltage level, the clock generator inserts a common pulse into each of the plurality of clock signals based on the common signal; and a gate driver configured to generate a gate signal based on the plurality of clock signals and sequentially provide the gate signals to the gate lines.

[0009] In one or more embodiments, the common signal may include a first pulse having an on-voltage level, the first pulse being repeated at a first time interval, the open clock signal may include a second pulse having an on-voltage level in a time period in which the common signal has a cut-off voltage level, and the second pulse may be repeated at a second time interval shorter than the first time interval in the time period in which the common signal has the cut-off voltage level.

[0010] In one or more embodiments, the off-clock signal may include a third pulse having an on-voltage level in a period in which the common signal has an off-voltage level. In one or more embodiments, the off-clock signal may have a phase that is p-0.5 times delayed from the on-clock signal by a second time interval, where p is a positive integer.

[0011] In one or more embodiments, the clock generator may generate the multiple clock signals based on the triggering of the on-clock signal and the off-clock signal having opposite polarities. In one or more embodiments, the clock generator may generate the multiple clock signals based on the rising edge of the second pulse of the on-clock signal and the falling edge of the third pulse of the off-clock signal. In one or more embodiments, the rising edges of the multiple clock signals may occur simultaneously with the rising edge of the second pulse, and the falling edges of the multiple clock signals may occur simultaneously with the falling edge of the third pulse.

[0012] In one or more embodiments, when the enable signal has the second voltage level, the common signal may include at least one of the first pulses.

[0013] In one or more embodiments, the plurality of clock signals output from the clock generator may include a first clock signal and a second clock signal. In one or more embodiments, when the enable signal has a second voltage level, the first clock signal and the second clock signal may have a common pulse at the same time.

[0014] In one or more embodiments, the clock generator may include: a masking circuit configured to generate a modulated on-clock signal by masking at least some pulses of the on-clock signal based on an enable signal having a second voltage level; a first clock generating circuit configured to generate a reference clock signal based on the modulated on-clock signal and the off-clock signal; a second clock generating circuit configured to generate a common pulse based on the enable signal having a second voltage level and a common signal; and a third clock generating circuit configured to generate the multiple clock signals by inserting a common pulse into the reference clock signal.

[0015] In one or more embodiments, at least some of the plurality of clock signals may overlap with a period in which the enable signal has the second voltage level.

[0016] In one or more embodiments, the clock generator may include a plurality of level shifters configured to generate some of the plurality of clock signals, respectively. In one or more embodiments, the on-clock signal, the off-clock signal, and the common signal may be provided to the plurality of level shifters in common. In one or more embodiments, the enable signal may be provided to the plurality of level shifters individually.

[0017] In one or more embodiments, the enable signal may include multiple sub-enable signals. In one or more embodiments, the sub-enable signals may have the same waveform with different phases.

[0018] In one or more embodiments, the gate driver may include a plurality of stages configured to generate gate signals respectively. In one or more embodiments, each of the plurality of stages may generate a carry signal based on a carry clock signal and a previous carry signal of a previous stage, and generate a scan signal based on a previous carry signal and a scan clock signal. In one or more embodiments, the scan signal may be included in one or more of the gate signals. In one or more embodiments, the carry clock signal and the scan clock signal may be included in the plurality of clock signals. In one or more embodiments, the clock generator may include: a first sub-level shifter configured to generate a scan clock signal based on an on-clock signal, an off-clock signal, an enable signal, and a common signal; and a second sub-level shifter configured to generate a carry clock signal based on an on-clock signal, an off-clock signal, and an enable signal.

[0019] In one or more embodiments, the second sub-level shifter may include: a masking circuit configured to generate a modulated on-clock signal by masking at least some pulses of the on-clock signal based on an enable signal having a second voltage level; and a first clock generating circuit configured to generate a carry clock signal based on the modulated on-clock signal and the off-clock signal.

[0020] In one or more embodiments, the gate driver may simultaneously generate gate signals having turn-on voltage levels based on a common pulse.

[0021] In one or more embodiments, the display device may further include a data driver configured to supply data signals to the pixels. The data driver may provide black data signals corresponding to a black image to at least some of the pixels in a period in which the gate signals simultaneously have a turn-on voltage level.

[0022] According to one or more example embodiments of the present disclosure, there is provided a display device, comprising: a display unit including a gate line and a pixel electrically coupled to the gate line; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, wherein the clock generator inserts a common pulse into each of the plurality of clock signals based on the enable signal and the common signal; and a gate driver configured to generate a gate signal based on the plurality of clock signals and sequentially provide the gate signal to the gate line, wherein the clock generator includes a common line, a dedicated line, and a plurality of level shifters to generate the plurality of clock signals, wherein the on-clock signal, the off-clock signal, and the common signal are commonly provided to the plurality of level shifters through the common line, and wherein the enable signal is individually provided to the plurality of level shifters through the dedicated line.

[0023] In one or more embodiments, the gate driver may include a plurality of stages configured to generate gate signals respectively. In one or more embodiments, each of the plurality of stages may generate a carry signal based on a carry clock signal and a previous carry signal of a previous stage, and generate a scan signal based on a previous carry signal and a scan clock signal. In one or more embodiments, the scan signal may be included in one or more of the gate signals. In one or more embodiments, the carry clock signal and the scan clock signal may be included in the plurality of clock signals. In one or more embodiments, the clock generator may include: a first sub-level shifter configured to generate a scan clock signal based on an on-clock signal, an off-clock signal, an enable signal, and a common signal; and a second sub-level shifter configured to generate a carry clock signal based on an on-clock signal, an off-clock signal, and an enable signal.

[0024] In one or more embodiments, the first sub-level shifter generates a scan clock signal based on a scan on clock signal, a scan off clock signal, a scan enable signal, and a scan common signal; and the second sub-level shifter generates a carry clock signal based on a carry on clock signal, a carry off clock signal, and a carry enable signal.

[0025] In one or more embodiments, the first sub-level shifter may include: a masking circuit configured to generate a modulated scan-on clock signal based on a scan enable signal having a second voltage level by masking at least some pulses of a scan-on clock signal; a first clock generating circuit configured to generate a reference scan clock signal based on the modulated scan-on clock signal and a scan-off clock signal; a second clock generating circuit configured to generate a scan common pulse based on a scan enable signal having a second voltage level and a scan common signal; and a third clock generating circuit configured to generate a scan clock signal by inserting a scan common pulse into the reference scan clock signal.

[0026] According to another example embodiment of the present disclosure, a clock generator is provided, which includes: a level shifter configured to generate a plurality of clock signals with different phases based on an on-clock signal and an off-clock signal, wherein the level shifter is configured to insert a common pulse into each of the plurality of clock signals based on an enable signal and a common signal; a common line configured to commonly provide the on-clock signal, the off-clock signal and the common signal to the level shifter; and a dedicated line configured to individually provide the enable signal to the level shifter.

[0027] In one or more embodiments, each of the level shifters may include: a first clock generating circuit configured to generate the multiple clock signals with different phases based on the on-clock signal and the off-clock signal when the enable signal has a first voltage level; and a second clock generating circuit configured to insert a common pulse into each of the outputs of the first clock generating circuit based on the common signal when the enable signal has a second voltage level different from the first voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, example embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0029] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals always refer to the same elements.

[0030] Figure 1 is a diagram illustrating an example display device according to one or more embodiments of the present disclosure.

[0031] Figure 2 It is a diagram showing one or more embodiments according to the present disclosure including Figure 1 An example circuit diagram of an example of a pixel in a display device is shown in FIG.

[0032] Figure 3 It is a diagram showing one or more embodiments according to the present disclosure including Figure 1 FIG. 4 is a diagram of an example operation of a display unit in a display device shown in FIG.

[0033] Figure 4A and Figure 4B The present invention is a diagram showing one or more embodiments of the present invention. Figure 2 A waveform diagram of an example operation of a pixel is shown in FIG.

[0034] Figure 5 It is a diagram showing one or more embodiments according to the present disclosure including Figure 1 A diagram of an example of a gate driver in a display device is shown in FIG.

[0035] Figure 6 It is a diagram showing one or more embodiments according to the present disclosure including Figure 5 A diagram of an example of a stage in a gate driver is shown in FIG.

[0036] Figure 7 It is a diagram showing one or more embodiments according to the present disclosure including Figure 1 A diagram of an example of a clock generator in a display device is shown in FIG.

[0037] Figure 8 It is a diagram showing one or more embodiments according to the present disclosure including Figure 7 FIG. 4 is a diagram of an example of a first level shifter in a clock generator shown in FIG.

[0038] Fig. 9 The present invention is a diagram showing one or more embodiments of the present invention. Figure 7 2 is a waveform diagram of an example of a signal measured in a clock generator.

[0039] Fig.10 According to one or more embodiments of the present disclosure Fig. 9 Amplified waveform of .

[0040] Fig.11 It is a diagram showing one or more embodiments according to the present disclosure including Figure 8 FIG. 4 is a diagram of an example of a first sub-level shifter in a first level shifter shown in FIG.

[0041] Fig. 12A and Fig. 12B The present invention is a diagram showing one or more embodiments of the present invention. Fig.11 2 is a waveform diagram of the operation of the first sub-level shifter shown in FIG.

[0042] Fig.13 It is a diagram showing one or more embodiments according to the present disclosure including Figure 8 FIG. 4 is a diagram of an example of a third sub-level shifter in a first level shifter shown in FIG.

[0043] Fig.14 The present invention is a diagram showing one or more embodiments of the present invention. Figure 7 FIG. 4 is a waveform diagram of another example of a signal measured in a clock generator shown in FIG.

[0044] Fig.15 and Fig.16 The present invention is a diagram showing one or more embodiments of the present invention. Figure 7 0 is a waveform diagram of yet another example of a signal measured in a clock generator shown in FIG. DETAILED DESCRIPTION

[0045] Hereinafter, example embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. The present disclosure may be implemented in various different forms and is not limited to the example embodiments described in this specification.

[0046] Parts not related to the description will be omitted to clearly describe the present disclosure, and throughout the specification, the same or similar constituent elements will be represented by the same reference numerals. Therefore, the same reference numerals may be used to identify the same or similar elements in different drawings.

[0047] In the present disclosure, for better understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. For clear expression, the thickness of several parts and regions is exaggerated.

[0048] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, first component, first region, first layer or first part discussed herein may be referred to as the second element, second component, second region, second layer or second part.

[0049] For ease of description, spatial relative terms such as "under ...", "below ...", "below ...", "below ...", "above ...", "on ...", etc. may be used here to describe the relationship between an element or feature and another (other) element or feature as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, such spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the figure is turned over, the element described as "below" or "below" or "below" other elements or features will then be positioned as "above" other elements or features. Therefore, the exemplary terms "below ..." and "below ..." can include both above and below orientations. The device can be positioned in addition (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used here should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between" two layers, the layer can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0050] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the terms "substantially," "about," and similar terms are used as approximate terms rather than terms of degree, and are intended to account for inherent deviations in measurements or calculations that would be recognized by those of ordinary skill in the art.

[0051] As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "one (person / kind)" are also intended to include plural forms. It will also be understood that when the term "including" is used in this specification, it is explained that the stated features, wholes, steps, operations, elements and / or components exist, but it does not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. When a statement such as "at least one (person / kind) of..." is located after a column of elements, it modifies the entire column of elements without modifying the individual elements in the column. In addition, when describing embodiments of the present disclosure, the use of "can" refers to "one or more embodiments of the present disclosure". In addition, the term "exemplary" is intended to indicate an example or explanation. As used herein, the term "use" can be considered to be synonymous with the term "utilize".

[0052] It will be understood that when an element or layer is referred to as being "on," "connected to," "bound to," or "adjacent to" another element or layer, the element or layer may be directly on, directly connected to, directly bound to, or directly adjacent to the other element or layer, or one or more intermediate elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," "directly bound to," or "directly adjacent to" another element or layer, there are no intermediate elements or layers.

[0053] Any numerical range stated herein is intended to include all subranges of the same numerical precision within the stated range. For example, the range of "1.0 to 10.0" is intended to include all subranges between the stated minimum value 1.0 and the stated maximum value 10.0 (and including the stated minimum value 1.0 and the stated maximum value 10.0), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit stated herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit stated in this specification is intended to include all larger numerical limits contained therein.

[0054] Figure 1 is a diagram illustrating an example display device according to one or more embodiments of the present disclosure.

[0055] Reference Figure 1 The display device 100 may include a display unit 110 (or a display panel), a gate driver 120 (or a scan driver), a data driver 130 (or a source driver), a sensing unit 140, a timing controller 150, and a clock generator 160.

[0056] The display unit 110 may include gate lines SC1 to SCn and SS1 to SSn (e.g., n is a positive integer), data lines D1 to Dm (e.g., m is a positive integer), sensing lines R1 to Rp (e.g., p is a positive integer less than or equal to m) (or receiving lines), and pixels PXij. The gate lines SC1 to SCn and SS1 to SSn may include scan lines SC1 to SCn and sensing scan lines SS1 to SSn. The pixels PXij may be disposed in an area defined by the scan lines SC1 to SCn and the data lines D1 to Dm.

[0057] The pixel PXij may be coupled to at least one of the scan lines SC1 to SCn, at least one of the sensing scan lines SS1 to SSn, one of the data lines D1 to Dm, and one of the sensing lines R1 to Rp. Figure 2 Describe the detailed configuration and operation of the pixel PXij.

[0058] The gate driver 120 may generate a gate signal based on a start signal FLM (or a start pulse) and a clock signal CLKS, and provide the gate signal to the gate lines SC1 to SCn and SS1 to SSn. The start signal FLM may be provided from the timing controller 150, and the clock signal CLKS may be provided from the clock generator 160. For example, the gate driver 120 may generate a scan signal and sequentially provide the scan signal to the scan lines SC1 to SCn. The gate driver 120 may generate a sensing scan signal and sequentially provide the sensing scan signal to the sensing scan lines SS1 to SSn. The scan signal and the sensing scan signal may be included in the gate signal. For example, the gate driver 120 may include a shift register (or stage). Reference will be made later to Figure 5 A detailed configuration of the gate driver 120 is described.

[0059] The data driver 130 may generate a data signal based on the image data DATA2 and the data control signal DCS received from the timing controller 150, and provide the data signal to the display unit 110 (or the pixel PXij) through the data lines D1 to Dm. The data control signal DCS is a signal for controlling the operation of the data driver 130, and may include a load signal (or a data enable signal) to instruct the data driver 130 to output a valid data signal, etc. For example, the data driver 130 may sample a gray value included in the image data DATA2, and provide a data signal corresponding to the gray value to the data lines D1 to Dm in units of pixel rows.

[0060] In one or more embodiments, the data driver 130 sequentially outputs valid data signals corresponding to the gate lines SC1 to SCn and SS1 to SSn during one frame (or frame period), and may periodically output black data signals corresponding to black images between the data signals. The pixel PXij may sequentially receive (and record) one of the valid data signal and at least one black data signal during one frame.

[0061] The sensing unit 140 may measure characteristic information of the pixel PXij based on the current or voltage received through the sensing lines R1 to Rp. For example, the sensing unit 140 may receive current and voltage information of the pixel PXij from the display unit 110 through the sensing lines R1 to Rp, and measure characteristic information of the pixel PXij based on the received current or voltage information. For example, the characteristic information of the pixel PXij may include mobility information and threshold voltage information of a driving transistor included in the pixel PXij, degradation information of a light emitting device included in the pixel PXij, and the like.

[0062] The timing controller 150 may receive input image data DATA1 and a control signal CS from the outside (e.g., a graphics processor), generate a gate control signal and a data control signal DCS based on the control signal CS, and generate image data DATA2 by converting the input image data DATA1. The gate control signal may include a start signal FLM, an on-clock signal ON_CLK, an off-clock signal OFF_CLK, an enable signal OE, and a common signal BI. The on-clock signal ON_CLK and the off-clock signal OFF_CLK may be reference clock signals for generating a clock signal CLKS in the clock generator 160 (or a level shifter), and the enable signal OE and the common signal BI may be used to implement a black frame insertion technique, for example, for determining the timing at which a black data signal provided from the data driver 130 is stored in the pixel PXij. This will be described later. Fig. 9 and Fig.10 Describe the on-clock signal ON_CLK, the off-clock signal OFF_CLK and the common signal BI.

[0063] The clock generator 160 may generate a clock signal CLKS based on the on-clock signal ON_CLK, the off-clock signal OFF_CLK, the enable signal OE, and the common signal BI.

[0064] In one or more embodiments, the clock generator 160 may generate clock signals CLKS having different phases based on the on-clock signal ON_CLK and the off-clock signal OFF_CLK when the enable signal OE has a first voltage level (e.g., a logic low level), and insert a common pulse into each of the clock signals CLKS based on the common signal BI when the enable signal OE has a second voltage level (e.g., a logic high level) different from the first voltage level. For example, the clock signal CLKS may include pulses having different phases in a period in which the enable signal OE has a first voltage level, and include common pulses having the same phase in a period in which the enable signal OE has a second voltage level.

[0065] Despite Figure 1 , the clock generator 160 is shown to be independent of the gate driver 120 , but the present disclosure is not limited thereto, and the clock generator 160 may be implemented integrally with the gate driver 120 or may be included in the gate driver 120 .

[0066] Hereinafter, the configuration and operation of the pixel PXij and the configuration of the gate driver 120 will be described, and then the configuration and operation of the clock generator 160 will be described in detail.

[0067] Figure 2 It is a diagram showing one or more embodiments according to the present disclosure including Figure 1 A circuit diagram of an example of a pixel in a display device is shown in FIG.

[0068] Reference Figure 2 , the pixel PXij may include thin film transistors (TFTs) M1, M2, and M3 (eg, switching elements or transistors), a storage capacitor Cst, and a light emitting device LD. The thin film transistors M1, M2, and M3 may be N-type transistors.

[0069] A gate electrode of the first thin film transistor M1 may be coupled to the gate node Na, one electrode (or first electrode) of the first thin film transistor M1 may be coupled to the first power line VDD (or first power source), and the other electrode (or second electrode) of the first thin film transistor M1 may be coupled to the source node Nb. The first thin film transistor M1 may be referred to as a driving transistor.

[0070] A gate electrode of the second thin film transistor M2 may be coupled to the scan line SCi, one electrode of the second thin film transistor M2 may be coupled to the data line Dj, and the other electrode of the second thin film transistor M2 may be coupled to the gate node Na. The second thin film transistor M2 may be referred to as a switching transistor, a scan transistor, etc.

[0071] A gate electrode of the third thin film transistor M3 may be coupled to the sensing scan line SSi, one electrode of the third thin film transistor M3 may be coupled to the sensing line Rj, and the other electrode of the third thin film transistor M3 may be coupled to the source node Nb. The third thin film transistor M3 may be referred to as an initialization transistor, a sensing transistor, etc.

[0072] One electrode of the storage capacitor Cst may be coupled to the gate node Na, and the other electrode of the storage capacitor Cst may be coupled to the source node Nb.

[0073] An anode of the light emitting device LD may be coupled to the source node Nb, and a cathode of the light emitting device LD may be coupled to the second power line VSS (or second power source). The light emitting device LD may be configured as an organic light emitting diode (OLED), an inorganic light emitting diode, or the like.

[0074] The first power voltage may be provided to the first power line VDD, and the second power voltage may be provided to the second power line VSS. The first power voltage and the second power voltage are voltages suitable for operation of the pixel PXij, and the first power voltage may have a voltage level higher than that of the second power voltage.

[0075] Figure 3 It is a diagram showing one or more embodiments according to the present disclosure including Figure 1 FIG. 1 is a diagram showing the operation of a display unit in a display device. Figure 3 ] The signals supplied to the pixels corresponding to the scanning lines SC1 to SCn according to the time TIME are shown in FIG.

[0076] Reference Figures 1 to 3 Each of the frame periods FRAME1 and FRAME2 may include a first period P1 and a second period P2. The first period P1 may be a period in which a pixel (eg, Figure 1 The pixel PXij shown in FIG. 1 is a period in which the pixel emits light at a brightness corresponding to the effective data signal IMAGE1, and the second period P2 may be a period in which the pixel emits light at a black and low brightness corresponding to the black data signal BLACK or does not emit light.

[0077] In one or more embodiments, at the beginning of the first period P1, a scan signal (or a first scan pulse) having a conduction level may be provided to the pixel coupled to the first scan line SC1 through the first scan line SC1. The conduction voltage level is a voltage level that turns on the transistors (e.g., M1, M2, M3) in the pixel. For example, the conduction voltage level may be such that the reference Figure 2 The voltage level at which the second thin film transistor M2 is turned on is described. The pixel coupled to the first scan line SC1 may emit light at effective brightness during the first period P1.

[0078] like Figure 3 As shown in , a scan signal (or a first scan pulse) having a turn-on voltage may be sequentially supplied to the scan lines SC1 to SCn, and pixels corresponding to the scan lines SC1 to SCn may sequentially emit light.

[0079] In one or more embodiments, at the start time of the second period P2, a scan signal (or a second scan pulse) having a turn-on voltage level may be provided to the pixel coupled to the first scan line SC1 through the first scan line SC1. The pixel coupled to the first scan line SC1 may store a black data signal and emit light having black and low brightness in response to the black data signal during the second period P2.

[0080] like Figure 3 As shown in , the scan signal (or the second scan pulse) having the on voltage may be commonly provided to k (k is an integer of two or more) of the scan lines SC1 to SCn, and provided to the scan lines SC1 to SCn in full in the form of steps. For example, the scan signal (or the second scan pulse) may provide the on voltage to the scan lines SC1 to SCn in the form of a step voltage signal, wherein each step may have an amplitude k, wherein k is an integer greater than or equal to two. The scan time for providing the same black data signal to the pixel may be reduced.

[0081] As reference Figure 3 As described, the display device 100 can control the pixel to effectively emit light during the first period P1 of a frame cycle, and control the pixel to emit light corresponding to a black image or not emit light during the second period P2 of a frame cycle. For example, the display device 100 can control the pixel to emit light having a brightness corresponding to the effective data signal IMAGE1 during the first period P1 of a frame cycle, and can also control the pixel to emit black light having a low brightness corresponding to the black data signal BLACK or not emit light during the second period P2 of a frame cycle. For example, the display device 100 can be driven using a black frame insertion technique.

[0082] Figure 4A and Figure 4B It is shown Figure 2 A waveform diagram of the pixel operation is shown in FIG.

[0083] First, refer to Figures 2 to 4A , the first frame FRAME1 may include a first period P1 and a second period P2.

[0084] During the first sub-period PS1 of the first period P1, a scan signal SCAN (or a first scan pulse) having a turn-on voltage level may be applied to the scan line SCi, and a sensing scan signal SEN (or a first sensing scan pulse) having a turn-on voltage level may be applied to the sensing scan line SSi. In one or more embodiments, a data signal VDATA corresponding to a specific grayscale value may be applied to the data line Dj during the first sub-period PS1 of the first period P1. For example, the data signal VDATA may have a first valid data voltage V_D1.

[0085] The second thin film transistor M2 may be turned on in response to the scan signal SCAN, and the data signal VDATA may be provided to one electrode of the storage capacitor Cst. In one or more embodiments, the third thin film transistor M3 may be turned on in response to the sensing scan signal SEN, and the first reference voltage applied to the sensing line Rj may be provided to the other electrode of the storage capacitor Cst. Therefore, a voltage corresponding to the difference between the data signal VDATA and the first reference voltage may be stored in the storage capacitor Cst. Subsequently, when the second thin film transistor M2 and the third thin film transistor M3 are turned off, the amount of the driving current flowing through the first thin film transistor M1 may be determined corresponding to the voltage stored in the storage capacitor Cst (e.g., the first effective data voltage V_D1), and the light emitting device LD may emit light at a brightness corresponding to the amount of the driving current during the first period P1.

[0086] Similarly, during the second sub-period PS2 of the second period P2, a scan signal SCAN (or a second scan pulse) having a turn-on voltage level may be applied to the scan line SCi, and a sensing scan signal SEN (or a second sensing scan pulse) having a turn-on voltage level may be applied to the sensing scan line SSi. The data signal VDATA applied to the data line Dj during the second sub-period PS2 of the second period P2 may have a black data voltage corresponding to black (i.e., a black data signal BLACK). Therefore, the light emitting device LD may emit black light during the second period P2 or may not emit light.

[0087] At the same time, despite Figure 4A 4 shows a case where the sensing scan signal SEN has a turn-on voltage level in the second sub-period PS2 of the second period P2, but the present disclosure is not limited thereto.

[0088] For example, Figure 4BAs shown in , the sensing scan signal SEN may have a cut-off voltage level in the second sub-period PS2. The data signal VDATA (i.e., the black data signal BLACK) may be provided to the one electrode of the storage capacitor Cst in response to the scan signal SCAN during the second sub-period PS2, and the first thin film transistor M1 may be cut off. The storage capacitor Cst maintains the black data signal BLACK during the second period P2, so that the cut-off state of the first thin film transistor M1 may be maintained.

[0089] Figure 5 It is shown that the Figure 1 A diagram of an example of a gate driver in a display device is shown in FIG.

[0090] Reference Figure 5 , the gate driver 120 may include a plurality of stages ST1 to STn. The stages ST1 to STn may be respectively connected to the reference Figure 1 The described scanning lines SC1 to SCn (and the sensing scanning lines SS1 to SSn) correspond to or can be respectively combined with the reference Figure 1 The scan lines SC1 to SCn (and the sensing scan lines SS1 to SSn) are described.

[0091] Stages ST1 to STn may be coupled to a clock line and receive a clock signal CLKS. Although reference will be made later Fig. 9 Description, but each of the stages ST1 to STn may be coupled to a corresponding clock line (eg, two clock lines) among the clock lines and receive a corresponding clock signal (eg, two clock signals) among the clock signals CLKS.

[0092] Each of the stages ST1 to STn may receive a start signal FLM or a carry signal of a previous stage (e.g., one of the carry signals CR1 to CRn-1), and generate a scan signal and a sensing scan signal by shifting the start signal FLM or the carry signal of the previous stage based on the corresponding clock signal CLKS. In one or more other embodiments, each of the stages ST1 to STn may output a corresponding clock signal among the clock signals CLKS as a scan signal and / or a sensing scan signal in response to the start signal FLM or the carry signal of the previous stage (e.g., one of the carry signals CR1 to CRn-1).

[0093] Each of the stages ST1 to STn may be coupled to a corresponding line among the scan lines SC1 to SCn, the sensing scan lines SS1 to SSn, and the carry line.

[0094] For example, the first stage ST1 may be coupled to the first scan line SC1, the first sensing scan line SS1, and the first carry line, the second stage ST2 may be coupled to the second scan line SC2, the second sensing scan line SS2, and the second carry line, and the third stage ST3 may be coupled to the third scan line SC3, the third sensing scan line SS3, and the third carry line. The nth stage STn may be coupled to the nth scan line SCn and the nth sensing scan line SSn.

[0095] The clock signals generated by the stages ST1 to STn may be applied to the scan lines SC1 to SCn, the sensing scan lines SS1 to SSn, and the carry line, respectively.

[0096] In one or more embodiments, although Figure 5 , each of the stages ST1 to STn receives a carry signal from a previous stage immediately adjacent thereto, but the stages ST1 to STn are not limited thereto. For example, each of the stages ST1 to STn may receive a carry signal from a previous stage located two stages before.

[0097] Figure 6 It is shown that the Figure 5 A diagram of an example of a stage in a gate driver is shown in FIG. Figure 5 The stages ST1 to STn shown in FIG. 1 are substantially identical to one another, and thus, the stage STi included in the stages ST1 to STn will be described.

[0098] Reference Figure 6 , stage STi may include a node control circuit SST1, a first output circuit SST2, a second output circuit SST3, and a third output circuit SST4. The clock signal CLKS may include a carry clock signal CR_CLK, a scan clock signal SC_CLK, and a sense clock signal SS_CLK. The carry clock signal CR_CLK, the scan clock signal SC_CLK, and the sense clock signal SS_CLK may be the same as or different from each other.

[0099] The node control circuit SST1 can control the node voltage of the first node Q (i.e., the first node voltage) and the node voltage of the second node QB (i.e., the second node voltage) based on the previous carry signal CRp (e.g., p is a positive integer) of the previous stage (or based on the start signal FLM) and the clock signal CLKS. For example, when the previous carry signal CRp has a cut-off voltage level, the node control circuit SST1 can control the second node QB so that the second node voltage of the second node QB has a turn-on voltage level, and control the first node Q so that the first node voltage of the first node Q remains at the cut-off voltage level. For example, when the previous carry signal CRp has a turn-on voltage level, the node control circuit SST1 can control the first node Q so that the first node voltage of the first node Q has a turn-on voltage level, and control the second node QB so that the second node voltage of the second node QB remains at the cut-off voltage level.

[0100] The first output circuit SST2 can output the carry clock signal CR_CLK as the carry signal CRi through the first output terminal OUT1 in response to the first node voltage of the first node Q, and pull the carry signal CRi down to the low voltage VGL (or cut-off voltage) or maintain the carry signal CRi in response to the second node voltage of the second node QB. The first output circuit SST2 may include a first transistor T1 and a second transistor T2. The first transistor T1 may include a first electrode receiving the carry clock signal CR_CLK, a second electrode coupled to the first output terminal OUT1, and a gate electrode coupled to the first node Q. The second transistor T2 may include a first electrode coupled to the first output terminal OUT1, a second electrode coupled to the low voltage VGL, and a gate electrode coupled to the second node QB.

[0101] The second output circuit SST3 may output the scan clock signal SC_CLK as a scan signal to the second output terminal OUT2 (or the scan line SCi) in response to the first node voltage of the first node Q, and pull the scan signal down to the low voltage VGL or maintain the scan signal in response to the second node voltage of the second node QB. The second output circuit SST3 may include a third transistor T3 and a fourth transistor T4. The third transistor T3 may include a first electrode receiving the scan clock signal SC_CLK, a second electrode coupled to the second output terminal OUT2, and a gate electrode coupled to the first node Q. The fourth transistor T4 may include a first electrode coupled to the second output terminal OUT2, a second electrode coupled to the low voltage VGL, and a gate electrode coupled to the second node QB.

[0102] The scan signal and the carry signal CRi may have different waveforms, and thus the scan clock signal SC_CLK different from the carry clock signal CR_CLK may be used. In one or more embodiments, a second output circuit SST3 different from the first output circuit SST2 may be provided in the stage STi.

[0103] In one or more embodiments, similar to the second output circuit SST3, the third output circuit SST4 may output the sensing clock signal SS_CLK as a sensing scan signal to the third output terminal OUT3 (or the sensing scan line SSi) in response to the first node voltage of the first node Q, and pull the sensing scan signal down to the low voltage VGL or maintain the sensing scan signal in response to the second node voltage of the second node QB. The third output circuit SST4 may include a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 may include a first electrode receiving the sensing clock signal SS_CLK, a second electrode coupled to the third output terminal OUT3, and a gate electrode coupled to the first node Q. The sixth transistor T6 may include a first electrode coupled to the third output terminal OUT3, a second electrode coupled to the low voltage VGL, and a gate electrode coupled to the second node QB.

[0104] The sensing scan signal and the scan signal may have different waveforms, and thus the sensing clock signal SS_CLK different from the scan clock signal SC_CLK may be used. In one or more embodiments, a third output circuit SST4 different from the second output circuit SST3 may be provided in the stage STi.

[0105] As reference Figures 5 and 6 As described above, the gate driver 120 (or stage STi) may generate a carry signal, a scan signal, and a sensing scan signal by using various clock signals CR_CLK, SC_CLK, and SS_CLK.

[0106] Figure 7 It is a diagram showing one or more embodiments according to the present disclosure including Figure 1 A diagram of an example of a clock generator in a display device is shown in FIG. Figure 8 It is a diagram showing one or more embodiments according to the present disclosure including Figure 7 FIG. 4 is a diagram of an example of a first level shifter in a clock generator shown in FIG.

[0107] Reference Figure 1 and Figure 7, the clock generator 160 may include a plurality of level shifters LS1 to LS4. For example, although the case where the clock generator 160 includes four level shifters LS1 to LS4 is shown, the clock generator 160 is not limited thereto. For example, the clock generator 160 may include two, three, five or more level shifters.

[0108] The first to fourth level shifters LS1 to LS4 may be coupled to each other through a common line L_C, and may be received from the timing controller 150 (see FIG. Figure 1 ) receives an on-clock signal, an off-clock signal and a common signal.

[0109] For example, the on-clock signal may include a carry-on clock signal CR_ON_CLK, a scan-on clock signal SC_ON_CLK, and a sense-on clock signal SS_ON_CLK, the off-clock signal may include a carry-off clock signal CR_OFF_CLK, a scan-off clock signal SC_OFF_CLK, and a sense-off clock signal SS_OFF_CLK, and the common signal may include a scan-common signal SC_BI and a sense-common signal SS_BI. Each of the first to fourth level shifters LS1 to LS4 may receive the carry-on clock signal CR_ON_CLK, the scan-on clock signal SC_ON_CLK, the sense-on clock signal SS_ON_CLK, the carry-off clock signal CR_OFF_CLK, the scan-off clock signal SC_OFF_CLK, the sense-off clock signal SS_OFF_CLK, the scan-common signal SC_BI, and the sense-common signal SS_BI through a common line L_C.

[0110] In addition, each of the first to fourth level shifters LS1 to LS4 can be connected to the timing controller 150 (see FIG. Figure 1 ) receives a carry enable signal, a scan enable signal and a sense enable signal.

[0111] For example, the first level shifter LS1 may receive the first carry enable signal CR_OE1, the first scan enable signal SC_OE1, and the first sense enable signal SS_OE1. The second level shifter LS2 may receive the second carry enable signal CR_OE2, the second scan enable signal SC_OE2, and the second sense enable signal SS_OE2. The third level shifter LS3 may receive the third carry enable signal CR_OE3, the third scan enable signal SC_OE3, and the third sense enable signal SS_OE3. The fourth level shifter LS4 may receive the fourth carry enable signal CR_OE4, the fourth scan enable signal SC_OE4, and the fourth sense enable signal SS_OE4.

[0112] Each of the first to fourth level shifters LS1 to LS4 may generate a clock signal based on the on-clock signal, the off-clock signal, the common signal, and the enable signal, and output the clock signal as an output signal OUTPUT SIGNAL.

[0113] Since the first to fourth level shifters LS1 to LS4 are substantially the same as or similar to one another, the first level shifter LS1 included in the first to fourth level shifters LS1 to LS4 will be described.

[0114] Reference Figure 8 , the first level shifter LS1 may include a first sub level shifter LS_S1 , a second sub level shifter LS_S2 , and a third sub level shifter LS_S3 .

[0115] The first sub level shifter LS_S1 may generate a first scan clock signal group SC_CLKS1 based on the scan-on clock signal SC_ON_CLK, the scan-off clock signal SC_OFF_CLK, the first scan enable signal SC_OE1 , and the scan common signal SC_BI.

[0116] Similarly, the second sub level shifter LS_S2 may generate the first sensing clock signal SS_CLKS1 based on the sensing on clock signal SS_ON_CLK, the sensing off clock signal SS_OFF_CLK, the first sensing enable signal SS_OE1 , and the sensing common signal SS_BI.

[0117] The third sub level shifter LS_S3 may generate the first carry clock signal CR_CLKS1 based on the carry-on clock signal CR_ON_CLK, the carry-off clock signal CR_OFF_CLK, and the first carry enable signal CR_OE1 .

[0118] Similar to the first level shifter LS1, the second level shifter LS2 can generate a second carry clock signal CR_CLKS2, a second scan clock signal group SC_CLKS2 and a second sensing clock signal SS_CLKS2, the third level shifter LS3 can generate a third carry clock signal CR_CLKS3, a third scan clock signal group SC_CLKS3 and a third sensing clock signal SS_CLKS3, and the fourth level shifter LS4 can generate a fourth carry clock signal CR_CLKS4, a fourth scan clock signal group SC_CLKS4 and a fourth sensing clock signal SS_CLKS4.

[0119] The first to fourth scanning clock signal groups SC_CLKS1 to SC_CLKS4 are included in the scanning clock signal, have the same waveform, and may have different phases. Similarly, the first to fourth sensing clock signals SS_CLKS1 to SS_CLKS4 are included in the sensing clock signal, have the same waveform, and may have different phases.

[0120] When the first to fourth level shifters LS1 to LS4 receive scan-on clock signals and scan-off clock signals with different phases, respectively, to generate scan clock signal groups SC_CLKS1, SC_CLKS2, SC_CLKS3, and SC_CLKS4 with different phases, each of the number of input terminals for receiving signals of the clock generator 160 (and the number of output terminals for outputting signals of the timing controller 150) and the number of lines (e.g., common lines L_C) will be eight, and as the number of level shifters increases, the number of lines will increase in proportion to the number of level shifters. The first to fourth level shifters LS1 to LS4 according to one or more embodiments of the present disclosure receive the on-clock signal, the off-clock signal, and the common signal through the common line L_C, so that the number of input terminals and the number of lines of the clock generator 160 can be reduced. Meanwhile, the clock generator 160 (or the first to fourth level shifters LS1 to LS4) may internally (or autonomously) generate each of a scan-on clock signal having a different phase and a scan-off clock signal having a different phase by using individually received scan enable signals SC_OE1, SC_OE2, SC_OE3, and SC_OE4.

[0121] As reference Figure 7 and Figure 8 As described above, the first to fourth level shifters LS1 to LS4 commonly receive the on-clock signal, the off-clock signal, and the common signal among the input signal INPUT SIGNAL through the common line L_C, and only individually receive the enable signal among the input signal INPUT SIGNAL through the dedicated line L_P. Therefore, the number of input terminals of the clock generator 160 including the first to fourth level shifters LS1 to LS4, the number of output terminals of the timing controller 150 corresponding to the number of input terminals of the clock generator 160, the number of lines connecting the input terminals of the clock generator 160 and the output terminals of the timing controller 150 to each other, etc. can be reduced.

[0122] Fig. 9 The present invention is a diagram showing one or more embodiments of the present invention. Figure 7 An example waveform diagram of a signal measured in a clock generator is shown in FIG. Fig. 9The clock generator 160 (see Figure 7 ) in the scan clock signal group SC_CLKS1, SC_CLKS2, SC_CLKS3 and SC_CLKS4. Fig.10 According to one or more embodiments of the present disclosure Fig. 9 Amplified waveform of . Fig.10 It is shown in Fig. 9 1 , the first scan clock signal group SC_CLKS1 (ie, scan clock signals SC_CLK1_1 , SC_CLK2_1 , SC_CLK3_1 , SC_CLK4_1 , SC_CLK5_1 , and SC_CLK6_1 ) is shown in FIG.

[0123] Reference Fig. 9 , shows a start signal STV, a scan on clock signal SC_ON_CLK, a scan off clock signal SC_OFF_CLK, scan enable signals SC_OE1, SC_OE2, SC_OE3 and SC_OE4, a scan common signal SC_BI and scan clock signal groups SC_CLKS1, SC_CLKS2, SC_CLKS3 and SC_CLKS4. The start signal STV can define the clock generator 160 (see Figure 7 ) operation. The scan clock signal groups SC_CLKS1, SC_CLKS2, SC_CLKS3, and SC_CLKS4 may have different phases (eg, 24 different phases). However, the scan clock signal groups SC_CLKS1, SC_CLKS2, SC_CLKS3, and SC_CLKS4 are not limited thereto.

[0124] After the pulse of the start signal STV is generated, pulses may appear in the scan on clock signal SC_ON_CLK, the scan off clock signal SC_OFF_CLK, the scan enable signals SC_OE1, SC_OE2, SC_OE3 and SC_OE4, the scan common signal SC_BI and the scan clock signal groups SC_CLKS1, SC_CLKS2, SC_CLKS3 and SC_CLKS4.

[0125] The scan common signal SC_BI may include a first pulse PLS_BI having a logic high level (eg, a second voltage level or a turn-on voltage level) (see Fig.10 ). The first pulse PLS_BI may be repeated at a first time interval. A period in which the respective first pulses PLS_BI are generated may be defined as a black period (eg, black periods P_B1, P_B2, P_B3, P_B4, ...).

[0126] The scan-on clock signal SC_ON_CLK may include a plurality of second pulses PLS_ON (see FIG. 1 ) having a logic high level in a period in which the scan common signal SC_BI has a logic low level (eg, a first voltage level, or a cut-off voltage level). Fig.10 ).

[0127] For example, refer to Fig.10 , the scan-on clock signal SC_ON_CLK may include 12 second pulses PLS_ON when it appears continuously in the period after the fourth time t4. A plurality of (i.e., 12) second pulses PLS_ON are provided in association with 24 phases (e.g., 24 different phases of the scan clock signal groups SC_CLKS1, SC_CLKS2, SC_CLKS3, and SC_CLKS4). However, the number of the second pulses PLS_ON is not limited to 12. The second pulse PLS_ON may be repeated at a second time interval (e.g., one unit time 1UT).

[0128] Similar to the scan-on clock signal SC_ON_CLK, the scan-off clock signal SC_OFF_CLK may include a plurality of third pulses PLS_OFF having a logic high level in a period in which the scan common signal SC_BI has a logic low level. In the normal period P_N, the scan-off clock signal SC_OFF_CLK may have a waveform substantially the same as that of the scan-on clock signal SC_ON_CLK, and have a phase delayed by p-0.5 times (e.g., p is a positive integer) of the second time interval than the scan-on clock signal SC_ON_CLK. For example, as Fig.10 As shown in , in an example embodiment, p may be 3, and the scan-off clock signal SC_OFF_CLK may have a phase delayed by 2.5 unit times 2.5UT than the scan-on clock signal SC_ON_CLK.

[0129] At the first time t1 or just before the first time t1, the first scan enable signal SC_OE1 may be changed from a logic high level to a logic low level. A period in which the first scan enable signal SC_OE1 has a logic low level may be defined as a normal period P_N.

[0130] In addition, at the first time t1 , the second pulse PLS_ON of the scan-on clock signal SC_ON_CLK may start to appear.

[0131] At the first time t1, in response to the rising edge of the first pulse of the scan-on clock signal SC_ON_CLK, the first scan clock signal SC_CLK1_1 may change from a logic low level (or a cut-off voltage level) to a logic high level (or a turn-on voltage level). The time when the rising edge of the first pulse of the first scan clock signal SC_CLK1_1 occurs may coincide with the time when the rising edge of the first pulse of the scan-on clock signal SC_ON_CLK occurs.

[0132] Subsequently, just before the second time t2 , the third pulse PLS_OFF of the scan-off clock signal SC_OFF_CLK may start to appear.

[0133] At the second time t2, the first scan clock signal SC_CLK1_1 may change from a logic high level to a logic low level in response to the falling edge of the first pulse of the scan off clock signal SC_OFF_CLK. The falling edge of the first pulse of the first scan clock signal SC_CLK1_1 may coincide with the falling edge of the first pulse of the scan off clock signal SC_OFF_CLK.

[0134] For example, clock generator 160 (see Figure 7 ) can generate the first pulse of the first scan clock signal SC_CLK1_1 based on the rising edge of the first pulse of the scan-on clock signal SC_ON_CLK and the falling edge of the first pulse of the scan-off clock signal SC_OFF_CLK. In other words, the clock generator 160 can generate the first scan clock signal SC_CLK1_1 based on the triggering of signals having opposite polarities to each other.

[0135] Similar to the first scan clock signal SC_CLK1_1, the first pulse of the second scan clock signal SC_CLK2_1 may correspond to the rising edge of the second pulse of the scan on clock signal SC_ON_CLK and the falling edge of the second pulse of the scan off clock signal SC_OFF_CLK. The first pulse of the second scan clock signal SC_CLK2_1 may appear to be delayed by one unit time 1UT than the first pulse of the first scan clock signal SC_CLK1_1.

[0136] Similarly, pulses of the third, fourth, fifth, and sixth scan clock signals SC_CLK3_1, SC_CLK4_1, SC_CLK5_1, and SC_CLK6_1 may be sequentially generated.

[0137] The scan common signal SC_BI may have a pulse of a logic high level (eg, PLS_BI) between the third time t3 and the fourth time t4. The width of the pulse of the scan common signal SC_BI may be 1.5 unit times 1.5UT, but the present disclosure is not limited thereto.

[0138] exist Fig. 9 The third scan clock signal group SC_CLKS3 and the fourth scan clock signal group SC_CLKS4 shown in FIG. 4 may have pulses of a logic high level corresponding to pulses of the scan common signal SC_BI.

[0139] Return to reference Fig.10 , in the period between the fifth moment t5 and the sixth moment t6, the scan-on clock signal SC_ON_CLK may have a second pulse of a logic high level. The fifth moment t5 may be a time after a specific time (e.g., 13 unit times 13UT) from the first moment t1. Subsequently, pulses of the second scan clock signal SC_CLK2_1, the third scan clock signal SC_CLK3_1, the fourth scan clock signal SC_CLK4_1, the fifth scan clock signal SC_CLK5_1, and the sixth scan clock signal SC_CLK6_1 may be sequentially generated.

[0140] For example, in the normal period P_N, each of the scan clock signals SC_CLK1_1 to SC_CLK6_1 may include a pulse having a certain period and have a different phase.

[0141] In the masking period P_M after the sixth time t6, the first scan enable signal SC_OE1 may have a logic high level. For example, a period in which the first scan enable signal SC_OE1 has a logic high level may be defined as the masking period P_M.

[0142] In the masking period P_M, the scan-on clock signal SC_ON_CLK may have a second pulse PLS_ON of a logic high level, and the scan-off clock signal SC_OFF_CLK may have a third pulse PLS_OFF of a logic high level. However, the first scan clock signal SC_CLK1_1 may not include a pulse corresponding to the second pulse PLS_ON of the scan-on clock signal SC_ON_CLK and the third pulse PLS_OFF of the scan-off clock signal SC_OFF_CLK. Similarly, in the masking period P_M, each of the second to sixth scan clock signals SC_CLK2_1 to SC_CLK6_1 may not include a pulse corresponding to the second pulse PLS_ON of the scan-on clock signal SC_ON_CLK and the third pulse PLS_OFF of the scan-off clock signal SC_OFF_CLK.

[0143] Meanwhile, the scan common signal SC_BI may have a pulse of a logic high level between the seventh time t7 and the eighth time t8.

[0144] The first scan clock signal SC_CLK1_1 may have a pulse of a logic high level corresponding to a pulse of a logic high level of the scan common signal SC_BI between the seventh moment t7 and the eighth moment t8. Similarly, each of the second scan clock signal SC_CLK2_1 to the sixth scan clock signal SC_CLK6_1 may have a pulse of a logic high level corresponding to a pulse of a logic high level of the scan common signal SC_BI between the seventh moment t7 and the eighth moment t8.

[0145] For example, in the masking period P_M, the first to sixth scanning clock signals SC_CLK1_1 to SC_CLK6_1 may have pulses (or common pulses) corresponding to the pulses of the scanning common signal SC_BI (i.e., pulses of a logic high level) at the same time (e.g., between the seventh time t7 and the eighth time t8). The common pulses of the first to sixth scanning clock signals SC_CLK1_1 to SC_CLK6_1 may be used to generate scanning signals for black frame insertion (e.g., referring to Figure 4A The pulses in the second sub-period PS2 described above).

[0146] Return to reference Fig. 9 , similar to the first to sixth scan clock signals SC_CLK1_1 to SC_CLK6_1, the seventh to twelfth scan clock signals SC_CLK7_2 to SC_CLK12_2 may include pulses with different phases in a period in which the second scan enable signal SC_OE2 has a logic low level, and simultaneously include pulses corresponding to pulses of the scan common signal SC_BI (i.e., pulses of a logic high level) in a period in which the second scan enable signal SC_OE2 has a logic high level (for example, a first black period P_B1 and a second black period P_B2).

[0147] The first scan clock signal SC_CLK1_3 to the sixth scan clock signal SC_CLK6_3 included in the third clock signal group SC_CLKS3 may include pulses with different phases in a time period in which the third scan enable signal SC_OE3 has a logic low level, and simultaneously include pulses corresponding to the pulses of the scan common signal SC_BI in a time period in which the third scan enable signal SC_OE3 has a logic high level (for example, the third black time period P_B3 and the fourth black time period P_B4).

[0148] The seventh scan clock signal SC_CLK7_4 to the twelfth scan clock signal SC_CLK12_4 included in the fourth clock signal group SC_CLKS4 may include pulses with different phases in a time period in which the fourth scan enable signal SC_OE4 has a logic low level, and simultaneously include pulses corresponding to the pulses of the scan common signal SC_BI in a time period in which the fourth scan enable signal SC_OE4 has a logic high level (for example, the third black time period P_B3 and the fourth black time period P_B4).

[0149] Therefore, clock signals SC_CLK1_1 to SC_CLK6_1, SC_CLK7_2 to SC_CLK12_2, SC_CLK1_3 to SC_CLK6_3, and SC_CLK7_4 to SC_CLK12_4 having 24 different phases may be generated.

[0150] As reference Fig. 9 and Fig.10 As described, the pulses of the scan clock signal output from the corresponding level shifter can have different phases in a time period (i.e., a normal time period P_N) in which the scan enable signal (e.g., the first scan enable signal SC_OE1) applied to the corresponding level shifter has a logic low level, and have the same phase corresponding to the scan common signal SC_BI in a time period (i.e., a masking time period P_M) in which the scan enable signal applied to the corresponding level shifter has a logic high level.

[0151] At the same time, with reference Fig. 9 and Fig.10 Similar to the scan clock signal described above, clock generator 160 (see Figure 7 ) can generate a sensing clock signal.

[0152] Fig.11 It is a diagram showing one or more embodiments according to the present disclosure including Figure 8 FIG. 4 is a diagram of an example of a first sub-level shifter in a first level shifter shown in FIG. Fig. 12A and Fig. 12B The present invention is a diagram showing one or more embodiments of the present invention. Fig.11 2 is a waveform diagram of the operation of the first sub-level shifter shown in FIG.

[0153] Reference Figure 8 and Fig.11, the first sub-level shifter LS_S1 and the second sub-level shifter LS_S2 are substantially the same or similar to each other, and therefore, the first sub-level shifter LS_S1 will be described, and it is understood that the description of the first sub-level shifter LS_S1 can also be applied to the description of the second sub-level shifter LS_S2. In one or more embodiments, the configuration for generating a scan clock signal and the configuration for generating a sensing clock signal are substantially the same as each other, and therefore, the configuration for generating a scan clock signal will be described, which is equivalent to describing the configuration for generating a scan clock signal and the configuration for generating a sensing clock signal.

[0154] The first sub level shifter LS_S1 may include a masking circuit MC, a first clock generating circuit CG1 (or a first clock generator), a second clock generating circuit CG2 (or a second clock generator), and a third clock generating circuit CG3 (or a third clock generator).

[0155] The masking circuit MC may generate the modulated scan-on clock signal SC_ON_CLK_M by masking at least some of the pulses of the scan-on clock signal SC_ON_CLK based on the first scan enable signal SC_OE1 having a logic high level (or a second voltage level).

[0156] The first clock generating circuit CG1 may generate a scan reference clock signal SC_CLKS0 based on the modulated scan-on clock signal SC_ON_CLK_M and the scan-off clock signal SC_OFF_CLK.

[0157] Will refer to Fig. 12A The operations of the masking circuit MC and the first clock generating circuit CG1 are described.

[0158] Reference Fig. 12A The scan on clock signal SC_ON_CLK, the scan off clock signal SC_OFF_CLK and the first scan enable signal SC_OE1 are respectively connected to the reference Fig. 9 and Fig.10 The described scan-on clock signal SC_ON_CLK, the scan-off clock signal SC_OFF_CLK, and the first scan enable signal SC_OE1 are substantially the same or similar, and thus, a repeated description will not be repeated.

[0159] In a period between the first time t1 ′ and the second time t2 ′, the first scan enable signal SC_OE1 may have a logic low level, and accordingly, any pulse of the scan-on clock signal SC_ON_CLK may not be masked in the period between the first time t1 ′ and the second time t2 ′.

[0160] Therefore, corresponding to the first pulse and the second pulse of the scan-on clock signal SC_ON_CLK, the first scan clock signal SC_CLK1_1 and the second scan clock signal SC_CLK2_1 may appear. For example, the first clock generating circuit CG1 may generate a pulse of the first scan clock signal SC_CLK1_1 and a pulse of the second scan clock signal SC_CLK2_1 based on the first pulse and the second pulse of the scan-on clock signal SC_ON_CLK.

[0161] In the first masking period P_M1, the first scan enable signal SC_OE1 may have a logic high level. Therefore, the masking circuit MC may mask the third pulse and the fourth pulse of the scan on clock signal SC_ON_CLK, and the third scan clock signal SC_CLK3_1 and the fourth scan clock signal SC_CLK4_1 may not have any pulses. For example, the third scan clock signal SC_CLK3_1 and the fourth scan clock signal SC_CLK4_1 may be maintained at a low level in the first masking period P_M1.

[0162] Subsequently, in a period in which the first scan enable signal SC_OE1 has a logic low level (i.e., a period between the first masking period P_M1 and the second masking period P_M2), the fifth pulse and the sixth pulse of the scan on clock signal SC_ON_CLK are not masked, and a pulse of the fifth scan clock signal SC_CLK5_1 and a pulse of the sixth scan clock signal SC_CLK6_1 may appear.

[0163] Since only the scan-on clock signal SC_ON_CLK is masked, the pulse of the first scan clock signal SC_CLK1_1 and the pulse of the second scan clock signal SC_CLK2_1 generated based on the scan-on clock signal SC_ON_CLK before the first masking period P_M1 may have a falling edge in the first masking period P_M1. For example, at least one of the pulses of the first scan clock signal SC_CLK1_1 and the pulse of the second scan clock signal SC_CLK2_1 may overlap with the first scan enable signal SC_OE1 (or the first masking period P_M1) having a logic high level.

[0164] In the second masking period P_M2 , the first scan enable signal SC_OE1 may have a logic high level and the masking circuit MC may mask the seventh and eighth pulses of the scan on clock signal SC_ON_CLK. Therefore, the seventh and eighth scan clock signals SC_CLK7_1 and SC_CLK8_1 may not have any pulses.

[0165] In one or more embodiments, at a fifth time t5' and a sixth time t6' both of which are a specific time later than the first time t1', the pulse of the scan on clock signal SC_ON_CLK is masked, and accordingly, the first scan clock signal SC_CLK1_1 and the second scan clock signal SC_CLK2_1 do not have any pulse.

[0166] Return to reference Fig.11 , the second clock generating circuit CG2 may generate a scan common pulse based on the first scan enable signal SC_OE1 having a logic high level (or a second voltage level) and the scan common signal SC_BI.

[0167] The third clock generating circuit CG3 may generate the first scan clock signal group SC_CLKS1 by inserting a scan common pulse into the scan reference clock signal SC_CLKS0.

[0168] Will refer to Fig. 12B Describe the operations of the second clock generating circuit CG2 and the third clock generating circuit CG3.

[0169] Reference Fig. 12B , the scan common signal SC_BI may have a logic high level in the period between the seventh moment t7' and the eighth moment t8' in the first masking period P_M1'. Therefore, the first scan clock signal SC_CLK1_1 to the eighth scan clock signal SC_CLK8_1 may concurrently (e.g., simultaneously) have a logic high level or have the same pulse in the period between the seventh moment t7' and the eighth moment t8'. For example, the second clock generating circuit CG2 may provide the first pulse of the scan common signal SC_BI to the third clock generating circuit CG3, and the third clock generating circuit CG3 may insert the first pulse of the scan common signal SC_BI as is into the first scan clock signal SC_CLK1_1 to the eighth scan clock signal SC_CLK8_1 (or combine it with the first scan clock signal SC_CLK1_1 to the eighth scan clock signal SC_CLK8_1).

[0170] In the period between the first masking period P_M1' and the second masking period P_M2', the scan common signal SC_BI may have a pulse of a logic high level. However, because the first scan enable signal SC_OE1 has a logic low level during the same period, the first scan clock signal SC_CLK1_1 to the eighth scan clock signal SC_CLK8_1 do not include any common pulses. For example, the second clock generating circuit CG2 may mask the pulse of the scan common signal SC_BI in the period between the first masking period P_M1' and the second masking period P_M2'.

[0171] Subsequently, the scan common signal SC_BI may have a logic high level in the period between the ninth moment t9' and the tenth moment t10' in the second masking period P_M2'. Therefore, the first to eighth scan clock signals SC_CLK1_1 to SC_CLK8_1 may concurrently (e.g., simultaneously) have a logic high level or have the same pulse in the period between the ninth moment t9' and the tenth moment t10'.

[0172] As reference Fig.11 , Fig. 12A and Fig. 12B The first sub-level shifter LS_S1 (eg, the first level shifter LS1 (see Figure 8 ) or clock generator 160 (see Figure 7 )) can mask at least a portion of the on-clock signal (or the pulse of the on-clock signal) based on the enable signal having a logic high level, and generate a clock signal based on the masked on-clock signal and the off-clock signal. In addition, while the enable signal has a logic high level, the first sub-level shifter LS_S1 can insert the pulse of the common signal into the clock signal as it is. For example, the clock generator 160 (see Figure 7 ) can generate clock signals with different phases to which a black frame insertion technique is applied by using an on-clock signal, an off-clock signal and a common signal (ie, a reduced input signal).

[0173] Fig.13 It is a diagram showing one or more embodiments according to the present disclosure including Figure 8 FIG. 4 is a diagram of an example of a third sub-level shifter in a first level shifter shown in FIG.

[0174] Reference Figure 8 and Fig.13 , the third sub level shifter LS_S3 may include a masking circuit MC and a first clock generating circuit CG1 (or a first clock generator). Fig.13 The masking circuit MC and the first clock generating circuit CG1 in the reference Fig.11 The described masking circuit MC and the first clock generating circuit CG1 are substantially the same or similar, and therefore, a duplicate description will not be repeated.

[0175] The masking circuit MC may generate the modulated carry-on clock signal CR_ON_CLK_M by masking at least some pulses of the carry-on clock signal CR_ON_CLK based on the first carry enable signal CR_OE1 having a logic high level (or a second voltage level).

[0176] The first clock generating circuit CG1 may generate a first carry clock signal CR_CLKS1 based on the modulated carry-on clock signal CR_ON_CLK_M and the carry-off clock signal CR_OFF_CLK.

[0177] For example, because the third sub level shifter LS_S3 does not receive any separate common signal, the third sub level shifter LS_S3 may output the output signal of the first clock generating circuit CG1 as the first carry clock signal CR_CLKS1.

[0178] Although about Fig.13 The third sub-level shifter LS_S3 described has the same Fig.11 The configuration of the first sub-level shifter LS_S1 shown in FIG. 1 is different from the configuration of the first sub-level shifter LS_S1, but the present disclosure is not limited thereto. For example, the third sub-level shifter LS_S3 may also include a reference Fig.11 The second clock generating circuit CG2 and the third clock generating circuit CG3 are described, and the second clock generating circuit CG2 may not receive any separate input signal.

[0179] Fig.14 The present invention is a diagram showing one or more embodiments of the present invention. Figure 7 FIG. 1 is a waveform diagram of another example of a signal measured in a clock generator. Fig.14 It is shown in Fig. 9 The corresponding waveform diagram.

[0180] Reference Fig. 9 and Fig.14 In addition to the scan common signal SC_BI, the scan clock signal groups SC_CLKS1, SC_CLKS2, SC_CLKS3 and SC_CLKS4 can be respectively connected to the reference Fig. 9 The described scan clock signal groups SC_CLKS1, SC_CLKS2, SC_CLKS3, and SC_CLKS4 are substantially the same or similar. Therefore, the duplicate description will not be repeated.

[0181] Fig. 9 The scan common signal SC_BI shown in FIG. 1 may have two pulses in a period in which at least one of the scan enable signals SC_OE1, SC_OE2, SC_OE3, and SC_OE4 has a logic high level. Fig.14 The scan common signal SC_BI shown in FIG. 4 may have only one pulse in a period in which at least one of the scan enable signals SC_OE1 , SC_OE2 , SC_OE3 , and SC_OE4 has a logic high level.

[0182] Therefore, in a period in which at least one of the scan enable signals SC_OE1 , SC_OE2 , SC_OE3 , and SC_OE4 has a logic high level, each of the scan clock signal groups SC_CLKS1 , SC_CLKS2 , SC_CLKS3 , and SC_CLKS4 may have only one common pulse.

[0183] Fig.15 and Fig.16 The present invention is a diagram showing one or more embodiments of the present invention. Figure 7 A waveform diagram of another example of a signal measured in a clock generator is shown in FIG. Fig.15 and Fig.16 It is shown in Fig.10 The corresponding waveform.

[0184] Reference Fig.10 , Fig.15 and Fig.16 , in addition to the number of second pulses PLS_ON of the scan-on clock signal SC_ON_CLK and the number of third pulses PLS_OFF of the scan-off clock signal SC_OFF_CLK according to the period of the first pulse PLS_BI of the scan common signal SC_BI, Fig.15 The scan clock signals SC_CLK1_1 to SC_CLK8_1 (or Fig.16 The scan clock signals SC_CLK1_1 to SC_CLK4_1 shown in FIG. Fig.10 The described scan clock signals SC_CLK1_1 to SC_CLK6_1 are substantially the same or similar, and therefore, the duplicate description will not be repeated.

[0185] like Fig.15 As shown in , in the period between the first pulses PLS_BI of the scan common signal SC_BI, the scan-on clock signal SC_ON_CLK may include 16 second pulses PLS_ON, and the scan-off clock signal SC_OFF_CLK may include 16 third pulses PLS_OFF.

[0186] Therefore, eight scan clock signals SC_CLK1_1 to SC_CLK8_1 (ie, the first to eighth scan clock signals SC_CLK1_1 to SC_CLK8_1 each having two pulses in the normal period P_N) having different phases can be generated. Figure 7 ) can generate 32 scan clock signals with different phases.

[0187] like Fig.16As shown in , in the period between the first pulses PLS_BI of the scan common signal SC_BI, the scan-on clock signal SC_ON_CLK may include 8 second pulses PLS_ON, and the scan-off clock signal SC_OFF_CLK may include 8 third pulses PLS_OFF.

[0188] Therefore, four scan clock signals SC_CLK1_1 to SC_CLK4_1 having different phases (ie, the first to fourth scan clock signals SC_CLK1_1 to SC_CLK4_1 each having two pulses in the normal period P_N) can be generated. Figure 7 ) can generate 16 scan clock signals with different phases.

[0189] As reference Fig.15 and Fig.16 As described above, the number of scanning clock signals (similarly, sensing clock signals) may be variously changed.

[0190] The clock generator and display device according to the present disclosure include a plurality of level shifters for generating clock signals. The level shifter receives an on-clock signal, an off-clock signal, and a common signal from the input signal in common through a common line, and receives only an enable signal from the input signal in a separate line. Therefore, the number of input terminals of the clock generator including the level shifter, the number of output terminals of the timing controller corresponding to the number of input terminals, and the number of lines connecting the input terminals and the output terminals can be reduced.

[0191] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, as of the time of filing this application, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display device, comprising: A display unit including a gate line and a pixel electrically coupled to the gate line; A timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator including a common line, an independent line, and a plurality of level shifters, configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal when the enable signal has a first voltage level, wherein when the enable signal has a second voltage level different from the first voltage level, the clock generator inserts a common pulse into each of the plurality of clock signals based on the common signal, wherein the on-clock signal, the off-clock signal, and the common signal are commonly provided to the plurality of level shifters through the common line, and wherein the enable signal is individually provided to the plurality of level shifters through the independent line; and The gate driver is configured to generate gate signals based on the plurality of clock signals and sequentially provide the gate signals to the gate lines.

2. The display device according to claim 1, wherein: The common signal includes a first pulse having a turn-on voltage level, wherein the first pulse is repeated at a first time interval, wherein the on-clock signal includes a second pulse having the on-voltage level in a period in which the common signal has the off-voltage level, and The second pulse is repeated at a second time interval shorter than the first time interval in the period in which the common signal has the cut-off voltage level.

3. The display device according to claim 2, wherein: The off-clock signal includes a third pulse having the on-voltage level in the period in which the common signal has the off-voltage level, and The off-clock signal has a phase that is delayed by p-0.5 times the second time interval than the on-clock signal, where p is a positive integer.

4. The display device according to claim 3, wherein: The clock generator generates the plurality of clock signals based on triggering of the on-clock signal and the off-clock signal having opposite polarities, wherein the clock generator generates the plurality of clock signals based on a rising edge of the second pulse of the on-clock signal and a falling edge of the third pulse of the off-clock signal, wherein the rising edges of the plurality of clock signals occur simultaneously with the rising edge of the second pulse, and Wherein, the falling edges of the multiple clock signals occur simultaneously with the falling edge of the third pulse.

5. The display device according to claim 4, wherein: When the enable signal has the second voltage level, the common signal includes at least one of the first pulses.

6. The display device according to any one of claims 1 to 5, wherein: The plurality of clock signals output from the clock generator include a first clock signal and a second clock signal, and When the enable signal has the second voltage level, the first clock signal and the second clock signal simultaneously have the common pulse.

7. A display device, comprising: A display unit including a gate line and a pixel electrically coupled to the gate line; A timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, wherein the clock generator inserts a common pulse into each of the plurality of clock signals based on the enable signal and the common signal; and a gate driver configured to generate gate signals based on the plurality of clock signals and sequentially provide the gate signals to the gate lines, The clock generator includes a common line, a dedicated line and a plurality of level shifters to generate the plurality of clock signals. wherein the on-clock signal, the off-clock signal and the common signal are commonly provided to the plurality of level shifters through the common line, and The enable signal is individually provided to the plurality of level shifters through the dedicated line.

8. The display device according to claim 7, wherein: The gate driver includes a plurality of stages configured to respectively generate the gate signals, wherein each of the plurality of stages is configured to generate a carry signal based on a carry clock signal and a previous carry signal of a previous stage, and to generate a scan signal based on a scan clock signal and the previous carry signal, wherein the scan signal is included in one or more of the gate signals, and The carry clock signal and the scan clock signal are included in the plurality of clock signals.

9. The display device according to claim 8, wherein: The clock generator comprises: a first sub-level shifter configured to generate the scan clock signal based on a scan-on clock signal, a scan-off clock signal, a scan enable signal and a scan common signal, and The second sub-level shifter is configured to generate the carry clock signal based on the carry-on clock signal, the carry-off clock signal and the carry enable signal.

10. A clock generator, comprising: a level shifter configured to generate a plurality of clock signals having different phases based on an on-clock signal and an off-clock signal, wherein the level shifter is configured to insert a common pulse into each of the plurality of clock signals based on an enable signal and a common signal; a common line configured to commonly provide the on-clock signal, the off-clock signal, and the common signal to the level shifter; and A separate line is configured to provide the enable signal to the level shifter separately.

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