Metal Gate Modulator and Method for In-Situ Formation Thereof

Abstract

The present disclosure relates to a metal gate modulator and an in-situ formation method thereof. A method includes: forming a gate dielectric on a semiconductor region; depositing a work function layer on the gate dielectric; depositing a silicon layer on the work function layer; and depositing a glue layer on the silicon layer. The work function layer, the silicon layer, and the glue layer are deposited in-situ. The method further includes depositing a filling metal on the glue layer; and performing a planarization process, wherein the remaining portions of the glue layer, the silicon layer, and the work function layer form part of the gate electrode.

Description

Technical Field

[0001] The present disclosure generally relates to a metal gate modulator and a method for in-situ formation thereof. Background Art

[0002] Metal-oxide semiconductor (MOS) devices typically include a metal gate formed to address the poly-depletion effect in conventional polysilicon gates. The poly-depletion effect occurs when the applied electric field sweeps carriers away from the gate region near the gate dielectric to form a depletion layer. In an n-doped polysilicon layer, the depletion layer includes ionized immobile donor sites, while in a p-doped polysilicon layer, the depletion layer includes ionized immobile acceptor sites. The depletion effect results in an increase in the effective gate dielectric thickness, making it more difficult to generate an inversion layer on the semiconductor surface.

[0003] The metal gate may include multiple layers to meet the different requirements of NMOS and PMOS devices. The formation of the metal gate typically includes: removing a dummy gate stack to form a trench, depositing multiple metal layers extending into the trench, forming a metal region to fill the remaining part of the trench, and then performing a chemical mechanical polishing (CMP) process to remove the excess portions of the metal layers. The remaining portions of the metal layers and the metal region form the metal gate. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method for forming an integrated circuit device is provided, including: forming a first gate dielectric on a first semiconductor region; depositing a first work function layer on the first gate dielectric; depositing a first silicon layer on the first work function layer; depositing a first glue layer on the first silicon layer, wherein the first work function layer, the first silicon layer, and the first glue layer are deposited in-situ; depositing a first fill metal on the first glue layer; and performing a planarization process, wherein the remaining portions of the first glue layer, the first silicon layer, and the first work function layer form part of a gate electrode.

[0005] According to another embodiment of the present disclosure, an integrated circuit device is provided, including: a semiconductor region; a gate dielectric on the semiconductor region; a work function layer on the gate dielectric; a silicon layer on the work function layer; a glue layer on the silicon layer and in contact with the silicon layer; and a fill metal region on the glue layer and in contact with the glue layer.

[0006] According to yet another embodiment of the present disclosure, there is provided an integrated circuit device including: a semiconductor fin; a high-k dielectric over the semiconductor fin; a work function layer over the high-k dielectric; a first titanium nitride layer over the work function layer; a silicon layer over the first titanium nitride layer; a second titanium nitride layer over the silicon layer, wherein an interface between the silicon layer and the second titanium nitride layer is oxygen-free; and a fill metal region over and in contact with the second titanium nitride layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of illustration, the dimensions of various features may be arbitrarily increased or reduced.

[0008] Figures 1 - 6 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figures 9 - 18 、 Figure 19A and Figure 19B show perspective views and cross-sectional views of intermediate stages of the formation of a fin field-effect transistor (FinFET) in accordance with some embodiments.

[0009] Figure 20 show time-dependent dielectric breakdown (TDDB) data of a gate stack formed in accordance with some embodiments.

[0010] Figure 21 show an example distribution map of some elements in a gate stack in accordance with some embodiments.

[0011] Figure 22 show a process flow for forming a FinFET in accordance with some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms, such as "under," "beneath," "below," "above," "above," etc., may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0014] According to some embodiments, a method for forming a metal gate of a transistor with improved reliability is provided. According to some embodiments, an intermediate stage of forming a transistor is shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, similar reference numerals are used to indicate similar elements. According to some embodiments, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concept of the present disclosure. The concept of the present disclosure can also be used to form other types of transistors, such as planar transistors, all-around gate (GAA, Gate-All-Around) transistors, etc. The embodiments discussed herein provide examples to enable the subject matter of the present disclosure to be performed or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of different embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0015] According to some embodiments of the present disclosure, a metal gate having a work function layer is formed for a transistor. A cap layer and a silicon layer are added on top of the work function layer to reduce oxidation of the work function layer. Since the silicon layer may be oxidized when exposed to air, the work function layer, the cap layer, the silicon layer, and the glue layer on the silicon layer are formed in situ, and there is no vacuum break between the formation processes, so that the oxidation of the silicon layer is at least reduced or eliminated. As a result, the gate contact resistance is reduced. In addition, the reliability of the gate dielectric under the work function layer is improved.

[0016] Figures 1 - 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figures 9 - 18 , Figure 19A and Figure 19B The cross-sectional and perspective views show intermediate stages of the formation of a fin field effect transistor (FinFET) according to some embodiments of the present disclosure. The processes shown in these figures are also schematically reflected in Figure 22 In the process flow 400 shown.

[0017] exist Figure 1In this case, a substrate 20 is provided. The substrate 20 can be a semiconductor substrate (such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc.), which can be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor substrate 20 can be a part of the wafer 10. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate that is typically a silicon or glass substrate. Other substrates can also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate 20 can include silicon; germanium; compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP); or combinations thereof.

[0018] Further referring to Figure 1 , a well region 22 is formed in the substrate 20. In Figure 22 the process flow 400 shown, the corresponding process is shown as process 402. According to some embodiments of the present disclosure, the well region 22 is a p-type well region formed by implanting p-type impurities (which can be boron, indium, etc.) into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is an n-type well region formed by implanting n-type impurities (which can be phosphorus, arsenic, antimony, etc.) into the substrate 20. The resulting well region 22 can extend to the top surface of the substrate 20. The n-type or p-type impurity concentration can be equal to or less than 10 18 cm -3 , for example, in the range between about 10 17 cm -3 and about 10 18 cm -3 .

[0019] Referring to Figure 2 , an isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is optionally referred to as a shallow trench isolation (STI) region. In Figure 22In the process flow 400 shown, the corresponding process is shown as process 404. The portion of the substrate 20 between adjacent STI regions 24 is referred to as a semiconductor strip 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 may be formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed using plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. Then, the patterned photoresist is used as an etch mask to pattern the hard mask layer 30 to form a hard mask 30 as shown in Figure 2 shown.

[0020] Next, the patterned hard mask layer 30 is used as an etch mask to etch the pad oxide layer 28 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with a (one or more) dielectric material. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to remove the excess portion of the dielectric material, and the remaining portion of the (one or more) dielectric materials is the STI region 24. The STI region 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc. formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. The STI region 24 also includes a dielectric material on top of the liner oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, etc. According to some embodiments, the dielectric material on top of the pad dielectric may include silicon oxide.

[0021] The top surface of the hard mask layer 30 and the top surface of the STI region 24 can be substantially flush with each other. The semiconductor strip 26 is between adjacent STI regions 24. According to some embodiments of the present disclosure, the semiconductor strip 26 is part of the original substrate 20, so the material of the semiconductor strip 26 is the same as that of the substrate 20. In alternative embodiments of the present disclosure, the semiconductor strip 26 is a replacement strip formed by etching a portion of the substrate 20 between the STI regions 24 to form a groove and performing epitaxy to regrow another semiconductor material in the groove. Thus, the semiconductor strip 26 is formed of a semiconductor material different from that of the substrate 20. According to some embodiments, the semiconductor strip 26 is formed of silicon germanium, silicon carbide, or a group III-V compound semiconductor material.

[0022] Reference Figure 3 , the STI region 24 is recessed such that the top of the semiconductor strip 26 protrudes above the top surface 24A of the remaining portion of the STI region 24 to form a protruding fin 36. In Figure 22 the process flow 400 shown, the corresponding process is shown as process 406. The etching can be performed using a dry etching process, where, for example, HF3 and NH3 are used as etching gases. In the etching process, a plasma may be generated. Argon may also be included. According to alternative embodiments of the present disclosure, the recessing of the STI region 24 is performed using a wet etching process. The etching chemical can include, for example, HF.

[0023] In the above embodiments, the fins can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the fins, including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, thus allowing the creation of patterns with, for example, a pitch smaller than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to pattern the fins.

[0024] Reference Figure 4 , a dummy gate stack 38 is formed to extend over the top surface and sidewalls of the (protruding) fin 36. In Figure 22In the process flow 400 shown, the corresponding process is shown as process 408. The dummy gate stack 38 may include a dummy gate dielectric 40 and a dummy gate electrode 42 over the dummy gate dielectric 40. The dummy gate electrode 42 may be formed of, for example, polysilicon and may also be formed of other materials. Each dummy gate stack 38 may further include one (or more) hard mask layers 44 over the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a multi-layer thereof. The dummy gate stack 38 may span a single or multiple protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a length direction perpendicular to the length direction of the protruding fins 36.

[0025] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. In Figure 22 the process flow 400 shown, the corresponding process is also shown as process 408. According to some embodiments of the present disclosure, the gate spacers 46 are formed of a dielectric material such as silicon nitride, silicon carbonitride, etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0026] Then, an etching process is performed to etch the portions of the protruding fins 36 not covered by the dummy gate stack 38 and the gate spacers 46, thereby obtaining the Figure 5 structure shown. In Figure 22 the process flow 400 shown. The corresponding process is shown as process 410. The recess may be anisotropic, so that the portions of the fins 36 directly under the dummy gate stack 38 and the gate spacers 46 are protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 may be lower than the top surface 24A of the STI region 24. Accordingly, a groove 50 is formed. The groove 50 includes portions on opposite sides of the dummy gate stack 38 and portions between the remaining portions of the protruding fins 36.

[0027] Next, an epitaxial region (source / drain region) 54 is formed by selectively growing a semiconductor material (by epitaxy) in the groove 50, thereby obtaining the Figure 6 structure in Figure 22In the process flow 400 shown, the corresponding process is shown as process 412. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be doped in-situ as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 54 includes a group III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or a multi-layer thereof. After the epitaxial region 54 is filled in the groove 50, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and a facet can be formed. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. Voids (air gaps) 56 may be generated. According to some embodiments of the present disclosure, the formation of the epitaxial region 54 can be completed when the top surface of the epitaxial region 54 is still wavy, or it can also be when the top surface of the merged epitaxial region 54 becomes flat, which is achieved by further growth as shown Figure 6 on the epitaxial region 54.

[0028] After the epitaxial process, the epitaxial region 54 can be further implanted with p-type or n-type impurities to form source and drain regions, which are also denoted by the reference numeral 54. According to an alternative embodiment of the present disclosure, when the epitaxial region 54 is doped with p-type or n-type impurities in-situ during epitaxy, the implantation step is skipped.

[0029] Figure 7A A perspective view of the structure after forming the contact etch stop layer (CESL) 58 and the interlayer dielectric (ILD) 60 is shown. In Figure 22 the process flow 400 shown, the corresponding process is shown as process 414. The CESL 58 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD 60 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. The ILD 60 can be formed of a dielectric material containing oxygen, which can be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process, such as a CMP process or a mechanical polishing process, can be performed to make the top surfaces of the ILD 60, the dummy gate stack 38, and the gate spacer 46 flush with each other.

[0030] Figure 7BShows a cross-sectional view of an intermediate structure when forming a first FinFET, a second FinFET, and a third FinFET on the same substrate 20 ( Figure 19A 198, 298, and 398 in Figure 7A ). It should be understood that FinFETs are examples, and other types of transistors (e.g., nanosheet transistors, nanowire transistors, planar transistors, gate-all-around transistors, etc.) can also be formed by applying the concepts of the present disclosure. According to some embodiments, the first FinFET, the second FinFET, and the third FinFET are respectively formed in device regions 100, 200, and 300. According to some embodiments, the three FinFETs shown in the illustrated exemplary embodiment are n-type FinFETs. According to alternative embodiments, the three FinFETs are p-type FinFETs. According to other embodiments, the three FinFETs include a mixture of n-type FinFETs and p-type FinFETs in any combination. A cross-sectional view of any one of the first FinFET, the second FinFET, and the third FinFET can correspond to a cross-sectional view obtained from a vertical plane containing Figure 7A line 7B-7B in

[0031] To distinguish features in the first FinFET, the second FinFET, and the third FinFET, the reference numerals of the corresponding features in Figure 7A can be used plus the number 100 to denote features in device region 100. The reference numerals of the corresponding features in Figure 7A can be used plus the number 200 to denote Figure 7B features in device region 200 in Figure 7A . Similarly, the reference numerals of the corresponding features in Figure 7A can be used plus the number 300 to denote features in the third FinFET in device region 300. For example, Figure 7B the source / drain regions 154, 254, and 354 in Figure 7A correspond to the source / drain region 54 in Figure 7B , while Figure 7B the gate spacers 146, 246, and 346 in Figure 7A correspond to the gate spacer 46 in Figure 7A . The corresponding features in device regions 100, 200, and 300 can be formed in a common process or can be formed in separate processes, and some example processes are discussed in the subsequent paragraphs.

[0032] After forming the Figure 7A and Figure 7B structures shown, as shown in Figure 8A , Figure 8B and Figures 9 - 18 , a metal gate and replacement gate dielectric are used to replace Figure 7BDummy gate stacks 138, 238, and 338 therein. In these figures, the top surface 24A of the STI region 24 is shown, and the semiconductor fins 124’, 224’, and 324’ protrude above the top surface 24A of the corresponding adjacent STI region 24.

[0033] To form replacement gates, first, the hard mask layers 144, 244, and 344, dummy gate electrodes 142, 242, and 342, and dummy gate dielectrics 140, 240, and 340 as shown in Figure 7A and Figure 7B are removed to form a trench 62 as shown in Figure 8A . In the process flow 400 shown in Figure 22 , the corresponding process is shown as process 416. Figure 8A The trench 62 in Figure 8B corresponds to the trench 162 in the device region 100, the trench 262 in the device region 200, and the trench 362 in the device region 300, as shown in

[0034] . The top surfaces and sidewalls of the protruding fins 124’, 224’, and 324’ are respectively exposed to the trenches 162, 262, and 362.

[0034] Next, referring to Figure 9 , gate dielectrics 161, 261, and 361 are formed that respectively extend into the trenches 162, 262, and 362. In Figure 22In the process flow 400 shown, the corresponding process is shown as process 418. According to some embodiments of the present disclosure, the gate dielectric includes interface layers (ILs) 164, 264, and 364, which are respectively formed on the exposed surfaces of the protruding fins 124', 224', and 324'. Each of the ILs 164, 264, and 364 may include an oxide layer such as a silicon oxide layer, which may be formed by thermal oxidation, chemical oxidation process, or deposition process of the protruding fins 124', 224', and 324'. The gate dielectric may further include high-k dielectric layers 166, 266, and 366 on the corresponding ILs 164, 264, and 364. Each of the high-k dielectric layers 166, 266, and 366 may be formed of lanthanum oxide, hafnium oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0. The high-k dielectric layers 166, 266, and 366 cover and may contact the corresponding underlying ILs 164, 264, and 364. The high-k dielectric layers 166, 266, and 366 are formed as conformal layers, and extend on the sidewalls of the protruding fins 124', 224', and 324' and on the top surfaces and sidewalls of the gate spacers 146, 246, and 346. According to some embodiments of the present disclosure, the high-k dielectric layers 166, 266, and 366 are formed using ALD or CVD. The high-k dielectric layers 166, 266, and 366 may be part of the same dielectric layer, and may be formed simultaneously using the same material and having the same thickness, or may be formed separately using different materials and / or different thicknesses.

[0035] Figure 9 The formation of the first metal-containing layers 168, 268, and 368 is further shown, which may be formed in a co-deposition process (and may be part of the same blanket layer) or in separate deposition processes. In Figure 22 the process flow 400 shown, the corresponding process is shown as process 420. The portion of the masking layer extending into the p-type FinFET region may be used as the work function layer of the p-type FinFET. According to some embodiments, the metal-containing layers 168, 268, and 368 include titanium nitride, tantalum nitride, etc. Conformal deposition methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. may be used to form the metal-containing layers 168, 268, and 368. The thickness T1 of the metal-containing layers 168, 268, and 368 may be in the range of about and about between.

[0036] Figure 10 The formation of the first etch mask is shown, which includes etch masks (portions) 170 and 370 in the device regions 100 and 300, respectively. InFigure 22 In the process flow 400 shown, the corresponding process is shown as process 422. According to some embodiments, the etch masks 170 and 370 include a bottom anti-reflective coating (BARC) and a photoresist layer on top of the BARC. A hard mask (not shown) may or may not be formed under the BARC. According to some embodiments, the hard mask may include a metal oxide layer (e.g., an alumina layer) and a metal nitride layer (e.g., a titanium nitride layer) on top of the metal oxide layer. The metal-containing layer 268 is exposed through the etch mask.

[0037] In the etching process, the exposed metal-containing layer 268 is removed, and the high-k dielectric layer 266 is exposed after the etching process. In Figure 22 the process flow 400 shown, the corresponding process is shown as process 424. In Figure 11 the resulting structure is shown. According to some embodiments of the present disclosure, the etching of the metal-containing layer 268 is performed by a wet etching process, while a dry etching process may also be used.

[0038] Next, the etch masks 170 and 370 are removed. In Figure 12 the resulting structure is shown. According to some embodiments, the photoresist can be removed by ashing, or an etch gas including hydrogen (H2) and nitrogen (N2) can be used. The hard mask (if any) can be removed by using an etch chemical, which can include ammonium hydroxide, hydrochloric acid peroxide, carbonic acid, etc.

[0039] Figures 13 - 15 The formation of the second metal-containing layers 172 and 272 in the transistor regions 100 and 200 is shown respectively. Referring to Figure 13 , for example, the metal-containing layers 172, 272, and 372 are formed in a co-deposition process. In Figure 22 the process flow 400 shown, the corresponding process is shown as process 426. The materials of the metal-containing layers 172, 272, and 372 can be similar to the material of the metal-containing layer 168. The thickness T2 of the metal-containing layers 172, 272, and 372 can be similar to the thickness of the metal-containing layer 168. Depending on the expected magnitude of the adjustment of the threshold voltage of the transistors in the device regions 100 and 200, the thickness T2 can be greater than, equal to, or less than the thickness T1 of the metal-containing layer 168. For example, according to some embodiments of the present disclosure, the thickness ratio T1 / T2 can be in the range of about 0.5 to 2.0.

[0040] Figure 14 The formation of second etch masks including etch masks 174 and 274 in the device regions 100 and 200 respectively is shown, which are formed in a co-deposition process, followed by a co-lithography process. In Figure 22In the process flow 400 shown, the corresponding process is shown as process 428. The materials, structures, and formation methods of the etch masks 174 and 274 can be selected from the same set of candidate materials, structures, and formation methods of the etch masks 170 and 370( Figure 10 ). In subsequent processes, the metal-containing layers 372 and 368 are removed by an etching process. In Figure 22 the process flow 400 shown, the corresponding process is shown as process 430. During the etching process, the etch masks 174 and 274 are used to protect the metal-containing layers 168 and 172 in the device region 100 and the metal-containing layer 272 in the device region 200. The etch masks 174 and 274 are then removed, and Figure 15 shows the resulting structure. The etching process of the metal-containing layers 372 and 368 can be similar to the etching process of the metal-containing layer 268( Figure 10 and 11 ), and the details are not repeated.

[0041] As shown in the previous patterning process, the etching of the metal-containing layer 368 and the etching of the metal-containing layer 372( Figure 15 ) are in the same process, rather than the etching of the metal-containing layer 268( Figure 11 ). This has the advantageous feature of exposing the high-k dielectric layer 366 to the etching chemical once instead of twice. This will reduce the loss in the high-k dielectric layer 366 caused by over-etching of the metal-containing layer. The high-k dielectric layer 366 is thus exposed, as Figure 15 shown.

[0042] Next, multiple layers are deposited to fill the trenches 162, 262, and 362, and Figure 16 shows the resulting structure. These stacked layers include a work function layer 76, a capping layer 78, a silicon capping layer 80, and a glue layer 82. In Figure 22In the process flow 400 shown, the corresponding process is shown as process 432. Stacked layers 76, 78, 80 and 82 are deposited in situ in the same production tool without vacuum damage. In other words, during the entire time period from the first time of depositing the work function layer 76 to the second time of depositing the glue layer 82, the wafer 10 is in a vacuum environment without vacuum damage. In addition, during the entire time period between the first time and the second time, the wafer 10 is not exposed to oxygen-containing gases such as O2, O3, etc., nor is it exposed to water vapor. On the other hand, the formation of the stacked layer can be located in the formation of the metal-containing layers 172 and 272, and there is a vacuum damage between the two. Each of the work function layer 76, the cap layer 78, the silicon cap layer 80 and the glue layer 82 includes a portion in the device area 100, 200 and 300. The work function layer 76 includes portions 176, 276 and 376. The cap layer 78 includes portions 178, 278 and 378. Silicon cap layer 80 includes portions 180 , 280 , and 380 . Glue layer 82 includes portions 182 , 282 , and 382 .

[0043] According to some embodiments, work function layer 76 is formed using ALD, CVD, etc., and includes portions 176, 276, and 376 in device regions 100, 200, and 300, respectively. The material may include an aluminum-based layer, which may be formed of or include TiAl, TiAlN, TiAlC, TaAlN, TaAlC, etc. as n-type work function materials. According to some embodiments, the thickness of work function layer 76 may be about 100 to 200 nm. Peace in the range between.

[0044] According to some embodiments, a cap layer 78 including portions 178, 278, and 378 in device regions 100, 200, and 300, respectively, is deposited over work function layer 76. Cap layer 78 may be formed of or include TiN, TaN, or the like deposited using methods such as ALD, CVD, or the like. The thickness of cap layer 78 may be less than about

[0045] Next, silicon capping layers 80 including portions 180, 280, and 380 are deposited on capping layer 78 in device regions 100, 200, and 300, respectively. According to some embodiments, the deposition of the silicon capping layer is performed by conducting a process gas including a silicon-based precursor (e.g., silane (SiH4), disilane (Si2H6), or a combination thereof) to a corresponding production tool. Other gases such as Ar, He, N2, etc. can be added to the process gas. The forming process includes thermal soaking, where the temperature of the thermal soaking process can be in the range between about 300 °C and about 500 °C. The duration of the thermal soaking process can be in the range between about 0.5 minutes and about 3 minutes. During the thermal soaking process, the partial pressure of the silicon-based precursor can be in the range between about 10 Torr and about 35 Torr. The resulting thickness of the silicon capping layer 80 can be less than about and can be in the range between about and about . The deposited silicon capping layer 80 can include elemental silicon atoms without forming compounds with other elements, and the atomic percentage of silicon atoms in the silicon capping layer 80 can be greater than about 90%, or about 95% to 100% at the time of deposition.

[0046] Next, after forming the silicon capping layer 82 and without breaking the vacuum, an adhesive layer 82 is formed. According to some embodiments, the adhesive layer 82 includes TiN, TaN, etc. The forming process can include ALD, CVD, etc. The thickness of the adhesive layer 82 can be less than and can be less than about According to some embodiments, the thickness of the adhesive layer 82 can be in the range between about and . The process of forming the adhesive layer 82 does not contain an oxygen-containing process gas.

[0047] Figure 17 The deposition of the fill metal regions 183, 283, and 383 is shown. At Figure 22In the illustrated process flow 400, the corresponding process is shown as process 434. Vacuum breakage may or may not occur between the formation of the glue layer 82 and the formation of the filled metal regions 183, 283, and 383. According to some embodiments, the filled metal regions 183, 283, and 383 are formed of tungsten, cobalt, etc., which can be deposited using ALD, CVD, etc. According to some embodiments, the filled metal regions 183, 283, and 383 are formed of tungsten (W) or include tungsten (W). Precursors for forming the filled metal regions 183, 283, and 383 may include WF6 and a reducing agent such as H2. According to some embodiments of using ALD to form the filled metal regions 183, 283, and 383, the ALD process may include multiple ALD cycles, each ALD cycle including conducting WF6, purging WF6, conducting H2, and purging H2. The deposition process may be a heat treatment performed at a high temperature, for example, in the range between about 250 °C and about 400 °C. According to alternative embodiments, the deposition of the filled metal regions 183, 283, and 383 is achieved by CVD, for example, using WF6 and H2 as process gases. According to some embodiments, the filled metal regions 183, 283, and 383 each extend into the unfilled portions of the corresponding trenches 162, 262, and 362( Figure 16 ). According to alternative embodiments, after the cap layer 82 is formed, trench 162 or both trenches 162 and 262 are completely filled, so that the filled metal region 183 or the filled metal regions 183 and 283 are completely outside the corresponding trenches 162 and 262.

[0048] After the trenches are completely filled, a planarization process is performed to remove the excess portions of the multiple layers, thereby forming the gate stacks 184, 284, and 384 as shown Figure 18 . In the process flow 400 shown Figure 22 , the corresponding process is shown as process 436. The gate stacks 184, 284, and 384 respectively include gate electrodes 186, 286, and 386.

[0049] Figure 19A The formation of the self-aligned hard masks 188, 288, and 388 according to some embodiments is shown, which may include performing an etching process to recess the gate stacks 184, 284, and 384 to form grooves. Then the grooves are filled with a dielectric material, followed by a planarization process to remove the excess dielectric material, and the remaining dielectric material forms the hard masks 188, 288, and 388. The hard masks 188, 288, and 388 may be formed of silicon nitride, silicon oxynitride, silicon oxycarbide nitride, etc.

[0050] Further referring to Figure 19A, silicide regions 195, 295, and 395 and source / drain contact plugs 196, 296, and 396 are formed to be electrically connected to source / drain regions 154, 254, and 354, respectively. Gate contact plugs 194, 294, and 394 are formed to be electrically connected to gate electrodes 186, 286, and 386, respectively. Thus, FinFETs 198, 298, and 398 are formed in device regions 100, 200, and 300, respectively.

[0051] Figure 19B A perspective view of FinFET 98 is shown, which can represent FinFETs 198, 298, and 398 as shown in Figure 19A Gate contact plug 94 (representing 194, 294, and 394 in Figure 19A ), source / drain silicide region 95 (representing 195, 295, and 395 in Figure 19A ), and source / drain contact plug 96 (representing 196, 296, and 396 in Figure 19A ) are also shown.

[0052] Transistors 198, 298, and 398 have different threshold voltages due to the tuning effect caused by the layers under the corresponding work function layers. For example, when transistors 198, 298, and 398 are n-type transistors, transistor 198 has layers 168 and 172 under the corresponding work function layer 176, transistor 298 has layer 272 under the corresponding work function layer 276, and transistor 398 does not have any layer between work function layer 376 and high-k dielectric layer 366. Therefore, the threshold voltages of transistors 198, 298, and 398 are different from each other. When transistors 198, 298, and 398 are n-type transistors, the threshold voltage of transistor 198 is the lowest among the three, and the threshold voltage of transistor 398 is the highest among the three.

[0053] As Figure 16 shown, work function layer 76, capping layer 78, silicon capping layer 80, and glue layer 82 are formed in-situ without any vacuum break between these processes. Thus, capping layer 78 and silicon capping layer 80 can effectively protect work function layer 76 from being exposed to oxygen, water, etc. in the open-air environment, and work function layer 76 is not oxidized adversely. In addition, since glue layer 82 is deposited on silicon capping layer 80 before any vacuum break occurs, silicon capping layer 80 is not oxidized. If a vacuum break occurs and silicon capping layer 80 is oxidized, the gate resistance will increase, resulting in a performance degradation of the resulting transistors. It should be noted that the oxide of the silicon capping layer does not completely electrically insulate the upper part from the lower part. Instead, it will increase the gate resistance Rg. In the embodiments of the present disclosure, by preventing silicon capping layer 80 from being oxidized, the gate resistance Rg can be reduced by up to about 22%.

[0054] In addition, if the silicon capping layer 80 is oxidized, the glue layer 82 must be formed thicker to effectively perform the function of bonding the upper fill metal regions 183, 283, and 383 to the corresponding underlying silicon capping layers 180, 280, and 380. For example, the thickness of the glue layer 82 needs to be greater than about Otherwise, delamination may occur between the silicon capping layers 180, 280, and 380 and the corresponding upper fill metal regions 183, 283, and 383. However, in the embodiments of the present disclosure, since the silicon capping layer 82 is not oxidized, the thickness of the glue layer 82 can be significantly reduced, for example, reduced to about and about without sacrificing its bonding function.

[0055] Another advantageous feature of reducing the thickness of the glue layer 82 is that by reducing the thickness of the glue layer 82, the distance between the fill metal regions 183, 283, and 383 and the corresponding underlying high-k dielectric layers 166, 266, and 366 is reduced. Therefore, more fluorine in the fill metal regions 183, 283, and 383 can diffuse into the high-k dielectric layer. Experimental results show that by adopting the embodiments of the present disclosure, the amount of fluorine diffused into the high-k gate dielectrics 166, 266, and 366 in the sample wafers can be increased by about 15.9%. This can significantly improve device reliability. For example, Figure 20 shows the time-dependent dielectric breakdown (TDDB) Vmax (Y-axis) of the high-k gate dielectric varying with the current Igi (leakage current flowing through the high-k gate dielectric, X-axis). The corresponding experiment was performed at 125 °C. The results show that when the glue layer thickness is (point 90), the TDDB Vmax is 0.99 volts. When the embodiments of the present disclosure are adopted and the thickness of the glue layer is reduced to , the TDDB Vmax increases by about 80 mV, indicating an increase in the reliability of the high-k gate dielectric.

[0056] Figure 21 shows an example distribution map of some elements in the gate electrode 386 ( Figure 19A ). The X-axis shows the position in the gate stack, and the Y-axis shows the signal intensity of the elements. The distributions of the elements Hf, O, Si, Al, and Ti in the high-k dielectric layer 366, the work function layer 376, the (TiN) capping layer 378, the silicon layer 380, the (TiN) glue layer 382, and the fill metal region 383 are shown. The results show that due to the in-situ deposition of these layers, there is no oxygen at the interface between the silicon layer 380 and the (TiN) glue layer 382.

[0057] Embodiments of the present disclosure have some advantageous features. By in-situ forming a metal-containing capping layer over the work function layer and in-situ forming a silicon capping layer over the metal-containing layer, the work function layer can be protected from oxidation. On the other hand, the silicon capping layer is also prone to oxidation. Therefore, an in-situ deposition process is performed to form a glue layer on the silicon capping layer to ensure that the silicon capping layer is not oxidized. This in turn enables the glue layer to be formed thinner, and the TDDB-related reliability of the gate dielectric of the resulting transistor is improved.

[0058] According to some embodiments of the present disclosure, a method includes: forming a first gate dielectric over a first semiconductor region; depositing a first work function layer over the first gate dielectric; depositing a first silicon layer over the first work function layer; depositing a first glue layer over the first silicon layer, wherein the first work function layer, the first silicon layer, and the first glue layer are deposited in-situ; depositing a first fill metal over the first glue layer; and performing a planarization process, wherein the remaining portions of the first glue layer, the first silicon layer, and the first work function layer form part of a gate electrode. In an embodiment, the method further includes depositing a metal-containing capping layer over the first work function layer, wherein the first silicon layer is further over the metal-containing capping layer, and wherein the deposition of the first work function layer, the metal-containing capping layer, the first silicon layer, and the first glue layer is performed in-situ. In an embodiment, the first glue layer includes titanium nitride and the first glue layer is in physical contact with the first silicon layer. In an embodiment, the first silicon layer is formed by thermally soaking a wafer including the first work function layer in a silicon-based precursor. In an embodiment, the method further includes: forming a second gate dielectric over a second semiconductor region; depositing a metal-containing layer over the second gate dielectric; depositing a second work function layer over the metal-containing layer, wherein the metal-containing layer and the second work function layer are formed of different materials; depositing a second silicon layer over the second work function layer; depositing a second glue layer over the second silicon layer, wherein the deposition of the second work function layer, the second silicon layer, and the second glue layer is performed in-situ; and depositing a second fill metal over the second glue layer. In an embodiment, the deposition of the metal-containing layer and the second work function layer is performed ex-situ with a vacuum break therebetween. In an embodiment, the thickness of the first glue layer is less than In an embodiment, oxygen (O2) is not used during the entire in-situ deposition process for depositing the first work function layer, the first silicon layer, and the first glue layer.

[0059] According to some embodiments of the present disclosure, an integrated circuit device includes: a semiconductor region; a gate dielectric over the semiconductor region; a work function layer over the gate dielectric; a silicon layer over the work function layer; a glue layer over the silicon layer and in contact with the silicon layer; and a fill metal region over the glue layer and in contact with the glue layer. In an embodiment, the thickness of the glue layer is less than In an embodiment, the silicon layer includes elemental silicon atoms, and the elemental silicon atoms are in physical contact with the glue layer. In an embodiment, the glue layer includes titanium nitride. In an embodiment, the integrated circuit device further includes: a titanium nitride layer between the work function layer and the silicon layer. In an embodiment, the work function layer is an n work function layer. In an embodiment, the thickness of the silicon layer is less than about

[0060] According to some embodiments of the present disclosure, a device includes: a semiconductor fin; a high-k dielectric on the semiconductor fin; a work function layer on the high-k dielectric; a first titanium nitride layer on the work function layer; a silicon layer on the first titanium nitride layer; a second titanium nitride layer on the silicon layer, wherein the interface between the silicon layer and the second titanium nitride layer is oxygen-free; and a filled metal region on the second titanium nitride layer and in contact with the second titanium nitride layer. In an embodiment, the first titanium nitride layer is in physical contact with the work function layer. In an embodiment, the thickness of the second titanium nitride layer is less than In an embodiment, the thickness of the second titanium nitride layer is in the range of about and about In an embodiment, the thickness of the silicon layer is less than about

[0061] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0062] Example 1 is a method of forming an integrated circuit device, including: forming a first gate dielectric on a first semiconductor region; depositing a first work function layer on the first gate dielectric; depositing a first silicon layer on the first work function layer; depositing a first glue layer on the first silicon layer, wherein the first work function layer, the first silicon layer, and the first glue layer are deposited in-situ; depositing a first filled metal on the first glue layer; and performing a planarization process, wherein the remaining portions of the first glue layer, the first silicon layer, and the first work function layer form part of a gate electrode.

[0063] Example 2 is the method of Example 1, further including: depositing a metal-containing capping layer on the first work function layer, wherein the first silicon layer is further on the metal-containing capping layer, and wherein the deposition of the first work function layer, the metal-containing capping layer, the first silicon layer, and the first glue layer is performed in-situ.

[0064] Example 3 is the method described in Example 1, wherein the first glue layer includes titanium nitride, and the first glue layer is in physical contact with the first silicon layer.

[0065] Example 4 is the method described in Example 1, wherein the first silicon layer is formed by thermally soaking a wafer including the first work function layer in a silicon-based precursor.

[0066] Example 5 is the method described in Example 1, further comprising: forming a second gate dielectric on a second semiconductor region; depositing a metal-containing layer on the second gate dielectric; depositing a second work function layer on the metal-containing layer, wherein the metal-containing layer and the second work function layer are formed of different materials; depositing a second silicon layer on the second work function layer; depositing a second glue layer on the second silicon layer, wherein the deposition of the second work function layer, the second silicon layer, and the second glue layer is performed in-situ; and depositing a second fill metal on the second glue layer.

[0067] Example 6 is the method described in Example 5, wherein the deposition of the metal-containing layer and the second work function layer is performed ex-situ with a vacuum break therebetween.

[0068] Example 7 is the method described in Example 1, wherein the thickness of the first glue layer is less than

[0069] Example 8 is the method described in Example 1, wherein no oxygen (O2) is used during the entire in-situ deposition process for depositing the first work function layer, the first silicon layer, and the first glue layer.

[0070] Example 9 is an integrated circuit device, comprising: a semiconductor region; a gate dielectric over the semiconductor region; a work function layer over the gate dielectric; a silicon layer over the work function layer; a glue layer over the silicon layer and in contact with the silicon layer; and a fill metal region over the glue layer and in contact with the glue layer.

[0071] Example 10 is the integrated circuit device described in Example 9, wherein the thickness of the glue layer is less than

[0072] Example 11 is the integrated circuit device described in Example 9, wherein the silicon layer includes elemental silicon atoms.

[0073] Example 12 is the integrated circuit device described in Example 9, wherein the glue layer includes titanium nitride.

[0074] Example 13 is the integrated circuit device described in Example 9, further comprising: a titanium nitride layer between the work function layer and the silicon layer.

[0075] Example 14 is the integrated circuit device described in Example 9, wherein the work function layer is an n work function layer.

[0076] Example 15 is the integrated circuit device described in Example 9, wherein the thickness of the silicon layer is less than about

[0077] Example 16 is an integrated circuit device, comprising: a semiconductor fin; a high-k dielectric on the semiconductor fin; a work function layer on the high-k dielectric; a first titanium nitride layer on the work function layer; a silicon layer on the first titanium nitride layer; a second titanium nitride layer on the silicon layer, wherein the interface between the silicon layer and the second titanium nitride layer is oxygen-free; and a filled metal region on the second titanium nitride layer and in contact with the second titanium nitride layer.

[0078] Example 17 is the device described in Example 16, wherein the first titanium nitride layer is physically in contact with the work function layer.

[0079] Example 18 is the device described in Example 16, wherein the thickness of the second titanium nitride layer is less than

[0080] Example 19 is the device described in Example 16, wherein the thickness of the second titanium nitride layer is in the range of about to about therebetween.

[0081] Example 20 is the device described in Example 16, wherein the thickness of the silicon layer is less than about

Claims

1. A method of forming an integrated circuit device, comprising: Form a first gate dielectric on a first semiconductor region; Deposit a first work function layer on top of the first gate dielectric; Deposit a first silicon layer on top of the first work function layer; Deposit a first glue layer on top of the first silicon layer, wherein the first work function layer, the first silicon layer, and the first glue layer are deposited in-situ; Deposit a first fill metal on top of the first glue layer; and Perform a planarization process, wherein the remaining portions of the first glue layer, the first silicon layer, and the first work function layer form part of a gate electrode, wherein the interface between the first silicon layer and the first glue layer is oxygen-free, wherein the first silicon layer is a conductive layer, and wherein the first glue layer comprises titanium nitride or tantalum nitride.

2. The method according to claim 1, further comprising: Deposit a metal-containing capping layer on top of the first work function layer, wherein the first silicon layer is further on top of the metal-containing capping layer, and wherein the deposition of the first work function layer, the metal-containing capping layer, the first silicon layer, and the first glue layer is performed in-situ.

3. The method according to claim 1, wherein, The first glue layer is in physical contact with the first silicon layer.

4. The method according to claim 1, wherein, The first silicon layer is formed by thermally soaking a wafer including the first work function layer in a silicon-based precursor.

5. The method according to claim 1, further comprising: Form a second gate dielectric on a second semiconductor region; Deposit a metal-containing layer on top of the second gate dielectric; Deposit a second work function layer on top of the metal-containing layer, wherein the metal-containing layer and the second work function layer are formed of different materials; Deposit a second silicon layer on top of the second work function layer; Deposit a second glue layer on top of the second silicon layer, wherein the deposition of the second work function layer, the second silicon layer, and the second glue layer is performed in-situ; and Deposit a second fill metal on top of the second glue layer.

6. The method according to claim 5, wherein, The deposition of the metal-containing layer and the second work function layer is performed ex-situ with a vacuum break therebetween.

7. The method according to claim 1, wherein, The thickness of the first adhesive layer is less than 8. The method according to claim 1, wherein, During the entire in-situ deposition process for depositing the first work function layer, the first silicon layer, and the first glue layer, oxygen O2 is not used.

9. An integrated circuit device, comprising: Semiconductor region; Gate dielectric, on top of the semiconductor region; Work function layer, on top of the gate dielectric; Silicon layer, on top of the work function layer, wherein the silicon layer is a conductive layer; Glue layer, on top of and in contact with the silicon layer, wherein the interface between the silicon layer and the glue layer is oxygen-free, and wherein the glue layer comprises titanium nitride or tantalum nitride; and Fill metal region, on top of and in contact with the glue layer.

10. The integrated circuit device according to claim 9, wherein, The thickness of the adhesive layer is less than 11. The integrated circuit device according to claim 9, wherein, The silicon layer comprises elemental silicon atoms.

12. The integrated circuit device according to claim 9, further comprising: Titanium nitride layer, between the work function layer and the silicon layer.

13. The integrated circuit device according to claim 9, wherein, The work function layer is an n work function layer.

14. The integrated circuit device according to claim 9, wherein, The thickness of the silicon layer is less than 15. An integrated circuit device, comprising: Semiconductor fin; High-k dielectric, on top of the semiconductor fin; Work function layer, on top of the high-k dielectric; First titanium nitride layer, on top of the work function layer; Silicon layer, on top of the first titanium nitride layer; Second titanium nitride layer, on top of the silicon layer, wherein the interface between the silicon layer and the second titanium nitride layer is oxygen-free, and wherein the silicon layer is configured to electrically interconnect the first titanium nitride layer and the second titanium nitride layer; and The filler metal region is on and in contact with the second titanium nitride layer.

16. The device according to claim 15, wherein, The first titanium nitride layer is physically in contact with the work function layer.

17. The device according to claim 15, wherein, The thickness of the second titanium nitride layer is less than 18. The device according to claim 15, wherein, The thickness of the second titanium nitride layer is within the range of to .

19. The device according to claim 15, wherein, The thickness of the silicon layer is less than

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