Semiconductor storage device

Abstract

An embodiment provides a semiconductor memory device that can suppress the melting of a through-hole contact between a local wiring connected to a source layer and an upper wiring located thereon. In the memory of this embodiment, the circuit is located below the memory cell array. The source layer is located between the memory cell array and the circuit. When viewed from the stacking direction, the first contact is located in the contact area. The first contact penetrates the contact area to reach the circuit. The second contact spans two adjacent cell areas and the contact area between the two cell areas. The second contact penetrates the cell area and the contact area in the stacking direction and is set to the source layer. The first wiring extends in the contact area in a direction that intersects with the extension direction of the second contact. The second wiring is set directly above the second contact, extends along the second contact in the contact area, and is connected to the first wiring. A plurality of third contacts are set between the second wiring and the second contact.

Description

[0001] [Related applications]

[0002] This application claims the priority of Japanese Patent Application No. 2020-5851 (filing date: January 17, 2020) as a basic application, and the present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] In recent years, a semiconductor memory device has been developed, which has a three-dimensional memory cell array in which memory cells are arranged three-dimensionally. In this semiconductor memory device, a local wiring that connects a source layer arranged under the memory cell array to an upper wiring is arranged in a tap region between adjacent memory cell arrays. In order to suppress the warping of the substrate and to form it in common with other contacts, a low-resistance metal such as tungsten is buried in the groove (slit) of the tap region, thereby forming the local wiring.

[0005] However, the current from the source layer flows from the local wiring to the upper wiring via the via contact. At this time, there is a problem that the current is concentrated on the via contact between the local wiring and the upper wiring, causing the via contact to melt. Summary of the invention

[0006] Embodiments provide a semiconductor memory device capable of suppressing melting of a via contact between a local wiring connected to a source layer and an upper-layer wiring located thereon.

[0007] The semiconductor memory device of the present embodiment has a memory cell array, which is arranged on a laminated body formed by alternately laminating a plurality of insulating layers and a plurality of conductive layers, and has a cell region including a plurality of memory cells and a contact region located between two adjacent cell regions. The circuit is arranged below the memory cell array. The source layer is located between the memory cell array and the circuit. When viewed from the lamination direction of the laminated body, the first contact is arranged in the contact region. The first contact is arranged in the contact region to the circuit through the lamination direction. When viewed from the lamination direction, the second contact is arranged across two adjacent cell regions and the contact region between the two cell regions. The second contact is arranged in the lamination direction through the cell region and the contact region to the source layer. When viewed from the lamination direction, the first wiring extends in the contact region in a direction intersecting with the extension direction of the second contact. The second wiring is arranged directly above the second contact, and when viewed from the lamination direction, extends along the second contact in the contact region to be connected to the first wiring. The plurality of third contacts are provided between the second wiring and the second contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a perspective view showing an example of the structure of a semiconductor memory device.

[0009] Figure 2 It is a cross-sectional view showing an example of the structure of the columnar portion.

[0010] Figure 3 It is a plan view showing an example of the structure of the columnar portion.

[0011] Figure 4 It is a plan view showing an example of the structure of the semiconductor memory device according to the present embodiment.

[0012] Figure 5 is a more detailed representation Figure 4 A top view of the memory cell array of frame B1.

[0013] Figure 6 is a more detailed representation Figure 5 A top view of the tap area of ​​box B2.

[0014] Figure 7 is a more detailed representation Figure 6 A top view of a portion of the memory cell array of frame B3.

[0015] Figure 8 It is a plan view showing the connection relationship between the columnar portion and the bit line.

[0016] Fig. 9 It is along Figure 7 A cross-sectional view taken along line 9-9.

[0017] Fig.10 It is along Figure 7 A cross-sectional view of line 10-10.

[0018] Fig.11 is a more detailed representation Figure 6 A top view of a portion of the tap area of ​​box B4.

[0019] Fig.12 It is along Fig.11 A cross-sectional view of line 12-12.

[0020] Fig.13 It is along Fig.11 A cross-sectional view taken along line 13-13.

[0021] Fig.14 It is along Fig.11 A cross-sectional view of line 14-14.

[0022] Fig.15 FIG. 1 is a plan view showing an example of the structure of a semiconductor memory device according to Modification 1. FIG.

[0023] Fig.16 It is a plan view showing an example of the structure of a semiconductor memory device according to Modification 2. DETAILED DESCRIPTION

[0024] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. This embodiment does not limit the present invention. In the following embodiments, the up-down direction of the semiconductor substrate represents the relative direction when the surface on which the semiconductor element is provided is upward, which is sometimes different from the up-down direction following the gravitational acceleration. The accompanying drawings are schematic diagrams or conceptual diagrams, and the ratios of the various parts may not be the same as the actual situation. In the specification and the drawings, the same symbols are marked for the elements that are the same as the elements described in the above drawings, and the detailed description is appropriately omitted.

[0025] Figure 1 1 is a perspective view showing an example of the structure of a semiconductor memory device. The semiconductor memory device 100 may be, for example, a NAND flash memory, and has a three-dimensional memory cell array MCA in which memory cells are three-dimensionally arranged. In this embodiment, the stacking direction of the stacked body 2 is set to the Z direction. A direction intersecting (e.g., orthogonal to) the Z direction is set to the Y direction. A direction intersecting (e.g., orthogonal to) the Z and Y directions is set to the X direction.

[0026] The semiconductor memory device 100 includes a base portion 1 , a laminated body 2 , and a plurality of columnar portions CL.

[0027] The base portion 1 includes a substrate 10, an insulating film 11, a conductive film 12, and a semiconductor layer 13. The insulating film 11 is provided on the substrate 10. The conductive film 12 is provided on the insulating film 11. The semiconductor layer 13 is provided on the conductive film 12. The substrate 10 is a semiconductor substrate, for example, a p-type silicon substrate. In the surface region of the substrate 10, for example, an element isolation region 10i is provided. The element isolation region 10i is, for example, an insulating region including silicon oxide, and an effective area AA is divided in the surface region of the substrate 10. In the effective area AA, source and drain regions of the transistor Tr are provided. The transistor Tr constitutes a peripheral circuit (for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit) of a nonvolatile memory. The insulating film 11 includes, for example, silicon oxide (SiO2), and insulates the transistor Tr. In the insulating film 11, a wiring 11a is provided. The wiring 11a is a wiring electrically connected to the transistor Tr. The conductive film 12 includes a conductive metal, for example, tungsten (W). The semiconductor layer 13 includes, for example, silicon. The conductivity type of silicon is, for example, n-type. A portion of the semiconductor layer 13 may include undoped silicon.

[0028] The laminate 2 is located in the Z direction relative to the semiconductor layer 13. The laminate 2 is formed by alternately laminating a plurality of conductive layers 21 and a plurality of insulating layers 22 along the Z direction. The conductive layer 21 includes a conductive metal, such as tungsten. The insulating layer 22 includes, for example, silicon oxide. The insulating layer 22 insulates the conductive layers 21 from each other. The number of layers of the conductive layer 21 and the insulating layer 22 is arbitrary. The insulating layer 22 can be, for example, an air gap. Between the laminate 2 and the semiconductor layer 13, for example, an insulating film 2g is provided. The insulating film 2g includes, for example, silicon oxide (SiO2). The insulating film 2g can include a high dielectric having a relative dielectric constant higher than that of silicon oxide. The high dielectric is, for example, a metal oxide.

[0029] The conductive layer 21 includes at least one source side selection gate SGS, a plurality of word lines WL, and at least one drain side selection gate SGD. The source side selection gate SGS is the gate electrode of the source side selection transistor STS. The word line WL is the gate electrode of the memory cell MC. The drain side selection gate SGD is the gate electrode of the drain side selection transistor STD. The source side selection gate SGS is disposed in the lower region of the laminate 2. The drain side selection gate SGD is disposed in the upper region of the laminate 2. The lower region refers to the region of the laminate 2 on the side close to the base portion 1, and the upper region refers to the region of the laminate 2 on the side away from the base portion 1. The word line WL is disposed between the source side selection gate SGS and the drain side selection gate SGD.

[0030] Among the plurality of insulating layers 22, the thickness in the Z direction of the insulating layer 22 insulating the source side selection gate SGS from the word line WL may be, for example, thicker than the thickness in the Z direction of the insulating layer 22 insulating the word line WL from the word line WL. Furthermore, a cap insulating film may be provided on the uppermost insulating layer 22 which is the farthest from the base portion 1. The cap insulating film includes, for example, silicon oxide.

[0031] The semiconductor memory device 100 has a plurality of memory cells MC connected in series between a source side selection transistor STS and a drain side selection transistor STD. The structure in which the source side selection transistor STS, the memory cells MC, and the drain side selection transistor STD are connected in series is called a "memory string" or a "NAND string". The memory string is connected to a bit line BL via a through-hole contact V0, for example. The bit line BL is provided above the laminate 2 and extends in the Y direction.

[0032] A plurality of deep slits ST and a plurality of shallow slits SHE are provided in the laminate 2. In addition, the "slit" refers to a portion including a groove and a conductor and / or an insulator buried in the groove. The deep slits ST extend in the X direction, penetrate the laminate 2 from the upper end of the laminate 2 to the base 1, and are provided in the laminate 2. Figure 1Although not shown in the figure, the deep slit ST is filled with an insulating material such as a silicon oxide film. Alternatively, the deep slit ST is filled with a conductor, which is electrically insulated from the laminate 2 by the insulating material and is electrically connected to the semiconductor layer 13. That is, the insulating material covers the inner side of the slit ST, and the conductor is buried inside the insulating material. For example, a low-resistance metal such as tungsten is used as the conductor. The conductor is connected to the semiconductor layer 13 in the slit ST. The shallow slit SHE extends in the X direction and is set from the upper end of the laminate 2 to the middle of the laminate 2. Figure 1 Although not shown in the figure, the shallow slit SHE is filled with an insulating material such as a silicon oxide film.

[0033] Thus, the semiconductor memory device 100 of the present embodiment includes the memory cell array MCA and the peripheral circuit (CMOS circuit) located below the memory cell array MCA. The semiconductor layer 13 located between the memory cell array MCA and the peripheral circuit functions as a source layer of the memory cell array MCA.

[0034] Figure 2 : is a cross-sectional view showing an example of the structure of the columnar portion CL. A plurality of columnar portions CL are respectively arranged in the memory hole MH provided in the laminate 2. The memory hole MH penetrates the laminate 2 from the upper end of the laminate 2 along the Z direction and is arranged in the laminate 2 and in the semiconductor layer 13. The plurality of columnar portions CL respectively include a semiconductor body 210, a memory film 220 and a core layer 230. The semiconductor body 210 is electrically connected to the semiconductor layer 13. The memory film 220 has a charge capture portion between the semiconductor body 210 and the conductive layer 21. The plurality of columnar portions CL selected one by one from each of the fingers described below are connected to one bit line BL via a through-hole contact V0. The columnar portions CL are respectively arranged in, for example, a memory cell array region.

[0035] Figure 3 : is a top view showing an example of the structure of the columnar portion CL. The shape of the memory hole MH on the XY plane is, for example, a circle or an ellipse. A blocking insulating film 21a constituting a part of the memory film 220 may also be provided between the conductive layer 21 and the insulating layer 22. The blocking insulating film 21a is, for example, a silicon oxide film or a metal oxide film. An example of a metal oxide is aluminum oxide. A barrier film 21b may also be provided between the conductive layer 21 and the insulating layer 22 and between the conductive layer 21 and the memory film 220. For example, when the conductive layer 21 is tungsten, the barrier film 21b may be, for example, a laminated structure film of titanium nitride and titanium. The blocking insulating film 21a suppresses reverse tunneling of charges from the conductive layer 21 to the memory film 220 side. The barrier film 21b improves the adhesion between the conductive layer 21 and the blocking insulating film 21a.

[0036] The shape of the semiconductor body 210 is, for example, a bottomed cylinder. The semiconductor body 210 contains, for example, silicon. For example, silicon is polycrystalline silicon obtained by crystallizing amorphous silicon. The semiconductor body 210 is, for example, undoped silicon. In addition, the semiconductor body 210 may be p-type silicon. The semiconductor body 210 serves as a channel for each of the drain side selection transistor STD, the memory cell MC, and the source side selection transistor STS.

[0037] The memory film 220 is provided between the inner wall of the memory hole MH and the semiconductor body 210 except for the blocking insulating film 21a. The shape of the memory film 220 is, for example, cylindrical. A plurality of memory cells MC have a storage region between the semiconductor body 210 and the conductive layer 21 that becomes the word line WL, and are stacked in the Z direction. The memory film 220 includes, for example, a cap insulating film 221, a charge trapping film 222, and a tunnel insulating film 223. The semiconductor body 210, the charge trapping film 222, and the tunnel insulating film 223 extend in the Z direction, respectively.

[0038] The cover insulating film 221 is provided between the insulating layer 22 and the charge trapping film 222. The cover insulating film 221 includes, for example, silicon oxide. The cover insulating film 221 protects the charge trapping film 222 from being etched when the sacrificial film (not shown) is replaced with the conductive layer 21 (replacement step). The cover insulating film 221 may also be removed from between the conductive layer 21 and the memory film 220 in the replacement step. In this case, Figure 2 and Figure 3 As shown, for example, a blocking insulating film 21a is provided between the conductive layer 21 and the charge trap film 222. When the replacement step is not used in the formation of the conductive layer 21, the cover insulating film 221 may not be provided.

[0039] The charge capture film 222 is provided between the blocking insulating film 21a and the cap insulating film 221 and the tunnel insulating film 223. The charge capture film 222 includes, for example, silicon nitride, and has a capture portion for capturing charges in the film. In the charge capture film 222, a portion sandwiched between the conductive layer 21, which becomes the word line WL, and the semiconductor body 210 constitutes a storage area of ​​the memory cell MC as a charge capture portion. The threshold voltage of the memory cell MC changes depending on the presence or absence of charges in the charge capture portion or the amount of charges captured in the charge capture portion. Thus, the memory cell MC stores information.

[0040] The tunnel insulating film 223 is disposed between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 includes, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 to the charge trapping portion (writing operation) and when holes are injected from the semiconductor body 210 to the charge trapping portion (erasing operation), the electrons and holes respectively pass through (tunnel) the potential barrier of the tunnel insulating film 223.

[0041] The core layer 230 is embedded in the inner space of the cylindrical semiconductor body 210. The core layer 230 is, for example, columnar. The core layer 230 includes, for example, silicon oxide and has insulating properties.

[0042] Figure 4 FIG. 1 is a top view showing an example of the structure of a semiconductor memory device according to the present embodiment. Figure 1 Similarly, the word line WL extends in the X direction, and the bit line BL extends in the Y direction. On both sides of the memory cell array MCA in the X direction, there are step regions TRC of the word line WL. The step region TRC is a region where the word line WL is processed into a step shape, and is provided in order to connect the contact plug to each word line WL. Figure 1 As shown, a peripheral circuit (eg, a CMOS circuit) for controlling the memory cell array MCA is provided below the memory cell array MCA.

[0043] Figure 5 is a more detailed representation Figure 4 FIG. 1 is a top view of a memory cell array MCA of a frame B1. There are two step regions TRC on both sides of the memory cell array MCA, and a cell region RMC and tap regions TAP_BL and TAP_VB are provided in the memory cell array MCA. The cell region RMC is a region including a plurality of memory cells MC, and has a plurality of columnar portions CL. The tap region TAP_BL is a contact region for forming a contact plug in order to connect the bit line BL to the CMOS circuit under the memory cell array MCA. The tap region TAP_VB is a contact region for forming a contact plug, which is used to connect a power supply (not shown) and the like to the CMOS circuit, and to connect a source voltage to the semiconductor layer 13.

[0044] Figure 6 is a more detailed representation Figure 5 FIG. 1 is a top view of the tap region TAP_VB in the frame B2. As described above, the memory cell array MCA includes the cell regions RMC and the tap region TAP_VB. The tap region TAP_VB is a contact region located between two adjacent cell regions RMC.

[0045] The deep slit ST includes a conductive slit LI_ST and an insulating slit OXI_ST. The conductive slit LI_ST is provided across two adjacent cell regions RMC and a tap region TAP_VB between the two cell regions RMC in the planar layout observed from the stacking direction (Z direction) of the stacked body 2. The conductive slit LI_ST extends continuously in the X direction intersecting (e.g., orthogonal to) the extending direction (Y direction) of the bit line BL in the planar layout. In addition, as described below with reference to Fig. 9 As described above, the conductor slit LI_ST is provided in the stacking direction (Z direction) through the cell region RMC and the tap region TAP_VB to the semiconductor layer 13 as the source layer. Thus, the conductor slit LI_ST functions as a contact connected to the semiconductor layer 13, and a specific source voltage can be applied to the semiconductor layer 13 from an upper wiring (not shown). The conductor slit LI_ST is filled with a conductor (e.g., tungsten), which is electrically insulated from the stacking body 2 by an insulator (e.g., a silicon oxide film), and is electrically connected to the semiconductor layer 13.

[0046] The insulator slit OXI_ST is arranged in the tap region TAP_VB in the plane layout observed from the stacking direction (Z direction), and extends in the X direction substantially parallel to the conductor slit LI_ST. Two insulator slits OXI_ST adjacent in the Y direction are arranged between the conductor slits LI_ST adjacent in the Y direction, and are arranged on both sides of the contact C4 so as to sandwich the contact C4. That is, the insulator slit OXI_ST is arranged between the conductor slit LI_ST and the contact C4 in the plane layout. The insulator slit OXI_ST is filled with an insulating material such as a silicon oxide film, for example. The insulating material in the insulator slit OXI_ST may be an air gap.

[0047] When viewed from the stacking direction (Z direction), the contact C4 is provided in the tap region TAP_VB, and is provided in the Z direction through the tap region TAP_VB to the peripheral circuit located therebelow. The contact C4 is provided, for example, to supply power to the peripheral circuit. In addition, between two adjacent insulator slits OXI_ST, a stack of insulating layers and sacrificial layers without a conductive layer is left, and the contact C4 penetrates the stack of insulating layers and sacrificial layers and is connected to the peripheral circuit. For example, a low-resistance metal such as tungsten is used for the contact C4.

[0048] The shallow slit SHE is provided in two adjacent cell regions RMC and in the tap region TAP_VB between the two cell regions RMC in the planar layout observed from the stacking direction (Z direction). The shallow slit SHE extends continuously in the X direction intersecting (for example, orthogonal) with respect to the extension direction (Y direction) of the bit line BL in the planar layout. In addition, the shallow slit SHE is provided in the upper part of the cell region RMC and the tap region TAP_VB in the stacking direction (Z direction), and has the function of separating the drain side selection gate SGD. Therefore, in the tap region TAP_VB provided with the stacking body 2 having a conductive layer, a part of the shallow slit SHE is continuously provided in the planar layout. However, in the case where Figure 6 Between the insulator slit OXI_ST, there is a tap region TAP_VB of the laminate of the insulating layer and the sacrificial layer, and the shallow slit SHE can also be separated.

[0049] In the cell region RMC, the memory cell array sandwiched by two adjacent conductive slits LI_ST in the Y direction is called a block BLK. Block BLK constitutes, for example, the minimum unit of data erasing. In the cell region RMC, the memory cell array located between the conductive slit LI_ST and the shallow slit SHE and between two adjacent shallow slits SHE in the Y direction is called a finger FNG. The drain side selection gate SGD is separated into fingers FNG by the shallow slit SHE or the conductive slit LI_ST. The finger FNG constitutes, for example, the minimum unit of data reading or writing. As a result, when writing and reading data, one finger FNG in the block BLK can be selectively accessed via the drain side selection gate SGD.

[0050] A plurality of bit lines BL are provided on the cell region RMC. The bit lines BL extend in the Y direction in a planar layout viewed from the stacking direction (Z direction). The bit lines BL are made of a low-resistance metal such as copper, aluminum, or tungsten.

[0051] The semiconductor memory device 100 of the present embodiment further includes wirings M0_1 and M0_2. The wiring M0_1 is a wiring that extends in a direction (Y direction) intersecting the extending direction of the conductor slit LI_ST in the tap region TAP_VB in the planar layout observed from the stacking direction (Z direction). Two wirings M0_1 are provided along the boundary between the two unit regions RMC located on both sides of the tap region TAP_VB and the tap region TAP_VB. The wirings M0_1 are commonly connected to a plurality of wirings M0_2 ​​provided in the tap region TAP_VB.

[0052] The wiring M0_2 ​​is provided just above the conductor slit LI_ST in the tap region TAP_VB, and extends along the conductor slit LI_ST in the planar layout viewed from the stacking direction (Z direction). The wiring M0_2 ​​extends between two wirings M0_1 provided on both sides of a tap region TAP_VB, and connects the two wirings M0_1. In this way, the wirings M0_1 and M0_2 ​​are formed in a ladder shape in the planar layout.

[0053] The wirings M0_1 and M0_2 ​​are located in a wiring layer above the conductive slit LI_ST and the insulating slit OXI_ST and are connected to each other. For example, a low-resistance metal such as copper, aluminum, or tungsten is used for the wirings M0_1 and M0_2.

[0054] The wirings M0_1 and M0_2 ​​are formed in the same wiring layer and in the same step. In addition, the wirings M0_1 and M0_2 ​​and the bit line BL are formed in the same wiring layer and in the same step. Therefore, the wirings M0_1 and M0_2 ​​and the bit line BL are made of the same material.

[0055] An interlayer insulating film is provided between the wirings M0_1 and M0_2 ​​and the conductive slit LI_ST. In addition, in the tap region TAP_VB, a plurality of via contacts V0 are provided with an interlayer insulating film ( Figure 6 (not shown) The wiring M0_1 and the conductive slit LI_ST and the wiring M0_2 ​​and the conductive slit LI_ST are connected. For example, a low-resistance metal such as tungsten is used for the via contact V0.

[0056] Figure 7 is a more detailed representation Figure 6 FIG. 1 is a top view of a portion of the memory cell array of the frame B3. The columnar portion CL, i.e., the memory hole MH, is arranged in a hexagonal closest-packed arrangement between two adjacent conductive slits LI_ST in the Y direction in the planar layout. In addition, the shallow slit SHE is provided on a portion of the columnar portion CL. The columnar portion CL located below the shallow slit SHE does not constitute a memory cell. Figure 7 In FIG. 1 , the bit line BL is omitted from the illustration. The connection relationship between the columnar portion CL and the bit line BL is as shown in FIG. Figure 8 to explain.

[0057] Figure 8 1 is a top view showing the connection relationship between the columnar portion CL and the bit line BL. The bit line BL is connected to the columnar portion CL via a via contact V0. The via contact V0 is arranged in a staggered manner in the planar layout. Thus, each bit line BL is connected to only one columnar portion CL among the plurality of columnar portions CL included in a finger FNG via the via contact V0.

[0058] Fig. 9 It is along Figure 7 A cross-sectional view taken along line 9-9. Fig.10 It is along Figure 7 The cross-sectional view of line 10-10. Figure 1 As described above, semiconductor elements such as transistors Tr are formed on the substrate 10 of the base 1. The semiconductor elements such as transistors Tr constitute peripheral circuits such as CMOS circuits. The peripheral circuits formed on the substrate 10 are covered by the interlayer insulating film ILD1. On the interlayer insulating film ILD1, a semiconductor layer 13 that functions as a source layer is provided.

[0059] The laminated body 2 is provided on the semiconductor layer 13 . The columnar portion CL is provided to penetrate the laminated body 2 to the semiconductor layer 13 . Thus, the semiconductor body 210 of the columnar portion CL is electrically connected to the semiconductor layer 13 .

[0060] The conductor slit LI_ST is also provided through the laminate 2 to the semiconductor layer 13. The conductor slit LI_ST is provided in a groove provided through the laminate 2 to the semiconductor layer 13 in the cell region RMC and the tap region TAP_VB in the lamination direction. The conductor slit LI_ST has an insulating layer 40 covering the inner side of the groove and a conductor 50 buried inside the insulating layer 40. The insulating layer 40 is interposed between the conductor 50 and the laminate 2, and electrically insulates the conductor 50 from the word line WL, the source side selection gate SGS, and the drain side selection gate SGD. On the other hand, the conductor 50 is electrically connected to the semiconductor layer 13 at the bottom of the conductor slit LI_ST. That is, the conductor 50 is electrically connected to the semiconductor layer 13 while being electrically insulated from the word line WL, the source side selection gate SGS, and the drain side selection gate SGD of the laminate 2 by the insulating layer 40. Thus, the conductive slit LI_ST can apply a source voltage from the wirings M0_1 and M0_2 ​​above the laminate 2 to the semiconductor layer 13 .

[0061] The shallow slit SHE is provided so as to cut off the drain-side selection gate SGD, and divides the columnar portion CL (that is, the memory cell array MCA) into the fingers FNG.

[0062] The through-hole contact V0 is arranged between the bit line BL and the corresponding columnar portion CL. An interlayer insulating film ILD2 is provided on the laminated body 2, and the through-hole contact V0 is arranged inside the interlayer insulating film ILD2. The through-hole contact V0 can be divided into a plurality of upper and lower through-hole contacts V0_1 and V0_2. The through-hole contact V0_1 is, for example, a relatively large (thicker) contact, which is arranged on all the columnar portions CL constituting the memory cell MC. The through-hole contact V0_2 is a relatively narrow (thinner) contact through hole, which is selectively provided on the contact V0_1 to electrically connect the bit line BL and the corresponding columnar portion CL. The through-hole contacts V0_1 and V0_2 use, for example, a low-resistance metal such as tungsten. In addition, Figure 8The via contact V0 shown represents the planar layout of the via contact V0_2.

[0063] Fig.11 is a more detailed representation Figure 6 A top view of a portion of the tap region TAP_VB of the frame B4. The through-hole contact V0 connects the bit line BL and the columnar portion CL in the cell region RMC. In the tap region TAP_VB, the through-hole contact V0 is provided between the conductor slit LI_ST and the wiring M0_2 ​​thereon, and electrically connects the conductor slit LI_ST and the wiring M0_2. A plurality of through-hole contacts V0 are arranged in the X direction along the conductor slit LI_ST and the wiring M0_2.

[0064] In this embodiment, the via contact V0 is also provided at the intersection region R_M0_LI between the conductor slit LI_ST and the wiring M0_1 to electrically connect the conductor slit LI_ST and the wiring M0_1. However, the via contact V0 may be provided only between the conductor slit LI_ST and the wiring M0_2 ​​as long as it can connect the conductor slit LI_ST and the wiring M0_2 ​​with low resistance.

[0065] Fig.12 It is along Fig.11 A cross-sectional view of line 12-12. Fig.13 It is along Fig.11 A cross-sectional view taken along line 13-13. Fig.14 It is along Fig.11 A cross-sectional view of line 14-14.

[0066] like Fig.12 and Fig.13 As shown, in the tap region TAP_VB, the conductive slit LI_ST, the columnar portion CL, and the shallow slit SHE are provided in the same manner as in the cell region RMC. However, the columnar portion CL does not function as a memory cell MC.

[0067] The through hole contact V0 is provided on the conductive slit LI_ST to electrically connect the conductive slit LI_ST to the wiring M0_1 or the wiring M0_2. Fig.14 As shown in FIG. 1 , a plurality of via contacts V0 are arranged along the wiring M0_2. The via contacts V0 are provided in the interlayer insulating film ILD2 to electrically connect the conductive slit LI_ST and the wiring M0_2. Fig.14 It can be seen that the wiring M0_2 ​​extends above the conductive slit LI_ST and substantially in parallel with the conductive slit LI_ST. It can also be seen that the conductive slit LI_ST is a plate-shaped member provided from the upper surface of the laminate 2 to the semiconductor layer 13 .

[0068] Fig.13The insulator slit OXI_ST is set between the contact C4 and the conductive slit LI_ST. The insulator slit OXI_ST is buried in the groove of the semiconductor layer 13 in the stacking direction (Z direction) penetrating the tap area TAP_VB. Between two adjacent insulator slits OXI_ST in the tap area TAP_VB, a stacking body of an insulating layer 22 and a sacrificial layer SAC is left. The sacrificial layer SAC is, for example, a silicon nitride film. In the cell area RMC, the sacrificial layer SAC is replaced by the conductive layer 21 (for example, tungsten) and replaced by the word line WL. However, between the insulator slits OXI_ST in the tap area TAP_VB, the insulator slit OXI_ST suppresses the etching of the sacrificial layer SAC, so that the sacrificial layer SAC remains without being replaced.

[0069] The contact C4 is provided on the laminate of the sacrificial layer SAC and the insulating layer 22. The contact C4 penetrates the laminate of the insulating layer 22 and the sacrificial layer SAC and is connected to any wiring of the peripheral circuit. For example, a low-resistance metal such as tungsten is used for the contact C4.

[0070] As described above, the semiconductor memory device 100 of the present embodiment includes a wiring M0_1 extending in the Y direction in the tap region TAP_VB and a wiring M0_2 ​​extending in the X direction and arranged directly above the conductor slit LI_ST. A plurality of through-hole contacts V0 are provided at least between the wiring M0_2 ​​and the conductor slit LI_ST. Thus, the wiring M0_2 ​​is connected to the conductor slit LI_ST with a low resistance. Thus, even if a relatively large source current flows, the source current is dispersed and flows to a plurality of through-hole contacts V0. Thus, it is possible to suppress the melting of the through-hole contacts V0 between the conductor slit LI_ST, which is the wiring connected to the semiconductor layer 13, and the wiring M0_1 and M0_2.

[0071] When the wiring M0_2 ​​is not provided and the via contact V0 is provided only at the intersection of the wiring M0_1 and the conductive slit LI_ST, the resistance value between the wiring M0_1 and the conductive slit LI_ST becomes relatively high. Therefore, even if a plurality of via contacts V0 are provided, there is a risk that the via contacts V0 may melt due to a large source current.

[0072] In contrast, the semiconductor memory device 100 of the present embodiment includes wiring M0_2, and a relatively large number of via contacts V0 can be provided between wiring M0_2 ​​and conductive slit LI_ST. Thus, even when a large source current flows, melting of via contacts V0 between conductive slit LI_ST and wirings M0_1 and M0_2 ​​can be suppressed.

[0073] In addition, when the portion of the conductor slit LI_ST other than the insulating layer 40 is filled with a low-resistance metal such as tungsten, the conductor slit LI_ST can flow a large source current due to its low resistance. This promotes the melting of the through-hole contact V0. Therefore, when the conductor portion of the conductor slit LI_ST is all low-resistance metal, the structure of this embodiment can effectively suppress the melting of the through-hole contact V0.

[0074] (Variation 1)

[0075] Fig.15 1 is a top view showing an example of the structure of a semiconductor memory device of Variation 1. In Variation 1, the wiring M0_2 ​​is separated and arranged in the unit region RMCa located on one side of the tap region TAP_VB and the unit region RMCb located on the other side of the tap region TAP_VB. The other structures of Variation 1 can be the same as the corresponding structures of the above-mentioned embodiment. In this way, even if the wiring M0_2 ​​is separated, it is not hindered because it is connected to the wiring M0_1 with a low resistance through the through-hole contact V0.

[0076] (Variation 2)

[0077] Fig.16 1 is a top view showing an example of the structure of a semiconductor storage device of Variation 2. In Variation 2, the through-hole contact V0 is arranged across the entire wiring M0_2 ​​in the X direction. As a result, the resistance between the wiring M0_2 ​​and the conductor slit LI_ST is further reduced. The other structures of Variation 2 can be the same as the corresponding structures of the above-mentioned embodiment. In this way, the through-hole contact V0 can be arranged in the entire wiring M0_2. The size and number of the through-hole contacts V0 can be set according to the current flowing in the through-hole contacts V0.

[0078] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and can be omitted, replaced, and changed in various ways without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the invention described in the claims and their equivalents.

[0079] [Explanation of Symbols]

[0080] 100 Semiconductor devices

[0081] 1 base part

[0082] 2 Layered body

[0083] CL column

[0084] 10 Substrate

[0085] 11 Insulation film

[0086] 12 Conductive film

[0087] 13 Semiconductor Division

[0088] MCA Memory Cell Array

[0089] BL bit line

[0090] WL Word Line

[0091] 21 Conductive layer

[0092] 22 Insulation layer

[0093] SGS Source Side Select Gate

[0094] SGD Drain side select gate

[0095] TAP_BL, TAP_VB tap area

[0096] LI_ST Conductive slit

[0097] OXI_ST Insulator Slit

[0098] RMC unit area

[0099] C4 contact

[0100] SHE Shallow Slit

[0101] M0_1, M0_2 ​​wiring

[0102] V0 through-hole contact.

Claims

1. A semiconductor storage device comprising: A memory cell array is provided on a laminated body formed by alternately laminating a plurality of insulating layers and a plurality of conductive layers, and has a cell region including a plurality of memory cells and a contact region located between two adjacent cell regions; A circuit, arranged below the memory cell array; A source layer, located between the memory cell array and the circuit; A first contact is provided in the contact region when viewed from the lamination direction of the laminate, and is provided through the contact region in the lamination direction to the circuit; A second contact, when viewed from the stacking direction, is arranged across two adjacent cell regions and the contact region between the two cell regions, and is arranged to extend through the cell regions and the contact region to the source layer in the stacking direction; a first wiring extending in a direction intersecting with an extending direction of the second contact in the contact region when viewed from the stacking direction; a second wiring, arranged just above the second contact, extending along the second contact in the contact region when viewed from the stacking direction, and connected to the first wiring; as well as A plurality of third contacts are provided between the second wiring and the second contact.

2. The semiconductor memory device according to claim 1, further comprising a plurality of fourth contacts, wherein the plurality of fourth contacts are provided at intersections of the first wiring and the second contact and connect the first wiring and the second contact. 3 . The semiconductor memory device according to claim 1 , wherein the first and second wirings are provided in the same layer.

4. The semiconductor memory device according to claim 1 or 2, further comprising a plurality of bit lines provided on the cell region, The first and second wirings are provided in the same layer as the plurality of bit lines.

5. A semiconductor storage device according to claim 1 or 2, wherein the second contact has an insulating film and a conductor buried inside the insulating film, and the insulating film is covered by the stacked body that penetrates the cell area and the contact area in the stacking direction and is set to the side of the groove of the source layer.

6. The semiconductor memory device according to claim 1, wherein two first wirings are provided along boundaries between two cell regions located on both sides of the contact region and the contact region, and are commonly connected to a plurality of second wirings provided in the contact region.

7. The semiconductor memory device according to claim 1, wherein the second wiring connects two of the first wirings provided on both sides of the contact region.

8. The semiconductor memory device according to claim 1, wherein the second wiring is separately provided in each of the cell region located on one side of the contact region and the cell region located on the other side of the contact region.

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