Storage devices and storage systems that perform host offload tasks

Abstract

A storage device and a storage system for performing an offload task of a host are provided. The storage device includes a first interface, an operation circuit, and a non-volatile memory. The first interface receives a first data block from a host device. The operation circuit generates first processed data by processing the first data block, and generates a first signal indicating the size of the first processed data. The non-volatile memory stores the first processed data in a storage location when the storage location to store the first processed data is assigned to the storage device based on the first signal. The first interface outputs the first signal to the host device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0009124 filed on January 23, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a storage device, and more particularly, to a storage device and a storage system for performing offloading work of a host. Background Art

[0004] Nowadays, various types of electronic devices are being used. Electronic devices perform unique functions based on the operation of the electronic circuits included therein. Electronic devices can perform unique functions while operating alone within themselves. In some cases, electronic devices can perform unique functions while communicating with various other electronic devices.

[0005] A storage device is an example of an electronic device. A storage device can store and output data according to the operation of the components included therein, thereby providing storage services to users. A storage device can manage data only within itself, or can manage data while communicating with various other electronic devices.

[0006] The host device may be an electronic device that provides services to a user by communicating with the storage device. The host device may provide the storage device with data to be stored therein. In addition, the host device may manage the data to be stored in the storage device.

[0007] As various information is distributed and the amount of data increases dramatically, multiple storage devices may be included in a single system. In this case, the host device may manage the data to be stored in the multiple storage devices. In the case where the host device processes and manages the data to be stored in the multiple storage devices, the workload of the host device may become very heavy. Summary of the invention

[0008] One aspect is to provide a storage device and a storage system for performing host offloading work.

[0009] According to an aspect of an exemplary embodiment, a storage device is provided, the storage device comprising: a first interface, the first interface being configured to receive a first data block from a host device; an operation circuit, the operation circuit being configured to generate first processed data by processing the first data block, and to generate a first signal indicating a size of the first processed data; and a non-volatile memory, the non-volatile memory being configured to store the first processed data in a storage location when the storage location to store the first processed data is designated to the storage device based on the first signal; wherein the first interface outputs the first signal to the host device.

[0010] According to another aspect of the exemplary embodiment, a storage system is provided, comprising: a first storage device, the first storage device being configured to receive a first data block from a host device, convert the first data block into first data, and output a first signal indicating a size of the first data to the host device; and a second storage device, the second storage device being configured to receive a second signal from the host device after the first signal is output; wherein, when the second signal indicates that the second storage device is to be used as a generation position for generating a parity bit for recovering the first data, the second storage device receives the first data from the first storage device and generates the parity bit based on the first data.

[0011] According to another aspect of the exemplary embodiment, a storage system is provided, the storage system comprising: a first storage device, the first storage device being configured to receive a first data block from a host device and generate first processed data by processing the first data block; and a second storage device, the second storage device being configured to receive a first parity bit block for recovering the first data block and generate first processed parity bit data by processing the first parity bit block, wherein the first storage device comprises a first memory, the first memory being configured to store the first processed data in a first size unit, and wherein the size of the first processed data is an integer multiple of the first size unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects will become apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating an exemplary configuration of an electronic system according to some embodiments;

[0014] Figure 2 is a conceptual diagram for describing a general RAID scheme in which a host processor performs work associated with data to be stored in a storage system;

[0015] Figure 3 is a conceptual diagram for describing a RAID scheme in which a storage device performs work associated with data to be stored in a storage system, according to some embodiments;

[0016] Figure 4 It is shown Figure 3 A conceptual diagram of another embodiment of a RAID scheme in which data and parity bits are stored in a storage device;

[0017] Figure 5 It is shown Figure 3 A block diagram of a configuration of a storage device of a RAID scheme;

[0018] Figures 6 to 11 is used to describe the Figure 3 A block diagram of exemplary operations associated with a storage device of a RAID scheme;

[0019] Fig.12 According to some embodiments, Figure 3 A flowchart of the operation of the host processor and storage system of the RAID scheme;

[0020] Fig.13 is a conceptual diagram for describing a RAID scheme according to another embodiment in which a storage device performs work associated with data to be stored in a storage system;

[0021] Fig.14 is a diagram showing some embodiments of the present invention. Fig.13 A block diagram of a configuration of a storage device of a RAID scheme;

[0022] Figures 15 to 17 is used to describe the Fig.13 A block diagram of exemplary operations associated with a storage device of a RAID scheme; and

[0023] Fig.18 According to some embodiments, Fig.13 A flow chart of the operation of the host processor and storage system of the RAID scheme. DETAILED DESCRIPTION

[0024] Below, various embodiments will be described in detail and clearly so that those skilled in the art can easily implement the embodiments.

[0025] Figure 1 is a block diagram illustrating an exemplary configuration of an electronic system according to some embodiments.

[0026] The electronic system 1000 may include a main processor 1100, a working memory 1200, a storage system 1300, a communication block 1400, a user interface 1500, and a bus 1600. For example, the electronic system 1000 may be one of electronic devices such as a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a video game console, a workstation, one or more servers, an electric vehicle, a home appliance, a medical device, etc.

[0027] The main processor 1100 may control the overall operation of the electronic system 1000. For example, the main processor 1100 may be implemented using a general-purpose processor including one or more processor cores, a dedicated processor, or an application processor.

[0028] The working memory 1200 may store data to be used for the operation of the electronic system 1000. For example, the working memory 1200 may temporarily store data processed by the main processor 1100 or to be processed by the main processor 1100. For example, the working memory 1200 may include a volatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM), and / or a nonvolatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM).

[0029] The storage system 1300 may include one or more storage devices. For example, the storage system 1300 may include storage devices 1310 , 1320 , and 1330 . Figure 1 1300 , but the number of storage devices included in the storage system 1300 may be variously changed or modified to meet the requirements of the electronic system 1000 .

[0030] Each of the storage devices 1310, 1320, and 1330 can store data regardless of whether power is supplied thereto. For example, in some embodiments, each of the storage devices 1310, 1320, and 1330 can include a non-volatile memory such as flash memory, PRAM, MRAM, ReRAM, or FRAM. For example, in some embodiments, each of the storage devices 1310, 1320, and 1330 can include a storage medium such as a solid state drive (SSD), card storage, or embedded storage.

[0031] The communication block 1400 may support at least one of various wireless / wired communication protocols for communicating with external devices / systems of the electronic system 1000. The user interface 1500 may include various input / output interfaces for performing communication arbitration between the user and the electronic system 1000.

[0032] The bus 1600 may provide a communication path between components of the electronic system 1000. The components of the electronic system 1000 may exchange data with each other according to the bus format of the bus 1600. For example, the bus format may include one or more of various interface protocols such as Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Double Data Rate (DDR), and Low Power DDR (LPDDR).

[0033] The main processor 1100 may be used as a host device. The main processor 1100 may provide services to a user by communicating with each of the storage devices 1310, 1320, and 1330. For example, the main processor 1100 may store data in the storage devices 1310, 1320, and 1330 and may read data stored in the storage devices 1310, 1320, and 1330.

[0034] According to an embodiment, the main processor 1100 may offload work associated with data to be stored in the storage devices 1310, 1320, and 1330 to the storage devices 1310, 1320, and 1330. The storage devices 1310, 1320, and 1330 may perform work associated with the data to be stored therein instead of the main processor 1100. For example, the storage device 1310 may receive data as uncompressed data from the main processor 1100, and may compress the received data. That is, work associated with the data to be stored in the storage device 1310 may be performed within the storage device 1310 rather than within the main processor 1100. Therefore, the workload of the host device may be reduced.

[0035] Below, an exemplary configuration of the PCIe protocol and an embodiment associated with storage devices 1310, 1320, and 1330 will be described. However, various changes or modifications may be made to the various embodiments described in the present disclosure so that they are applied to any other interface protocol other than the PCIe protocol. In addition, the various embodiments described in the present disclosure may be applied to any electronic device (e.g., working memory 1200) capable of storing and outputting data and storage devices 1310, 1320, and 1330. The following description is provided for better understanding, but is not intended to limit the embodiments.

[0036] Figure 2 is a conceptual diagram for describing a general RAID scheme in which a host processor performs work associated with data to be stored in a storage system.

[0037] The main processor 2100 may include a RAID controller 2110. According to the RAID scheme, data may be managed in units of stripes. For better understanding, it is assumed that each of the data D0 and the different data to be described later has a size corresponding to one stripe. However, the embodiment is not limited to this assumption. In some embodiments, some data may have a size less than one stripe, or may have a size corresponding to multiple stripes.

[0038] A stripe may be divided into a plurality of data chunks. For example, the RAID controller 2110 may divide data D0 into data chunks D1 and D2. Figure 2 For example, in some embodiments, RAID parameters such as the data size corresponding to one stripe, the data size corresponding to one data block, the number of data blocks included in one stripe, etc. may be changed or modified according to various factors such as performance, reliability, and storage capacity.

[0039] The data blocks D1 and D2 may be converted into a format that can be stored in the storage system 2300. For example, the RAID controller 2110 may compress the data blocks D1 and D2 into data D1' and D2'. The size of the data D1' may be smaller than the size of the data block D1, and the size of the data D2' may be smaller than the size of the data block D2. For example, the sizes of the data blocks D1 and D2 may both be 128 KB, and the sizes of the data D1' and D2' may both be smaller than 128 KB.

[0040] The RAID controller 2110 may generate a parity bit P0 associated with the data D1' and the data D2' by using the data D1' and the data D2'. The RAID controller 2110 may perform various operations to generate the data D1', the data D2', and the parity bit P0 based on the data D0. In the event that a portion of the data D1' and the data D2' is lost or damaged, the parity bit P0 may be used to recover or restore the lost or damaged data.

[0041] The RAID controller 2110 may store data D1′, data D2′, and parity P0 in the storage devices 2310, 2320, and 2330. That is, data D1′, data D2′, and parity P0 may be stored in different storage devices 2310, 2320, and 2330, respectively, under the control of the RAID controller 2110.

[0042] Figure 3 is a conceptual diagram for describing a RAID scheme in which storage devices perform work associated with data to be stored in a storage system, according to some embodiments.

[0043] As reference Figure 1 As described, the main processor 1100 can provide services to the user by communicating with each of the storage devices 1310, 1320, and 1330. The main processor 1100 may include a RAID controller 1110. The RAID controller 1110 may divide the data D0 into data blocks D1 and D2. The size of each of the data blocks D1 and D2 may be smaller than the size of the data D0.

[0044] The RAID controller 1110 may output the data blocks D1 and D2 to different storage devices 1310 and 1320, respectively. In the following description, for ease of description, it is assumed that the data blocks D1 and D2 are output to the storage devices 1310 and 1320, respectively, but the embodiment is not limited thereto. For example, the data blocks D1 and D2 may be output to different storage devices among the storage devices 1310, 1320, and 1330.

[0045] That is, the RAID controller 1110 according to the embodiment can output the data blocks D1 and D2 to the storage devices 1310 and 1320 without performing a process of performing work associated with the data blocks D1 and D2. The RAID controller 1110 can request the work associated with the data blocks D1 and D2 from the storage devices 1310 and 1320 when the RAID controller 1110 outputs the data blocks D1 and D2 to the storage system 1300.

[0046] The storage system 1300 may include storage devices 1310, 1320, and 1330. Storage devices 1310 and 1320 among the storage devices 1310, 1320, and 1330 may receive data blocks D1 and D2. Storage devices 1310 and 1320 may perform work associated with data blocks D1 and D2 in response to a request of the RAID controller 1110. In the following description, for ease of description, it is assumed that the work associated with data blocks D1 and D2 is a compression work, but the embodiment is not limited thereto. The work associated with data blocks D1 and D2 may include compression, deduplication, checksum, encryption, etc.

[0047] The storage devices 1310 and 1320 may compress the data blocks D1 and D2 to generate data D1' and data D2', respectively. The size of the data D1' may be smaller than the size of the data block D1, and the size of the data D2' may be smaller than the size of the data block D2.

[0048] The storage devices 1310 and 1320 may respectively output information indicating the respective sizes of data D1' and data D2' to the RAID controller 1110. The RAID controller 1110 may specify the storage locations where data D1' and data D2' are respectively to be stored based on the respective size information of data D1' and data D2'. For example, in a case where one of the storage devices 1310, 1320, and 1330 is designated as the storage location where data D1' is to be stored, one of the remaining storage devices may be designated as the storage location where data D2' is to be stored. Furthermore, the remaining storage devices other than the storage device designated as the storage location for data D1' and data D2' may be designated as areas for generating and storing parity bits P0. Figure 3 , it is assumed that the storage device 1310 is designated as a storage location of data D1', the storage device 1320 is designated as a storage location of data D2', and the storage device 1330 is designated as a generation and storage location of the parity bit P0, but the embodiment is not limited thereto.

[0049] RAID controller 1110 may store size information of each of data D1' and data D2' and information of locations where data D1', data D2' and parity P0 are stored. RAID controller 1110 may search for data D1', data D2' and parity P0 in storage devices 1310, 1320 and 1330 based on the stored information.

[0050] The RAID controller 1110 may output a signal including information about the storage location of data D1', data D2', and parity P0. Storage devices 1310, 1320, and 1330 may store data D1', data D2', and parity P0 based on the signal received from the RAID controller 1110. Storage devices 1310 and 1320 may store data D1' and data D2' in the storage location of data D1' and data D2' based on the signal received from the RAID controller 1110. In addition, storage devices 1310 and 1320 may output data D1' and data D2' to the generation location of parity P0 based on the signal received from the RAID controller 1110. For example, storage devices 1310 and 1320 may output data D1' and data D2' to storage device 1330 as the generation location of parity P0. Storage device 1330 may generate parity P0 based on data D1' and data D2'. In addition, the storage device 1330 may store a parity bit P0.

[0051] According to an embodiment, in Figure 2The work performed in the universal RAID controller 2110 of the main processor 1100 can be performed in the storage devices 1310, 1320 and 1330. In detail, the storage devices 1310, 1320 and 1330 can perform work such as compression, deduplication, checksum, or encryption on the data D1' and the data D2', and can generate a parity bit P0. Therefore, the workload of the main processor 1100 can be reduced.

[0052] In addition, the storage devices 1310, 1320, and 1330 may transmit size information of the data D1' and the data D2' to the main processor 1100 instead of the data D1' and the data D2' themselves, thereby reducing the amount of information exchanged between the storage devices 1310, 1320, and 1330 and the main processor 1100. Therefore, the speed at which the storage devices 1310, 1320, and 1330 and the main processor 1100 communicate with each other may be increased.

[0053] Figure 4 It is shown Figure 3 A conceptual diagram of another embodiment of a RAID scheme for storing data and parity bits in a storage device.

[0054] Reference Figure 4 , describes the following case: data D1' and data D2' are generated at storage devices 1310 and 1320, respectively, and then stored in storage devices 1320 and 1330 and parity bit P0 is generated at storage device 1310. In this case, storage device 1310 may compress data block D1, and may provide data D1' as compressed data to storage device 1320. Storage device 1320 may store provided data D1'. Storage device 1320 may compress data block D2, and may provide data D2' as compressed data to storage device 1330. Storage device 1330 may store provided data D2'. In addition, storage device 1320 may provide data D2' to storage device 1310. Storage device 1310 may generate parity bit P0 based on data D1' and data D2'. Storage device 1310 may store the generated parity bit P0.

[0055] Figure 5 is a diagram showing some embodiments of the present invention. Figure 3 A block diagram of a storage device configuration of a RAID scheme.

[0056] The main processor 1100 may communicate with the storage devices 1310, 1320, and 1330. The storage devices 1310, 1320, and 1330 may perform work associated with the data blocks D1 and D2, which refer to Figure 3Described. In some embodiments, storage devices 1310, 1320, and 1330 may perform work associated with data blocks D1 and D2 in response to a request from the main processor 1100. In some embodiments, the request may be to output data blocks D1 and D2 from the main processor 1100 to the storage system 1300. In other embodiments, the request may be a request different from outputting data blocks D1 and D2. Storage devices 1310, 1320, and 1330 may perform peer-to-peer communication with each other. Storage devices 1310, 1320, and 1330 may store data D1' and data D2' in a specified location by performing peer-to-peer communication without transmitting data D1' and data D2' to the main processor 1100.

[0057] The configuration and operation of storage devices 1320 and 1330 are substantially the same as the configuration and operation of storage device 1310, and therefore, for the sake of brevity, reference will be made to the configuration and operation of storage device 1310. Figure 5 The configuration and operation of the storage device 1310 are mainly described.

[0058] The storage device 1310 may include a first memory 1311 , a computing circuit 1312 , a controller 1313 , and a second memory 1314 .

[0059] The first memory 1311 may store data to be used for the operation of the storage device 1310. The first memory 1311 may temporarily store intermediate results and final results of the operation of the storage device 1310. The first memory 1311 may be a volatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM). However, the embodiment is not limited thereto. For example, the first memory 1311 may be a non-volatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM).

[0060] The first memory 1311 may store the data block D1 received from the main processor 1100 and the data D1' as a result of compressing the data block D1. In detail, the first memory 1311 may temporarily store the data D1' until the main processor 1100 specifies the storage location of the data D1'. In the case where the parity bit is calculated at the storage device 1310, the first memory 1311 may store the intermediate result and the final result generated and processed when the parity bit is calculated.

[0061] The calculation circuit 1312 may include an operation logic 1312_1 and a parity bit generator 1312_2. The calculation circuit 1312 may respond to a request for storing a data block D1 received from the main processor 1100 by using the operation logic 1312_1. In response to the request of the main processor 1100, the operation logic 1312_1 may perform work on the data block D1 to generate data D1'. For example, the operation logic 1312_1 may compress the data block D1 to generate data D1'.

[0062] In the case where the parity bits are calculated by the storage device 1310 , the calculation circuit 1312 may generate the parity bits by using the parity bit generator 1312_2 . The parity bit generator 1312_2 may generate the parity bit P0 based on a signal received from the main processor 1100 .

[0063] The controller 1313 may include interfaces 1313_1 and 1313_2. The interfaces 1313_1 and 1313_2 may each include a physical layer and / or a logical layer configured to transmit / receive and process data, signals and / or data packets to allow the controller 1313 to communicate with components that exist outside the controller 1313. The interfaces 1313_1 and 1313_2 may each include a hardware circuit configured to process communications between the controller 1313 and external components.

[0064] The controller 1313 may communicate with the main processor 1100 by using the interface 1313_1. By using the interface 1313_1, the controller 1313 may receive the data block D1 from the main processor 1100, and may transmit size information of the data D1′ to the main processor 1100. In addition, by using the interface 1313_1, the controller 1313 may receive information about a storage location where the data D1′ is to be stored from the main processor 1100.

[0065] The controller 1313 may perform peer-to-peer communication with different storage devices 1320 and 1330 by using the interface 1313_2. By using the interface 1313_2, the controller 1313 may receive data and signals from different storage devices 1320 and 1330, and may transmit data and signals to different storage devices 1320 and 1330. For example, the controller 1313 may output data D1' to a storage location designated by the main processor 1100 by using the interface 1313_2.

[0066] The second memory 1314 may store data D1', data D2', or parity bit P0 according to the storage location indicated by the main processor 1100. In detail, in the case where the main processor 1100 specifies the storage location of the data D1' as the storage device 1310, the second memory 1314 may store the data D1'. In the case where a read request is received from the main processor 1100, the storage device 1310 may read the data D1' from the second memory 1314. The second memory 1314 may be a nonvolatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM).

[0067] Figures 6 to 11 is used to describe the Figure 3 A block diagram of exemplary operations associated with a RAID scheme for a storage device. Figures 6 to 11 The exemplary operation of shows a process in which the storage devices 1310 , 1320 , and 1330 perform work associated with the data blocks D1 and D2 and store the data D1 ′ and D2 ′ through peer communication without a process of transferring the data D1 ′ and D2 ′ to the main processor 1100 .

[0068] Reference Figure 6 , the main processor 1100 may output data blocks D1 and D2 to storage devices 1310 and 1320. The storage devices 1310 and 1320 may receive data blocks D1 and D2 through interfaces 1313_1 and 1323_1, respectively. The first memories 1311 and 1321 may store data blocks D1 and D2, respectively. In the following description, it is assumed that data blocks D1 and D2 are transmitted to storage devices 1310 and 1320, respectively, but the embodiment is not limited thereto. Data blocks D1 and D2 may be transmitted to two different storage devices among the storage devices 1310, 1320, and 1330, respectively.

[0069] Reference Figure 7, the operation logic 1312_1 and 1322_1 can receive data blocks D1 and D2 from the first memory 1311 and 1321, respectively. The operation logic 1312_1 and 1322_1 can perform the work requested from the main processor 1100 and associated with the data blocks D1 and D2. In the following description, it is assumed that the work requested from the main processor 1100 is compression, but the embodiment is not limited to this. In some embodiments, the work requested from the main processor 1100 can be a work performed on the data blocks D1 and D2 in order to generate data D1', data D2' and parity bit P0 to be stored in the storage devices 1310, 1320 and 1330, such as compression, deduplication, checksum, or encryption. The operation logic 1312_1 and 1322_1 can compress the data blocks D1 and D2 to generate data D1' and data D2', respectively.

[0070] Reference Figure 8 , the first memories 1311 and 1321 may include data D1' and data D2'. The operation logics 1312_1 and 1322_1 may generate signals ds0 and ds1 based on the data D1' and data D2' stored in the first memories 1311 and 1321, respectively. The signals ds0 and ds1 may include size information of the data D1' and data D2', respectively. The storage devices 1310 and 1320 may output the signals ds0 and ds1 to the main processor 1100 through the interfaces 1313_1 and 1323_1, respectively.

[0071] Reference Fig. 9 , the main processor 1100 may determine the location where data D1', data D2', and parity bit P0 are to be stored based on the signals ds0 and ds1. In detail, the main processor 1100 may determine the location where data D1', data D2', and parity bit P0 are to be stored based on the size information of data D1' and data D2'. The main processor 1100 may generate signals rs0, rs1, and rs2. The signals rs0, rs1, and rs2 may indicate the storage locations where data D1', data D2', and parity bit P0 are to be stored, respectively.

[0072] The storage devices 1310, 1320, and 1330 may receive signals rs0, rs1, and rs2 through interfaces 1313_1, 1323_1, and 1333_1, respectively. The storage devices 1310 and 1320 may transmit data D1' and data D2' stored in the first memories 1311 and 1321 to different storage devices based on signals rs0 and rs1, respectively. In detail, the storage devices 1310 and 1320 may transmit data D1' and data D2' to the storage devices indicated by signals rs0 and rs1, respectively. The storage devices 1310 and 1320 may transmit data D1' and data D2' to the storage locations of data D1' and data D2' and the generation location of the parity bit P0, respectively.

[0073] As reference Figure 3 As described, in some embodiments, storage device 1310 may be designated as a storage location for data D1', storage device 1320 may be designated as a storage location for data D2', and storage device 1330 may be designated as a generation and storage location for parity bit P0. In this case, storage devices 1310 and 1320 may output data D1' and data D2' to storage device 1330 through interfaces 1313_2 and 1323_2, respectively, and storage device 1330 may receive data D1' and data D2' through interface 1333_2.

[0074] In some embodiments, the storage devices 1310 and 1320 may output data D1' and data D2' to the storage locations of data D1' and data D2' indicated by signals rs0 and rs1, respectively. In some embodiments, the storage devices 1310 and 1320 may output data D1' and data D2' to the storage location of parity bit P0 indicated by signal rs2. Figure 4 As described, in some embodiments, storage devices 1320 and 1330 may be designated as storage locations for data D1' and data D2', respectively, and storage device 1310 may be designated as a generation and storage location for parity bit P0. In this case, storage device 1310 may output data D1' to storage device 1320. Storage device 1320 may output data D2' to storage device 1330. In addition, in detail, storage device 1320 may output data D2' to storage device 1310.

[0075] Reference Fig.10 , the parity generator 1332_2 may perform parity calculation based on the data D1' and the data D2'. The parity generator 1332_2 may generate a parity bit P0 by performing the parity calculation.

[0076] Reference Fig.11, the storage devices 1310, 1320, and 1330 may store data D1', data D2', and parity P0 in the second memories 1314, 1324, and 1334, respectively. The main processor 1100 may retain address information indicating the locations where the data D1', data D2', and parity P0 are stored. The main processor 1100 may read or search for data D1' or data D2' based on the address information.

[0077] Fig.12 According to some embodiments, Figure 3 A flow chart of the operation of the host processor and storage system of the RAID scheme.

[0078] In operation S110 , the main processor 1100 may output the data blocks D1 and D2 to the memory system 1300 .

[0079] In operation S115 , the memory system 1300 may store the data blocks D1 and D2 received from the main processor 1100 in the first memories 1311 and 1321 , respectively.

[0080] In operation S120, the storage system 1300 may perform work associated with the data blocks D1 and D2. In some embodiments, the storage system 1300 may perform work associated with the data blocks D1 and D2 in response to a request from the main processor 1100. In some embodiments, the request may be the output data blocks D1, D2 in operation S110. In other embodiments, the request may be a request different from the output data blocks D1 and D2. The storage system 1300 may perform work associated with the data blocks D1 and D2 to generate data D1' and data D2'.

[0081] In operation S125, the memory system 1300 may generate signals ds0 and ds1 based on the data D1' and the data D2', respectively. The signals ds0 and ds1 may include information about the sizes of the data D1' and the data D2', respectively.

[0082] In operation S130 , the memory system 1300 may output signals ds0 and ds1 to the main processor 1100 .

[0083] In operation S135 , the main processor 1100 may determine storage locations of data D1 ′ and data D2 ′ and a generation location of the parity bit P0 based on the signals ds0 and ds1 .

[0084] In operation S140, the main processor 1100 may generate signals rs0, rs1, and rs2. The signals rs0, rs1, and rs2 may include information about storage locations of data D1' and data D2' and information about a generation location of the parity bit P0, respectively.

[0085] In operation S145 , the main processor 1100 may output signals rs0 , rs1 , and rs2 to the memory system 1300 .

[0086] In operation S150 , the memory system 1300 may internally transmit data D1 ′ and data D2 ′ to a storage location of the data D1 ′ and data D2 ′ and a generation location of the parity bit P0 through peer communication based on signals rs0 , rs1 , and rs2 .

[0087] In operation S160 , the memory system 1300 may generate a parity P0 based on the data D1 ′ and the data D2 ′.

[0088] In operation S170 , the memory system 1300 may store data D1 ′, data D2 ′, and parity P0 in the second memories 1314 , 1324 , and 1334 , respectively.

[0089] Fig.13 is a conceptual diagram for describing a RAID scheme according to another embodiment, in which a storage device performs work associated with data to be stored in a storage system. The main processor 3100 and the storage system 3300 may correspond to Figure 1 The main processor 1100 and the storage system 1300 are provided.

[0090] The main processor 3100 may include a RAID controller 3110. According to the RAID scheme, data may be managed in stripes. For better understanding, it is assumed that data D10 and different data to be described later each have a size corresponding to one stripe. However, the embodiment is not limited to this assumption. In some embodiments, some data may have a size smaller than one stripe, or may have a size corresponding to multiple stripes.

[0091] A stripe can be divided into multiple data blocks. For example, the RAID controller 3110 can divide the data D10 into data blocks D11 and D12. The size of the data blocks D11 and D12 can be greater than Figure 3 For example, when the sizes of data blocks D1 and D2 are both 128KB, the sizes of data blocks D11 and D12 can be integer multiples of 128KB. The sizes of data blocks D11 and D12 can be large enough to make the sizes of data D11' and data D12' both integer multiples of 128KB.

[0092] The RAID controller 3110 may adjust the sizes of the data blocks D11 and D12 based on the type of the storage system 3300 or the situation of the storage system 3300. For example, in the case where the storage space of the storage system 3300 is insufficient, the RAID controller 3110 may divide the data D10 into relatively small-sized data blocks D11 and D12. For another example, in the case where the compression rate in the storage system 3300 is high, the RAID controller 3110 may divide the data D10 into relatively large-sized data blocks D11 and D12. The high compression rate in the storage system 3300 means that the ratio of the size of the data D11' to the size of the data block D11 is low. In the case where the storage space of the storage system 3300 is sufficient, the RAID controller 3110 may divide the data D10 into relatively large-sized data blocks D11 and D12. In the case where the compression rate in the storage system 3300 is low, the RAID controller 3110 may divide the data D10 into relatively small-sized data blocks D11 and D12. A low compression ratio in the storage system 3300 means that the ratio of the size of the data D11 ′ to the size of the data block D11 is high.

[0093] The RAID controller 3110 may calculate parity based on the data blocks D11 and D12. The RAID controller 3110 may generate a parity block P10 based on the data blocks D11 and D12. The size of the parity block P10 may be equal to the size of each of the data blocks D11 and D12.

[0094] The RAID controller 3110 may output the data blocks D11 and D12 and the parity block P10 to the storage devices 3310, 3320, and 3330. Figures 13 to 18 , it is assumed that the data blocks D11 and D12 and the parity block P10 are output to the storage devices 3310 , 3320 , and 3330 , respectively, but the embodiment is not limited thereto.

[0095] The storage devices 3310, 3320, and 3330 may perform work associated with the data blocks D11 and D12 and the parity block P10. In some embodiments, the storage system 3300 may perform work associated with the data blocks D11 and D12 and the parity block P10 in response to a request from the main processor 3100. In some embodiments, the request may be to output the data blocks D11 and D12 and the parity block P10 to the storage system 3300. In other embodiments, the request may be a request different from outputting the data blocks D11 and D12 and the parity block P10. For example, the work associated with the data blocks D11 and D12 and the parity block P10 may be one of compression, deduplication, checksum, encryption, and the like. The storage devices 3310 , 3320 , and 3330 may respectively perform work associated with the data blocks D11 and D12 and the parity block P10 to generate data D11 ′, data D12 ′, and parity P10 ′.

[0096] The memories in the storage devices 3310, 3320, and 3330 may store data D11', data D12', and parity P10' in a minimum size unit. The size of each of data D11', data D12', and parity P10' may be an integer multiple of the minimum size unit.

[0097] In the case where the size of the data is smaller than the minimum size unit, the storage device may increase the size of the data to the minimum size unit by padding the data with meaningless values ​​such as "0" or "1" for storing the data in the memory. In this case, the storage area of ​​the storage device is wasted. Alternatively, the main processor may store all information about the irregular size of the data. In this case, the storage area of ​​the main processor is wasted, and the process of searching for data in the storage device becomes complicated.

[0098] In contrast, the main processor 3100 according to the embodiment can generate data blocks D11 and D12 and parity block P10 that are large enough so that the size of each of data D11', data D12' and parity P10' is an integer multiple of the minimum size unit. Therefore, the storage area of ​​the storage device can be saved. In addition, the storage area of ​​the main processor 3100 can be saved, and the process of searching for data in the storage device can be simplified.

[0099] Fig.14 is a diagram showing some embodiments of the present invention. Fig.13 A block diagram of a storage device configuration of a RAID scheme.

[0100] The main processor 3100 may communicate with the storage devices 3310, 3320, and 3330. The storage devices 3310, 3320, and 3330 may perform work associated with the data blocks D11 and D12 by communicating with the main processor 3100. Fig.13 The storage devices 3310, 3320 and 3330 can be stored in memory without Fig.13 The data D11 ′ and the data D12 ′ are transmitted to the main processor 3100 in the case where the process stores the data D11 ′ and the data D12 ′.

[0101] The configuration and operation of storage devices 3320 and 3330 are substantially the same as the configuration and operation of storage device 3310, and therefore, for the sake of brevity, reference will be made to the configuration and operation of storage device 3310. Fig.14 The configuration and operation of the storage device 3310 are mainly described.

[0102] The storage device 3310 may include a first memory 3311, a computing circuit 3312, a controller 3313, a second memory 3314, and an internal bus (not shown). The components 3311, 3312, 3313, and 3314 in the storage device 3310 may exchange data and signals through the internal bus.

[0103] The first memory 3311 may store data to be used for the operation of the storage device 3310. The first memory 3311 may temporarily store intermediate results and final results of the operation of the storage device 3310. The first memory 3311 may store a data block D11 received from the main processor 3100. The first memory 3311 may be a volatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM). However, the embodiment is not limited thereto. For example, the first memory 3311 may be a non-volatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM).

[0104] The computing circuit 3312 may include an operation logic 3312_1. The computing circuit 3312 may respond to a request for storing the data block D11 received from the main processor 3100 by using the operation logic 3312_1. In response to the request of the main processor 3100, the operation logic 3312_1 may perform work on the data block D11 to generate data D11'. For example, the operation logic 3312_1 may compress the data block D11 to generate data D11'.

[0105] The controller 3313 may include an interface 3313_1. The interface 3313_1 may include a physical layer and / or a logical layer configured to transmit / receive and process data, signals and / or data packets to allow the controller 3313 to communicate with components existing outside the controller 3313. The interface 3313_1 may include a hardware circuit configured to handle communication between the controller 3313 and external components.

[0106] The controller 3313 may communicate with the main processor 3100 by using the interface 3313_1. By using the interface 3313_1, the controller 3313 may receive the data block D11 from the main processor 3100, and may transmit the size information of the data D11' to the main processor 3100. Subsequently, the main processor 3100 may request the storage device 3310 to read the data D11' based on the size information of the data D11'.

[0107] The second memory 3314 may store data D11'. In the case of receiving a read request from the main processor 3100, the storage device 3310 may read data D11' from the second memory 3314. The second memory 3314 may be a nonvolatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM).

[0108] Figures 15 to 17 is used to describe the Fig.13 A block diagram of exemplary operations associated with a RAID scheme for a storage device. Figures 15 to 17 The exemplary operation shows that the storage devices 3310, 3320 and 3330 perform work associated with the data blocks D11 and D12 and the parity block P10, and store the data D11', data D12' and parity P10' without transmitting the data D11' and data D12' to the main processor 3100.

[0109] Reference Fig.15 , the main processor 3100 may output the data blocks D11 and D12 and the parity block P10 to the storage devices 3310, 3320, and 3330, respectively. The storage devices 3310, 3320, and 3330 may receive the data blocks D11 and D12 and the parity block P10 through the interfaces 3313_1, 3323_1, and 3333_1, respectively. The first memories 3311, 3321, and 3331 may store the data blocks D11 and D12 and the parity block P10, respectively. In the following description, it is assumed that the data blocks D11 and D12 and the parity block P10 are transmitted to the storage devices 3310, 3320, and 3330, respectively, but the embodiment is not limited thereto.

[0110] Reference Fig.16 , the operation logic 3312_1, 3322_1 and 3332_1 can receive data blocks D11 and D12 and parity block P10 from the first memory 3311, 3321 and 3331, respectively. The operation logic 3312_1, 3322_1 and 3332_1 can perform the work associated with the data blocks D11 and D12 and the parity block P10 requested from the main processor 3100. In the following description, it is assumed that the work requested from the main processor 3100 is compression, but the embodiment is not limited thereto. The work requested from the main processor 3100 can be a work performed on the data blocks D11 and D12 and the parity block P10 in order to generate data D11', data D12' and parity P10' to be stored in the storage devices 3310, 3320 and 3330, such as compression, deduplication, checksum, or encryption. The operation logics 3312_1 , 3322_1 , and 3332_1 may compress the data blocks D11 and D12 and the parity block P10 , respectively, to generate data D11 ′, data D12 ′, and parity P10 ′.

[0111] Reference Fig.17 , the operation logic 3312_1, 3322_1 and 3332_1 can generate signals ds10, ds11 and ds12 based on the data D11', the data D12' and the parity bit P10', respectively. The signals ds10, ds11 and ds12 can respectively indicate the size of the data D11', the data D12' and the parity bit P10'. The storage devices 3310, 3320 and 3330 can output the signals ds10, ds11 and ds12 to the main processor 3100 through the interfaces 3313_1, 3323_1 and 3333_1, respectively.

[0112] The main processor 3100 may receive the signals ds10, ds11, and ds12. The main processor 3100 may store information about the size of the data D11', the data D12', and the parity bit P10' based on the signals ds10, ds11, and ds12. Subsequently, the main processor 3100 may read or search for the data D11' or the data D12' based on the information about the size of the data D11', the data D12', and the parity bit P10'.

[0113] Fig.18 According to some embodiments, Fig.13 A flow chart of the operation of the host processor and storage system of the RAID scheme.

[0114] In operation S210 , the main processor 3100 may output the data blocks D11 and D12 and the parity block P10 to the memory system 3300 .

[0115] In operation S220 , the memory system 3300 may store the data blocks D11 and D12 and the parity block P10 received from the main processor 3100 in the first memories 3311 , 3321 , and 3331 , respectively.

[0116] In operation S230, the storage system 3300 may perform work associated with the data blocks D11 and D12 and the parity block P10 in response to a request of the main processor 3100. In some embodiments, the storage system 3300 may perform work associated with the data blocks D11 and D12 and the parity block P10 in response to a request of the main processor 3100. In some embodiments, the request may be to output the data blocks D11 and D12 and the parity block P10 to the storage system 3300 in operation S210. In other embodiments, the request may be a request different from outputting the data blocks D11 and D12 and the parity block P10. The storage system 3300 may perform work associated with the data blocks D11 and D12 and the parity block P10 to generate data D11', data D12', and parity P10', respectively.

[0117] In operation S240 , the memory system 3300 may store data D11 ′, data D12 ′, and parity P10 ′ in the second memories 3314 , 3324 , and 3334 , respectively.

[0118] In operation S250, the memory system 3300 may generate signals ds10, ds11, and ds12 based on data D11', data D12', and parity P10', respectively. The signals ds10, ds11, and ds12 may indicate sizes of data D11', data D12', and parity P10', respectively.

[0119] In operation S260, the memory system 3300 may output the signals ds10, ds11, and ds12 to the main processor 3100. Subsequently, the main processor 3100 may read or search for data D11' or data D12' based on the signals ds10, ds11, and ds12.

[0120] According to various embodiments, work associated with data to be stored in a storage device may be performed within the storage device rather than within the host device, thereby reducing the workload of the host device.

[0121] In addition, since the storage device can perform peer-to-peer communication with different storage devices, the storage device can transmit processed data to different storage devices without the need to transmit the processed data to the host device. Therefore, the amount of information exchanged between the host device and the storage device and / or the number of communications between the host device and the storage device can be reduced.

[0122] While various exemplary embodiments have been described, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A storage device, comprising: a first interface configured to receive a first data block from a host device; an operation circuit configured to generate first processed data by processing the first data block, and generate a first signal indicating a size of the first processed data; and a nonvolatile memory configured to: store the first processed data in a storage location where the first processed data is to be stored when the storage location is designated to the storage device by the host device based on the first signal; Wherein, the first interface is configured to output the first signal to the host device.

2. The storage device according to claim 1, wherein: The first interface receives a second signal from the host device, Wherein, the storage device further includes a second interface, When the second signal indicates that another storage device outside the storage device is used as the storage location, the second interface outputs the first processed data to the other storage device, and Wherein, the storage location is determined based on the first signal.

3. The storage device according to claim 1, wherein: The processing may include compression, deduplication, checksumming, or encryption.

4. The storage device according to claim 2, wherein: The second signal indicates a generation position where a parity bit is to be generated; wherein, when the storage device is designated as the generation location, the second interface is configured to receive second processing data from the other storage device outside the storage device; and The storage device further includes a parity generator configured to generate the parity bits for restoring the first processed data and the second processed data based on the first processed data and the second processed data.

5. The storage device according to claim 4, wherein: When the parity bit is generated by the parity bit generator, the nonvolatile memory stores the parity bit.

6. The storage device according to claim 2, wherein: The second signal indicates a generation position at which a parity bit is to be generated, and Wherein, when the other storage device outside the storage device is designated as the generation location, the second interface outputs the first processed data to the other storage device.

7. The storage device according to claim 1, further comprising: A volatile memory is configured to store the first data block.

8. A storage system comprising: a first storage device, the first storage device being configured to: receive a first data block from a host device, convert the first data block into first data, and output a first signal indicating a size of the first data to the host device; and a second storage device configured to receive a second signal from the host device after the first signal is output; When the second signal indicates that the second storage device is used as a generation location for generating parity bits for recovering the first data, the second storage device is configured to receive the first data from the first storage device and generate the parity bits based on the first data.

9. The storage system according to claim 8, wherein: The second storage device comprises: a first interface configured to receive the second signal from the host device; and A second interface is configured to receive the first data from the first storage device.

10. The storage system according to claim 8, wherein: The second storage device comprises: a first memory configured to store the first data; and A second memory is configured to store the parity bit.

11. The storage system according to claim 10, wherein: The first memory is a volatile memory, and Wherein, the second memory is a non-volatile memory.

12. The storage system according to claim 8, further comprising: a third storage device configured to receive a second data block from the host device, convert the second data block into second data, and output a third signal indicating a size of the second data to the host device, When receiving the second signal, the second storage device receives the second data from the third storage device and generates the parity bit based on the first data and the second data.

13. The storage system according to claim 8, wherein: The first storage device includes a nonvolatile memory, and the first storage device receives a third signal from the host device after outputting the first signal, and When the third signal indicates that the first storage device is used as a storage location to store the first data, the first storage device stores the first data in the non-volatile memory.

14. The storage system according to claim 8, wherein: The second storage device includes a non-volatile memory, and When the second signal indicates that the second storage device is used as a storage location for storing the first data, the second storage device receives the first data from the first storage device and stores the first data in the non-volatile memory.

15. The storage system according to claim 8, wherein: The second signal is a signal generated based on the first signal.

16. A storage system comprising: a first storage device, the first storage device being configured to receive a first data block from a host device, generate first processed data by processing the first data block, generate a signal indicating a size of the first processed data, and output the signal to the host device; and a second storage device, the second storage device being configured to receive a first parity bit block for recovering the first data block, and to generate first processed parity bit data by processing the first parity bit block, The first storage device includes a first memory configured to store the first processed data in a first size unit, and The size of the first processed data is an integer multiple of the first size unit.

17. The storage system according to claim 16, wherein: The first storage device also includes a second memory configured to store the first data block.

18. The storage system according to claim 17, wherein: The first memory is a non-volatile memory, and Wherein, the second memory is a volatile memory.

19. The storage system according to claim 16, wherein: The size of the first data block is inversely proportional to a first ratio, which is a ratio of the size of the first processed data to the size of the first data block.

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