Method for forming a semiconductor element

Abstract

A semiconductor device and method of forming the same includes forming a dielectric material, wet oxidizing the dielectric material, and dry annealing the dielectric material. The dielectric material can be a flowable material. The wet oxidizing can include an acid and oxidizer mixture.

Description

Technical Field

[0001] This disclosure relates to methods for forming semiconductor devices, and more particularly to the formation of dielectric materials. Background Technology

[0002] Semiconductor components are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication of semiconductor components typically involves successively depositing insulating or dielectric films, conductive layers, and semiconductor layers onto a semiconductor substrate, and using photolithography to pattern various material films to form circuit components and components thereon.

[0003] The semiconductor industry has been continuously improving the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. Summary of the Invention

[0004] A method for forming a semiconductor device includes: forming a flowable dielectric material; performing a wet oxidation treatment on the flowable dielectric material, the wet oxidation treatment including coating the flowable dielectric material with a mixture of acid and oxidant; and performing dry annealing on the flowable dielectric material to cure the flowable dielectric material.

[0005] A method for forming a semiconductor device includes: depositing a fluid dielectric material on a substrate; and performing a first cycle of a conversion process to convert the fluid dielectric material into an oxide, the conversion process including: applying an acid mixture to the fluid dielectric material; and dry annealing the fluid dielectric material with a water volume percentage of less than 10%.

[0006] A method for forming a semiconductor device includes: depositing a first dielectric material between a first fin and a second fin; ozone curing the first dielectric material; ultraviolet curing the first dielectric material; performing at least one cycle of a conversion process to convert the first dielectric material into an oxide, the conversion process including: applying a sulfuric acid-hydrogen peroxide mixture to the first dielectric material; dry annealing the first dielectric material; planarizing and removing excess portions of the oxide on the first and second fins; and etching the oxide to form shallow trench isolation regions between the first and second fins. Attached Figure Description

[0007] The various aspects of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this disclosure.

[0008] Figure 1This is an example of a three-dimensional schematic diagram of a fin field-effect transistor (FinFET) based on some embodiments.

[0009] Figures 2-8 This is a cross-sectional schematic diagram of an intermediate stage in the manufacturing of a fin field-effect transistor, according to some embodiments.

[0010] Figures 9-11 The physical properties of the film are illustrated according to some embodiments.

[0011] Figure 12 , Figure 13 , Figure 14 , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 23A , Figure 23B This is a cross-sectional schematic diagram of an intermediate stage in the manufacturing of a fin field-effect transistor, according to some embodiments.

[0012] Figure 24 The flowchart illustrates a method for manufacturing a fin field-effect transistor, based on some embodiments.

[0013] The reference numerals in the attached figures are explained as follows:

[0014] 50: Base

[0015] 50N: N-type region

[0016] 50P: P-type area

[0017] 51: Divider

[0018] 52: Fins

[0019] 54: Insulation materials

[0020] 56: (Shallow trench) isolation zone

[0021] 58: Passage Area

[0022] 60: Virtual dielectric layer

[0023] 62: Dummy gate layer

[0024] 64: Masking layer

[0025] 72: Dummy Gate

[0026] 74: Mask

[0027] 76: Gate tail dielectric

[0028] 80: Gate sealing spacer

[0029] 82: Source / Drain Region

[0030] 86: Gate spacer

[0031] 87: Contact Etching Stop Layer

[0032] 88: First interlayer dielectric

[0033] 89: Region

[0034] 90: Groove

[0035] 92: Gate dielectric layer

[0036] 94: Gate electrode

[0037] 94A: Liner

[0038] 94B: Work Function Adjustment Layer

[0039] 94C: Filler material

[0040] 96: Gate mask

[0041] 108: Interlayer dielectric

[0042] 110: Gate contact

[0043] 112: Source / Drain Contact

[0044] 154: Dielectric Materials

[0045] 200: First Curing

[0046] 254: Oxide Dielectric Materials

[0047] 300: Second Curing

[0048] 400: Wet oxidation treatment

[0049] 500: Dry annealing

[0050] 1100: Flowchart

[0051] 1102: First Step

[0052] 1104: Second Step

[0053] 1106: Third step

[0054] 1108: Fourth Step

[0055] 1110: Fifth Step

[0056] 1112: Sixth Step

[0057] 1114: Seventh Step

[0058] AA: Section

[0059] BB: Cross-section

[0060] CC: Section Detailed Implementation

[0061] The following disclosure provides numerous different embodiments or examples for implementing various components of the embodiments of this disclosure. Specific examples of components and configurations are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to limit the embodiments of this disclosure. For example, references to a first component being formed on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplification and clarity and does not in itself govern the relationship between the various embodiments and / or configurations discussed.

[0062] Furthermore, spatially related terms such as “below,” “under,” “lower,” “above,” “above,” and similar terms may be used here to describe the relationship between one element or component and other elements or components as shown in the figure. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations shown in the figures. When the device is rotated to other orientations (rotated 90° or other orientations), the spatial relative descriptions used herein can also be interpreted according to the orientation after rotation.

[0063] The embodiments described herein include methods for forming insulating materials such as oxide layers, and the resulting structures. Generally, the embodiments include processes for forming oxides, including depositing oxides, curing the oxides using, for example, an oxygen environment and / or ultraviolet curing process, performing wet oxidation, and performing dry (vapor-free) annealing. In some embodiments, a flowable chemical vapor deposition (FCVD) process can be used to form the oxides. In some embodiments, the processes described herein may present fewer problems, such as oxide definition (OD) region consumption, silicon and / or silicon-germanium fin oxidation, and metal gate threshold voltage (V). t ) offset, and / or other similar conditions.

[0064] Figure 1 This is an example illustrating a three-dimensional schematic diagram of a fin field-effect transistor (FinFET) according to some embodiments. The fin FET includes fins 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fins 52 protrude from adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated as separate from the substrate 50, the term "substrate" as used herein may be used to refer to a semiconductor substrate consisting only of semiconductor substrates or a semiconductor substrate including the isolation regions. Additionally, although the fins 52 are illustrated as a single continuous material like the substrate 50, the fins 52 and / or the substrate 50 may comprise a single material or a plurality of materials. In this document, fins 52 refer to portions extending between adjacent isolation regions 56.

[0065] The gate dielectric layer 92 is along the sidewalls and top surface of the fin 52, while the gate electrode 94 is above the gate dielectric layer 92. Source / drain regions 82 are disposed on both sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Schematic cross-sectional views for use in subsequent figures are also shown. Section AA is along the longitudinal axis of the gate electrode 94 and, for example, perpendicular to the current flow direction between the source / drain regions 82 of the fin field-effect transistor. Section BB is perpendicular to section AA and along the longitudinal axis of the fin 52, for example, between the source / drain regions 82 of the fin field-effect transistor. Section CC is parallel to section AA and extends through the source / drain regions of the fin field-effect transistor. These reference cross-sections will be referenced in subsequent figures for clarity.

[0066] Some embodiments described herein are discussed in the context of fin field-effect transistors formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments are also contemplated for use with planar devices (such as planar field-effect transistors), nanostructure field-effect transistors (NSFETs) (such as nanosheets, nanowires, gate-all-around (GAA), or other similar structures), or other similar devices.

[0067] Figures 2 to 8 and Figures 12 to 23B This is a cross-sectional schematic diagram of an intermediate stage in the fabrication of a fin field-effect transistor, according to some embodiments. Figures 2 to 8 and Figures 12 to 14 Draw Figure 1 The reference cross-section AA is shown, but the difference lies in depicting multiple finned / fin-type field-effect transistors. Along... Figure 1 The reference section AA shown is illustrated. Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A ,and Figure 23A And along similar Figure 1 The cross section BB shown is illustrated. Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 21C , Figure 22B ,and Figure 23B However, the difference lies in the depiction of multiple finned / fin-type field-effect transistors. Along... Figure 1 The reference section CC shown is plotted. Figure 17C and Figure 17D However, the difference lies in the fact that multiple finned / finned field-effect transistors are shown.

[0068] exist Figure 2In this configuration, a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or other similar materials, which can be doped (e.g., with P-type or N-type dopants) or undoped. The semiconductor substrate 50 can be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a semiconductor material film formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or other similar materials. The insulating layer provided on the substrate is typically a silicon or glass substrate. Other substrates (such as multilayer or gradient substrates) can also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or combinations thereof.

[0069] The substrate 50 has an N-type region 50N and a P-type region 50P. The N-type region 50N can be used to form N-type devices, such as N-type metal-oxide-semiconductor (NMOS) transistors, for example, N-type FinFETs. The P-type region 50P can be used to form P-type devices, such as P-type metal-oxide-semiconductor (PMOS) transistors, for example, P-type FinFETs. The N-type region 50N can be physically separated from the P-type region 50P (e.g., by means of the separator 51 shown), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the N-type region 50N and the P-type region 50P.

[0070] exist Figure 3 In this process, fins 52 are formed in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be formed in the substrate 50 by etching trenches. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), other similar methods, or combinations thereof. The etching can be anisotropic.

[0071] Fins can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fins. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the created patterns to have, for example, smaller pitches than those obtained using a single or direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins. In some embodiments, a mask (or other film layer) may be retained on the fin 52.

[0072] exist Figure 4 In this process, a dielectric material 154 is formed on the fin 52 and the substrate 50. The dielectric material 154 may be a flowable dielectric material that can flow during the deposition process to fill voids between gaps. In a particular embodiment, the dielectric material is a flowable material, such as perhydro-polysilazane (PSZ), silicon oxide formed from tetraethyl orthosilicate (TES), or silyl-amine, such as trisilylamine (TSA), combinations thereof, or similar materials. However, any suitable material may be used to help fill gaps and avoid creating voids.

[0073] High-density plasma chemical vapor deposition (HDP-CVD), flow-through chemical vapor deposition, combinations thereof, or other similar methods can be used to form dielectric material 154, wherein a precursor material is introduced onto the surface of the structure and reacts with each other to deposit the desired material (such as perhydropolysiloxane). Additionally, in some embodiments, various chemicals may be added to the precursor to allow the deposited material (such as perhydropolysiloxane) to flow once deposited.

[0074] For example, in one particular embodiment, the desired dielectric material 154 is a perhydropolysiloxane, and a combination of a precursor and a diluent can be introduced to deposit the dielectric material 154. The first precursor introduced may be a silicon-containing precursor, such as trisilylamine.

[0075] A second precursor may also be introduced to react with trisilylamine. In some embodiments, the choice of the second precursor may help to add additional nitrogen hydride bonds to the dielectric material to facilitate the flow of the deposited material. For example, in embodiments where the first precursor is trisilylamine, the second precursor may be a nitrogen-containing precursor, such as ammonia (NH3). However, any suitable second precursor may be used.

[0076] Additionally, several other chemicals can be introduced to aid the process without directly reacting. For example, diluents, carrier gases, or other similar substances (such as argon) can be used to help move or dilute the first or second precursor, but they will not directly participate in the chemical reactions of the deposition process.

[0077] Although the dielectric material 154 is depicted as a single film layer, some embodiments may utilize multiple film layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 50 and the fin 52. Subsequently, the dielectric material 154 is deposited on the liner as a filler material.

[0078] By utilizing a fluid dielectric material (such as perhydropolysiloxane) as the dielectric material 154, the dielectric material 154 will settle or "flow" after deposition. In this way, any gaps or voids formed during deposition, particularly those formed between the fins 52, will be filled. This results in a more complete filling of the area between the fins 52.

[0079] exist Figure 5 In this process, the dielectric material 154 may undergo an optional first curing 200. In one embodiment, the first curing 200 may be, for example, ozone (O3) curing, which can improve the properties of the dielectric material 154 by introducing additional oxygen into the dielectric material 154. The first curing 200 may be performed at a temperature of about 300°C to 1000°C, at a flow rate of about 10 standard cubic centimeters per minute to 10 L per minute, and for a time of about 15 minutes to 8 hours. However, any suitable parameters may be used.

[0080] exist Figure 6 In this process, the dielectric material 154 may undergo an optional second curing 300. In some embodiments, the second curing 300 may be ultraviolet (UV) curing, which can cleave silicon-nitrogen bonds (Si-N bonds) to produce a more solid oxide in subsequent processes, such as those corresponding to... Figure 7 and Figure 8As described below, the second curing 300 can be performed at a wavelength of approximately 10 nm to 400 nm. The time interval for the second curing 300 can be between approximately 10 seconds and 30 minutes, although other time values ​​are also possible.

[0081] Additionally, the multi-step curing process described above (e.g., first curing 200 followed by second curing 300) is intended to be illustrative rather than restrictive. In contrast, the references... Figure 5 and Figure 6 In some embodiments, only the first curing 200 is performed without the second curing 300. In some embodiments, only the second curing 300 is performed without the first curing 200. In some embodiments, the first curing 200 is performed before the second curing 300. In some embodiments, the second curing 300 is performed before the first curing 200. All suitable combinations are intended to be fully included within the scope of the embodiments.

[0082] exist Figure 7 In this process, the first step includes applying a wet oxidation treatment 400 to dielectric material 154 to convert dielectric material 154 into oxidized dielectric material 254. In some embodiments, oxidation can be performed using a mixture of chemicals, wherein the mixture includes components that facilitate the oxidation process, such as a first acid and a first oxidant. In one embodiment, the first acid may be an acid such as sulfuric acid (H2SO4), nitric acid (HNO3), hydrochloric acid (HCl), combinations thereof, or other similar chemicals. Additionally, the first oxidant may be an oxygen-containing chemical such as hydrogen peroxide (H2O2), ozone, combinations thereof, or other similar chemicals. However, any suitable first acid and first oxidant may be used.

[0083] In one particular embodiment, a wet oxidation treatment 400 is performed using a sulfuric acid and hydrogen peroxide mixture (SPM). For example, the mixture is a solution of liquid sulfuric acid and liquid hydrogen peroxide. In such embodiments, the sulfuric acid and hydrogen peroxide mixture can be in a ratio range of about 1:1 to 10:1, which is advantageous for sufficiently oxidizing the dielectric material 154. A wet oxidation treatment 400 can be performed using a sulfuric acid and hydrogen peroxide mixture at a molarity in the range of about 2M to 18.4M, which is advantageous for sufficiently oxidizing the dielectric material 154. The wet oxidation treatment 400 can be applied at temperatures greater than about 50°C and less than or equal to about 170°C. In some embodiments, the wet oxidation treatment 400 includes applying a sulfuric acid and hydrogen peroxide mixture at a temperature greater than about 50°C, referred to as a high-temperature sulfuric acid and hydrogen peroxide mixture (HTSPM) treatment. Applying the wet oxidation treatment 400 at temperatures less than about 50°C may not sufficiently oxidize the dielectric material 154. A wet oxidation treatment 400 can be uniformly applied to the dielectric material 154. The wet oxidation treatment 400 can be applied using a wet apparatus (such as a spray gun) at a flow rate of approximately 500 mL per minute to 2200 mL per minute. However, any suitable parameters and appropriate application can be used.

[0084] Wet oxidation treatment 400 oxidizes dielectric material 154 into oxide dielectric material 254. Using wet oxidation treatment 400 facilitates the conversion of dielectric material 154 into oxide and reduces oxidation of other components (such as fins 52, which may contain silicon and / or silicon-germanium), and reduces consumption of oxide-defined regions in fins 52. In some embodiments, wet oxidation treatment 400 is performed followed by dry annealing 500 (see below). Figure 8 Multiple loops, such as two loops.

[0085] Figure 8The second step of the conversion process is illustrated, including dry annealing 500, which converts the oxidized dielectric material 254 into an insulating material 54, such as silicon oxide and / or silicon dioxide. Dry annealing 500 is performed using a suitable vapor-free annealing process, also known as vapor-free annealing 500, such as thermal annealing in an inert gas environment (e.g., argon, helium, other similar chemicals, or combinations thereof) or in a mixed gas environment (including hydrogen, oxygen, nitrogen, other similar chemicals, or combinations thereof), with a water volume percentage of less than about 10%. For example, dry annealing 500 is performed with a water volume percentage of less than about 1%. Dry annealing 500 with a water volume percentage of less than about 1% can improve the film oxidation of the insulating material 54, while reducing the unwanted side effects of oxidized fins 52. Dry annealing 500 can be performed at pressures ranging from about 0.5 atm to 1.2 atm. Specifically, while a water concentration greater than 1% water volume percentage can result in better film quality, it may also lead to the side effect of oxidation of the silicon fins. Dry annealing 500 can be performed at temperatures between approximately 300°C and 800°C, and performing dry annealing 500 at temperatures within this range enhances the oxidation capacity of both wet oxidation treatment 400 and dry annealing 500. Annealing at temperatures below approximately 300°C may not allow sufficient oxidation to form the insulating material 54. Additionally, annealing at temperatures above approximately 800°C can lead to unwanted fin oxidation.

[0086] In some embodiments, a wet oxidation treatment 400 is performed (see above). Figure 7 Multiple cycles of wet oxidation 400 and dry annealing 500 help ensure complete process completion. For example, in some embodiments, a second wet oxidation treatment 400 may be performed, and a second dry annealing 500 may be performed to complete another cycle. Additionally, the cycle can be repeated any number of times desired. Accordingly, one or more cycles of wet oxidation treatment 400 and dry annealing 500 of the disclosed embodiments convert dielectric material 154 into insulating material 54. During the conversion from dielectric material 154 to insulating material 54, steam annealing processes with high temperatures greater than 450°C and steam volume percentages greater than 10% can be avoided. Steam annealing processes can cause the side effect of oxidation of the silicon fins.

[0087] Figure 9 The infrared spectrum of dielectric material 154 (e.g., all-hydrogen polysiloxane) is shown according to some embodiments. Figure 9 The dielectric material 154 shown above can be similar to the one above. Figure 4 The dielectric material 154 shown is illustrated. Infrared spectroscopy can plot wavelengths corresponding to bonds such as Si-H and Si-N bonds, which are common in dielectric material 154. Above... Figure 7 and Figure 8The wet oxidation treatment 400 and dry annealing 500 shown can oxidize dielectric material 154 and cleave Si-H and Si-N bonds.

[0088] Figure 10 Drawing in progress Figure 7 and Figure 8 Infrared spectra of insulating material 54 (e.g., silicon dioxide) after at least one cycle of wet oxidation treatment 400 and dry annealing 500, as shown above. Peaks corresponding to wavelengths such as Si-H and Si-N bonds (as shown above). Figure 9 The dielectric material 154 (as shown) no longer exists, and the infrared spectrum mainly consists of peaks corresponding to Si-O bonds. This indicates that the dielectric material 154 has been transformed into the insulating material 54 through wet oxidation treatment 400 and dry annealing 500. In some embodiments, the insulating material 54 is essentially composed of silicon oxide and / or silicon dioxide on the top surface, and the degree of oxidation reduction is proportional to the distance from the top surface.

[0089] Figure 11 The thickness of the test wafer containing silicon is shown, drawn along the bottom axis, on which dielectric material 154 is formed and wet-oxidized 400 (see above). Figure 7 ) and dry annealing 500 (see above) Figure 8 The wafer thickness can represent the amount of oxidation expected to occur on the surface of, for example, fin 52, by wet oxidation treatment 400 and dry annealing 500. In some embodiments, according to Figure 11 A wet oxidation process 400 is performed at a temperature of approximately 170°C and a molar concentration ranging from approximately 2M to 18M. Prior to the wet oxidation process 400, the wafer has a thickness of approximately 8.5 Å. After one cycle of wet oxidation process 400 and dry annealing 500, the wafer thickness increases to 10.0 Å, while after a second cycle of wet oxidation process 400 and dry annealing 500, the wafer thickness remains at approximately 10.0 Å. This indicates that during actual mass production of devices such as transistors, the wet oxidation process 400 and dry annealing 500 do not produce significant oxidation of the silicon components similar to those on the wafer, which helps reduce the consumption of oxide-defined regions in the fin 52 and / or unwanted oxidation during the conversion of dielectric material 154 into insulating material 54.

[0090] These fluidized silica materials are formed in a multi-step process. After depositing a fluidized film, the film is cured and annealed to remove unwanted components (such as solvents) to form silica. As unwanted components are removed, the fluidized film densifies and shrinks. In some embodiments, a multiple annealing process is performed. Curing and annealing can result in wider oxide and isolation zones on the trench sidewalls.

[0091] exist Figure 12In this process, a removal process is applied to the insulating material 54 to remove excess insulating material 54 from the fin 52. In some embodiments, a planarization process (such as chemical mechanical polishing (CMP)), an etch-back process, a combination thereof, or other similar methods may be used. The planarization process exposes the fin 52 such that, after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 are flush. In embodiments where a mask remains on the fin 52, the planarization process may expose or remove the mask such that, after the planarization process is completed, the top surface of the mask or the fin 52 is flush with the top surface of the insulating material 54.

[0092] exist Figure 13 In this process, insulating material 54 is etched to form shallow trench isolation (STI) regions 56. The etching of insulating material 54 causes the upper portions of fins 52 in N-type regions 50N and P-type regions 50P to protrude between adjacent shallow trench isolation regions 56. Furthermore, the top surface of the shallow trench isolation region 56 may have a flat surface, a convex surface, a concave surface (such as a dishing), or a combination thereof, as shown. The top surface of the shallow trench isolation region 56 can be formed into a flat, convex, and / or concave shape by suitable etching. Acceptable etching processes can be used to etch the shallow trench isolation region 56, such as processes selective for the material of insulating material 54 (e.g., etching the material of insulating material 54 at a higher rate than etching the material of fins 52). For example, diluted hydrofluoric acid (dHF) can be used to remove oxides.

[0093] Compared to Figures 2 to 13 The described process is merely one example of how fin 52 can be formed. In some embodiments, fins can be formed via epitaxial growth processes. For example, a dielectric layer can be formed on the top surface of substrate 50, and grooves can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be epitaxially grown in the trenches, and the retractable dielectric layer can be etched so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. Additionally, in some embodiments, heteroepitaxial structures can be used for fin 52. For example, retractable... Figure 5The fin 52 is an epitaxial layer on which a different material from the fin 52 can be epitaxially grown. In such an embodiment, the fin 52 comprises the etched material and the epitaxially grown material deposited on the etched material. In a further embodiment, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer. Then, a heteroepitaxial structure can be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer can be etched so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments of epitaxially growing homoepitaxial and heteroepitaxial structures, the epitaxially grown material can be in situ doped during growth, which eliminates the need for previous and subsequent implantation processes, although in-situ and implantation doping can be used together.

[0094] Furthermore, it is advantageous to epitaxially grow a different material in the N-type region 50N (e.g., an N-type metal-oxide-semiconductor region) than in the P-type region 50P (e.g., a P-type metal-oxide-semiconductor region). In various embodiments, silicon-germanium (Si...) can be used. x Ge 1-x The upper portion of fin 52 is formed from silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or other similar materials, where x can be in the range of 0 to 1. For example, usable materials for forming III-V compound semiconductors include indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and other similar materials, but this disclosure is not limited thereto.

[0095] Further in Figure 13 Suitable wells (not shown) may be formed in the fins 52 and / or the substrate 50. In some embodiments, a P-type well may be formed in the N-type region 50N, and an N-type well may be formed in the P-type region 50P. In some embodiments, either a P-type well or an N-type well may be formed in both the N-type region 50N and the P-type region 50P.

[0096] In embodiments with different types of wells, photoresist and / or other masks (not shown) can be used to achieve different implantation steps for the N-type region 50N and the P-type region 50P. For example, photoresist can be formed on the fins 52 and shallow trench isolation regions 56 in the N-type region 50N. The photoresist is patterned to expose the P-type region 50P of the substrate 50. The photoresist can be formed using spin coating technology, and the photoresist can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, N-type impurity implantation is performed in the P-type region 50P, while the photoresist acts as a mask to substantially prevent the implantation of N-type impurities into the N-type region 50N. The N-type impurity can be phosphorus, arsenic, antimony, or other similar materials, implanted in its region to a level equal to or less than 10. 18 cm -3 The concentration, such as at approximately 1016 cm -3 and 10 18 cm -3 Between. After the implantation step, the photoresist is removed via an acceptable ashing process.

[0097] Following the implantation of the P-type region 50P, photoresist is formed on the fins 52 and shallow trench isolation regions 56 within the P-type region 50P. The photoresist is patterned to expose the N-type region 50N of the substrate 50. The photoresist can be formed using spin coating technology, and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, P-type impurities are implanted in the N-type region 50N, while the photoresist acts as a mask to substantially prevent the implantation of P-type impurities into the P-type region 50P. The P-type impurities can be boron, boron fluoride, indium, or other similar materials, implanted in the region to a value equal to or less than 10. 18 cm -3 The concentration, such as at approximately 10 16 cm -3 and 10 18 cm -3 Between. After the implantation step, the photoresist is removed via an acceptable ashing process.

[0098] Following implantation of the N-type region 50N and the P-type region 50P, annealing can be performed to repair implantation damage and activate the implanted P-type and / or N-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can eliminate the need for the implantation process, although in-situ and implantation doping can be used together.

[0099] exist Figure 14In this process, a dummy dielectric layer 60 is formed on fin 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, combinations thereof, or other similar materials, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a masking layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 may be deposited on the dummy dielectric layer 60 and planarized by means such as chemical mechanical polishing. The masking layer 64 may be deposited on the dummy gate layer 62. The dummy gate layer 62 may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering deposition, or other techniques to deposit the selected material. The dummy gate layer 62 may be formed of other materials that have a high etch selectivity compared to the etching of the isolation region (e.g., shallow trench isolation region 56) and / or the dummy dielectric layer 60. The mask layer 64 may include one or more films, such as silicon nitride, silicon oxynitride, or other similar materials. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed spanning the N-type region 50N and the P-type region 50P. It should be noted that the dummy dielectric layer 60 is illustrated only over the fin 52 for illustrative purposes. In some embodiments, the dummy dielectric layer 60 may be deposited such that it covers the shallow trench isolation region 56, extends over the shallow trench isolation region, and is located between the dummy gate layer 62 and the shallow trench isolation region 56.

[0100] Figures 15A to 23B Various additional steps in the manufacturing of the components are illustrated. Figures 15A to 23B The characteristics are illustrated in either the N-type region 50N or the P-type region 50P. For example, in... Figures 15A to 23B The structure shown is applicable to both N-type region 50N and P-type region 50P. Any differences in the structure between N-type region 50N and P-type region 50P will be described in the text in conjunction with each figure.

[0101] exist Figure 15A and Figure 15B In this process, acceptable photolithography and etching techniques can be used to pattern the mask layer 64 (see reference). Figure 14A mask 74 is formed. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using an acceptable etching technique to form the dummy gate 72. The dummy gate 72 covers individual channel regions 58 of the fin 52. Adjacent dummy gates 72 can be physically separated from each other using the pattern of the mask 74. The dummy gate 72 may also have a lengthwise direction that is substantially perpendicular to the lengthwise direction of the individual epitaxial fin 52.

[0102] Further in Figure 15A and Figure 15B In this process, a gate sealing spacer 80 is formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fin 52. The gate sealing spacer 80 can be formed by thermal oxidation or deposition followed by anisotropic etching. The gate sealing spacer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, or other similar materials.

[0103] After the gate sealing spacer 80 is formed, implantation can be performed for lightly doped source / drain (LDD) regions (not explicitly shown). In embodiments with different device types, similar to... Figure 13 As described above, a photoresist-like mask can be formed on the N-type region 50N, exposing the P-type region 50P, and a suitable type (e.g., P-type) impurity can be implanted in the exposed fins 52 in the P-type region 50P. The mask can then be removed. Subsequently, a photoresist-like mask can be formed on the P-type region 50P, exposing the N-type region 50N, and a suitable type (e.g., N-type) impurity can be implanted in the exposed fins 52 in the N-type region 50N. The mask can then be removed. The N-type impurity can be any of the previously described N-type impurities, and the P-type impurity can be any of the previously described P-type impurities. The lightly doped source / drain regions can have approximately 10... 15 cm -3 Up to 10 19 cm -3 The concentration of impurities. Annealing can be used to repair implant damage and revitalize implanted impurities.

[0104] exist Figure 16A and Figure 16B In this process, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, or other similar materials.

[0105] It should be noted that the above disclosure generally describes the process for forming spacers and lightly doped source / drain regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, and steps in different sequences can be used (e.g., the gate sealing spacer 80 can be left unetched before forming the gate spacer 86, an L-shaped gate sealing spacer can be formed and removed, and / or other similar steps). Furthermore, different structures and steps can be used to form N-type and P-type devices. For example, the lightly doped source / drain regions of an N-type device can be formed before forming the gate sealing spacer 80, while the lightly doped source / drain regions of a P-type device can be formed after forming the gate sealing spacer 80.

[0106] exist Figure 17A and Figure 17B In this process, epitaxial source / drain regions 82 are formed in fin 52. The epitaxial source / drain regions 82 are formed in fin 52 such that each dummy gate 72 is disposed between individual adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into and penetrate fin 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by a suitable lateral distance such that the epitaxial source / drain regions 82 do not short-circuit with the gates of subsequently formed fin field-effect transistors. The material of the epitaxial source / drain regions 82 may be selected to apply stress in individual channel regions 58, thereby improving performance.

[0107] The epitaxial source / drain region 82 in the N-type region 50N is formed by shielding the P-type region 50P and etching the source / drain regions of the fins 52 in the N-type region 50N to form a groove in the fins 52. The epitaxial source / drain region 82 in the N-type region 50N is then epitaxially grown in the groove. The epitaxial source / drain region 82 may comprise any acceptable material, such as that suitable for an N-type fin field-effect transistor. For example, if the fins 52 are silicon, the epitaxial source / drain region 82 in the N-type region 50N may comprise a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or other similar materials. The epitaxial source / drain region 82 in the N-type region 50N may have a surface raised from the surface of the individual fins 52 and may have facets.

[0108] The epitaxial source / drain region 82 in the P-type region 50P is formed by shielding the N-type region 50N and etching the source / drain regions of the fins 52 in the P-type region 50P to form a groove in the fins 52. The epitaxial source / drain region 82 in the P-type region 50P is then epitaxially grown in the groove. The epitaxial source / drain region 82 may comprise any acceptable material, such as that suitable for a P-type fin field-effect transistor. For example, if the fins 52 are silicon, the epitaxial source / drain region 82 in the P-type region 50P may comprise a material that applies compressive strain to the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or other similar materials. The epitaxial source / drain region 82 in the P-type region 50P may have a surface raised from the surface of the individual fins 52 and may have facets.

[0109] Dopant can be implanted into the epitaxial source / drain region 82 and / or fin 52 to form the source / drain region (similar to the aforementioned process for forming lightly doped source / drain regions), followed by annealing. The source / drain region can have a density between approximately 10... 19 cm -3 and 10 21 cm -3 The impurity concentrations between these values. The N-type and / or P-type impurities in the source / drain regions can be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0110] The result of forming the epitaxial source / drain regions 82 using an epitaxial process in the N-type region 50N and the P-type region 50P is that the upper surface of the epitaxial source / drain regions 82 has facets that extend outward beyond the sidewalls of the fin 52. In some embodiments, these facets cause adjacent source / drain regions 82 of the same fin field-effect transistor to merge, such as Figure 17C As shown. In other embodiments, after the epitaxial process is completed, the adjacent source / drain regions 82 remain separated, as shown. Figure 17D As shown. In Figure 17C and Figure 17D In the illustrated embodiment, the gate spacer 86 is formed to cover a portion of the sidewall of the fin 52 extending over the shallow trench isolation region 56, thereby blocking epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacer 86 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the shallow trench isolation region 56.

[0111] exist Figure 18A and Figure 18B In Figure 17A and Figure 17BA first interlayer dielectric (ILD) 88 is deposited on the structure shown. The first interlayer dielectric 88 can be formed of a dielectric material and can be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flow-through chemical vapor deposition. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped-silicate glass (USG), or other similar materials. An insulating material formed by any acceptable process can be used. In some embodiments, an insulating material formed by a process similar to [the previous one] can be used. Figures 4-9 The first interlayer dielectric 88 is formed from substantially the same material and process as the insulating material 54. In some embodiments, a contact etch stop layer (CESL) 87 is provided between the first interlayer dielectric 88 and the source / drain region 82, the mask 74, and the gate spacer 86. The contact etch stop layer 87 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or other similar materials, having a lower etch rate than the material of the overlying first interlayer dielectric 88.

[0112] exist Figure 19A and Figure 19B In this process, a planarization process, such as chemical mechanical polishing, can be performed to make the top surface of the first interlayer dielectric 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, as well as portions of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacers 80, the gate spacers 86, and the first interlayer dielectric 88 are flush. Accordingly, the top surface of the dummy gate 72 is exposed through the first interlayer dielectric 88. In some embodiments, the mask 74 may be retained, in which case the planarization process flushes the top surface of the first interlayer dielectric 88 with the top surface of the mask 74.

[0113] In some embodiments, a gate tail dielectric 76 is formed on the tail sidewall of the dummy gate 72. The gate tail dielectric 76 can be used, for example, to separate different gate electrodes. For example, in some embodiments, the dummy gate 72 may extend over several fins on a substrate or wafer to form multiple transistors. Depending on the desired circuitry, these transistors may require different gate electrodes. In this way, the gate tail dielectric 76 can be used as an insulating material between different gate electrodes. As described later, the remaining portion of the dummy gate 72 is replaced by a conductive active gate, wherein the gate tail dielectric 76 remains electrically insulated from the conductive active gate to avoid short-circuiting between them. In some embodiments, the gate tail dielectric 76 is formed after the formation of the gate electrode 94 and the gate mask 96 (as corresponding to...). Figures 21A to 22B (As described below). The formation of the gate tail dielectric 76 can be achieved by suitable lithography, patterning, and etching processes to remove portions of the dummy gate 72 or gate electrode 94 and gate mask 96, or by performing a dummy gate or metal gate dicing process to form an opening adjacent to or within the dummy gate 72 or gate electrode 94 and gate mask 96. The gate tail dielectric 76 is then formed in individual openings in the tail sidewalls adjacent to the dummy gate 72 or gate electrode 94 and gate mask 96, and can be deposited by any suitable method, such as plasma-assisted chemical vapor deposition, flowable chemical vapor deposition, or atomic layer deposition (ALD). In some embodiments, a method using... Figures 4-9 The insulating material 54 is largely the same material and process used to form the gate tail dielectric 76.

[0114] exist Figure 20A and Figure 20BIn the etching step, a dummy gate 72 and a mask 74 (if present) are removed to form a recess 90. A portion of the dummy dielectric layer 60 within the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, while the dummy dielectric layer 60 remains and is exposed by the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from a recess 90 in a first region of the die (e.g., a core logic region), while the dummy dielectric layer 60 remains in a recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 while minimally or not at all etching the first interlayer dielectric 88 or the gate spacer 86. Each recess 90 exposes and / or covers a channel region 58 of an individual fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, when etching the dummy gate 72, the dummy dielectric layer 60 can be used as an etch stop layer. Then, the dummy dielectric layer 60 can be optionally removed after the dummy gate 72 is removed.

[0115] exist Figure 21A and Figure 21B In this process, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 21C Draw Figure 21B A detailed schematic diagram of region 89. The gate dielectric layer 92 may be one or more films deposited within the recess 90 (e.g., on the top surface and sidewalls of fin 52 and on the sidewalls of gate sealing spacer 80 / gate spacer 86). The gate dielectric layer 92 may also be formed on the top surface of the first interlayer dielectric 88. In some embodiments, the gate dielectric layer 92 includes one or more dielectric layers, such as one or more films of silicon oxide, silicon nitride, metal oxide, metal silicide, or other similar materials. For example, in some embodiments, the gate dielectric layer 92 includes an interfacial layer (IL) of silicon oxide formed by thermal or chemical oxidation, and an overlying high-k dielectric material (such as metal oxide or silica of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof). The gate dielectric layer 92 may include a dielectric layer having a dielectric constant value greater than about 7.0. Methods for forming the gate dielectric layer 92 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, or other similar methods. In embodiments where a portion of the dummy dielectric layer 60 is retained in the recess 90, the gate dielectric layer 92 comprises the material of the dummy dielectric layer 60 (e.g., silicon dioxide).

[0116] Gate electrodes 94 are deposited on the gate dielectric layer 92, filling the remaining portion of the trench 90. The gate electrodes 94 may comprise a metallic material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although in Figure 21B The diagram illustrates a single-layer gate electrode 94. Gate electrode 94 may include any number of substrates 94A, any number of work function adjustment layers 94B, and filler material 94C, such as... Figure 21C As shown. After filling the recess 90, a planarization process such as chemical mechanical polishing can be performed to remove excess material from the gate dielectric layer 92 and the gate electrode 94, which are located on the top surface of the first interlayer dielectric 88. The remaining material of the gate electrode 94 and the gate dielectric layer 92 thus form the replacement gate of the resulting fin field-effect transistor. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as the "gate stack". The gate and the gate stack can extend along the sidewall of the channel region 58 of the fin 52.

[0117] The formation of the gate dielectric layer 92 in the N-type region 50N and the P-type region 50P can occur simultaneously, such that the gate dielectric layer 92 formed in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, such that the gate electrode 94 formed in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed using a unique process, such that the gate dielectric layer 92 can be made of different materials, and / or the gate electrode 94 in each region can be formed using a unique process, such that the gate electrode 94 can be made of different materials. When using a unique process, various masking steps can be used to mask and expose appropriate areas.

[0118] exist Figure 22A and Figure 22B In this process, a gate mask 96 is formed on the gate stack (including the gate dielectric layer 92 and the corresponding gate electrode 94), and the gate mask 96 may be disposed between the two side portions of the gate spacer 86. In some embodiments, forming the gate mask 96 includes etching the gate stack such that a groove is formed directly above the gate stack and between the two side portions of the gate spacer 86. The groove is filled with the gate mask 96 (including one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or other similar materials), and a planarization process is followed to remove excess portions of the dielectric material extending onto the first interlayer dielectric 88.

[0119] Just like Figure 22A and Figure 22BAs shown, a second interlayer dielectric 108 is deposited on the first interlayer dielectric 88. In some embodiments, the second interlayer dielectric 108 is a fluid film layer formed by a fluid chemical vapor deposition method. In some embodiments, the second interlayer dielectric 108 is formed of a dielectric material (such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or other similar materials) and can be deposited by any suitable method (such as chemical vapor deposition and plasma-assisted chemical vapor deposition). In some embodiments, a second interlayer dielectric 108 can be used... Figures 4-9 The second interlayer dielectric 108 is formed using largely the same material and process as the insulating material 54. Forming the second interlayer dielectric 108 using the same process and materials reduces oxidation of the gate electrode 94, thus reducing the metal gate critical voltage offset. The subsequently formed gate contact 110 ( Figure 23A and Figure 23B It penetrates the second interlayer dielectric 108 and the gate shield 96 to contact the top surface of the etched gate electrode 94.

[0120] exist Figure 23A and Figure 23B In some embodiments, gate contact 110 and source / drain contact 112 are formed through a second interlayer dielectric 108. An opening forming the source / drain contact 112 extends through a first interlayer dielectric 88 and a second interlayer dielectric 108, while an opening forming the gate contact 110 extends through the second interlayer dielectric 108 and a gate mask 96. The openings can be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesive layer, or other similar material, and a conductive material are formed within the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or other similar materials. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or other similar materials. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the surface of the second interlayer dielectric 108. The remaining liner and conductive material are formed in the openings of the source / drain contact 112 and the gate contact 110. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, while the gate contact 110 is physically and electrically coupled to the gate electrode 94. The source / drain contact 112 and the gate contact 110 can be formed in different processes or in the same process. Although they are shown formed in the same cross-section, it should be understood that each source / drain contact 112 and the gate contact 110 can be formed in different cross-sections to avoid short circuits in the contacts.

[0121] Figure 24A flowchart 1100 illustrates an embodiment of a method for forming an insulating material 54. In some embodiments, the forming method includes a first step 1102 (e.g., forming a fluid dielectric material 154) to form a fluid dielectric material 154. Figure 4 As shown), an optional second step 1104 is performed to carry out the first curing 200 (as shown). Figure 5 As shown), an optional third step 1106 is performed for the second curing 300 (as shown). Figure 6 As shown), the fourth step 1108 of the wet oxidation treatment 400 (as shown) Figure 7 As shown), perform the fifth step 1110 of dry annealing at 500°C (as shown). Figure 8 (as shown), repeating steps 1108 and 1110X of the fourth step to convert the fluid dielectric material 154 into the insulating material 54, the sixth step 1112, and the seventh step 1114, providing a chemical mechanical polishing operation or etching step to remove excess portions of the insulating material 54 on the surface of the mask layer (as shown), repeating steps 1108 and 1110X of the sixth step to convert the fluid dielectric material 154 into the insulating material 54, and providing a chemical mechanical polishing operation or etching step to remove excess portions of the insulating material 54 on the surface of the mask layer. Figure 12 (As shown).

[0122] In some embodiments, it may be for Figure 24 Flowchart 1100 removes process steps or adds additional process steps. In some embodiments, the order of steps shown in flowchart 1100 may be reordered.

[0123] The disclosed fin field-effect transistor embodiments are also applicable to nanostructured devices, such as nanostructured field-effect transistors (e.g., nanosheets, nanowires, fully wound gates, or other similar structures). In embodiments of nanostructured field-effect transistors, the fins are replaced by nanostructures formed by a patterned staggered stack of channel layers and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a manner similar to the embodiments described above. After removing the dummy gate stacks, the sacrificial layers can be partially or completely removed from the channel regions. Replacement gate structures are formed in a manner similar to the embodiments described above, which can partially or completely fill the openings left by removing the sacrificial layers, and can partially or completely surround the channel layers in the channel regions of the nanostructured field-effect transistor. Interlayer dielectrics and contacts for the replacement gate structures and source / drain regions are formed in a manner similar to the embodiments described above. The formation of nanostructured devices, as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, is incorporated herein by reference in its entirety.

[0124] The above embodiments offer several advantages. Forming an insulating material may include steps such as depositing a dielectric material, curing the dielectric material using, for example, an oxygen environment and / or ultraviolet curing process, performing wet oxidation, and performing dry (vapor-free) annealing. A flowable chemical vapor deposition process can be used to form the dielectric material. Using wet oxidation and dry annealing can reduce adverse effects such as the consumption of oxide-defined regions, oxidation of silicon and / or silicon-germanium in fins or other structures, critical voltage shift due to gate electrode oxidation, and / or other similar effects.

[0125] According to one embodiment, a method for forming a semiconductor device includes: forming a fluid dielectric material; performing a wet oxidation treatment on the fluid dielectric material, the wet oxidation treatment including coating the fluid dielectric material with a mixture of acid and oxidant; and performing dry annealing on the fluid dielectric material to cure the fluid dielectric material. In one embodiment, the acid and oxidant mixture includes a mixture of sulfuric acid and hydrogen peroxide. In one embodiment, the mixture has a sulfuric acid to hydrogen peroxide ratio of 1:1 to 10:1. In one embodiment, the wet oxidation treatment is performed at a temperature greater than 50°C. In one embodiment, the mixture is coated at a flow rate of 500 ml to 2200 ml per minute. In one embodiment, the dry annealing is performed at a water volume percentage of less than 1%. In one embodiment, the dry annealing is performed at a temperature of 300°C to 800°C. In one embodiment, the forming method further includes performing a second wet oxidation treatment and a second dry annealing on the fluid dielectric material.

[0126] According to another embodiment, a method for forming a semiconductor device includes: depositing a fluid dielectric material on a substrate; and performing a first cycle of a conversion process to convert the fluid dielectric material into an oxide, the conversion process including: applying an acid mixture to the fluid dielectric material; and dry annealing the fluid dielectric material with a water volume percentage of less than 10%. In one embodiment, the forming method further includes ozone curing and ultraviolet curing of the fluid dielectric material. In one embodiment, ozone curing is performed before ultraviolet curing. In one embodiment, ultraviolet curing is performed before ozone curing. In one embodiment, the acid mixture includes sulfuric acid and hydrogen peroxide. In one embodiment, the acid mixture has a sulfuric acid to hydrogen peroxide ratio of 1:1 to 10:1. In one embodiment, the annealing of the fluid dielectric material is performed with a water volume percentage of less than 1%. In one embodiment, the forming method further includes etching the oxide to form shallow trench isolation regions.

[0127] According to another embodiment, a method for forming a semiconductor device includes: depositing a first dielectric material between a first fin and a second fin; ozone curing the first dielectric material; ultraviolet curing the first dielectric material; performing at least one cycle of a conversion process to convert the first dielectric material into an oxide, the conversion process including: applying a sulfuric acid-hydrogen peroxide mixture to the first dielectric material; and dry annealing the first dielectric material; planarizing to remove excess portions of the oxide on the first and second fins; and etching the oxide to form a shallow trench isolation region between the first and second fins. In one embodiment, the first dielectric material comprises a perhydropolysiloxane. In one embodiment, depositing the first dielectric material includes using trisilylamine as a precursor. In one embodiment, the conversion process is performed in at least two cycles.

[0128] The foregoing outlines components of several embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily design or modify other processes and structures based on the embodiments of this disclosure to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A fluid dielectric material is formed on the sidewall of a semiconductor fin; The fluid dielectric material is subjected to ozone curing, wherein the fluid dielectric material includes Si-H bonds and Si-N bonds; After ozone curing, the fluid dielectric material is then subjected to ultraviolet curing. Performing a first cycle of a conversion process, wherein the first cycle of the conversion process oxidizes the sidewalls of the semiconductor fin, and wherein the first cycle of the conversion process includes: After the flowable dielectric material is cured with ultraviolet light, it is subjected to a first wet oxidation treatment to convert it into an oxide. This first wet oxidation treatment includes coating the flowable dielectric material with a mixture of an acid and an oxidant, wherein the acid and oxidant mixture has a molar concentration in the range of 2 M to 18.4 M. The fluid dielectric material is subjected to a first dry annealing to solidify the fluid dielectric material and form an insulating material. The first wet oxidation treatment and the first dry annealing cleave the Si-H and Si-N bonds of the fluid dielectric material and establish Si-O bonds in the oxide. The top surface of the insulating material includes silicon and oxygen. The degree of oxidation reduction of the insulating material is proportional to the distance from the top surface of the insulating material. The first dry annealing is performed with a water volume percentage of less than 10% and greater than 0%. Performing a second cycle of the conversion process, wherein the second cycle of the conversion process does not cause additional oxidation to the sidewalls of the semiconductor fin, and wherein the second cycle of the conversion process includes: A second wet oxidation treatment is performed on the fluid dielectric material, the second wet oxidation treatment comprising coating the fluid dielectric material with the mixture of acid and oxidant; and The fluid dielectric material is subjected to a second dry annealing, wherein the second dry annealing is carried out with a water volume percentage of less than 10% and greater than 0%.

2. The method for forming a semiconductor element as described in claim 1, wherein, The acid-oxidant mixture includes a mixture of sulfuric acid and hydrogen peroxide.

3. The method for forming a semiconductor element as described in claim 2, wherein, The acid-oxidant mixture has a sulfuric acid to hydrogen peroxide ratio of 1:1 to 10:

1.

4. The method for forming a semiconductor element as described in claim 1, wherein, The first wet oxidation treatment was carried out at a temperature greater than 50°C.

5. The method for forming a semiconductor element as described in claim 2, wherein, The acid-oxidant mixture was coated at a flow rate of 500 ml to 2200 ml per minute.

6. The method for forming a semiconductor element as described in claim 1, wherein, The first dry annealing is carried out with less than 1% water by volume.

7. The method for forming a semiconductor element as claimed in claim 1, wherein, The first dry annealing is carried out at a temperature of 300°C to 800°C.

8. A method for forming a semiconductor device, comprising: A fluid dielectric material is deposited on the sidewall of a semiconductor fin; The fluid dielectric material is subjected to ozone curing, wherein the fluid dielectric material includes Si-H bonds and Si-N bonds; After ozone curing, the fluid dielectric material is then subjected to ultraviolet curing; and After the flowable dielectric material is cured with ultraviolet light, a first cycle of a conversion process is performed to convert the flowable dielectric material into an oxide and cure the flowable dielectric material into an insulating material. The first cycle of the conversion process breaks the Si-H and Si-N bonds of the flowable dielectric material and establishes Si-O bonds in the oxide. The top surface of the insulating material comprises silicon and oxygen, and the degree of oxidation reduction of the insulating material is proportional to the distance from the top surface of the insulating material. The first cycle of the conversion process oxidizes the sidewalls of the semiconductor fins and includes: A first acid mixture is applied to the fluid dielectric material, wherein the first acid mixture comprises sulfuric acid and hydrogen peroxide having a molar concentration in the range of 2M to 18.4M; and The fluid dielectric material is annealed with a first dry annealing having a water volume percentage of less than 10% and greater than 0%. Performing a second cycle of the conversion process, wherein the second cycle of the conversion process does not cause additional oxidation to the sidewalls of the semiconductor fin, and wherein the second cycle of the conversion process includes: A second acid mixture is applied to the fluid dielectric material, wherein the second acid mixture comprises sulfuric acid and hydrogen peroxide having a molar concentration in the range of 2M to 18.4M; and The fluid dielectric material is subjected to a second dry annealing, wherein the second dry annealing is carried out with a water volume percentage of less than 10% and greater than 0%.

9. The method for forming a semiconductor element as described in claim 8, wherein, The first acid mixture has a sulfuric acid to hydrogen peroxide ratio of 1:1 to 10:

1.

10. The method for forming a semiconductor element as claimed in claim 8, wherein, The first dry annealing is carried out with less than 1% water by volume.

11. The method of forming a semiconductor element as claimed in claim 8, further comprising etching the oxide to form a shallow trench isolation region.

12. A method for forming a semiconductor device, comprising: A first dielectric material is deposited between a first fin and a second fin; The first dielectric material is subjected to ozone curing, wherein the first dielectric material includes Si-H bonds and Si-N bonds; After ozone curing, the first dielectric material is then subjected to ultraviolet curing. After the first dielectric material is cured with ultraviolet light, a first cycle of a conversion process is performed to convert the first dielectric material into an oxide and cure the first dielectric material into an insulating material. The first cycle of the conversion process breaks the Si-H and Si-N bonds of the first dielectric material and establishes Si-O bonds in the oxide. The top surface of the insulating material comprises silicon and oxygen, and the degree of oxidation reduction of the insulating material is proportional to the distance from the top surface of the insulating material. The first cycle of the conversion process oxidizes the sidewalls of the first fin and the second fin, and the first cycle of the conversion process includes: A first sulfuric acid-hydrogen peroxide mixture is applied to the first dielectric material, wherein the first sulfuric acid-hydrogen peroxide mixture has a molar concentration in the range of 2M to 18.4M; and The first dielectric material is subjected to a first dry annealing, wherein the first dry annealing is performed with a water volume percentage of less than 10% and greater than 0%. A second cycle of the conversion process is performed, wherein the second cycle of the conversion process does not cause additional oxidation to the sidewalls of the first fin and the second fin, and wherein the second cycle of the conversion process includes: A second sulfuric acid-hydrogen peroxide mixture is applied to the first dielectric material, wherein the second sulfuric acid-hydrogen peroxide mixture has a molar concentration in the range of 2M to 18.4M; and The first dielectric material is subjected to a second dry annealing, wherein the second dry annealing is performed with a water volume percentage of less than 10% and greater than 0%. Planarization removes an excess portion of the oxide on the first and second fins; and The oxide is etched to form a shallow trench isolation zone between the first fin and the second fin.

13. The method for forming a semiconductor element as described in claim 12, wherein, The first dielectric material comprises all-hydrogen polysiloxane.

14. The method for forming a semiconductor element as described in claim 12, wherein, Depositing the first dielectric material involves using trisilylamine as a precursor.

Images