Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed in the semiconductor layer. The first insulating film is formed on an inner side surface of the first trench so that a part of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected to the semiconductor substrate and is formed on the inner side surface of the first trench through the first insulating film. In a plan view, a first length of the first trench in an extension direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extension direction, and is equal to or smaller than 30 µm.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The disclosed technologies are listed below.

[0003] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2015-037099

[0004] A semiconductor device is known, comprising a conductive film embedded in a trench formed in an insulating layer or a semiconductor layer. For example, a semiconductor device is known to include contacts such as substrate contacts and vias (see, for example, Patent Document 1). The semiconductor device described in Patent Document 1 includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, and an interlayer insulating layer formed on the semiconductor layer. Trenches reaching the semiconductor substrate are formed in the interlayer insulating layer and the semiconductor layer. An insulating film is formed on the inner surface of the trench. The semiconductor device also includes a conductive film formed on the insulating film such that the conductive film buries the trench. The conductive film is formed, for example, by forming a conductive layer on the interlayer insulating layer to bury the trench and then removing a portion of the conductive layer outside the trench by a CMP method.

[0005] In semiconductor devices, conductive films formed in trenches constitute contacts. For example, in Patent Document 1, the GND potential of the semiconductor substrate is fixed through contacts. Summary of the Invention

[0006] However, depending on the material and size of the conductive film, voids (gaps) may form within the conductive film due to stress induced by the contacts during its formation. The cleaning solution used in the CMP step then enters these voids and forms reaction products of the conductive film material and cleaning solution components on the conductive film. Therefore, in conventional semiconductor devices, short circuits may occur between two closely spaced wirings via these reaction products. As described above, conventional semiconductor devices can be improved from the viewpoint of enhancing their reliability.

[0007] The problem with these embodiments is to improve the reliability of semiconductor devices. Other problems and novel features will become clear through the description in the specification and drawings.

[0008] A semiconductor device according to an embodiment includes: a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench extending to the semiconductor substrate is formed in the semiconductor layer. The first insulating film is formed on an inner surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected to the semiconductor substrate and extends through the first insulating film to form on the inner surface of the first trench. In a plan view, a first length of the first trench in its extension direction is greater than a second length of the first trench in its width direction perpendicular to the extension direction, and the first length is equal to or less than 30 μm.

[0009] A method of manufacturing a semiconductor device according to an embodiment includes: forming a first trench penetrating a semiconductor layer to reach a semiconductor substrate; forming an insulating film on an inner surface of the first trench to expose a portion of the semiconductor substrate in the first trench; and forming a conductive film on the insulating film formed on the inner surface of the first trench to electrically connect with the semiconductor substrate. In a plan view, a first length of the first trench in the extension direction of the first trench is greater than a second length of the first trench in the width direction perpendicular to the extension direction, and the first length is equal to or less than 30 μm.

[0010] A semiconductor device according to another embodiment includes: a first wiring, an insulating film formed on the first wiring and having a trench exposing a portion of the first wiring, a conductive film formed in the trench, and a second wiring formed on the insulating layer and passing through the conductive film, electrically connected to the first wiring. In a plan view, a first length of the trench in the trench's extension direction is greater than a second length of the trench in the width direction perpendicular to the extension direction, and the first length is equal to or less than 30 μm.

[0011] According to the embodiments, the reliability of semiconductor devices can be improved. Attached Figure Description

[0012] Figure 1 This is a plan view illustrating an exemplary configuration of the main parts of a semiconductor device according to an embodiment;

[0013] Figure 2 This is a cross-sectional view illustrating an exemplary configuration of the main portions of a semiconductor device according to an embodiment;

[0014] Figure 3 This is a cross-sectional view illustrating exemplary steps included in a method for manufacturing a semiconductor device according to an embodiment;

[0015] Figure 4 This is a cross-sectional view illustrating exemplary steps included in a method for manufacturing a semiconductor device according to an embodiment;

[0016] Figure 5This is a cross-sectional view illustrating exemplary steps included in a method for manufacturing a semiconductor device according to an embodiment;

[0017] Figure 6 This is a cross-sectional view illustrating exemplary steps included in a method for manufacturing a semiconductor device according to an embodiment;

[0018] Figure 7 This is a cross-sectional view illustrating exemplary steps included in a method for manufacturing a semiconductor device according to an embodiment;

[0019] Figure 8 This is a cross-sectional view illustrating exemplary steps included in a method for manufacturing a semiconductor device according to an embodiment;

[0020] Figure 9 This is a cross-sectional view illustrating exemplary steps included in a method for manufacturing a semiconductor device according to an embodiment;

[0021] Figure 10 This is a cross-sectional view illustrating exemplary steps included in a method for manufacturing a semiconductor device according to an embodiment;

[0022] Figure 11 This is a graph showing the relationship between the stress caused by the substrate contacts and the dimensions of the substrate contacts;

[0023] Figure 12 This is a diagram showing the stress caused by the substrate contact versus the distance from the substrate contact; and

[0024] Figure 13 This is an enlarged perspective view showing an exemplary configuration of the main parts of a semiconductor device according to a modified example. Detailed Implementation

[0025] In the following, a semiconductor device according to an embodiment and a method of manufacturing the semiconductor device will be described in detail with reference to the accompanying drawings. In the specification and drawings, the same or corresponding elements are indicated by the same reference numerals or the same shading lines, and repeated descriptions are omitted. In the drawings, configurations may be omitted or simplified for ease of description. Cross-sectional views may be shown as end views.

[0026] [Semiconductor device configuration]

[0027] Figure 1 This is a plan view illustrating an exemplary configuration of the main parts of the semiconductor device SD according to this embodiment. Figure 2 This is a cross-sectional view showing an exemplary configuration of the main parts of the semiconductor device SD according to this embodiment. Figure 2 It is along Figure 1 The cross-sectional view taken from line AA in the diagram.

[0028] The semiconductor device SD includes a semiconductor substrate SUB, a semiconductor layer SL, semiconductor elements SE, and a multilayer wiring layer MWL. As will be described in detail later, the semiconductor device SD includes a first element isolation portion EI1, a second isolation portion EI2, and substrate contacts SC, which are formed from elements of a portion of the multilayer wiring layer MWL. Figure 1 The components of the multilayer wiring layer MWL located above the first wiring WR1 are omitted.

[0029] A semiconductor substrate SUB supports a semiconductor layer SL. The semiconductor substrate SUB has a first conductivity type. The first conductivity type is P-type or N-type. Examples of impurities contained in a P-type semiconductor substrate include boron (B) and indium (In). Examples of impurities contained in an N-type semiconductor substrate include phosphorus (P), arsenic (As), and antimony (Sb).

[0030] A semiconductor layer SL is formed on a semiconductor substrate SUB. The semiconductor layer SL includes a first epitaxial layer EL1, a buried layer BL, a second epitaxial layer EL2, and a buried insulating film BIF. The first epitaxial layer EL1, the buried layer BL, and the second epitaxial layer EL2 are formed sequentially from the semiconductor substrate SUB side.

[0031] A first epitaxial layer EL1 is formed on the surface of the semiconductor substrate SUB. The first epitaxial layer EL1 is a semiconductor layer having a first conductivity type. The impurity concentration of the first epitaxial layer EL1 is preferably, for example, 1 × 10⁻⁶. 13 cm -3 Above and 1×10 19 cm -3 The following, and preferably 1×10 13 cm -3 Above and 1×10 16 cm -3 The first epitaxial layer EL1 is not a required component. The first epitaxial layer EL1 can be a silicon-on-insulator (SOI) layer on a so-called SOI substrate.

[0032] A buried layer BL is formed on all or part of the first epitaxial layer EL1. The semiconductor layer SL preferably has a buried layer BL such that the semiconductor element SE and the semiconductor substrate SUB formed on the buried layer BL in the semiconductor layer SL are electrically insulated from each other. The buried layer BL is a semiconductor layer having a second conductivity type opposite to the first conductivity type. The impurity concentration of the buried layer BL is preferably, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0033] The second epitaxial layer EL2 is formed on the buried layer BL. When the buried layer BL is formed over the entire first epitaxial layer EL1, the second epitaxial layer EL2 is formed on the buried layer BL. When the buried layer BL is formed over a portion of the first epitaxial layer EL1, the second epitaxial layer EL2 is formed on both the buried layer BL and the first epitaxial layer EL1. The impurity concentration of the second epitaxial layer EL2 is preferably, for example, 1 × 10⁻⁶. 13 cm -3 Above and 1×10 19 cm -3 Hereinafter, 1×10 is more preferably preferred. 13 cm -3 Above and 1×10 16 cm -3 the following.

[0034] Incidentally, the semiconductor layer SL may also include one or more embedding layers as needed. The embedding layer may be formed within the first epitaxial layer EL1 or the second epitaxial layer EL2. In a planar view, the embedding layer may be formed to overlap the entire buried layer BL, or it may be formed to overlap a portion of the buried layer BL. The conductivity type of the embedding layer may be P-type or N-type.

[0035] A buried insulating film (BIF) is formed in the second epitaxial layer EL2 of the semiconductor layer SL. The buried insulating film BIF is formed such that it surrounds the semiconductor element SE in a plan view. The buried insulating film BIF is an insulating film formed on the main surface of the semiconductor layer SL. There are no particular restrictions on the location, number, and size of the buried insulating film BIF, as long as the semiconductor element SE can be electrically insulated from other semiconductor elements (not shown). The buried insulating film BIF is, for example, formed of silicon oxide (SiO2).

[0036] A first trench TR1, a second trench TR2, and a third trench TR3 are formed on the main surface of the semiconductor layer SL, reaching the semiconductor substrate. Specifically, the first trench TR1, the second trench TR2, and the third trench TR3 open in the main surface of the semiconductor layer SL. The first trench TR1 defines the location, size, and shape of the first element isolation portion EI1. The second trench TR2 defines the location, size, and shape of the second element isolation portion EI2. The third trench TR3 defines the location, size, and shape of the substrate contact SC.

[0037] A semiconductor element SE is formed on the main surface of the semiconductor layer SL. There are no particular limitations on the semiconductor element SE, and it can be a so-called planar MOSFET or a laterally diffused MOSFET (LDMOSFET). In this embodiment, the semiconductor element SE is a planar MOSFET. The semiconductor element SE includes a source region SR, a drain region DR, a gate insulating film GI, and a gate electrode GE. The main surface of the substrate SUB is the surface on which the semiconductor element SE is formed.

[0038] A multilayer wiring layer (MWL) is formed on a semiconductor layer (SL) such that the MWL covers the semiconductor device (SE). The MWL consists of two or more wiring layers. A wiring layer is a layer that includes an interlayer insulating layer, and one or both of wiring and vias formed within the interlayer insulating layer. A via is a conductive element that electrically connects two wirings formed in different layers.

[0039] The multilayer wiring layer (MWL) includes a first interlayer insulating layer (IL1), a first via (V1), a conductive film (CF), a first wiring layer (WR1), a second interlayer insulating layer (IL2), a second via (V2), a second wiring layer (WR2), and a third interlayer insulating layer (IIL3). As will be described in detail later, a first portion of the first interlayer insulating layer (IIL1) constitutes a first element isolation portion (EI1). A second portion of the first interlayer insulating layer (IIL1) constitutes a second element isolation portion (EI2). The third portion of the first interlayer insulating layer (IIL1) and the conductive film (CF) constitute a substrate contact (SC).

[0040] A first interlayer insulating layer IIL1 is formed on the semiconductor layer SL such that the first interlayer insulating layer IIL1 covers the semiconductor device SE. The first interlayer insulating layer IIL1 can be formed from a single layer or multiple layers. In this embodiment, the first interlayer insulating layer IIL1 includes a first insulating film IF1, a second insulating film IF2, and a third insulating film IF3.

[0041] A first insulating film IF1 is formed on the semiconductor layer SL such that the first insulating film IF1 covers the semiconductor element SE. Examples of materials for the first insulating film IF1 include silicon oxide and silicon nitride. The thickness of the first insulating film IF1 is, for example, 10 nm or more and 100 nm or less.

[0042] A second insulating film IF2 is formed on the first insulating film IF1. Examples of materials for the second insulating film IF2 include silicon oxide and silicon nitride. The thickness of the second insulating film IF2 is, for example, 50 nm or more and 1 μm or less.

[0043] The third insulating film IF3 is formed in the first trench TR1, the second trench TR2 and the third trench TR3, as well as on the second insulating film IF2.

[0044] A first portion of the third insulating film IF3 is formed on the inner and bottom surfaces of the first trench TR1. This first portion of the third insulating film IF3 constitutes a first element isolation portion EI1. For example, the first element isolation portion EI1 insulates the substrate contact SC from the semiconductor element SE. Preferably, the first portion of the third insulating film IF3 is formed in the first trench TR1 such that a first gap VD1 is formed within the first trench TR1. In this embodiment, the first gap VD1 is formed within the first portion of the third insulating film IF3. Therefore, the insulation characteristics of the first element isolation portion EI1 are improved.

[0045] like Figure 1 As shown, the first element isolation portion EI1 (first portion) is formed such that in the plan view, the first element isolation portion EI1 surrounds the substrate contact SC. In the first element isolation portion EI1, a first gap VD1 is formed within the first portion of the third insulating film IF3. From the viewpoint of improving the insulation characteristics of the first element isolation portion EI1, the first length of the first gap VD1 in the depth direction of the first trench TR1 is preferably larger. Furthermore, from the viewpoint of improving the insulation characteristics of the first element isolation portion EI1, the second length of the first gap VD1 in the width direction of the first trench TR1 is preferably larger. The depth direction of the first trench TR1 is the same as the thickness direction of the semiconductor layer SL.

[0046] The second portion of the third insulating film IF3 is formed on the inner and bottom surfaces of the second trench TR2. This second portion of the third insulating film IF3 constitutes the second element isolation portion EI2. For example, the second element isolation portion EI2 insulates the semiconductor element SE from other semiconductor elements (not shown). Preferably, the second portion of the third insulating film IF3 is formed in the second trench TR2 such that a second gap VD2 is formed within the second trench TR2. In this embodiment, the second gap VD2 is formed within the second portion of the third insulating film IF3. Therefore, the insulation properties of the second isolation portion EI2 are further improved.

[0047] like Figure 1 As shown, the second element isolation portion EI2 (second portion) is formed such that in the plan view, the second element isolation portion EI2 surrounds the semiconductor element SE. In the second element isolation portion EI2, a second gap VD2 is formed within the second portion of the third insulating film IF3. From the viewpoint of improving the insulation characteristics of the second element isolation portion EI2, the first length of the second gap VD2 in the depth direction of the second trench TR2 is preferably larger. From the viewpoint of improving the insulation characteristics of the second isolation portion EI2, the second length of the second gap VD2 in the width direction of the second trench TR2 is preferably larger. The depth direction of the second trench TR2 is the same as the thickness direction of the semiconductor layer SL.

[0048] The first length of the second gap VD2 may be the same as or different from the first length of the first gap VD1. The second length of the second gap VD2 may be the same as or different from the second length of the first gap VD1.

[0049] In the third trench TR3, a third portion of the third insulating film IF3 is formed on the inner surface of the third trench TR3 such that a portion of the semiconductor substrate SUB is exposed from the third insulating film IF3. The third portion of the third insulating film IF3 suppresses short circuits between the semiconductor layer SL and the conductive film CF. As will be described in detail later, the third portion of the third insulating film IF3, together with the conductive film CF, constitutes the substrate contact SC.

[0050] Examples of materials for the third insulating film IF3 include silicon oxide. The thickness of a portion of the third insulating film IF3 formed on the second insulating film IF2 is, for example, 0.1 μm or more and 1 μm or less. The thickness of a portion of the third insulating film IF3 formed on the inner surfaces of the first trench TR1 and the second trench TR2 is, for example, 0.1 μm or more and 1 μm or less. The thickness of a portion of the third insulating film IF3 formed on the inner surface of the third trench TR3 is, for example, 0.1 μm or more and 1 μm or less.

[0051] A first via V1 is formed in the first interlayer insulating layer IIL1 such that the first via V1 reaches the semiconductor device SE. More specifically, the first via V1 is formed in the first interlayer insulating layer IIL1 such that the first via V1 reaches the source region SR, the drain region DR, or the gate electrode GE. The first via V1 electrically connects the source region SR, the drain region DR, or the gate electrode GE to the first wiring WR1. The first via V1 includes, for example, a barrier film and a conductive film formed on the barrier film. Examples of materials for the barrier film include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). Examples of materials for the conductive film include tungsten (W) and aluminum (Al). The barrier film is not an essential element.

[0052] A conductive film CF is formed on the inner surface of the third trench TR3, with a third insulating film IF3 disposed therebetween. The conductive film CF is electrically connected to the portion of the semiconductor substrate SUB exposed from the third insulating film IF3 in the third trench TR3. As described above, the conductive film CF and the third portion of the third insulating film IF3 together form a substrate contact SC.

[0053] In the width direction of the third trench TR3, the ratio of the conductive film CF inside the third trench TR3 (the thickness of the conductive film CF / the width of the third trench TR3) is preferably 1 / 10 or more and 4 / 5 or less, more preferably 1 / 10 or more and 2 / 3 or less.

[0054] In the plan view, the first length L1 of the third trench TR3 in the extension direction of the third trench TR3 (see...) Figure 1 The first length L1 of the third trench TR3 is greater than the second length L2 in the width direction perpendicular to the extension direction, and the first length is equal to or less than 30 μm. When the first length L1 of the conductive film CF is greater than 30 μm, the reliability of the semiconductor device SD is insufficient. Therefore, the first length L1 of the third trench TR3 is preferably smaller. From the viewpoint of further improving the reliability of the semiconductor device SD, the first length L1 of the third trench TR3 is preferably greater than the second length L2 in the plan view, and the first length is equal to or less than 10 μm, which will be described in detail later. The first length L1 of the third trench TR3 is, for example, the length of the third trench TR3 in the main surface of the semiconductor layer SL.

[0055] In the plan view, the extension direction of the third groove TR3 is perpendicular to the width direction of the third groove TR3. In the plan view, the first length L1 of the third groove TR3 in the extension direction of the third groove TR3 is greater than the second length L2 of the third groove TR3 in the width direction of the third groove TR3.

[0056] The second length L2 of the third trench TR3 in the width direction (reference) Figure 1 and 2 The length L2 of the third trench TR3 is appropriately set according to the burial characteristics of the conductive film CF and the conductivity of the substrate contact SC. For example, the second length L2 of the third trench TR3 is more than 0.1 μm and less than 2 μm. The second length L2 of the third trench TR3 is, for example, the length of the third trench TR3 in the main surface of the semiconductor layer SL.

[0057] The depth D of the third trench TR3 is appropriately set according to the thickness of the semiconductor layer SL. The depth of the third trench TR3 is preferably, for example, 1 μm or more and 100 μm or less, and more preferably 6 μm or more and 30 μm or less.

[0058] The number of conductive films CF (substrate contacts SC) is not particularly limited. In this embodiment, in the plan view, the number of conductive films CF surrounded by a first element isolation portion EI1 is five. In this embodiment, the extension direction of the third trench TR3 is the arrangement direction of the five conductive films CF. In the plan view, the conductive films CF may not be surrounded by the first element isolation portion EI1.

[0059] From the viewpoint of reducing the size of semiconductor device SD, the distance d between the third trench TR3 (substrate contact SC) and the first trench TR1 (first element isolation portion EI1) in the width direction of the third trench TR3 (see...) Figure 1 and 2Preferably, the distance d is small. From this point of view, the distance d is preferably less than 5 μm, more preferably less than 2 μm, and even more preferably less than 1 μm. Here, the distance d is, for example, the distance between the third trench TR3 and the first trench TR1 in the main surface of the semiconductor layer SL.

[0060] On the other hand, from the viewpoint that the distance d is preferably large, it suppresses deformation of the first element isolation portion EI1 caused by stress due to the substrate contact SC, thereby preventing cracks from forming in the first multilayer wiring layer IIL1. From this viewpoint, the distance d is preferably 1 μm or more, more preferably 2 μm or more, and even more preferably 5 μm or more.

[0061] From the viewpoint of simultaneously satisfying the insulation characteristics of the first element isolation portion EI1 and the crack resistance of the first multilayer wiring layer IIL1, the distance d is preferably 1 μm or more and 2 μm or less.

[0062] In the plan view, the shape and position of the third groove TR3 are not particularly limited. The shape of the third groove TR3 in the plan view can be, for example, approximately rectangular, elliptical, or rounded rectangle. In this embodiment, the third groove TR3 extends along the first groove TR1 in the plan view and is surrounded by the first groove TR1.

[0063] In this embodiment, a conductive film CF is formed in a third trench TR3 such that a third void VD3 is formed in the third trench TR3. The third void VD3 is formed within a third portion of the third insulating film IF3. From the viewpoint of improving the conductivity of the substrate contact SC, the first length of the third void VD3 in the depth direction of the third trench TR3 is preferably small. From the viewpoint of improving the conductivity of the substrate contact SC, the second length of the third void VD3 in the width direction of the third trench TR3 is preferably small. The depth direction of the third trench TR3 is the same as the thickness direction of the semiconductor layer SL.

[0064] From the viewpoint of compatibility between the conductivity of the substrate contact SC and the insulation characteristics of the first element isolation portion EI1 and the second element isolation portion EI2, the size of the third gap VD3 in the substrate contact SC is preferably smaller than the size of the first gap VD1 in the first element isolation portion EI1 and the size of the second gap VD2 in the second element isolation portion EI2. More specifically, in the depth direction of the third trench TR3, the first length of the third gap VD3 is smaller than the first length of the first gap VD1 and the first length of the second gap VD2. Preferably, in the width direction of the second trench TR3, the second length of the third gap VD3 is smaller than the second length of the first gap VD1 and the second length of the second gap VD2.

[0065] The material of the conductive film CF is, for example, a conductive metal. Examples of materials for the conductive film CF include tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), copper (Cu), and nickel (Ni).

[0066] A first wiring WR1 is formed on a first interlayer insulating layer IIL1. The first wiring WR1 is electrically connected to the semiconductor substrate SUB via a conductive film CF. For the first wiring WR1, a known structure used for wiring in semiconductor technology can be employed. The first wiring WR1 is, for example, a stacked film in which a barrier metal, a conductive film, and a barrier metal are stacked in this order. Examples of materials constituting the barrier metal include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). Examples of materials for the conductive film include aluminum, copper, and tungsten.

[0067] A second interlayer insulating layer IIL2 is formed on the first interlayer insulating layer IIL1 such that the second interlayer insulating layer IIL2 covers the first wiring WR1. An example of the material of the second interlayer insulating layer IIL2 is silicon oxide.

[0068] A second via V2 is formed within the second interlayer insulating layer IIL2 to electrically connect the first wiring WR1 and the second wiring WR2 to each other. An example of the material for the second via V2 is the same as an example of the material for the first via V1.

[0069] The second wiring WR2 is formed on the second interlayer insulation layer IIL2. An example of the material of the second wiring WR2 is similar to an example of the material of the first wiring WR1.

[0070] A third interlayer insulating layer IIL3 is formed on the second interlayer insulating layer IIL2 such that the third interlayer insulating layer IIL3 covers the second wiring WR2. An example of the material of the third interlayer insulating layer IIL3 is silicon oxide.

[0071] Methods for manufacturing semiconductor devices

[0072] Figures 3 to 10 This is a cross-sectional view illustrating exemplary steps included in a method for manufacturing a semiconductor device SD according to this embodiment.

[0073] The method for manufacturing a semiconductor device SD according to this embodiment includes: (1) providing a semiconductor wafer SW; (2) forming a semiconductor element SE; (3) forming a first insulating film IF1 and a second insulating film IF2; (4) forming a first trench TR1, a second trench TR2 and a third trench TR3; (5) forming a third insulating film IF3; (6) forming a trench TRcf for a conductive film and a via CTv1 for a first via; (7) forming a conductive film CF and a first via V1; and (8) forming the remainder of a multilayer wiring layer MWL.

[0074] (1) Provide semiconductor wafers SW

[0075] like Figure 3 As shown, a semiconductor wafer SW is provided. The semiconductor wafer SW includes a semiconductor substrate SUB and a semiconductor layer SL formed on the semiconductor substrate SUB. The semiconductor wafer SW can be purchased as an off-the-shelf product or manufactured. The semiconductor substrate SUB is held on an electrostatic chuck.

[0076] The semiconductor substrate SUB is, for example, a semiconductor substrate of a first conductivity type or a second conductivity type.

[0077] The semiconductor layer SL comprises a first epitaxial layer EL1, a buried layer BL, a second epitaxial layer EL2, and a buried insulating film BIF. The semiconductor layer SL can be formed using methods known in the semiconductor field for forming semiconductor layers.

[0078] The first epitaxial layer EL1 is formed on the semiconductor substrate SUB by an epitaxial growth method. The buried layer BL is formed on the first epitaxial layer EL1 by ion implantation and activation annealing. The second epitaxial layer EL2 is formed on the buried layer BL by an epitaxial growth method.

[0079] The buried insulating film (BIF) can be formed by etching a recess on the main surface of the second epitaxial layer EL2 and then burying the recess with an insulating film. Alternatively, the buried insulating film (BIF) can be formed by oxidizing a portion of the main surface of the second epitaxial layer EL2 using the LOCOS method.

[0080] (2) Forming a semiconductor element SE

[0081] Subsequently, as Figure 4 As shown, a semiconductor element SE is formed on the main surface of the semiconductor layer SL. There are no particular limitations on the method for forming the semiconductor element SE; any known method can be used. In this embodiment, the semiconductor element SE includes a source region SR, a drain region DR, a gate insulating film GI, and a gate electrode GE.

[0082] The source region SR and drain region DR are formed, for example, by ion implantation and activation annealing. In the plan view, the gate insulating film GI is formed on a portion of the main surface of the semiconductor layer SL located between the source region SR and the drain region DR. The gate electrode GE is formed on the gate insulating film GI.

[0083] (3) Forming the first insulating film IF1 and the second insulating film IF2

[0084] Subsequently, as Figure 5As shown, a first insulating film IF1 and a second insulating film IF2 are formed on the semiconductor layer SL to cover the semiconductor element SE. The method for forming the first insulating film IF1 and the second insulating film IF2 is, for example, CVD.

[0085] (4) Forming the first trench TR1, the second trench TR2 and the third trench TR3

[0086] Subsequently, as Figure 6 As shown, a first trench TR1, a second trench TR2, and a third trench TR3 are formed, extending along the thickness direction of the semiconductor layer SL to reach the semiconductor substrate SUB and penetrating the second insulating film IF2, the first insulating film IF1, and the semiconductor layer SL. In this embodiment, the first trench TR1, the second trench TR2, and the third trench TR3 penetrate the buried insulating film BIF, the second epitaxial layer EL2, the buried layer BL, and the first epitaxial layer EL1 in the semiconductor layer SL. The method for forming the first trench TR1, the second trench TR2, and the third trench TR3 is, for example, a dry etching method.

[0087] (5) Formation of the third insulating film IF3

[0088] Subsequently, as Figure 7 As shown, a third insulating film IF3 is formed in the first trench TR1, the second trench TR2, and the third trench TR3, as well as on the second insulating film IF2. Therefore, the first interlayer insulating layer IIL1 is formed.

[0089] A first void VD1 is formed in the first trench TR1. Therefore, a first element isolation portion EI1 is formed. A second void VD2 is formed in the second trench TR2. Therefore, a second element isolation portion EI2 is formed. A fourth void VD4 is formed in the third trench TR3. The dimensions of the first void VD1, the second void VD2, and the fourth void VD4 are appropriately adjusted according to the aspect ratio (the ratio of trench depth to trench width) of the first trench TR1, the second trench TR2, and the third trench TR3, and the material of the third insulating film IF3. The method for forming the third insulating film IF3 is, for example, CVD.

[0090] (6) Forming a trench TRcf for the conductive film and a via CTv1 for the first via.

[0091] Subsequently, as Figure 8As shown, a trench TRcf for the conductive film and a via CTv1 for the first via are formed. The trench TRcf for the conductive film is a via formed in the third insulating film IF3 to communicate with the fourth void VD4 and expose a portion of the semiconductor substrate SUB. The via CTv1 for the first via is a via that penetrates the first interlayer insulating layer IIL1 to reach the source region SR, the drain region DR, and the gate electrode GE, respectively. The method for forming the trench TRcf for the conductive film and the via CTv1 for the first via is, for example, dry etching.

[0092] (7) Forming the conductive film CF and the first via V1

[0093] Subsequently, as Figure 9 As shown, a conductive film CF and a first via V1 are formed. Specifically, a conductive layer is formed in the trench TRcf for the conductive film and the via CTv1 for the first via, as well as on the third insulating film IF3, and the conductive layer formed outside the trench TRcf for the conductive film and the via CTv1 for the first via is removed. The conductive film CF is formed on the third insulating film IF3 to be electrically connected to the semiconductor substrate SUB, and the third insulating film IF3 is formed on the inner surface of the third trench TR3. The method for forming the conductive layer is, for example, CVD. The method for removing the conductive layer is, for example, CMP. The conductive layer is removed (polished) in the following state: a CMP slurry is applied to the conductive layer. After the CMP treatment, a cleaning solution is provided on the surface to be polished.

[0094] (8) Form the remaining part of the multilayer wiring layer (MWL).

[0095] Subsequently, as Figure 10 As shown, a first wiring WR1, a second interlayer insulating layer IL2, a second via V2, a second wiring WR2, and a third interlayer insulating layer IL3 are formed.

[0096] The second interlayer insulating layer IIL2 and the third interlayer insulating layer IIL3 are formed, for example, by CVD. The first wiring WR1 is formed by sputtering a conductive layer onto the first interlayer insulating layer IIL1 and then patterning the conductive layer into a desired pattern. The second wiring WR2 is formed by sputtering a conductive layer onto the second interlayer insulating layer IIL2 and then patterning the conductive layer into a desired pattern. The second via V2 is formed by forming a via in the second interlayer insulating layer IIL2 and then burying the via with a conductive material.

[0097] Subsequently, the structure obtained through the above steps is separated from the electrostatic chuck and cut into small pieces to obtain multiple monolithic semiconductor devices (SDs).

[0098] The semiconductor device SD according to this embodiment is manufactured by the above-described manufacturing method. The method for manufacturing the semiconductor device SD according to this embodiment may also include other steps as needed. Other steps may be appropriately adopted based on methods known in the semiconductor field.

[0099] [simulation]

[0100] A simulation was performed to study the relationship between the stress induced by the substrate contact SC and the dimensions of the substrate contact SC. The simulation used a viscoelastic model and took into account the process temperatures during the formation of each element. The conditions for this simulation are as follows.

[0101] The semiconductor layer SL is made of silicon. The first insulating film IF1 is made of silicon nitride (SiN). The second insulating film IF2 and the third insulating film IF3 are made of silicon oxide (SiO2). The conductive film CF is made of tungsten (W).

[0102] The width of the third trench TR3 is 0.90 μm. The length of the conductive film CF in the width direction of the third trench TR3 is 0.60 μm. The thickness of the third insulating film IF3, formed on the inner surface of the third trench TR3, in the width direction of the third trench TR3 is 0.15 μm.

[0103] Simulations were performed on the third trench TR3 with depths of 4 μm, 8 μm, 12 μm and 16 μm.

[0104] Figure 11 This is a graph showing the relationship between the stress induced by the substrate contact SC and the dimensions of the substrate contact SC. The horizontal axis represents the length L1 [μm] of the third trench TR3 in its extension direction. The vertical axis represents the width ΔW of the third gap VD3 at the upper end of the conductive film CF. The width of the third gap VD3 is its length in the width direction of the third trench TR3. As the width of the third gap VD3 increases, this indicates that the stress induced by the substrate contact SC is greater.

[0105] exist Figure 11 In the diagram, the black circle represents the simulation result when the depth of the third trench TR3 is 16 μm. The black square represents the simulation result when the depth of the third trench TR3 is 12 μm. The black triangle represents the simulation result when the depth of the third trench TR3 is 8 μm. The black rhombus represents the simulation result when the depth of the third trench TR3 is 4 μm.

[0106] like Figure 11As shown, regardless of the depth of the third trench TR3, the width ΔW of the third gap VD3 decreases as the length L1 of the third trench TR3 decreases. Specifically, it can be seen that when the length L1 of the third trench TR3 is less than 30 μm, the width ΔW of the third gap VD3 decreases rapidly. When the length L1 of the third trench TR3 is less than 10 μm, the width ΔW of the third gap VD3 becomes negligible. Therefore, when the length L1 of the third trench TR3 is less than 10 μm, the third gap VD3 of the conductive film CF is essentially closed, i.e., it can be ignored.

[0107] Simulation results show that when the length L1 of the third trench TR3 is less than 30 μm, the cleaning solution used in the CMP step is unlikely to enter the third void VD3 of the conductive film CF. Therefore, the reliability of the semiconductor device SD is improved. When the length L1 of the third trench TR3 is less than 10 μm, the cleaning solution used in the CMP step is unlikely to penetrate into the third void VD3 of the conductive film CF. Therefore, the reliability of the semiconductor device SD is further improved.

[0108] [Reference Experiment]

[0109] Subsequently, a reference experiment was performed to investigate the relationship between the stress induced by the substrate contact SC and the distance from the substrate contact SC. Here, the distance from the substrate contact SC is the distance from the opening end of the third trench TR3 in the width direction of the third trench TR3.

[0110] In a reference experiment, the current characteristics of a MOSFET formed at a predetermined distance from the substrate contact SC were evaluated. Subsequently, based on the results obtained through the above simulation (the relationship between the stress caused by the substrate contact SC and the size of the substrate contact SC), the impact on the current characteristics was estimated for cases where the length L1 of the third trench TR3 is 5 μm and 50 μm, respectively.

[0111] Figure 12 This is a graph showing the relationship between the stress caused by the substrate contact SC and the distance from the substrate contact SC. The horizontal axis represents the distance d [μm] from the third trench TR3 in the width direction of the third trench TR3. The vertical axis represents the rate of change ΔI [%] of the MOSFET's current characteristics. The greater the rate of change of the MOSFET's current characteristics, the greater the stress caused by the substrate contact SC.

[0112] exist Figure 12 In the diagram, the solid line represents the simulation results when the length L1 of the third trench TR3 is 5 μm. The dashed line represents the simulation results when the length L1 of the third trench TR3 is 50 μm.

[0113] From comparison Figure 12As can be clearly seen from the solid and dashed lines, the smaller the length L1 of the third trench TR3, the smaller the rate of change ΔI of the MOSFET's current characteristics. For example, if the length L1 of the third trench TR3 is 50 μm, then when the distance d from the substrate contact SC decreases from 5 μm to 1 μm, the rate of change ΔI decreases by approximately 10%. On the other hand, when the length L1 of the third trench TR3 is 5 μm, even if the distance d from the substrate contact SC decreases from 5 μm to 1 μm, the rate of change ΔI only decreases by approximately 3%.

[0114] The results of the reference experiment show that when the length L1 of the third trench TR3 is small, the stress generated near the substrate contact SC can be reduced. Therefore, in the semiconductor device SD according to this embodiment, the first element isolation portion EI1, the second element isolation portion EI2, and the semiconductor element SE can be formed even near the substrate contact SC. For example, when the first gap VD1 is formed in the first element isolation portion EI1, the stress concentrates at the top of the first gap VD1 and tends to generate cracks in the first interlayer insulating layer IIL1. However, in the semiconductor device SD according to this embodiment, since the length L1 of the third trench TR3 is 30 μm or less, the first element isolation portion EI1 can be formed near the substrate contact SC. For example, in the width direction of the third trench TR3, the first element isolation portion EI1 can be formed in a range of 1 μm or more and 2 μm or less from the third trench TR3.

[0115] (Effect)

[0116] In the semiconductor device SD according to this embodiment, the first length L1 of the third trench TR3 in the extension direction of the third trench TR3 is greater than the second length of the third trench TR3 in the width direction perpendicular to the extension direction, and the first length is equal to or less than 30 μm. When the length L1 of the third trench TR3 is less than 30 μm, the stress caused by the third insulating film IF3 and the conductive film CF formed in the third trench TR3 decreases rapidly. Therefore, the third void VD3 formed in the conductive film CF is easily formed in a closed state through the conductive film CF. Therefore, during the CMP step for forming the conductive film CF, it is unlikely that the cleaning liquid will enter the third void VD3 in the conductive film CF. The formation of reaction products between the material of the conductive film CF and the cleaning liquid is suppressed. Therefore, short circuits between adjacent wirings caused by reaction products are suppressed. For example, short circuits between the first wiring WR1 and the second wiring WR2 caused by reaction products are suppressed. As described above, according to this embodiment, the reliability of the semiconductor device SD can be improved.

[0117] [Modified Example]

[0118] Figure 13This is an enlarged perspective view showing an exemplary configuration of the main parts of a semiconductor device according to a modified example. More specifically, Figure 13 This is an enlarged perspective view showing an exemplary configuration of the via mV according to the modified example. For example, Figure 13 It shows the relationship with Figure 12 The area enclosed by the dashed line corresponds to the area in the diagram. Figure 13 For clarity, the second interlayer insulation layer IL2 and the third interlayer insulation layer IL3 have been omitted.

[0119] The stress on the substrate contact SC has been described in the above embodiments, but the present invention is not limited to these embodiments. For example, as... Figure 13 As shown, for vias formed in a multilayer wiring layer (MWL), the semiconductor device according to the modified example includes a second via mV2 formed in a trench mTR. That is, the first length mL1 of the trench mTR for the via in its extension direction can be greater than the second length mL2 of the trench mTR for the via in its width direction perpendicular to the extension direction, and the first length mL1 is equal to or less than 30 μm. The second via mV2 is a so-called slot via. The first length mL1 of the trench mTR for the via in its extension direction is greater than the second length mL2 of the trench mTR for the via in its width direction. Because the trench mTR for the via is formed in an interlayer insulating layer, the insulating film on the inner surface of the trench mTR for the via is not an essential element.

[0120] The simulation results clearly show that regardless of the depth of the trench in which the conductive film is formed, the stress caused by the conductive film decreases as the length of the trench in its extension direction decreases. For example, regardless of the depth of the trench in which the conductive film is formed, the stress caused by the conductive film decreases rapidly when the trench length is less than 30 μm. Therefore, the simulation results clearly demonstrate that this invention can be applied not only to substrate contacts SC, but also to the second via mV2 in a multilayer wiring layer MWL.

[0121] It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit. For example, the insulating film formed in the first trench TR1, the insulating film formed in the second trench TR2, and the insulating film formed in the third trench TR3 can be formed of the same material or can be formed of different materials.

[0122] Furthermore, even when describing a specific numerical example, it can be a value exceeding or falling below that specific value, except where it is theoretically clearly limited to that value. Additionally, a component refers to "B that contains A as the main component," etc., and does not exclude patterns that include other components.

[0123] Furthermore, at least a portion of the embodiments and at least a portion of the modifications can be arbitrarily combined with each other. The semiconductor device may include: a substrate contact SC formed in a third trench TR3; and a second via mV2 formed in a trench mTR for vias.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; A semiconductor layer is formed on the semiconductor substrate, the semiconductor layer having a first trench and a second trench, both the first trench and the second trench extending along the depth direction such that the first trench and the second trench extend toward the semiconductor substrate; A first insulating film is formed on the inner surface of each of the first trench and the second trench, such that a portion of the semiconductor substrate is exposed in each of the first trench and the second trench; as well as A conductive film, electrically connected to the semiconductor substrate, is formed on the inner surface of each of the first and second trenches via the first insulating film. In the plan view, the first groove extends a first length in an extension direction perpendicular to the depth direction. In the plan view, the second groove extends a third length in an extension direction perpendicular to the depth direction. In the plan view, the first groove extends a second length in the width direction perpendicular to both the depth direction and the extension direction. In the plan view, the second groove extends a fourth length in the width direction perpendicular to both the depth direction and the extension direction. In the plan view, the first length of the first groove extending in the extension direction is greater than the second length of the first groove extending in the width direction. In the plan view, the third length of the second groove extending in the extension direction is greater than the fourth length of the second groove extending in the width direction. Wherein the first length of the first trench and the third length of the second trench are equal to or less than 30 μm. The first groove and the second groove are arranged in the extending direction. The semiconductor device further includes a second insulating film formed in a third trench in the semiconductor layer such that the third trench extends in the depth direction and toward the semiconductor substrate. The first trench is surrounded by the third trench in the plan view.

2. The semiconductor device according to claim 1, in, In the plan view, the first length is greater than the second length. In the plan view, the third length is greater than the fourth length, and The first length and the third length are equal to or less than 10 μm.

3. The semiconductor device according to claim 1, wherein, The second insulating film is formed in the third trench, such that a first void is formed within the second insulating film.

4. The semiconductor device of claim 1, wherein the first trench and the second trench extend along the third trench in a plan view.

5. The semiconductor device according to claim 4, wherein, In the plan view, the distance between the first trench and the third trench, and the distance between the second trench and the third trench, are greater than 1 μm and less than 2 μm in the width direction.

6. The semiconductor device according to claim 1, wherein, In the plan view, the distance between the first trench and the third trench, and the distance between the second trench and the third trench, are greater than 1 μm and less than 2 μm in the width direction.

7. The semiconductor device of claim 1, further comprising a third insulating film formed on the semiconductor layer. in, The first trench and the second trench penetrate the third insulating film and the semiconductor layer, such that the first trench and the second trench extend toward the semiconductor substrate.

8. The semiconductor device of claim 1, further comprising a third insulating film formed on the semiconductor layer. in, The first trench, the second trench, and the third trench penetrate the third insulating film and the semiconductor layer, such that the first trench, the second trench, and the third trench extend toward the semiconductor substrate.

9. The semiconductor device of claim 7, comprising wiring formed on the third insulating film. The wiring is electrically connected to the semiconductor substrate through a conductive film.

10. The semiconductor device according to claim 3, in, The conductive film is formed in each of the first trench and the second trench, such that a second void is formed within the conductive film in each of the first trench and the second trench. The length of the second gap is less than the length of the first gap in the thickness direction of the semiconductor layer.

11. The semiconductor device of claim 1, wherein the material of the conductive film comprises tungsten.

12. The semiconductor device of claim 1, wherein the semiconductor substrate has a first conductivity type, and The semiconductor layer includes: The first buried layer has a second conductivity type opposite to the first conductivity type; as well as A second epitaxial layer is formed on the first buried layer.

13. A method of manufacturing a semiconductor device, comprising: (a) Providing a semiconductor wafer, the semiconductor wafer comprising: Semiconductor substrates; and A semiconductor layer formed on the semiconductor substrate; (b) Forming a first trench and a second trench, the first trench and the second trench extending in the depth direction and penetrating the semiconductor layer to extend toward the semiconductor substrate; (c) Forming an insulating film on the inner surface of each of the first trench and the second trench, such that a portion of the semiconductor substrate is exposed in each of the first trench and the second trench; and (d) A conductive film is formed on the insulating film formed on the inner surface of each of the first trench and the second trench to electrically connect to the semiconductor substrate. In the plan view, the first groove extends a first length in an extension direction perpendicular to the depth direction. In the plan view, the second groove extends a third length in an extension direction perpendicular to the depth direction. In the plan view, the first groove extends a second length in a width direction perpendicular to both the depth direction and the extension direction; and in the plan view, the second groove extends a fourth length in a width direction perpendicular to both the depth direction and the extension direction. In the plan view, the first length of the first groove extending in the extension direction is greater than the second length of the first groove extending in the width direction. Wherein the first length of the first trench and the third length of the second trench are equal to or less than 30 μm, and The first groove and the second groove are arranged in the extending direction. The method further includes (e) forming a third trench penetrating the semiconductor layer to extend toward the semiconductor substrate, and (f) forming a second insulating film in the third trench. The first trench is surrounded by the third trench in the plan view.

14. The method according to claim 13, in, In the plan view, the first length is greater than the second length. In the plan view, the third length is greater than the fourth length, and The first length and the third length are equal to or less than 10 μm.

15. The method according to claim 13, in, In the plan view, the distance between the first groove and the second groove, and the distance between the second groove and the third groove, are greater than 1 μm and less than 2 μm in the width direction.

16. A semiconductor device, comprising: Semiconductor substrate; A semiconductor layer formed on the semiconductor substrate; A first trench is formed in the semiconductor layer, the first trench extending a first length in the extension direction in a plan view; A second trench is formed in the semiconductor layer, the second trench extending a second length in the extending direction in a plan view; A third trench is formed in the semiconductor layer, the third trench surrounding the first trench and the second trench in a plan view; A first insulating film is formed on the inner surface of each of the first trench and the second trench; A second insulating film is formed in the third trench; as well as A conductive film is formed, through the first insulating film, on the inner surface of each of the first and second trenches. The first groove and the second groove are arranged adjacent to each other in the extending direction, and Each of the first length of the first trench and the second length of the second trench is equal to or less than 30 μm.

17. The semiconductor device according to claim 16, The first trench, the second trench, and the third trench extend toward the semiconductor substrate in the depth direction. In the plan view, the first groove extends a third length in the width direction perpendicular to the extending direction. In the plan view, the second groove extends a fourth length in the width direction. The first length is greater than the third length of the first trench, and the second length is greater than the fourth length of the second trench.

18. The semiconductor device according to claim 17, The conductive film is electrically connected to the semiconductor substrate.

19. The semiconductor device according to claim 17, Each of the first length and the second length is equal to or less than 10 μm.

20. The semiconductor device according to claim 17, The second insulating film is formed in the third trench, thereby creating a first void within the second insulating film.

21. The semiconductor device according to claim 17, in, In the plan view, the distance between the first trench and the third trench, and the distance between the second trench and the third trench, are greater than 1 μm and less than 2 μm in the width direction.

22. The semiconductor device of claim 17, comprising A third insulating film is formed on the semiconductor layer. in, The first trench, the second trench, and the third trench penetrate the third insulating film, such that the first trench, the second trench, and the third trench extend toward the semiconductor substrate.

23. The semiconductor device of claim 22, comprising: Wiring formed on the third insulating film, The wiring is electrically connected to the semiconductor substrate through the conductive film.

24. The semiconductor device according to claim 20, The conductive film is formed in each of the first trench and the second trench, such that a second void is formed within the conductive film in each of the first trench and the second trench. in, In the thickness direction of the semiconductor layer, the length of the second gap is less than the length of the first gap.

25. The semiconductor device according to claim 17, The conductive film is made of tungsten.

26. The semiconductor device according to claim 17, The semiconductor substrate has a first conductivity type, and The semiconductor layer includes: A first buried layer having a second conductivity type opposite to the first conductivity type; as well as A second epitaxial layer is formed on the first buried layer.

27. The semiconductor device according to claim 26, The first trench, the second trench, and the third trench penetrate the first buried layer and the second epitaxial layer.

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