Display device

Abstract

Embodiments of the present invention relate to a display device, the display device comprising: a substrate including a display area and a non-display area outside the display area; a planarization layer above the substrate, wherein a first contact hole, a second contact hole, and a dummy hole are defined to pass through the planarization layer; a first pixel on the planarization layer and including a first pixel electrode, wherein the first pixel electrode overlaps with the first contact hole and the dummy hole; and a second pixel on the planarization layer and including a second pixel electrode, wherein the second pixel electrode overlaps with the second contact hole.

Description

Technical Field

[0001] One or more embodiments relate to a display device, and more particularly, to a display device with reduced color separation caused by reflected light. Background Art

[0002] Generally, a display device can be used in various environments. Thus, a display device can be used in an external light environment. In particular, when the display device is a mobile device, there is a high possibility that the mobile device is used in an environment with external light in an outdoor space. Summary of the Invention

[0003] However, in a conventional display device, color bands may be observed because external light is reflected by the display device.

[0004] One or more embodiments include a display device that can reduce the degree of appearance of color bands caused by external light reflection.

[0005] According to an embodiment, a display device includes: a substrate including a display area and a non-display area outside the display area; a planarization layer above the substrate, wherein a first contact hole, a second contact hole, and a dummy hole are defined to pass through the planarization layer; a first pixel on the planarization layer and including a first pixel electrode, wherein the first pixel electrode overlaps with the first contact hole and the dummy hole; and a second pixel on the planarization layer and including a second pixel electrode, wherein the second pixel electrode overlaps with the second contact hole.

[0006] In an embodiment, the first pixel electrode and the second pixel electrode may be inclined in the same direction as each other.

[0007] In an embodiment, the display device may further include: a pixel defining layer on the first pixel electrode, wherein a first opening is defined to pass through the pixel defining layer to expose at least a part of the first pixel electrode, and the first contact hole and the dummy hole may be separated from each other, and the first opening of the pixel defining layer is located between the first contact hole and the dummy hole.

[0008] In an embodiment, the dummy hole may overlap with the pixel defining layer.

[0009] In an embodiment, the pixel defining layer may include a light-shielding material.

[0010] In an embodiment, the planarization layer may include a first planarization layer and a second planarization layer, and the first contact hole may be defined in the first planarization layer and the second planarization layer.

[0011] In one embodiment, the dummy holes may be defined in the first planarization layer and the second planarization layer.

[0012] In one embodiment, the dummy holes may be defined only in the second planarization layer.

[0013] In one embodiment, the first planarization layer and the second planarization layer may include different materials from each other.

[0014] In one embodiment, the display device may further include: a first thin film transistor and a second thin film transistor, each of the first thin film transistor and the second thin film transistor being above the substrate, wherein the first thin film transistor may be connected to the first pixel electrode through the first contact hole, and the second thin film transistor may be connected to the second pixel electrode through the second contact hole.

[0015] In one embodiment, the first pixel may further include a first intermediate layer on the first pixel electrode, the second pixel may further include a second intermediate layer on the second pixel electrode, one of the first intermediate layer and the second intermediate layer emits light with a green wavelength, and the other of the first intermediate layer and the second intermediate layer emits light with a red or blue wavelength.

[0016] In one embodiment, the first intermediate layer may emit light with the red or blue wavelength, and the second intermediate layer may emit light with the green wavelength.

[0017] In one embodiment, the display device may further include: a light-shielding layer overlapping with the pixel defining layer, wherein a second opening is defined to pass through the light-shielding layer, the light-shielding layer may be separated from the dummy holes by a first distance, and the first distance may be defined as the shortest distance between the inner surface of the second opening and the dummy holes.

[0018] According to one embodiment, a display device includes: a first thin film transistor and a second thin film transistor, each of the first thin film transistor and the second thin film transistor being above the substrate; a planarization layer above the substrate, wherein a first contact hole, a second contact hole, and dummy holes are defined to pass through the planarization layer; a first pixel electrode on the planarization layer, overlapping with the dummy holes, and connected to the first thin film transistor through the first contact hole; and a second pixel electrode on the planarization layer and connected to the second thin film transistor through the second contact hole.

[0019] In one embodiment, the first pixel electrode and the second pixel electrode may be inclined in the same direction as each other.

[0020] In one embodiment, the display device may further include: a pixel defining layer on the first pixel electrode and the second pixel electrode, wherein an opening is defined to pass through the pixel defining layer to expose at least a part of the first pixel electrode and the second pixel electrode, and the first contact hole may be separated from the dummy hole, and the opening of the pixel defining layer is located between the first contact hole and the dummy hole.

[0021] In one embodiment, the planarization layer may include a first planarization layer and a second planarization layer, and the first contact hole may be defined in the first planarization layer and the second planarization layer.

[0022] In one embodiment, the dummy hole may be defined in the first planarization layer and the second planarization layer.

[0023] In one embodiment, the dummy hole may be defined only in the second planarization layer.

[0024] In one embodiment, the display device may further include: a first intermediate layer and a second intermediate layer, the first intermediate layer and the second intermediate layer are respectively on the first pixel electrode and the second pixel electrode; and a counter electrode covering the first intermediate layer and the second intermediate layer, wherein one of the first intermediate layer and the second intermediate layer emits light with a green wavelength, and the other of the first intermediate layer and the second intermediate layer emits light with a red or blue wavelength.

[0025] These and / or other features of the embodiments of the present invention will become apparent and more readily understood from the following description of the embodiments, the drawings, and the claims. Description of the Drawings

[0026] The above and other features of the embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the drawings, in which:

[0027] Figure 1 is a perspective view of a display device according to an embodiment;

[0028] Figure 2 is a plan view of a display device according to an embodiment;

[0029] Figure 3 and Figure 4 is an equivalent circuit diagram of a pixel in a display device according to an embodiment;

[0030] Figure 5 is a plan view of a display device according to an embodiment;

[0031] Figure 6 is a cross-sectional view of a display device according to an embodiment;

[0032] Figure 7A , Figure 7B and Figure 7C are schematic views of a display device according to an embodiment;

[0033] Figure 8 and Figure 9 are cross-sectional views of a display device according to an alternative embodiment;

[0034] Figure 10 is a plan view of a display device according to an alternative embodiment;

[0035] Figure 11 is a cross-sectional view of a display device according to an embodiment;

[0036] Figure 12A , Figure 12B , Figure 12C are plan views of a display device according to an embodiment; and

[0037] Figure 13 and Figure 14 are cross-sectional views of a display device according to alternative embodiments. Specific Embodiments

[0038] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

[0039] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0040] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, one component, one region, one layer or one section from another element, another component, another region, another layer or another section. Thus, the "first element", "first component", "first region", "first layer" or "first section" discussed below may be referred to as a second element, second component, second region, second layer or second section without departing from the teachings herein.

[0041] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to be limiting. Unless the context clearly dictates otherwise, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. As used herein, “at least one of A and B” means A, B, or both A and B. Throughout the disclosure, the statement “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof. It will also be understood that when used in the specification, the terms “comprises” and / or “comprising” and / or “includes” and / or “including” indicate the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0042] Additionally, relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship of one element to another as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is flipped, an element described as on the “lower” side of another element will then be oriented on the “upper” side of the other element. Thus, the exemplary term “lower” can encompass both the orientation of “lower” and the orientation of “upper,” depending on the specific orientation of the figure. Similarly, if the device in one of the figures is flipped, an element described as “beneath” or “under” another element will then be oriented “above” the other element. Thus, the exemplary terms “beneath” or “under” can encompass both the orientation of “above” and the orientation of “beneath.”

[0043] Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, “about” or “approximately” includes the stated value and means within an acceptable deviation range for the particular value as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense.

[0045] As used herein, when a wiring is said to "extend in a first direction or a second direction", this means that the wiring extends not only in a straight shape in the first direction or the second direction, but also in a zigzag or in a curve in the first direction or the second direction.

[0046] As used herein, "in a plan view" means observing the target part from above, and "in a cross-sectional view" means observing a vertically intercepted cross-section of the target part from the side. As used herein, "overlap with..." includes "overlap with... in a plan view" and "overlap with... in a cross-sectional view".

[0047] Embodiments are described herein with reference to cross-sectional views, which are schematic views of idealized embodiments. Thus, for example, deviations from the shape of the views due to manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but will include, for example, deviations in shape resulting from manufacturing. For example, a region shown or described as flat may typically have rough and / or non-linear features. Moreover, the sharp corners shown may be rounded. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the exact shape of the regions and are not intended to limit the scope of the invention.

[0048] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0049] Figure 1 is a perspective view of a display device 1 according to an embodiment.

[0050] Reference Figure 1 , an embodiment of the display device 1 includes a display area DA and a non-display area NDA outside the display area DA. The non-display area NDA may surround the display area DA. The display device 1 may display an image by using light emitted from a plurality of pixels P arranged in the display area DA. The non-display area NDA may include an area where no image is displayed.

[0051] Hereinafter, for ease of description, an embodiment in which the display device 1 is an organic light-emitting display device will be described in detail, but the display device 1 is not limited thereto. In an alternative embodiment, the display device 1 may be another type of display device, such as an inorganic light-emitting display or a quantum dot light-emitting display. In one embodiment, for example, the emission layer of the display element of the display device 1 may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

[0052] Figure 1 An embodiment is shown in which the display device 1 has a flat display surface, but the embodiment is not limited thereto. In an alternative embodiment, the display device 1 may include a three-dimensional display surface or a curved display surface.

[0053] In an embodiment in which the display device 1 includes a three-dimensional display surface, the display device 1 may include a plurality of display regions indicating different directions and may include, for example, a multi-prism type display surface. In an embodiment in which the display device 1 includes a curved display surface, the display device 1 may be implemented in various forms such as a flexible display device, a foldable display device, or a rollable display device.

[0054] Figure 1 An embodiment is shown in which the display device 1 is a mobile phone terminal. Although not shown, in such an embodiment, electronic modules, camera modules, power modules, etc. mounted on the main board may be arranged together with the display device 1 on the bracket / case so that the mobile phone terminal can be configured. In one embodiment, the display device 1 can be applied to small and medium-sized electronic devices such as tablet personal computers, car navigation devices, game consoles, and smart watches, as well as large electronic devices such as televisions and monitors.

[0055] Figure 1 An embodiment is shown in which the display area DA of the display device 1 is quadrilateral, but the embodiment is not limited thereto. Alternatively, the display area DA may have a circular shape, an oval shape, or a polygonal shape such as a triangle or a pentagon.

[0056] Figure 2 is a plan view of the display device 1 according to an embodiment.

[0057] Reference Figure 2, An embodiment of the display device 1 includes a plurality of pixels P arranged in the display area DA. Each of the plurality of pixels P may include a display element such as an organic light emitting diode OLED. Each of the plurality of pixels P may emit, for example, red light, green light, blue light, or white light from the organic light emitting diode OLED. In an embodiment as described above, the pixel P of the display device 1 may include pixels that emit red light, green light, blue light, or white light, that is, red pixels, green pixels, blue pixels, or white pixels.

[0058] Each pixel P may be electrically connected to an external circuit arranged in the non-display area NDA. The first scan driving circuit 110, the first emission driving circuit 115, the second scan driving circuit 120, the second emission driving circuit 125, the terminal 140, the data driving circuit 150, the first power supply line 160, and the second power supply line 170 may be arranged in the non-display area NDA.

[0059] The first scan driving circuit 110 may provide a scan signal to each pixel P through the scan line SL. The first emission driving circuit 115 may provide an emission control signal to each pixel P through the emission control line EL. The second scan driving circuit 120 may be arranged in parallel with the first scan driving circuit 110, and the display area DA is between the second scan driving circuit 120 and the first scan driving circuit 110. Some of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 110, and the remaining pixels of the pixel P may be electrically connected to the second scan driving circuit 120. The second emission driving circuit 125 may be arranged in parallel with the first emission driving circuit 115, and the display area DA is between the second emission driving circuit 125 and the first emission driving circuit 115. Some of the pixels P arranged in the display area DA may be electrically connected to the first emission driving circuit 115, and the remaining pixels of the pixel P may be electrically connected to the second emission driving circuit 125.

[0060] In an embodiment, the first emission driving circuit 115 may be separated from the first scan driving circuit 110 in the x direction and arranged in the non-display area NDA. In such an embodiment, the first emission driving circuit 115 may be arranged alternately with the first scan driving circuit 110 in the y direction.

[0061] In an embodiment, the second emission driving circuit 125 may be separated from the second scan driving circuit 120 in the x direction and arranged in the non-display area NDA. In such an embodiment, the second emission driving circuit 125 may be arranged alternately with the second scan driving circuit 120 in the y direction.

[0062] The terminal 140 may be disposed on one side or an edge portion of the substrate 100. The terminal 140 may be exposed by not being covered with an insulating layer and may be electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display device 1. The printed circuit board PCB transmits signals or power of a controller (not shown) to the display device 1. The control signal generated by the controller may be transmitted to the first scan driving circuit 110, the first emission driving circuit 115, the second scan driving circuit 120, and the second emission driving circuit 125 through the printed circuit board PCB. The controller may supply the first power voltage ELVDD (see Figure 3 )(also referred to as a driving voltage) and the second power voltage ELVSS (see Figure 3 )(also referred to as a common voltage) to the first power line 160 and the second power line 170 through the first connection line 161 and the second connection line 171, respectively. The first power voltage ELVDD may be supplied to the pixel P through the driving voltage line PL connected to the first power line 160, and the second power voltage ELVSS may be supplied to the opposite electrode of the pixel P connected to the second power line 170.

[0063] In an embodiment of the display device 1, the data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be supplied to each pixel P through the connection line 151 and the data line DL. The connection line 151 is connected to the terminal 140, and the data line DL is connected to the connection line 151.

[0064] In an embodiment, as shown in Figure 2 , the data driving circuit 150 may be disposed on the printed circuit board PCB, but the embodiment is not limited thereto. Alternatively, the data driving circuit 150 may be disposed on the substrate 100. In one embodiment, for example, the data driving circuit 150 may be disposed between the terminal 140 and the first power line 160.

[0065] The first power line 160 may include a first sub-line 162 and a second sub-line 163. The first sub-line 162 and the second sub-line 163 extend parallel to each other in the x direction, and the display area DA is between the first sub-line 162 and the second sub-line 163. The second power line 170 may have an annular shape with an open side and may partially surround the display area DA.

[0066] Figure 3 And Figure 4 are equivalent circuit diagrams of the pixel P in the display device 1 according to the embodiment.

[0067] Refer to Figure 3, an embodiment of pixel P includes a pixel circuit PC and an organic light-emitting diode OLED. Among them, the pixel circuit PC is connected to a scan line SL and a data line DL, and the organic light-emitting diode OLED is connected to the pixel circuit PC.

[0068] The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and based on a scan signal Sn input through the scan line SL, transmits a data signal Dm input through the data line DL to the driving thin-film transistor T1.

[0069] The storage capacitor Cst is connected to the switching thin-film transistor T2 and a driving voltage line PL, and stores a voltage corresponding to the difference between the voltage transmitted from the switching thin-film transistor T2 and the first power supply voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0070] The driving thin-film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage stored in the storage capacitor Cst. The organic light-emitting diode OLED can emit light with a brightness corresponding to the driving current.

[0071] In one embodiment, as Figure 3 shown, the pixel circuit PC includes two thin-film transistors T1, T2 and a single storage capacitor Cst, but the embodiment is not limited thereto. In an alternative embodiment, as Figure 4 shown, the pixel circuit PC may include seven thin-film transistors T1, T2, T3, T4, T5, T6 and T7 and a single storage capacitor Cst.

[0072] Referring to Figure 4 , an embodiment of pixel P includes a pixel circuit PC and an organic light-emitting diode OLED, and the organic light-emitting diode OLED is electrically connected to the pixel circuit PC. The pixel circuit PC may include a plurality of thin-film transistors T1, T2, T3, T4, T5, T6 and T7 and a storage capacitor Cst. The plurality of thin-film transistors T1, T2, T3, T4, T5, T6 and T7 and the storage capacitor Cst may be connected to signal lines SL, SL-1, SL+1, EL and DL, a first initialization voltage line VL1, a second initialization voltage line VL2, and a driving voltage line PL.

[0073] The signal lines SL, SL-1, SL+1, EL, and DL may include a scan line SL, a previous scan line SL-1, a next scan line SL+1, an emission control line EL, and a data line DL. In such an embodiment, the scan line SL may transmit a scan signal Sn, the previous scan line SL-1 may transmit a previous scan signal Sn-1 to the first initialization thin film transistor T4, the next scan line SL+1 may transmit the scan signal Sn to the second initialization thin film transistor T7, the emission control line EL may transmit an emission control signal to the operation control thin film transistor T5 and the emission control thin film transistor T6, and the data line DL intersecting with the scan line SL may transmit a data signal Dm. The driving voltage line PL may transmit a driving voltage ELVDD to the driving thin film transistor T1, the first initialization voltage line VL1 may transmit an initialization voltage Vint to the first initialization thin film transistor T4, and the second initialization voltage line VL2 may transmit the initialization voltage Vint to the second initialization thin film transistor T7.

[0074] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the first electrode CE1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL through the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm based on the switching operation of the switching thin film transistor T2, and supplies a driving current I OLED to the organic light emitting diode OLED.

[0075] The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL. The switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, and the switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and is simultaneously connected to the driving voltage line PL through the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to the scan signal Sn transmitted through the scan line SL, and performs a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0076] The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL. The compensation source electrode S3 of the compensation thin film transistor T3 is connected to the drive drain electrode D1 of the drive thin film transistor T1 and is simultaneously connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. And the compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the first electrode CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the drive gate electrode G1 of the drive thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line SL, and diode-connects the drive thin film transistor T1 by electrically connecting the drive gate electrode G1 of the drive thin film transistor T1 to the drive drain electrode D1 of the drive thin film transistor T1.

[0077] The first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the first initialization voltage line VL1. And the first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the first electrode CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the drive gate electrode G1 of the drive thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and performs an initialization operation of initializing the voltage of the drive gate electrode G1 of the drive thin film transistor T1 by transmitting the initialization voltage Vint to the drive gate electrode G1 of the drive thin film transistor T1.

[0078] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL. The operation control source electrode S5 of the operation control thin film transistor T5 is connected to the drive voltage line PL. And the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the drive source electrode S1 of the drive thin film transistor T1 and the switch drain electrode D2 of the switch thin film transistor T2.

[0079] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL. The emission control source electrode S6 of the emission control thin film transistor T6 is connected to the drive drain electrode D1 of the drive thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3. And the emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0080] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to an emission control signal En transmitted through an emission control line EL, a driving voltage ELVDD is transmitted to the organic light emitting diode OLED, and a driving current I OLED flows through the organic light emitting diode OLED.

[0081] A second initialization gate electrode G7 of a second initialization thin film transistor T7 is connected to a subsequent scan line SL+1, a second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to an emission control drain electrode D6 of the emission control thin film transistor T6 and a pixel electrode of the organic light emitting diode OLED, and a second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to a second initialization voltage line VL2.

[0082] In an embodiment in which the scan line SL is electrically connected to the subsequent scan line SL+1, the same scan signal Sn may be applied to the scan line SL and the subsequent scan line SL+1. Accordingly, the second initialization thin film transistor T7 may be turned on in response to the scan signal Sn transmitted through the subsequent scan line SL+1, and an operation of initializing the pixel electrode of the organic light emitting diode OLED may be performed.

[0083] In such an embodiment, a second electrode CE2 of a storage capacitor Cst is connected to a driving voltage line PL, and a common electrode of the organic light emitting diode OLED is connected to a common voltage ELVSS. Accordingly, the organic light emitting diode OLED may display an image by receiving the driving current I OLED from the driving thin film transistor T1 and emitting light.

[0084] In one embodiment, as Figure 4 shown, the compensation thin film transistor T3 and the first initialization thin film transistor T4 may each have a dual gate electrode, but the embodiment is not limited thereto. Alternatively, the compensation thin film transistor T3 and the first initialization thin film transistor T4 may each have a single gate electrode.

[0085] Figure 5 is a plan view of a display device 1 according to an embodiment, Figure 6 is a cross-sectional view of a display device 1 according to an embodiment, and Figure 7A 、 Figure 7B 、 Figure 7C are schematic views of a display device 1 according to an embodiment.

[0086] More specifically, Figure 5 is Figure 2 an enlarged view of region A of Figure 6 is along Figure 5Cross-sectional views of the display device 1 taken along lines I-I', II-II', and III-III', and Figure 7A 、 Figure 7B 、 Figure 7C are Figure 6 enlarged views of regions B, C, and D.

[0087] Referring Figure 5 and Figure 6 , an embodiment of the display device 1 may include a green pixel Pg, a red pixel Pr, and a blue pixel Pb. In such an embodiment, the green pixel Pg emits light having a green wavelength, the red pixel Pr emits light having a red wavelength, and the blue pixel Pb emits light having a blue wavelength. In Figure 5 one embodiment, the green pixel Pg may define a first pixel, and the red pixel Pr and the blue pixel Pb may define a second pixel.

[0088] An embodiment of the display device 1 may include a first planarization layer 109 (as Figure 6 shown), a green pixel Pg, and a red pixel Pr. In such an embodiment, the first planarization layer 109 may be disposed above the substrate 100, and first contact holes 113a, second contact holes 113b, and dummy holes 114 are defined to pass through the first planarization layer 109. The green pixel Pg is disposed on the first planarization layer 109 and includes a first pixel electrode 210a overlapping with the first contact hole 113a and the dummy hole 114, and the red pixel Pr is disposed on the first planarization layer 109 and includes a second pixel electrode 210b overlapping with the second contact hole 113b.

[0089] In one embodiment, the display device 1 may further include a blue pixel Pb, which is disposed on the first planarization layer 109 and includes a third pixel electrode 210c overlapping with a third contact hole 113c.

[0090] In one embodiment, the substrate 100 may include glass or a polymer resin. In such an embodiment, the polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure, and the multilayer structure includes a layer including the polymer resin and an inorganic layer (not shown).

[0091] In an embodiment of the display device 1, the buffer layer 101 may be disposed on the substrate 100. The buffer layer 101 may be located on the substrate 100, may reduce or prevent foreign substances, moisture, or external air from penetrating from below the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 101 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite material, and may include a single layer or multiple layers including an inorganic material and an organic material.

[0092] In an embodiment of the display device 1, the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 may be disposed on the buffer layer 101. Each of the thin film transistors TFT1, TFT2, and TFT3 may include a semiconductor layer 134, a gate electrode 136, a source electrode 137, and a drain electrode 138, and the source electrode 137 and the drain electrode 138 serve as connection electrodes.

[0093] The first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 may be respectively and electrically connected to the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3 described below to drive the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3.

[0094] The semiconductor layer 134 is disposed on the buffer layer 101 and may include a channel region 132, a source region 131, and a drain region 133. In such an embodiment, the channel region 132 may overlap with the gate electrode 136, and the source region 131 and the drain region 133 may be disposed on two opposite sides of the channel region 132 and may include impurities having a higher concentration than the concentration of the channel region 132. Here, the impurities may include N-type impurities or P-type impurities. Although not shown, the source region 131 and the drain region 133 may be electrically connected to the connection electrodes.

[0095] The semiconductor layer 134 may include an oxide semiconductor and / or a silicon semiconductor. In one embodiment where the semiconductor layer 134 includes an oxide semiconductor, the semiconductor layer 134 may include an oxide of at least one selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). In one embodiment, for example, the semiconductor layer 134 may include at least one selected from InSnZnO (“ITZO”), InGaZnO (“IGZO”), etc. In one embodiment where the semiconductor layer 134 includes a silicon semiconductor, the semiconductor layer 134 may include amorphous silicon (“a-Si”) or low-temperature polycrystalline silicon (“LTPS”) formed by crystallizing a-Si.

[0096] In one embodiment of the display device 1, the first insulating layer 103 may be disposed on the semiconductor layer 134. The first insulating layer 103 may include at least one inorganic insulating material selected from silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO). The first insulating layer 103 may be a single layer or multiple layers including the above-mentioned inorganic insulating materials.

[0097] The gate electrode 136 may be disposed on the first insulating layer 103. The gate electrode 136 may be a single layer or multiple layers including at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The gate electrode 136 may be connected to a gate line that applies an electrical signal to the gate electrode 136.

[0098] In one embodiment of the display device 1, the second insulating layer 105 may be disposed on the gate electrode 136. The second insulating layer 105 may include at least one inorganic insulating material selected from silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO). The second insulating layer 105 may be a single layer or multiple layers including the above-mentioned inorganic insulating materials.

[0099] The storage capacitor Cst may be disposed on the first insulating layer 103. The storage capacitor Cst may include a bottom electrode 144 and a top electrode 146 overlapping the bottom electrode 144. The bottom electrode 144 of the storage capacitor Cst may overlap the gate electrode 136 of the first thin film transistor TFT1, and the bottom electrode 144 of the storage capacitor Cst may be integrally formed with the gate electrode 136 of the first thin film transistor TFT1 into a single whole body. In one embodiment, the storage capacitor Cst may not overlap with the first thin film transistor TFT1 and may be a separate element independent of the gate electrode 136 of the first thin film transistor TFT1.

[0100] The top electrode 146 of the storage capacitor Cst may include at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be a single layer or multiple layers including the above materials.

[0101] In one embodiment of the display device 1, a third insulating layer 107 may be disposed on the top electrode 146. The third insulating layer 107 may include at least one inorganic insulating material selected from silicon oxide (SiO2), silicon nitride (SiN x )), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO). The third insulating layer 107 may be a single layer or multiple layers including the above inorganic insulating materials.

[0102] The source electrode 137 and the drain electrode 138 for connecting the electrodes may be disposed on the third insulating layer 107. The source electrode 137 and the drain electrode 138 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be a single layer or multiple layers including the above materials. In one embodiment, for example, the source electrode 137 and the drain electrode 138 may have a multi-layer structure of Ti / Al / Ti.

[0103] In an embodiment of the display device 1, the first planarization layer 109 may be disposed on the source electrode 137 and the drain electrode 138. The first contact hole 113a, the second contact hole 113b, the third contact hole 113c, and the dummy hole 114 may be defined in the first planarization layer 109. The first planarization layer 109 may be a single layer or multiple layers including an organic material or an inorganic material. In an embodiment, the first planarization layer 109 may include common polymers such as benzocyclobutene (“BCB”), polyimide (“PI”), hexamethyldisiloxane (“HMDSO”), polymethyl methacrylate (“PMMA”), or polystyrene (“PS”); polymer derivatives having a phenol group; acrylic-based polymers; imide-based polymers; aryl ether-based polymers; amide-based polymers; fluorine-based polymers; parylene polymers; vinyl alcohol-based polymers; or mixtures thereof. The first planarization layer 109 may include silicon dioxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). In one embodiment, for example, the first planarization layer 109 may include a siloxane-based polymer material or PI.

[0104] In an embodiment of the display device 1, the first organic light-emitting diode OLED1, the second organic light-emitting diode OLED2, and the third organic light-emitting diode OLED3 may be disposed on the first planarization layer 109. In such an embodiment, the first organic light-emitting diode OLED1 may include a first pixel electrode 210a, a first intermediate layer 220a, and a counter electrode 230, the second organic light-emitting diode OLED2 may include a second pixel electrode 210b, a second intermediate layer 220b, and a counter electrode 230, and the third organic light-emitting diode OLED3 may include a third pixel electrode 210c, a third intermediate layer 220c, and a counter electrode 230.

[0105] The first thin-film transistor TFT1 may be connected to the first pixel electrode 210a through the first contact hole 113a to drive the first organic light-emitting diode OLED1, the second thin-film transistor TFT2 may be connected to the second pixel electrode 210b through the second contact hole 113b to drive the second organic light-emitting diode OLED2, and the third thin-film transistor TFT3 may be connected to the third pixel electrode 210c through the third contact hole 113c to drive the third organic light-emitting diode OLED3.

[0106] The first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may be disposed on the first planarization layer 109. The first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may be separated from each other and may be provided in the same layer as each other.

[0107] Each of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may include a (semi)transparent electrode or a reflective electrode. In one embodiment, for example, the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer. In such an embodiment, the reflective layer may include at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and their compounds. The transparent or semi-transparent electrode layer may include at least one selected from indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), and aluminum zinc oxide (“AZO”). Each of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may have a stacked structure of ITO / Ag / ITO.

[0108] In one embodiment of the display device 1, the shielding member 212 may also be disposed on the first planarization layer 109. In one embodiment, as Figure 5As shown in [Fig.], the shielding member 212 may extend in the x direction along a part of the edges of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c so as not to overlap the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c in a plan view, and may be disposed above or below each row. Depending on the arrangement of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c in the same row, the shielding member 212 may extend in a straight line or in a zigzag. The shielding member 212 may include a metal having a light-shielding property. In one embodiment, for example, the shielding member 212 may include at least one selected from aluminum (Al), copper (Cu), and titanium (Ti), and may be a single layer or a multi-layer including the above materials. In one embodiment, for example, the shielding member 212 may be a multi-layer of Ti / Al / Ti. The shielding member 212 may include the same material as that of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c. The shielding members 212 may be separated from each other and provided independently for each row. The shielding member 212 may be floating and electrically connected to a constant voltage wiring (e.g., a power supply voltage line, an initialization voltage line, etc.) to receive a constant voltage from the constant voltage wiring.

[0109] In an embodiment of the display device 1, the pixel defining layer 180 may be disposed on the first planarization layer 109. The pixel defining layer 180 may overlap with the first contact hole 113a, the second contact hole 113b, the third contact hole 113, and the dummy hole 114 defined in the first planarization layer 109, and may be disposed on the first planarization layer 109.

[0110] In one embodiment, a first opening OP1 exposing at least a part of the first pixel electrode 210a is defined to pass through the pixel defining layer 180. The area exposed by the pixel defining layer 180 may be defined as a first emission area EA1. The non-emission area is around the first emission area EA1, and the non-emission area may surround the first emission area EA1.

[0111] A second opening OP2 exposing at least a part of the second pixel electrode 210b is defined to pass through the pixel defining layer 180. The area exposed by the pixel defining layer 180 may be defined as a second emission area EA2. The non-emission area is around the second emission area EA2, and the non-emission area may surround the second emission area EA2.

[0112] A third opening OP3 exposing at least a part of the third pixel electrode 210c is defined to pass through the pixel defining layer 180. An area exposed by the pixel defining layer 180 may be defined as a third emission area EA3. A non-emission area surrounds the third emission area EA3, and the non-emission area may surround the third emission area EA3.

[0113] By increasing the distances between the edges of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c and the counter electrode 230, the pixel defining layer 180 can prevent the occurrence of arcing or the like at the edges of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c. The pixel defining layer 180 may include, for example, an organic insulating material including PI, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed by spin coating.

[0114] In one embodiment, the pixel defining layer 180 may include a black matrix including a light-shielding material. The black matrix may include at least one of various materials selected from, for example, a mixed black pigment, chromium (Cr), or chromium oxide (CrO x ) and the like. In one embodiment where the black matrix includes chromium (Cr) or chromium oxide (CrO x ), the black matrix may be a single layer or multiple layers including chromium (Cr) or chromium oxide (CrO x ).

[0115] The first contact hole 113a and the dummy hole 114 defined in the first planarization layer 109 may be separated from each other, and the first opening OP1 of the pixel defining layer 180 is between the first contact hole 113a and the dummy hole 114. In one embodiment, for example, as Figure 5 shown, the first contact hole 113a and the dummy hole 114 may be separated from each other in the y direction, and the first opening OP1 of the pixel defining layer 180 is between the first contact hole 113a and the dummy hole 114.

[0116] The first thin film transistor TFT1 may be connected to the first pixel electrode 210a on the first planarization layer 109 through the first contact hole 113a defined in the first planarization layer 109, the second thin film transistor TFT2 may be connected to the second pixel electrode 210b on the first planarization layer 109 through the second contact hole 113b defined in the first planarization layer 109, and the third thin film transistor TFT3 may be connected to the third pixel electrode 210c on the first planarization layer 109 through the third contact hole 113c defined in the first planarization layer 109.

[0117] By completely forming a planarization layer and then patterning the planarization layer using a mask, contact holes defined in the planarization layer are formed. The height of a patterned part of the contact holes in the planarization layer is less than the height of other parts. Thus, the pixel electrodes on the planarization layer may be inclined on one side. In one embodiment, as Figure 5 shown, in the green pixel Pg, in a plan view, a first contact hole 113a is defined in a top portion of a first pixel electrode 210a. In the red pixel Pr and the blue pixel Pb, in a plan view, a second contact hole 113b and a third contact hole 113c are defined in bottom portions of a second pixel electrode 210b and a third pixel electrode 210c, respectively. Thus, the first pixel electrode 210a of the green pixel Pg and the second pixel electrode 210b of the red pixel Pr and the third pixel electrode 210c of the blue pixel Pb are inclined in different directions, and thus color bands caused by external light reflection may occur.

[0118] In one embodiment of the present invention, by including dummy holes 114 in a first planarization layer 109 and thus making the inclination directions of the first pixel electrode 210a of the green pixel Pg and the second pixel electrode 210b of the red pixel Pr and the third pixel electrode 210c of the blue pixel Pb the same, color bands caused by external light reflection can be effectively prevented.

[0119] To make the inclination direction of the first pixel electrode 210a of the green pixel Pg the same as the inclination directions of the second pixel electrode 210b of the red pixel Pr and the third pixel electrode 210c of the blue pixel Pb, the first planarization layer 109 of the display device 1 may include dummy holes 114 overlapping with the first pixel electrode 210a of the green pixel Pg.

[0120] Referring to Figure 7A 、 Figure 7B and Figure 7C , in one embodiment, the first planarization layer 109 includes dummy holes 114 such that the height of a part of the first planarization layer 109 adjacent to a patterned part of the dummy holes 114 of the first planarization layer 109 becomes less than the height of a patterned part of the first contact hole 113a of the first planarization layer 109. Thus, the first pixel electrode 210a of the green pixel Pg is inclined in the same direction as the inclination directions of the second pixel electrode 210b of the red pixel Pr and the third pixel electrode 210c of the blue pixel Pb, and thus the occurrence of color bands caused by external light reflection can be effectively prevented.

[0121] More specifically, the first pixel electrode 210a of the green pixel Pg may form a first tilt angle θ1 with respect to the first axis 11 toward the z direction in a plane including the first axis 11 and the second axis 12. The first axis 11 extends in the y direction and the second axis 12 extends in the z direction intersecting the y direction. The first pixel electrode 210a may be disposed on the first planarization layer 109. The second pixel electrode 210b of the red pixel Pr may form a second tilt angle θ2 with respect to the first axis 11 toward the z direction in a plane including the first axis 11 and the second axis 12. The second pixel electrode 210b may be disposed on the first planarization layer 109. The third pixel electrode 210c of the blue pixel Pb may form a third tilt angle θ3 with respect to the first axis 11 toward the z direction in a plane including the first axis 11 and the second axis 12. The third pixel electrode 210c may be disposed on the first planarization layer 109. In one embodiment, the first tilt angle θ1, the second tilt angle θ2, and the third tilt angle θ3 may have an angle in the range of about 0° to about 3°, may have an angle in the range of about 0° to about 2°, or may have an angle in the range of about 0° to about 1.5°. In such an embodiment, various modifications may be made. In one embodiment, for example, the first tilt angle θ1, the second tilt angle θ2, and the third tilt angle θ3 may have a tilt angle in the range of about 0° to about 1°.

[0122] In such an embodiment, the first pixel electrode 210a of the green pixel Pg, the second pixel electrode 210b of the red pixel Pr, and the third pixel electrode 210c of the blue pixel Pb have tilt angles in the same direction (i.e., tilted in the same direction), such that the occurrence of color bands caused by external light reflection can be effectively prevented.

[0123] Referring back Figure 6 , the first intermediate layer 220a may be disposed on at least a part of the first pixel electrode 210a exposed by the pixel defining layer 180, the second intermediate layer 220b may be disposed on at least a part of the second pixel electrode 210b exposed by the pixel defining layer 180, and the third intermediate layer 220c may be disposed on at least a part of the third pixel electrode 210c exposed by the pixel defining layer 180.

[0124] The first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may each include an emission layer. The first functional layer and the second functional layer may be selectively disposed above and below the emission layer.

[0125] The first functional layer may include a hole injection layer and / or a hole transport layer, and the second functional layer may include an electron transport layer and / or an electron injection layer. The emission layer may include an organic material including a fluorescent material or a phosphorescent material that emits red light, green light, blue light, or white light. The emission layer may include a low molecular weight organic material or a polymeric organic material.

[0126] In one embodiment where the emission layer includes a low molecular weight organic material, the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may have a structure in which a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, an electron injection layer, etc. are stacked in a single or composite configuration. The emission layer may include at least one selected from various organic materials such as copper phthalocyanine (“CuPc”), N,N'-di(1-naphthyl)-N,N'-diphenylbenzidine (“NPB”), and tris(8-hydroxyquinoline) aluminum (“Alq3”). These layers may be formed by vacuum deposition.

[0127] In one embodiment where the emission layer includes a polymeric organic material, the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may have a structure that generally includes a hole transport layer and an emission layer. In such an embodiment, the hole transport layer may include poly(3,4-ethylenedioxythiophene) (“PEDOT”), and the emission layer may include polymeric materials such as poly(phenylene vinylene) (“PPV”) - based materials and polyfluorene - based materials. The emission layer may be formed by screen printing, inkjet printing, or laser - induced thermal imaging (“LITI”).

[0128] In one embodiment, the first intermediate layer 220a of the green pixel Pg may emit light at a green wavelength, the second intermediate layer 220b of the red pixel Pr may emit light at a red wavelength, and the third intermediate layer 220c of the blue pixel Pb may emit light at a blue wavelength.

[0129] The counter electrode 230 may be disposed on the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c. The counter electrode 230 may be arranged to completely cover the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c. The counter electrode 230 may be disposed in the display area DA and arranged to completely cover the display area DA. In one embodiment, by using an open mask, the counter electrode 230 may be formed as a single integral body over the entire display panel to cover a plurality of pixels P disposed in the display area DA. The counter electrode 230 may include a conductive material having a low work function. In one embodiment, for example, the counter electrode 230 may include a (semi) transparent layer, the (semi) transparent layer including at least one selected from silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof. Alternatively, the counter electrode 230 may also be a layer including ITO, IZO, zinc oxide (ZnO), or indium oxide (In2O3) on the (semi) transparent layer including the above materials.

[0130] In one embodiment of the display device 1, the thin film encapsulation layer 300 may be disposed on the counter electrode 230. The thin film encapsulation layer 300 may include an inorganic encapsulation layer and an organic encapsulation layer. In one embodiment, the thin film encapsulation layer 300 may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0131] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include an inorganic insulating material. The inorganic insulating material may include at least one selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymer-based material. The polymer-based material may include at least one selected from acrylic-based resins, epoxy-based resins, polyimides, and polyethylene. In one embodiment, for example, the organic encapsulation layer 320 may include an acrylic-based resin such as PMMA or polyacrylic acid.

[0132] In an embodiment of the display device 1, the touch unit 400 may be disposed on the thin film encapsulation layer 300. The touch unit 400 may be directly disposed on the thin film encapsulation layer 300. The touch unit 400 may include a first conductive layer 410, a second conductive layer 430, a first touch insulating layer 420, and a second touch insulating layer 440. In such an embodiment, the second conductive layer 430 may be disposed on the first conductive layer 410, the first touch insulating layer 420 may be between the first conductive layer 410 and the second conductive layer 430, and the second touch insulating layer 440 may be disposed on the second conductive layer 430. At least one insulating layer may also be disposed between the thin film encapsulation layer 300 and the first conductive layer 410.

[0133] The first conductive layer 410 and the second conductive layer 430 may include sensing electrodes and signal lines. In an embodiment, the first conductive layer 410 and the second conductive layer 430 may overlap with the pixel defining layer 180 to prevent the user from observing the first conductive layer 410 and the second conductive layer 430, and may have a mesh shape.

[0134] The first conductive layer 410 and the second conductive layer 430 may have a single-layer structure or a stacked multi-layer structure. The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include at least one selected from molybdenum, silver, titanium, copper, aluminum, and alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as ITO, IZO, zinc oxide (ZnO), or indium tin zinc oxide (ITZO). In an embodiment, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, and graphene. The conductive layer having a multi-layer structure may include multi-layer metal layers. The multi-layer metal layers may include a three-layer structure of Ti / Al / Ti. The conductive layer having a multi-layer structure may include a metal layer and a transparent conductive layer.

[0135] Each of the first touch insulating layer 420 and the second touch insulating layer 440 may have a single-layer structure or a multi-layer structure. Each of the first touch insulating layer 420 and the second touch insulating layer 440 may include an inorganic material, an organic material, or a composite material.

[0136] At least one of the first touch insulating layer 420 and the second touch insulating layer 440 may include an inorganic layer. The inorganic layer may include at least one selected from aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, tantalum oxide, zirconium oxide, and hafnium oxide.

[0137] At least one of the first touch insulating layer 420 and the second touch insulating layer 440 may include an organic layer. The organic layer may include at least one selected from an acrylic-based resin, a methacrylic-based resin, polyisoprene, a vinyl resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, and a parylene resin.

[0138] The touch unit 400 may sense an external input by using, for example, a capacitive method. In one embodiment, the operation method of the touch unit 400 is not specifically limited. One embodiment of the touch unit 400 may sense an external input by using electromagnetic induction or an input sensing method.

[0139] In one embodiment of the display device 1, a color filter layer may be disposed on the touch unit 400. The color filter layer may include a first color filter 520a, a second color filter 520b, and a third color filter 520c. The first color filter 520a overlaps with the first pixel electrode 210a, the second color filter 520b overlaps with the second pixel electrode 210b, and the third color filter 520c overlaps with the third pixel electrode 210c. In one embodiment, a light-shielding layer 510 may further be included, and the light-shielding layer 510 may be disposed between the first color filter 520a, the second color filter 520b, and the third color filter 520c.

[0140] The light-shielding layer 510 may be disposed on the touch unit 400. An opening (e.g., a fourth opening OP4) exposing at least a part of the touch unit 400 may be defined to pass through the light-shielding layer 510. The fourth opening OP4 of the light-shielding layer 510 may overlap with a first emission region EA1, a second emission region EA2, and a third emission region EA3 defined by the pixel defining layer 180. That is, the light-shielding layer 510 may not overlap with the first emission region EA1, the second emission region EA2, and the third emission region EA3 defined by the pixel defining layer 180.

[0141] The light-shielding layer 510 may overlap with the pixel defining layer 180. The light-shielding layer 510 may include at least one of various materials selected from, for example, a mixed black pigment, chromium (Cr), or chromium oxide (CrO x ) and other organic materials. In one embodiment in which the light-shielding layer 510 includes chromium or chromium oxide, the light-shielding layer 510 may be a single layer or multiple layers of chromium (Cr) or chromium oxide (CrO x ). In one embodiment, the light-shielding layer 510 may include the same material as that of the pixel defining layer 180.

[0142] The first color filter 520a, the second color filter 520b, and the third color filter 520c may be disposed in the fourth opening OP4 that exposes at least a portion of the touch unit 400. The first color filter 520a, the second color filter 520b, and the third color filter 520c may include organic material patterns including pigments or dyes. The first color filter 520a may selectively transmit light at a green wavelength, the second color filter 520b may selectively transmit light at a red wavelength, and the third color filter 520c may selectively transmit light at a blue wavelength. In one embodiment, for example, the first color filter 520a may be arranged to correspond to the first pixel electrode 210a, the second color filter 520b may be arranged to correspond to the second pixel electrode 210b, and the third color filter 520c may be arranged to correspond to the third pixel electrode 210c.

[0143] In one embodiment, by using the light-shielding layer 510 and the color filters 520a, 520b, 520c instead of a polarizing plate, the flexibility of the display device 1 can be improved.

[0144] The light-shielding layer 510 may overlap with the dummy hole 114 defined in the first planarization layer 109. The light-shielding layer 510 may be separated from the dummy hole 114 by a first distance d1, where the first distance d1 is defined as the shortest distance between the inner surface of the opening (i.e., the fourth opening OP4) formed in the light-shielding layer 510 and the dummy hole 114 defined in the first planarization layer 109. That is, when the dummy hole 114 and the light-shielding layer 510 are disposed on the same plane, the dummy hole 114 may be separated from the light-shielding layer 510 by a first distance d1, where the first distance d1 is defined as the shortest distance from the inner surface of the fourth opening OP4 in the light-shielding layer 510 to the dummy hole 114. In one embodiment, the first distance d1 may be about 5 micrometers (μm) or greater, about 6 μm or greater, or about 7 μm or greater. Various modifications may be made. In one embodiment, for example, the first distance d1 may be about 5.5 μm or greater.

[0145] In one embodiment, the display device 1 may include a first pixel and a second pixel. In such an embodiment, the first pixel may be disposed on the planarization layer and may include a first pixel electrode overlapping with the first contact hole and the dummy hole, and the second pixel may be disposed on the planarization layer and may include a second pixel electrode overlapping with the second contact hole. In one embodiment, for example, the first pixel may include a green pixel Pg, and the second pixel may include a red pixel Pr or a blue pixel Pb. Since the first pixel includes the first pixel electrode overlapping with the dummy hole, the direction in which the first pixel electrode is inclined becomes the same as the direction in which the second pixel electrode is inclined, and thus the appearance of color bands caused by external light reflection can be effectively prevented.

[0146] Figure 8 and Figure 9 is a cross-sectional view of the display device 1 according to an alternative embodiment.

[0147] Except that a second planarization layer 111 is provided on the first planarization layer 109, Figure 8 and Figure 9 the embodiment of Figure 6 is substantially the same as the embodiment of Figure 8 and Figure 9 The same or similar elements shown in Figure 6 have been labeled with the same reference numerals as those used above to describe the embodiment of the display device 1 shown in Figure 8 and Figure 9 Any repeated detailed descriptions of the same or similar elements shown in

[0148] will be omitted or simplified hereinafter. Figure 8 Referring to

[0149] An embodiment of the display device 1 may include a first planarization layer 109 and a second planarization layer 111. x ) and may include at least one selected from silicon oxide (SiO2), silicon nitride (SiN

[0150] The second planarization layer 111 may include general polymers such as BCB, PI, HMDSO, PMMA or PS; polymer derivatives having phenolic groups; acrylic polymers; imide polymers; aryl ether polymers; amide polymers; fluorine polymers; parylene polymers; vinyl alcohol polymers; or mixtures thereof. The second planarization layer 111 may include at least one selected from silicon oxide (SiO2), silicon nitride (SiN x ) and may include at least one selected from silicon oxide (SiO2), silicon nitride (SiN

[0151] In one embodiment, the first planarization layer 109 may include a material different from that of the second planarization layer 111. In one embodiment, for example, the first planarization layer 109 may include a siloxane-based polymer material, and the second planarization layer 111 may include PI.

[0152] The first planarization layer 109 and the second planarization layer 111 may include materials having the same material as each other. In one embodiment, for example, the first planarization layer 109 may include PI, and the second planarization layer 111 may include PI.

[0153] The first contact hole 113a, the second contact hole 113b, and the third contact hole 113c may be defined in the first planarization layer 109 and the second planarization layer 111. The first thin film transistor TFT1 may be connected to the first pixel electrode 210a of the first organic light emitting diode OLED1 through the first contact hole 113a defined in the first planarization layer 109 and the second planarization layer 111. The second thin film transistor TFT2 may be connected to the second pixel electrode 210b of the second organic light emitting diode OLED2 through the second contact hole 113b defined in the first planarization layer 109 and the second planarization layer 111. The third thin film transistor TFT3 may be connected to the third pixel electrode 210c of the third organic light emitting diode OLED3 through the third contact hole 113c defined in the first planarization layer 109 and the second planarization layer 111.

[0154] Dummy holes 114 may be defined in the first planarization layer 109 and the second planarization layer 111 that respectively overlap with the first pixel electrode 210a. In such an embodiment, the dummy holes 114 are provided in the first planarization layer 109 and the second planarization layer 111 that respectively overlap with the first pixel electrode 210a, so that the direction in which the first pixel electrode 210a of the green pixel Pg is inclined becomes the same as the direction in which the second pixel electrode 210b of the red pixel Pr is inclined and the direction in which the third pixel electrode 210c of the blue pixel Pb is inclined, and thus the occurrence of color bands caused by external light reflection can be effectively prevented.

[0155] Reference Figure 9 , one embodiment of the display device 1 may include a first planarization layer 109 and a second planarization layer 111.

[0156] The first planarization layer 109 may include a material different from that of the second planarization layer 111. In one embodiment, for example, the first planarization layer 109 may include a siloxane-based polymer material, and the second planarization layer 111 may include PI.

[0157] The first planarization layer 109 and the second planarization layer 111 may include materials of the same kind as each other. In one embodiment, for example, the first planarization layer 109 may include PI, and the second planarization layer 111 may include PI.

[0158] Dummy holes 114 may be defined in the second planarization layer 111 overlapping with the first pixel electrode 210a. In such an embodiment, the dummy holes 114 are provided in the second planarization layer 111 overlapping with the first pixel electrode 210a, such that the direction in which the first pixel electrode 210a of the green pixel Pg is inclined becomes the same as the direction in which the second pixel electrode 210b of the red pixel Pr and the direction in which the third pixel electrode 210c of the blue pixel Pb are inclined, and thus the occurrence of color bands caused by external light reflection can be effectively prevented. In such an embodiment, since the dummy holes 114 are provided only in the second planarization layer 111 overlapping with the first pixel electrode 210a, flattening layer loss can be effectively prevented and the display device 1 may have a more stable structure.

[0159] Figure 10 is a plan view of the display device 1 according to an alternative embodiment, Figure 11 is a cross-sectional view of the display device 1 according to an embodiment, and Figure 12A 、 Figure 12B and Figure 12C are plan views of the display device 1 according to an embodiment.

[0160] More specifically, Figure 10 is Figure 2 an enlarged view of region A of Figure 11 is a cross-sectional view of the display device 1 taken along lines I-I’, II-II’ and III-III’ of Figure 5 and Figure 12A 、 Figure 12B and Figure 12C are respectively Figure 11 enlarged views of regions B, C and D of

[0161] Except for providing the first dummy holes 114a and the second dummy holes 114b respectively overlapping with the red pixel Pr and the blue pixel Pb, Figure 10 、 Figure 11 、 Figure 12A 、 Figure 12B and Figure 12C the embodiments of Figure 5 、 Figure 6 、 Figure 7A 、 Figure 7B and Figure 7C are substantially the same as the embodiments of Figure 10 、 Figure 11 、 Figure 12A 、 Figure 12Band Figure 12C The same or similar elements shown in have been labeled with the same reference numerals as those used above to describe the embodiments of the display device 1 in Figure 5 , Figure 6 , Figure 7A , Figure 7B and Figure 7C and any repeated detailed descriptions of the same or similar elements shown in will be omitted or simplified hereinafter. Figure 10 , Figure 11 , Figure 12A , Figure 12B and Figure 12C Referring to, an embodiment of the display device 1 may include a green pixel Pg, a red pixel Pr, and a blue pixel Pb. In such an embodiment, the green pixel Pg emits light at a green wavelength, the red pixel Pr emits light at a red wavelength, and the blue pixel Pb emits light at a blue wavelength. In

[0162] Referring to Figures 10 to 11 , an embodiment of the display device 1 may include a green pixel Pg, a red pixel Pr, and a blue pixel Pb. In such an embodiment, the green pixel Pg emits light at a green wavelength, the red pixel Pr emits light at a red wavelength, and the blue pixel Pb emits light at a blue wavelength. In an embodiment of Figure 10 , the red pixel Pr and the blue pixel Pb may jointly define a first pixel, and the green pixel Pg may define a second pixel.

[0163] The display device 1 may include a first planarization layer 109, a green pixel Pg, and a red pixel Pr. In such an embodiment, the first planarization layer 109 may be disposed above the substrate 100, and the first contact hole 113a, the second contact hole 113b, and the first dummy hole 114a may be defined to pass through the first planarization layer 109. In such an embodiment, the green pixel Pg may be disposed on the first planarization layer 109 and may include a first pixel electrode 210a overlapping with the first contact hole 113a, and the red pixel Pr may be disposed on the first planarization layer 109 and may include a second pixel electrode 210b overlapping with the second contact hole 113b and the first dummy hole 114a.

[0164] In one embodiment, the display device 1 may further include a blue pixel Pb. In such an embodiment, the first planarization layer 109 may be disposed over the substrate 100, and the first contact hole 113a, the second contact hole 113b, the third contact hole 113c, the first dummy hole 114a, and the second dummy hole 114b may be defined to penetrate through the first planarization layer 109. In such an embodiment, the green pixel Pg may be disposed on the first planarization layer 109 and may include a first pixel electrode 210a overlapping with the first contact hole 113a, the red pixel Pr may include a second pixel electrode 210b, and the blue pixel Pb may include a third pixel electrode 210c. In such an embodiment, the second pixel electrode 210b may be disposed on the first planarization layer 109 and overlap with the second contact hole 113b and the first dummy hole 114a, and the third pixel electrode 210c may be disposed on the first planarization layer 109 and overlap with the third contact hole 113c and the second dummy hole 114b.

[0165] The first planarization layer 109 may be disposed over the source electrode 137 and the drain electrode 138. The first contact hole 113a, the second contact hole 113b, the third contact hole 113c, the first dummy hole 114a, and the second dummy hole 114b may be defined in the first planarization layer 109. The first planarization layer 109 may be a single layer or multiple layers including an organic material or an inorganic material. In one embodiment, the first planarization layer 109 may include a general polymer such as BCB, PI, HMDSO, PMMA, or PS; a polymer derivative having a phenolic group; an acrylic-based polymer; an imide-based polymer; an aryl ether-based polymer; an amide-based polymer; a fluorine-based polymer; a parylene polymer; a vinyl alcohol-based polymer; or a mixture thereof. The first planarization layer 109 may include at least one selected from silicon dioxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO). In one embodiment, for example, the first planarization layer 109 may include a siloxane-based polymer material or PI.

[0166] The first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may be disposed on the first planarization layer 109. The first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may be separated from each other and may be provided in the same layer as each other.

[0167] The pixel defining layer 180 may be disposed on the first planarization layer 109. The pixel defining layer 180 may overlap with the first contact hole 113a, the second contact hole 113b, the third contact hole 113c, the first dummy hole 114a, and the second dummy hole 114b respectively defined in the first planarization layer 109, and may be disposed on the first planarization layer 109.

[0168] The second contact hole 113b and the first dummy hole 114a defined in the first planarization layer 109 may be separated from each other, and the second opening OP2 of the pixel defining layer 180 is between the second contact hole 113b and the first dummy hole 114a. The third contact hole 113c and the second dummy hole 114b defined in the first planarization layer 109 may be separated from each other, and the third opening OP3 of the pixel defining layer 180 is between the third contact hole 113c and the second dummy hole 114b. In one embodiment, for example, as Figure 10 shown, the second contact hole 113b and the first dummy hole 114a may be separated from each other in the y direction, and the second opening OP2 of the pixel defining layer 180 is between the second contact hole 113b and the first dummy hole 114a. The third contact hole 113c and the second dummy hole 114b may be separated from each other in the y direction, and the third opening OP3 of the pixel defining layer 180 is between the third contact hole 113c and the second dummy hole 114b.

[0169] The first thin film transistor TFT1 may be connected to the first pixel electrode 210a disposed on the first planarization layer 109 through the first contact hole 113a defined in the first planarization layer 109. The second thin film transistor TFT2 may be connected to the second pixel electrode 210b disposed on the first planarization layer 109 through the second contact hole 113b defined in the first planarization layer 109. The third thin film transistor TFT3 may be connected to the third pixel electrode 210c disposed on the first planarization layer 109 through the third contact hole 113c defined in the first planarization layer 109.

[0170] In such an embodiment, the first planarization layer 109 includes the first dummy hole 114a and the second dummy hole 114b, so that the direction in which the first pixel electrode 210a of the green pixel Pg is inclined becomes the same as the direction in which the second pixel electrode 210b of the red pixel Pr is inclined and the direction in which the third pixel electrode 210c of the blue pixel Pb is inclined, and thus the appearance of color bands caused by external light reflection can be effectively prevented.

[0171] In one embodiment, the first dummy hole 114a overlaps with the second pixel electrode 210b of the red pixel Pr, and the second dummy hole 114b overlaps with the third pixel electrode 210c of the blue pixel Pb. The first dummy hole 114a and the second dummy hole 114b are defined to pass through the first planarization layer 109 of the display device 1, so that the direction in which the first pixel electrode 210a of the green pixel Pg is inclined is the same as the direction in which the second pixel electrode 210b of the red pixel Pr and the third pixel electrode 210c of the blue pixel Pb are inclined.

[0172] Reference Figure 12A , Figure 12B and Figure 12C , because the first dummy hole 114a and the second dummy hole 114b are defined to pass through the first planarization layer 109, the height of the first planarization layer 109 adjacent to the patterned part of the first dummy hole 114a becomes smaller than the height of the patterned part of the second contact hole 113b of the first planarization layer 109, and the height of the first planarization layer 109 adjacent to the patterned part of the second dummy hole 114b becomes smaller than the height of the patterned part of the third contact hole 113c of the first planarization layer 109, so that the second pixel electrode 210b of the red pixel Pr and the third pixel electrode 210c of the blue pixel Pb are inclined in the same direction as the first pixel electrode 210a of the green pixel Pg. Therefore, the appearance of color bands caused by external light reflection can be effectively prevented.

[0173] More specifically, a first pixel electrode 210a of a green pixel Pg may form a fourth tilt angle θ4 in a plane including a first axis 11 and a second axis 12 with respect to the first axis 11 toward the -z direction, where the first axis 11 extends in the y direction and the second axis 12 extends in the z direction intersecting the y direction. The first pixel electrode 210a may be disposed on a first planarization layer 109. A second pixel electrode 210b of a red pixel Pr may form a fifth tilt angle θ5 in a plane including the first axis 11 and the second axis 12 with respect to the first axis 11 toward the -z direction. The second pixel electrode 210b may be disposed on the first planarization layer 109. A third pixel electrode 210c of a blue pixel Pb may form a sixth tilt angle θ6 in a plane including the first axis 11 and the second axis 12 with respect to the first axis 11 toward the -z direction. The third pixel electrode 210c may be disposed on the first planarization layer 109. In such an embodiment, the fourth tilt angle θ4, the fifth tilt angle θ5, and the sixth tilt angle θ6 may have an angle in a range of about 0° to about 3°, may have an angle in a range of about 0° to about 2°, or may have an angle in a range of about 0° to about 1.5°. Various modifications may be made. In one embodiment, for example, the first tilt angle θ1, the second tilt angle θ2, and the third tilt angle θ3 may have an angle in a range of about 0° to about 1°.

[0174] In one embodiment, as described above, the first pixel electrode 210a of the green pixel Pg, the second pixel electrode 210b of the red pixel Pr, and the third pixel electrode 210c of the blue pixel Pb have tilt angles in the same direction (i.e., tilted in the same direction), such that the appearance of color bands caused by external light reflection can be effectively prevented.

[0175] Referring back to Figure 11, the light-shielding layer 510 may overlap with the first dummy hole 114a and the second dummy hole 114b defined in the first planarization layer 109. The light-shielding layer 510 may be separated from the first dummy hole 114a by a first distance d1, where the first distance d1 is defined as the shortest distance between the inner surface of the opening formed in the light-shielding layer 510 (i.e., the fourth opening OP4) and the first dummy hole 114a defined in the first planarization layer 109. That is, when the first dummy hole 114a and the light-shielding layer 510 are disposed in the same plane, the first dummy hole 114a may be separated from the light-shielding layer 510 by the first distance d1, where the first distance d1 is defined as the shortest distance between the inner surface of the fourth opening OP4 in the light-shielding layer 510 and the first dummy hole 114a. In such an embodiment, the light-shielding layer 510 may be separated from the second dummy hole 114b by the first distance d1, where the first distance d1 is defined as the shortest distance between the inner surface of the opening formed in the light-shielding layer 510 (i.e., the fourth opening OP4) and the second dummy hole 114b defined in the first planarization layer 109. That is, when the second dummy hole 114b and the light-shielding layer 510 are disposed in the same plane, the second dummy hole 114b may be separated from the light-shielding layer 510 by the first distance d1, where the first distance d1 is defined as the shortest distance between the inner surface of the fourth opening OP4 in the light-shielding layer 510 and the second dummy hole 114b. In one embodiment, the first distance d1 may be about 5 μm or greater, about 6 μm or greater, or about 7 μm or greater. Various modifications can be made. In one embodiment, for example, the first distance d1 may be about 5.5 μm or greater.

[0176] An embodiment of the display device 1 may include a first pixel and a second pixel. In such an embodiment, the first pixel includes a first pixel electrode, the second pixel includes a second pixel electrode, the first pixel electrode is disposed on the planarization layer and overlaps with the first contact hole and the dummy hole, and the second pixel electrode is disposed on the planarization layer and overlaps with the second contact hole. In one embodiment, for example, the first pixel may include a red pixel Pr or a blue pixel Pb, and the second pixel may include a green pixel Pg. In such an embodiment, since the first pixel includes the first pixel electrode overlapping with the dummy hole, the direction in which the first pixel electrode of the first pixel is inclined becomes the same as the direction in which the second pixel electrode of the second pixel is inclined, and thus the appearance of color bands caused by external light reflection can be effectively prevented.

[0177] Figure 13 and Figure 14 is a cross-sectional view of the display device 1 according to an alternative embodiment.

[0178] Except that the second planarization layer 111 is provided on the first planarization layer 109, Figure 13 and Figure 14 the embodiment ofFigure 11 The embodiments are substantially the same. In Figure 13 and Figure 14 the same or similar elements shown have been labeled with the same reference numerals as those used above to describe the embodiments of the display device 1 shown in Figure 11 , and any repeated detailed descriptions of the same or similar elements shown in Figure 13 and Figure 14 will be omitted or simplified hereinafter.

[0179] Referring to Figure 13 , an embodiment of the display device 1 may include a first planarization layer 109 and a second planarization layer 111.

[0180] The first planarization layer 109 may include a general polymer such as BCB, PI, HMDSO, PMMA, or PS; a polymer derivative having a phenolic group; an acrylic-based polymer; an imide-based polymer; an aryl ether-based polymer; an amide-based polymer; a fluorine-based polymer; a parylene polymer; a vinyl alcohol-based polymer; or a mixture thereof. In one embodiment, the first planarization layer 109 may include at least one selected from silicon dioxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0181] The second planarization layer 111 may include a general polymer such as BCB, PI, HMDSO, PMMA, or PS; a polymer derivative having a phenolic group; an acrylic-based polymer; an imide-based polymer; an aryl ether-based polymer; an amide-based polymer; a fluorine-based polymer; a parylene polymer; a vinyl alcohol-based polymer; or a mixture thereof. In one embodiment, the second planarization layer 111 may include at least one selected from silicon dioxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0182] In one embodiment, the first planarization layer 109 may include a material different from that of the second planarization layer 111. In one embodiment, for example, the first planarization layer 109 may include a siloxane-based polymer material, and the second planarization layer 111 may include PI.

[0183] The first planarization layer 109 and the second planarization layer 111 may include materials having the same material as each other. In one embodiment, for example, the first planarization layer 109 may include PI, and the second planarization layer 111 may include PI.

[0184] The first contact hole 113a, the second contact hole 113b, and the third contact hole 113c may be defined in the first planarization layer 109 and the second planarization layer 111. The first thin film transistor TFT1 may be connected to the first pixel electrode 210a of the first organic light emitting diode OLED1 through the first contact hole 113a defined in the first planarization layer 109 and the second planarization layer 111. The second thin film transistor TFT2 may be connected to the second pixel electrode 210b of the second organic light emitting diode OLED2 through the second contact hole 113b defined in the first planarization layer 109 and the second planarization layer 111. The third thin film transistor TFT3 may be connected to the third pixel electrode 210c of the third organic light emitting diode OLED3 through the third contact hole 113c defined in the first planarization layer 109 and the second planarization layer 111.

[0185] The first dummy hole 114a may be defined in the first planarization layer 109 and the second planarization layer 111 that respectively overlap with the second pixel electrode 210b. The second dummy hole 114b may be defined in the first planarization layer 109 and the second planarization layer 111 that respectively overlap with the third pixel electrode 210c. In such an embodiment, since the first dummy hole 114a is provided in the first planarization layer 109 and the second planarization layer 111 that respectively overlap with the second pixel electrode 210b, and the second dummy hole 114b is provided in the first planarization layer 109 and the second planarization layer 111 that respectively overlap with the third pixel electrode 210c, the tilting directions of the second pixel electrode 210b of the red pixel Pr and the third pixel electrode 210c of the blue pixel Pb become the same as the tilting direction of the first pixel electrode 210a of the green pixel Pg, and thus the appearance of color bands caused by external light reflection can be effectively prevented.

[0186] Reference Figure 14 An embodiment of the display device 1 may include a first planarization layer 109 and a second planarization layer 111.

[0187] The first planarization layer 109 may include a material different from that of the second planarization layer 111. In one embodiment, for example, the first planarization layer 109 may include a siloxane-based polymer material, and the second planarization layer 111 may include PI.

[0188] The first planarization layer 109 and the second planarization layer 111 may include materials with the same material as each other. In one embodiment, for example, the first planarization layer 109 may include PI, and the second planarization layer 111 may include PI.

[0189] The first dummy hole 114a may be defined in the second planarization layer 111 overlapping with the second pixel electrode 210b, and the second dummy hole 114b may be defined in the second planarization layer 111 overlapping with the third pixel electrode 210c. In such an embodiment, since the first dummy hole 114a is provided in the second planarization layer 111 overlapping with the second pixel electrode 210b, and the second dummy hole 114b is provided in the second planarization layer 111 overlapping with the third pixel electrode 210c, the tilting directions of the second pixel electrode 210b of the red pixel Pr and the third pixel electrode 210c of the blue pixel Pb become the same as the tilting direction of the first pixel electrode 210a of the green pixel Pg, and thus the appearance of color bands caused by external light reflection can be effectively prevented.

[0190] In such an embodiment, since only the first dummy hole 114a and the second dummy hole 114b are provided in the second planarization layer 111, flattening layer loss can be prevented and the display device 1 can have a more stable structure.

[0191] In a plan view, in pixels for emitting light having a green wavelength, contact holes are defined in the top portion of the pixel electrodes, and in pixels for emitting light having a red wavelength and pixels for emitting light having a blue wavelength, contact holes are defined in the bottom portion of the pixel electrodes. The tilting direction of the pixel electrode of the pixel for emitting light having a green wavelength is different from the tilting directions of the pixel electrodes of the pixels for emitting light having a red wavelength and the pixels for emitting light having a blue wavelength, and thus color bands caused by external light reflection appear.

[0192] In an embodiment of the present invention, a dummy hole overlapping with the pixel electrode of a pixel for emitting light having a green wavelength is patterned in the planarization layer such that the tilting direction of the pixel electrode of the pixel for emitting light having a green wavelength becomes the same as the tilting directions of the pixel electrodes of the pixels for emitting light having a red wavelength and the pixels for emitting light having a blue wavelength, and thus the appearance of color bands caused by external light reflection can be effectively prevented.

[0193] In an embodiment of the present invention, since dummy holes overlapping with the pixel electrodes of the pixels for emitting light having a red wavelength and the pixels for emitting light having a blue wavelength are patterned in the planarization layer, the tilting directions of the pixel electrodes of the pixels for emitting light having a red wavelength and the pixels for emitting light having a blue wavelength become the same as the tilting direction of the pixel electrode of the pixel for emitting light having a green wavelength, and thus a display device capable of preventing the appearance of color bands caused by external light reflection can be provided.

[0194] According to an embodiment, a display device that can reduce the appearance degree of color bands caused by external light reflection can be realized.

[0195] The present invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will convey the concept of the present invention fully to those skilled in the art.

[0196] Although the present invention has been specifically shown and described with reference to embodiments of the present invention, those of ordinary skill in the art will understand that various changes in form and detail may be made in the embodiments of the present invention without departing from the spirit or scope of the present invention.

Claims

1. A display device, wherein, The display device includes: a substrate including a display area and a non-display area outside the display area; a planarization layer above the substrate, wherein a first contact hole, a second contact hole, and a dummy hole are defined to pass through the planarization layer; a first pixel on the planarization layer and including a first pixel electrode, wherein the first pixel electrode overlaps with the first contact hole and the dummy hole, the first contact hole and the dummy hole are spaced apart from each other, and the first pixel electrode is disposed in the first contact hole and the dummy hole; and a second pixel on the planarization layer and including a second pixel electrode, wherein the second pixel electrode overlaps with the second contact hole; wherein the first pixel electrode and the second pixel electrode are inclined in the same direction as each other.

2. The display device according to claim 1, wherein, The display device further includes: a pixel defining layer on the first pixel electrode, wherein a first opening is defined to pass through the pixel defining layer to expose at least a part of the first pixel electrode, wherein the first opening of the pixel defining layer is located between the first contact hole and the dummy hole.

3. The display device according to claim 2, wherein, The dummy hole overlaps with the pixel defining layer.

4. The display device according to claim 2, wherein, The pixel defining layer includes a light-shielding material.

5. The display device according to claim 1, wherein the planarization layer includes a first planarization layer and a second planarization layer, and a first contact hole is defined in the first planarization layer and the second planarization layer.

6. The display device according to claim 5, wherein, The dummy hole is defined in the first planarization layer and the second planarization layer.

7. The display device according to claim 5, wherein, The dummy hole is only defined in the second planarization layer.

8. The display device according to claim 5, wherein, The first planarization layer and the second planarization layer include different materials from each other.

9. The display device according to claim 1, wherein, The display device further includes: a first thin film transistor and a second thin film transistor, each of the first thin film transistor and the second thin film transistor above the substrate, wherein the first thin film transistor is connected to the first pixel electrode through the first contact hole, and the second thin film transistor is connected to the second pixel electrode through the second contact hole.

10. The display device according to claim 1, wherein the first pixel further includes a first intermediate layer on the first pixel electrode, the second pixel further includes a second intermediate layer on the second pixel electrode, one of the first intermediate layer and the second intermediate layer emits light with a green wavelength, and the other of the first intermediate layer and the second intermediate layer emits light with a red or blue wavelength.

11. The display device according to claim 10, wherein the first intermediate layer emits light with the red or blue wavelength, and The second intermediate layer emits light at the green wavelength.

12. The display device according to claim 2, wherein, The display device further includes: a light-shielding layer overlapping with the pixel defining layer, wherein a second opening is defined to pass through the light-shielding layer, wherein the light-shielding layer is separated from the dummy hole by a first distance, the first distance is defined as the shortest distance between the inner surface of the second opening and the dummy hole.

13. A display device, wherein, The display device includes: a first thin film transistor and a second thin film transistor, each of the first thin film transistor and the second thin film transistor above the substrate; a planarization layer above the substrate, wherein a first contact hole, a second contact hole, and a dummy hole are defined to pass through the planarization layer; a first pixel electrode on the planarization layer and connected to the first thin film transistor through the first contact hole, wherein the first pixel electrode overlaps with the first contact hole and the dummy hole, the first contact hole and the dummy hole are spaced apart from each other, and the first pixel electrode is disposed in the first contact hole and the dummy hole; and a second pixel electrode on the planarization layer and connected to the second thin film transistor through the second contact hole; wherein the first pixel electrode and the second pixel electrode are inclined in the same direction as each other.

14. The display device according to claim 13, wherein, The display device further includes: A pixel defining layer is on the first pixel electrode and the second pixel electrode, wherein an opening is defined to pass through the pixel defining layer to expose at least a part of the first pixel electrode and the second pixel electrode. Wherein, the opening of the pixel defining layer is located between the first contact hole and the dummy hole.

15. The display device according to claim 13, wherein the planarization layer includes a first planarization layer and a second planarization layer, and the first contact hole is defined in the first planarization layer and the second planarization layer.

16. The display device according to claim 15, wherein, The dummy hole is defined in the first planarization layer and the second planarization layer.

17. The display device according to claim 15, wherein, The dummy hole is only defined in the second planarization layer.

18. The display device according to claim 13, wherein, The display device further includes: A first intermediate layer and a second intermediate layer, the first intermediate layer and the second intermediate layer are respectively on the first pixel electrode and the second pixel electrode; and A counter electrode covering the first intermediate layer and the second intermediate layer, Wherein, one of the first intermediate layer and the second intermediate layer emits light with a green wavelength, and The other of the first intermediate layer and the second intermediate layer emits light with a red or blue wavelength.

Images