Display device and method of manufacturing a display device

Abstract

The present disclosure relates to a display device and a method of manufacturing the same, the display device including a substrate, a first conductive layer on the substrate and including a first signal line, an insulating layer pattern on the first conductive layer, a semiconductor pattern on the insulating layer pattern, a gate insulating layer on the semiconductor pattern, and a second conductive layer including a gate electrode on the gate insulating layer, and a first source / drain electrode and a second source / drain electrode each on at least a portion of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have the same planar shape, the semiconductor pattern includes a channel region overlapping the gate electrode, a first source / drain region on a first side of the channel region, and a second source / drain region on a second side of the channel region, and the first source / drain electrode electrically connects the first source / drain region and the first signal line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0014723, filed on February 7, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some aspects of exemplary embodiments of this disclosure relate to a display device and a method of manufacturing the display device. Background Technology

[0004] Electronic devices that display images to users, such as televisions, smartphones, tablet PCs, digital cameras, laptops, and navigation devices, include display devices for displaying images.

[0005] The display device may include a plurality of pixels and pixel circuitry for driving each of the pixels. Each pixel circuitry is formed using wiring and thin-film transistors formed on an insulating substrate.

[0006] Display devices can be formed using multiple masking processes. Masking processes can be useful for patterning wiring or insulating layers. However, as the number of masking processes increases, process efficiency may decrease.

[0007] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0008] Aspects of some exemplary embodiments of this disclosure provide a display device manufactured using a relatively reduced number of mask processes, thereby improving manufacturing efficiency and reducing manufacturing costs.

[0009] Aspects of some exemplary embodiments of this disclosure also provide a method for manufacturing a display device using a relatively reduced number of mask processes.

[0010] However, the aspects of embodiments according to this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the following detailed description of the disclosure.

[0011] According to some exemplary embodiments of this disclosure, a display device includes: a substrate; a first conductive layer located on the substrate and including a first signal line; an insulating layer pattern located on the first conductive layer; a semiconductor pattern located on the insulating layer pattern; a gate insulating layer located on the semiconductor pattern; and a second conductive layer including a gate electrode located on the gate insulating layer, and a first source / drain electrode and a second source / drain electrode, the first source / drain electrode and the second source / drain electrode each located on at least a portion of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have the same planar shape, the semiconductor pattern includes a channel region overlapping the gate electrode, a first source / drain region located on a first side of the channel region and a second source / drain region located on a second side of the channel region, and the first source / drain electrode is electrically connected to the first source / drain region and the first signal line.

[0012] According to some exemplary embodiments of this disclosure, a display device includes: a substrate; a first conductive layer located on the substrate and including data wiring and a first power wiring; a first insulating layer pattern and a second insulating layer pattern located on the first conductive layer; a semiconductor pattern including a first semiconductor pattern located on the first insulating layer pattern and having the same planar shape as the first insulating layer pattern and a second semiconductor pattern located on the second insulating layer pattern and having the same planar shape as the second insulating layer pattern; a gate insulating layer located on the semiconductor pattern; a second conductive layer including a first gate electrode and a second gate electrode disposed on the gate insulating layer and including a first source / drain electrode, a second source / drain electrode, a third source / drain electrode, and a fourth source / drain electrode, wherein the first source / drain electrode, the second source / drain electrode, the third source / drain electrode, and the fourth source / drain electrode are each located on at least a portion of the semiconductor pattern; and an interlayer insulating film disposed on the second conductive layer. On the electrical layer; and a pixel electrode, located on the interlayer insulating film, wherein the first gate electrode overlaps with the first semiconductor pattern, the second gate electrode overlaps with the second semiconductor pattern, the first semiconductor pattern includes a first channel region overlapping with the first gate electrode, a first source / drain region located on one side of the first channel region, and a second source / drain region located on the other side of the first channel region, the second semiconductor pattern includes a second channel region overlapping with the second gate electrode, a third source / drain region located on a first side of the second channel region, and a fourth source / drain region located on a second side of the second channel region, the first source / drain electrode is electrically connected to the first source / drain region and the data wiring, the second source / drain electrode is electrically connected to the second source / drain region and the first gate electrode, the third source / drain electrode is electrically connected to the third source / drain region and the first power wiring, and the fourth source / drain electrode is electrically connected to the fourth source / drain region and the pixel electrode.

[0013] According to some example embodiments of this disclosure, in a method of manufacturing a display device, the display device includes a plurality of pixels and a first transistor and a second transistor in each of the pixels. The method includes: forming a first conductive layer on a substrate, the first conductive layer including a first power supply wiring electrically connected to a first source / drain electrode of the first transistor, a lower light-blocking pattern electrically connected to a second source / drain electrode of the first transistor, and a data wiring electrically connected to a first source / drain electrode of the second transistor; sequentially coating an insulating layer material, a semiconductor layer material, and a gate insulating layer material on the substrate to cover the first conductive layer; and patterning the gate insulating layer, the semiconductor layer, and the insulating layer by etching the gate insulating layer material, the semiconductor layer material, and the insulating layer material using a halftone mask, the gate insulating layer including the gate insulating layer of the first transistor and the gate insulating layer of the second transistor, the semiconductor layer including the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor, and the insulating layer including a first insulating pattern having the same planar shape as the semiconductor pattern of the first transistor and a second insulating pattern having the same planar shape as the semiconductor pattern of the second transistor.

[0014] The display device and the method of manufacturing the display device according to some example embodiments can reduce the number of mask processes, thereby reducing process costs and improving process efficiency.

[0015] However, the features of the embodiments according to this disclosure are not limited to those set forth herein. The above and other features of the embodiments will become more apparent to those skilled in the art upon reference to the claims and their equivalents. Attached Figure Description

[0016] These and / or other aspects will become more apparent and readily understood from the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 This is a plan view of a display device according to some example embodiments;

[0018] Figure 2 These are schematic block diagrams of a display device according to some example embodiments;

[0019] Figure 3 This is an equivalent circuit diagram of a pixel of a display device according to some example embodiments;

[0020] Figure 4 It is a layout diagram of a pixel of a display device according to some example embodiments;

[0021] Figure 5This is a layout diagram of the buffer layer based on some example embodiments;

[0022] Figure 6 This is a layout diagram of the semiconductor layer according to some example embodiments;

[0023] Figure 7 It is along Figure 4 A cross-sectional view taken from line VII-VII';

[0024] Figure 8 This is a flowchart illustrating a method of manufacturing a display device according to some example embodiments;

[0025] Figures 9 to 18 It shows the manufacturing process. Figure 7 A cross-sectional view of the operation in the method of displaying the device;

[0026] Figure 19 This is a layout diagram of the buffer layer based on some example embodiments;

[0027] Figure 20 This is a layout diagram of the semiconductor layer according to some example embodiments;

[0028] Figure 21 It is a layout diagram of a pixel of a display device according to some example embodiments;

[0029] Figure 22 It is along Figure 21 A cross-sectional view taken from line XXII-XXII';

[0030] Figure 23 It is along Figure 21 A cross-sectional view taken from line XXIII-XXIII'; and

[0031] Figure 24 and Figure 25 This is a cross-sectional view of a display panel according to some example embodiments. Detailed Implementation

[0032] Aspects of some exemplary embodiments of the invention will now be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments of the invention are illustrated. However, the invention may be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be more thorough and complete, and will more fully convey to those skilled in the art the scope of embodiments according to the invention.

[0033] It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or there may be an intermediate layer. Throughout the specification, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions is exaggerated for clarity.

[0034] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Therefore, a first element discussed below may be referred to as a second element without departing from the teachings of one or more embodiments. Describing an element as a “first” element does not necessarily imply the presence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0035] In summarizing the detailed description, those skilled in the art will recognize that many variations and modifications can be made to the embodiments without substantially departing from the principles of embodiments according to the invention. Therefore, the exemplary embodiments of the invention disclosed herein are used only in a general and descriptive sense and are not intended to be limiting.

[0036] In the following description, specific embodiments will be described in more detail with reference to the accompanying drawings.

[0037] Figure 1 This is a plan view of a display device 1 according to some example embodiments. Figure 2 This is a schematic block diagram of a display device 1 according to some example embodiments.

[0038] Display device 1 is a device for displaying moving (e.g., video) images or still (e.g., static) images. Display device 1 can be used as a display screen in portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), as well as in various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IoT).

[0039] The display device 1 according to some example embodiments may be substantially rectangular in a plan view (e.g., when viewed in a direction perpendicular or orthogonal to the main plane of the display surface). The display device 1 may be shaped like a rectangle with right-angled corners in a plan view. However, embodiments according to this disclosure are not limited thereto, and the display device 1 may also be shaped like a rectangle with rounded corners in a plan view.

[0040] In the accompanying drawings, the first direction DR1 represents the horizontal direction of the display device 1 in a plan view, and the second direction DR2 represents the vertical direction of the display device 1 in a plan view. Additionally, the third direction DR3 represents the thickness direction of the display device 1. The first direction DR1 and the second direction DR2 intersect each other perpendicularly, and the third direction DR3 intersects both the first direction DR1 and the second direction DR2 perpendicularly in the direction intersecting the plane containing them. However, the directions mentioned with respect to the described exemplary embodiments should be understood as relative directions, and the embodiments are not limited to the mentioned directions.

[0041] Unless otherwise defined, the terms “upper,” “upper surface,” and “upper side” as used herein by DR3 refer to the display surface side of the display device 1, and the terms “lower,” “lower surface,” and “lower side” refer to the side of the display device 1 opposite to the display surface side.

[0042] The display device 1 according to some example embodiments may include a display panel 10, a timing controller 21, a data driver 22, and a scan driver 30.

[0043] Display panel 10 may be an organic light-emitting display panel. In the following example embodiments, an embodiment in which an organic light-emitting display panel is used as display panel 10 will be described as an example. However, the embodiments according to this disclosure are not limited to this embodiment, and other types of display panels such as liquid crystal display (LCD) panels, quantum dot organic light-emitting display (QD-OLED) panels, quantum dot LCD (QD-LCD) panels, quantum nano-light-emitting display (QNED) panels, and micro light-emitting diode (Micro LED) display panels are also applicable.

[0044] Display panel 10 may include a display area DA in which an image may be displayed and a non-display area NDA in which no image is displayed (e.g., a border area or an area without pixels). In a plan view, display panel 10 may be divided into display area DA and non-display area NDA. Non-display area NDA may surround display area DA. Non-display area NDA may form a border.

[0045] The display area DA can be shaped like a rectangle with right-angled corners or a rectangle with rounded corners, similar to those in a planar drawing. The planar shape of the display area DA is not limited to a rectangle, but can also be a circle, an ellipse, or various other shapes.

[0046] The display area DA may include multiple pixels (PX). The pixels (PX) may be arranged in a matrix shape. Each pixel (PX) may include an emissive layer and a circuit layer for controlling the amount of light emitted from the emissive layer. The circuit layer may include wiring, electrodes, and at least one transistor. The emissive layer may include an organic light-emitting material. The emissive layer may be sealed with an encapsulation layer. The detailed configuration of each pixel (PX) will be described in more detail later.

[0047] The non-display area NDA can be positioned adjacent to the two short sides and two long sides of the display area DA. In this case, the non-display area NDA can surround all the sides of the display area DA and can form the edge of the display area DA. However, embodiments according to this disclosure are not limited to this, and the non-display area NDA can also be positioned adjacent only to the two short sides or the two long sides of the display area DA.

[0048] Within the display area DA, not only can pixels PX be arranged, but also multiple scan lines SL1 to SLk (where k is an integer of 2 or greater), multiple data lines DL1 to DLj (where j is an integer of 2 or greater), and multiple power lines connected to pixels PX can be arranged. Scan lines SL (i.e., scan lines SL1 to SLk) can extend along a first direction DR1 and can be arranged along a second direction DR2. Data lines DL (i.e., data lines DL1 to DLj) can extend along the second direction DR2 and can be arranged along the first direction DR1.

[0049] The display panel 10 includes pixels PX located at the intersections of scan lines SL1 to SLk (where k is an integer of 2 or greater) and data lines DL1 to DLj (where j is an integer of 2 or greater) and arranged in a matrix shape. Each of the pixels PX can be connected to at least any one of the scan lines SL (i.e., scan lines SL1 to SLk) and at least any one of the data lines DL (i.e., data lines DL1 to DLj).

[0050] The timing controller 21 receives input image data RGB from the host system and converts it into digital video data DATA. The host system can be an application processor of a smartphone or tablet PC, or a system-on-a-chip of a monitor or television (TV).

[0051] The timing controller 21 receives the control signal CS from the host system and generates a source control signal CONT2 for controlling the operating timing of the data driver 22 and a scan control signal CONT1 for controlling the operating timing of the scan driver 30 based on the control signal CS. Here, the control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal, etc.

[0052] The scan driver 30 receives a scan control signal CONT1 from the timing controller 21. The scan driver 30 generates scan signals S1 to Sk (where k is an integer of 2 or greater) according to the scan control signal CONT1, and supplies the scan signals S1 to Sk to the scan lines SL1 to SLk of the display panel 10. The scan driver 30 may include multiple thin-film transistors and may be formed in the non-display area NDA of the display panel 10. Alternatively, the scan driver 30 may be formed as an integrated circuit. In this case, the scan driver 30 may be mounted on a gate flexible film attached to the other side of the display panel 10.

[0053] Data driver 22 receives digital video data DATA and source control signal CONT2 from timing controller 21. Data driver 22 converts the digital video data DATA into an analog data voltage according to the source control signal CONT2 and supplies the analog data voltage to data lines DL1 to DLj of display panel 10. Each pixel PX, in response to one of the data signals D1 to Dj (where j is an integer of 2 or greater) received through data lines DL1 to DLj, emits light at a brightness level (e.g., a predetermined brightness level) according to the driving current supplied to the light-emitting element.

[0054] The power supply circuit can generate the voltage required to drive the display panel 10 from the main power supply applied from the system board, and can supply the generated voltage to the display panel 10. For example, the power supply circuit can generate a first power supply voltage ELVDD for driving the light-emitting element OLED of the display panel 10 from the main power supply (see [link to relevant documentation]). Figure 3 ) and the second power supply voltage ELVSS (see Figure 3 The generated power supply voltages ELVDD and ELVSS can be supplied to the first power line ELVDL of the display panel 10 (see...). Figure 3 ) and the second power line ELVSL (see Figure 3 Additionally, the power supply circuit can generate drive voltages from the main power supply to drive the timing controller 21, data driver 22, scan driver 30, etc., and can supply the generated drive voltages. The power supply circuit can be formed as an integrated circuit and can be mounted on a circuit board, but the embodiments according to this disclosure are not limited thereto.

[0055] Figure 3 This is an equivalent circuit diagram of a pixel PX of a display device 1 according to some example embodiments.

[0056] Reference Figure 3 A pixel PX may include a first transistor TR1, a second transistor TR2, a light-emitting element OLED, and a capacitor Cst. Although in Figure 3 Each pixel PX has a 2T1C structure including two transistors TR1 and TR2 and a capacitor Cst; however, embodiments according to this disclosure are not limited thereto. Each pixel PX may also include multiple pixels and multiple capacitors. For example, each pixel PX may also have various modified pixel structures such as 3T1C, 6T1C, and 7T1C structures.

[0057] Each of the first transistor TR1 and the second transistor TR2 may include a first source / drain electrode, a second source / drain electrode, and a gate electrode. One of the first source / drain electrode and the second source / drain electrode may be a source electrode, and the other may be a drain electrode.

[0058] Each of the first transistor TR1 and the second transistor TR2 can be formed as a thin-film transistor. Furthermore, although in Figure 3 In this specification, each of transistors TR1 and TR2 is described as an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), but this disclosure is not limited thereto. Each of the first transistor TR1 and the second transistor TR2 may also be formed as a P-type MOSFET. In this case, the positions of the source and drain electrodes of each of the first transistor TR1 and the second transistor TR2 can be changed. Embodiments in which each of the first transistor TR1 and the second transistor TR2 is an N-type MOSFET will be described in more detail below.

[0059] The first transistor TR1 can be a driving transistor. For example, the gate electrode of the first transistor TR1 is connected to the second source / drain electrode of the second transistor TR2 and the second electrode of the capacitor Cst. The first source / drain electrode of the first transistor TR1 is connected to the first power supply line ELVDL. The second source / drain electrode of the first transistor TR1 is connected to the anode of the light-emitting element OLED. The first transistor TR1 receives a data signal Dj (where j is an integer of 1 or greater) according to the switching operation of the second transistor TR2, and supplies driving current to the light-emitting element OLED.

[0060] The gate electrode of the second transistor TR2 is connected to the scan line SL. The first source / drain electrode of the second transistor TR2 is connected to the data line DL. The second source / drain electrode of the second transistor TR2 is connected to the gate electrode of the first transistor TR1 and the second electrode of the capacitor Cst. The second transistor TR2 is turned on by the scan signal Sk (where k is an integer of 1 or greater) to perform a switching operation for transmitting the data signal Dj (where j is an integer of 1 or greater) to the gate electrode of the first transistor TR1.

[0061] The first electrode of capacitor Cst can be connected to the first power line ELVDL and the first source / drain electrode of the first transistor TR1, and the second electrode of capacitor Cst can be connected to the gate electrode of the first transistor TR1 and the second source / drain electrode of the second transistor TR2. Capacitor Cst can maintain a constant data voltage applied to the gate electrode of the first transistor TR1.

[0062] The OLED light-emitting element can emit light according to the driving current of the first transistor TR1. The OLED light-emitting element can be an organic light-emitting diode including an anode (or a first electrode), an organic light-emitting layer, and a cathode (or a second electrode). The anode of the OLED light-emitting element can be connected to the second source / drain electrode of the first transistor TR1, and the cathode of the OLED light-emitting element can be connected to the second power supply line ELVSL. A second power supply voltage ELVSS, which is lower than the first power supply voltage ELVDD, is applied to the second power supply line ELVSL.

[0063] The planar layout and cross-sectional structure of the aforementioned pixel PX will now be described in more detail.

[0064] Figure 4 This is a layout diagram of a pixel PX of a display device 1 according to some example embodiments. Figure 5 This is a layout diagram of buffer layer 120 according to some example embodiments. Figure 6 This is a layout diagram of semiconductor layer 130 according to some example embodiments. Figure 7 It is along Figure 4 The cross-sectional view taken from line VII-VII'.

[0065] Reference Figures 4 to 7 A pixel PX may include an emission region EA and a circuit region CA. The emission region EA is the area where the light-emitting element OLED is arranged and emits light. The circuit region CA is electrically connected to the data line DL and the scan line SL, and includes a first transistor TR1, a second transistor TR2, and a capacitor Cst. Furthermore, the circuit region CA may include a first transistor region TRR1, a second transistor region TRR2, and a capacitor region CPR. The circuit region CA is the area used to drive the light-emitting element OLED.

[0066] Each of transistors TR1 and TR2 includes a conductive layer forming electrodes, a semiconductor pattern forming a channel, and an insulating layer. Capacitor Cst includes a conductive layer forming electrodes and an insulating layer disposed between the conductive layers. For example, capacitor Cst includes a first electrode 113 (or a lower electrode of the capacitor), a second electrode 143 (or an upper electrode of the capacitor), and an insulating layer disposed between the first electrode 113 and the second electrode 143. The conductive material or conductive layer, the semiconductor layer, and the aforementioned insulating layer are disposed on a substrate 101.

[0067] A display panel 10 according to some example embodiments includes a semiconductor layer 130, a plurality of conductive layers, and a plurality of insulating layers disposed on a substrate 101. The conductive layers may include a first conductive layer 110, a second conductive layer 140, and an anode (ANO). The insulating layers may include a buffer layer 120, a gate insulating layer (GI), a passivation layer (PVX), and a via layer (VIA). The layers of the display panel 10 may be disposed on the substrate 101 in the following order: a barrier layer 102, a first conductive layer 110, a buffer layer 120, a semiconductor layer 130, a gate insulating layer (GI), a second conductive layer 140, a passivation layer (PVX), a via layer (VIA), an anode (ANO), and a pixel defining layer (PDL). Each of the above layers may be a single layer or a stack of multiple layers. Another layer may also be disposed between the above layers.

[0068] The substrate 101 supports each layer disposed on the substrate 101. The substrate 101 may be made of an insulating material such as a polymer resin. The polymer material may be, for example, polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. The substrate 101 may also include a metallic material.

[0069] The substrate 101 can be a flexible substrate capable of being bent, folded, rolled, etc. The material forming the flexible substrate can be, but is not limited to, polyimide (PI).

[0070] When the organic light-emitting display panel is bottom-emitting or double-sided-emitting, a transparent substrate can be used. When the organic light-emitting display panel is top-emitting, not only transparent substrates but also translucent or opaque substrates can be used.

[0071] A barrier layer 102 may be disposed on a substrate 101. The barrier layer 102 can prevent or reduce the diffusion of impurity ions, prevent or reduce the penetration of moisture or external air, and perform surface planarization. The barrier layer 102 may include silicon nitride, silicon oxide, or silicon oxynitride. Depending on the type of substrate 101 or processing conditions, the barrier layer 102 may be omitted.

[0072] The first conductive layer 110 is disposed on the barrier layer 102. However, this disclosure is not limited thereto. When the barrier layer 102 is omitted, the first conductive layer 110 may be disposed on the substrate 101. The first conductive layer 110 may be disposed in the display area DA and may include a first power line ELVDL (see [link to documentation]). Figure 3 The corresponding first power supply wiring 111, the lower light-blocking pattern 114, and the data cable DL (see...) Figure 3 The corresponding data wiring 112 and the first electrode 113 of capacitor Cst.

[0073] In the plan view, the first power supply wiring 111 can be positioned to the right of pixel PX. The first power supply wiring 111 can extend in the second direction DR2. The first power supply wiring 111 can extend in the second direction DR2 to another pixel PX adjacent to pixel PX.

[0074] The first power supply wiring 111 may pass through the first transistor region TRR1. In the figures, a portion of the first power supply wiring 111 extending in the second direction DR2 protrudes in the first direction DR1, and the protruding portion overlaps with the first transistor region TRR1. However, this disclosure is not limited thereto. For example, the first power supply wiring 111 may also extend in the second direction DR2 while passing through the first transistor region TRR1 without the aforementioned protruding portion.

[0075] The first power supply wiring 111 can pass through at least a portion of the first transistor region TRR1 to overlap with at least a portion of the first source / drain electrode 141a of the first transistor TR1 in the thickness direction and can directly contact at least a portion of the first source / drain electrode 141a of the first transistor TR1, which will be described later. In other words, the first source / drain electrode 141a of the first transistor TR1 can be formed on the first power supply wiring 111, and at least a portion of the upper surface and / or side surface of the first power supply wiring 111 can be covered by the first source / drain electrode 141a of the first transistor TR1.

[0076] Data routing 112 can be positioned to the left of pixel PX in the plan view and can extend in the second direction DR2. Data routing 112 can extend in the second direction DR2 to another pixel PX adjacent to pixel PX. Data routing 112 can be positioned to the left of the first power routing 111 and can be spaced apart from the first power routing 111.

[0077] Data wiring 112 may pass through the second transistor region TRR2. In the figures, a portion of the data wiring 112 extending in the second direction DR2 protrudes in the first direction DR1, and the protruding portion overlaps with the second transistor region TRR2. However, this disclosure is not limited thereto. For example, data wiring 112 may also extend in the second direction DR2 while passing through the second transistor region TRR2 without the aforementioned protruding portion.

[0078] Data wiring 112 can pass through at least a portion of the second transistor region TRR2 to overlap in the thickness direction and can directly contact at least a portion of the first source / drain electrode 142a of the second transistor TR2, which will be described later. In other words, the first source / drain electrode 142a of the second transistor TR2 can be formed on the data wiring 112, and at least a portion of the upper surface and / or side surface of the data wiring 112 can be covered by the first source / drain electrode 142a of the second transistor TR2. The first electrode 113 of capacitor Cst can protrude from the first power supply wiring 111 in the first direction DR1 and can be generally located in the central portion of the circuit region CA. In a plan view, the first electrode 113 of capacitor Cst can be arranged between the first power supply wiring 111 and the data wiring 112. For example, the first electrode 113 of capacitor Cst can be connected to the first power supply wiring 111 on the left side of the first power supply wiring 111 and on the right side of the data wiring 112, and can be spaced apart from the data wiring 112. According to some example embodiments, the first electrode 113 of the capacitor Cst may be substantially rectangular, but this disclosure is not limited thereto.

[0079] A lower light-blocking pattern 114 can be formed in the first transistor region TRR1. The lower light-blocking pattern 114 can prevent or reduce light incident from below the display panel 10 from entering the semiconductor pattern 131 of the first transistor TR1 positioned above the lower light-blocking pattern 114, particularly entering the channel region 131c of the semiconductor pattern 131. That is, the lower light-blocking pattern 114 can cover at least the channel region 131c of the semiconductor pattern 131 of the first transistor TR1, and can extend to cover the entire semiconductor pattern 131 of the first transistor TR1. In other words, the lower light-blocking pattern 114 can overlap with at least the channel region 131c of the semiconductor pattern 131 of the first transistor TR1. Additionally, the lower light-blocking pattern 114 can serve as another gate electrode of the oxide transistor. In this case, the lower light-blocking pattern 114 can be electrically connected to the gate electrode 141c of the first transistor TR1.

[0080] The first conductive layer 110 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 110 may be a single layer or multiple layers.

[0081] A buffer layer 120 is disposed on the first conductive layer 110. The buffer layer 120 can be disposed entirely on the first conductive layer 110 and the barrier layer 102 exposed by the first conductive layer 110 in the display area DA and the non-display area DA.

[0082] The buffer layer 120 may cover the first conductive layer 110 in the display area DA and the non-display area NDA, and may be disposed on the entire surface of the barrier layer 102. The buffer layer 120 may serve as an interlayer insulating film that insulates the first conductive layer 110 and the semiconductor layer 130 from each other. As will be described later, the buffer layer 120 may be formed to have the same planar shape as the semiconductor layer 130.

[0083] Buffer layer 120 may include a first buffer 121, a second buffer 122, and a third buffer 123. The first buffer 121 and the second buffer 122 may be arranged in each pixel PX, and the third buffer 123 may be arranged across multiple pixels PX. The first buffer 121 and the second buffer 122 may be arranged in the circuit region CA of each pixel PX, and the third buffer 123 may be arranged across multiple pixels PX as described above, while also being arranged in a large portion of the emission region EA and the circuit region CA of each pixel PX. For example, the first buffer 121 may be arranged in the first transistor region TRR1, and the second buffer 122 may be arranged in the second transistor region TRR2. A portion of the third buffer 123 may be arranged in the capacitor region CPR to fill the remaining area of ​​the pixel PX where the first buffer 121 and the second buffer 122 are not arranged. That is, the third buffer 123 may occupy a large portion of the area of ​​buffer layer 120.

[0084] The first buffer 121 and the second buffer 122 may extend in the first direction DR1 and may be spaced apart from each other. However, this disclosure is not limited thereto, and the first buffer 121 and / or the second buffer 122 may also extend in the second direction DR2. Alternatively, the first buffer 121 and the second buffer 122 may be connected to each other and may be spaced apart from the third buffer 123.

[0085] Buffer layer 120 may further include a first buffer opening OPB1 and a second buffer opening OPB2 defined by a third buffer 123. The first buffer opening OPB1 and the second buffer opening OPB2 may be arranged in the circuit region CA and may be spaced apart from each other.

[0086] A first buffer 121 may be arranged in a first buffer opening OPB1, and a second buffer 122 may be arranged in a second buffer opening OPB2. In a plan view, the first buffer 121 and the second buffer 122 may be spaced apart from each other and may be formed in an island shape. The first buffer 121 and the second buffer 122 may be spaced apart from a third buffer 123 and may be surrounded by the third buffer 123. The first buffer opening OPB1 and the second buffer opening OPB2 may expose at least a portion of the underlying barrier layer 102 and / or at least a portion of the underlying first conductive layer 110 in areas in which the first buffer 121 and the second buffer 122 are not arranged.

[0087] At least a portion of the first conductive layer 110 may be disposed in the first buffer opening OPB1 and the second buffer opening OPB2. In the figures, only a portion of the first power supply wiring 111 and only a portion of the data wiring 112 are disposed in the first buffer opening OPB1 and the second buffer opening OPB2, and the entire lower light-blocking pattern 114 is disposed in the first buffer opening OPB1. However, this disclosure is not limited thereto.

[0088] The first buffer opening OPB1 can overlap with the first transistor region TRR1, and the second buffer opening OPB2 can overlap with the second transistor region TRR2. In other words, in the plan view, the first transistor TR1 can be arranged in the first buffer opening OPB1. That is, the semiconductor pattern 131, the first source / drain electrode 141a, the second source / drain electrode 141b, and the gate electrode 141c of the first transistor TR1 can overlap with the first buffer opening OPB1 in the thickness direction (third direction DR3). Furthermore, in the plan view, the second transistor TR2 can be arranged in the second buffer opening OPB2. That is, the semiconductor pattern 132, the first source / drain electrode 142a, the second source / drain electrode 142b, and the gate electrode 142c of the second transistor TR2 can overlap with the second buffer opening OPB2 in the thickness direction (third direction DR3).

[0089] The second conductive layer 140, the passivation layer PVX, and / or the via layer VIA can be arranged in the space between the first buffer zone 121, the second buffer zone 122, and the third buffer zone 123. That is, in the first buffer opening OPB1 and the second buffer opening OPB2, the second conductive layer 140, the passivation layer PVX, and / or the via layer VIA can fill the space where the first buffer zone 121 and the second buffer zone 122 are not arranged.

[0090] The buffer layer 120 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. Depending on the type of substrate 101 or the processing conditions, the buffer layer 120 may be omitted.

[0091] Semiconductor layer 130 can be disposed on buffer layer 120. In other words, semiconductor layer 130 can overlap with buffer layer 120 and can have the same planar shape as buffer layer 120. Semiconductor layer 130 can be disposed on the entire surface of buffer layer 120 in display area DA and non-display area NDA. Semiconductor layer 130 can be disposed in emission area EA and circuit area CA of pixel PX.

[0092] For example, semiconductor layer 130 may include a semiconductor pattern 131 of a first transistor TR1, a semiconductor pattern 132 of a second transistor TR2, and a semiconductor dummy portion 133. The semiconductor pattern 131 of the first transistor TR1 may be an active layer of the first transistor TR1, and the semiconductor pattern 132 of the second transistor TR2 may be an active layer of the second transistor TR2. The semiconductor dummy portion 133 may be a portion of semiconductor layer 130 other than the semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2, and may occupy a large portion of the area of ​​semiconductor layer 130.

[0093] The semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2 can be arranged in each pixel PX, and the semiconductor dummy portion 133 can be arranged to span multiple pixels PX. The semiconductor pattern 131 of the first transistor TR1 can be arranged in the first transistor region TRR1, and the semiconductor pattern 132 of the second transistor TR2 can be arranged in the second transistor region TRR2. The semiconductor dummy portion 133 can be arranged in the capacitor region CPR and can be arranged in most of the circuit region CA and the emission region EA of the pixel PX.

[0094] The semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2 may extend in the first direction DR1 and may be spaced apart from each other. However, this disclosure is not limited thereto, and the semiconductor pattern 131 of the first transistor TR1 and / or the semiconductor pattern 132 of the second transistor TR2 may also extend in the second direction DR2. Alternatively, the semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2 may be connected to each other and may be spaced apart from the semiconductor dummy portion 133.

[0095] The semiconductor pattern 131 of the first transistor TR1, the semiconductor pattern 132 of the second transistor TR2, and the semiconductor dummy portion 133 of the semiconductor layer 130 may have substantially the same planar shape as the first buffer 121, the second buffer 122, and the third buffer 123 of the buffer layer 120.

[0096] For example, the planar shape of the semiconductor pattern 131 of the first transistor TR1 can be substantially the same as the planar shape of the first buffer 121 of the buffer layer 120. The length of the semiconductor pattern 131 of the first transistor TR1 extending in the first direction DR1 can be equal to or less than the length of the first buffer 121 extending in the first direction DR1. In addition, the width of the semiconductor pattern 131 of the first transistor TR1 in the second direction DR2 can be equal to or less than the width of the first buffer 121 in the second direction DR2. In this case, the semiconductor pattern 131 of the first transistor TR1 and the first buffer 121 can completely overlap each other, such that the side surface of the semiconductor pattern 131 of the first transistor TR1 is aligned with the side surface of the first buffer 121, or such that the entire semiconductor pattern 131 of the first transistor TR1 overlaps with at least a portion of the first buffer 121.

[0097] The planar shape of the semiconductor pattern 132 of the second transistor TR2 can be substantially the same as the planar shape of the second buffer 122 of the buffer layer 120. The length of the semiconductor pattern 132 of the second transistor TR2 extending in the first direction DR1 can be equal to or less than the length of the second buffer 122 extending in the first direction DR1. Additionally, the width of the semiconductor pattern 132 of the second transistor TR2 in the second direction DR2 can be equal to or less than the width of the second buffer 122 in the second direction DR2. In this case, the semiconductor pattern 132 of the second transistor TR2 and the second buffer 122 can completely overlap each other, such that the side surface of the semiconductor pattern 132 of the second transistor TR2 is aligned with the side surface of the second buffer 122, or such that the entire semiconductor pattern 132 of the second transistor TR2 overlaps with at least a portion of the second buffer 122.

[0098] The planar shape of the semiconductor dummy portion 133 may be substantially the same as the planar shape of the third buffer 123 of the buffer layer 120. The semiconductor dummy portion 133 may completely overlap with the third buffer 123 of the buffer layer 120, and the side surface of the semiconductor dummy portion 133 may be aligned with the side surface of the third buffer 123 of the buffer layer 120. However, this disclosure is not limited thereto, and the entire semiconductor dummy portion 133 may also overlap with a portion of the third buffer 123.

[0099] The semiconductor layer 130 may further include a first semiconductor opening OPS1 and a second semiconductor opening OPS2 defined by the semiconductor dummy portion 133. The first semiconductor opening OPS1 and the second semiconductor opening OPS2 of the semiconductor layer 130 may be formed to have substantially the same shape as the first buffer opening OPB1 and the second buffer opening OPB2 of the buffer layer 120, respectively. In other words, the planar shape of the first semiconductor opening OPS1 may be substantially the same as the planar shape of the first buffer opening OPB1, and the first semiconductor opening OPS1 may overlap with the first buffer opening OPB1. The planar shape of the second semiconductor opening OPS2 may be substantially the same as the planar shape of the second buffer opening OPB2, and the second semiconductor opening OPS2 may overlap with the second buffer opening OPB2.

[0100] The semiconductor pattern 131 of the first transistor TR1 can be arranged in the first semiconductor opening OPS1, and the semiconductor pattern 132 of the second transistor TR2 can be arranged in the second semiconductor opening OPS2. That is, the semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2 can be spaced apart from each other and can be formed into an island shape in the planar view. In addition, the semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2 can be spaced apart from the semiconductor dummy portion 133 and can be surrounded by the semiconductor dummy portion 133.

[0101] The second conductive layer 140, the passivation layer PVX, and / or the via layer VIA can be disposed in the space between the semiconductor pattern 131 of the first transistor TR1, the semiconductor pattern 132 of the second transistor TR2, and the semiconductor dummy portion 133. That is, in the first semiconductor opening OPS1 and the second semiconductor opening OPS2, the second conductive layer 140, the passivation layer PVX, and / or the via layer VIA can fill the space in which the semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2 are not disposed.

[0102] The first semiconductor opening OPS1 can overlap with the first transistor region TRR1, and the second semiconductor opening OPS2 can overlap with the second transistor region TRR2.

[0103] The semiconductor pattern 131 of the first transistor TR1 may include a channel region 131c of the first transistor TR1, a first source / drain region 131a of the first transistor TR1, and a second source / drain region 131b of the first transistor TR1. The channel region 131c of the first transistor TR1 is overlapped in the thickness direction by the gate electrode 141c covering the first transistor TR1. The first source / drain region 131a and the second source / drain region 131b of the first transistor TR1 are respectively located on one side and the other side of the channel region 131c. The first source / drain region 131a and the second source / drain region 131b of the first transistor TR1 may be conductive regions, and may have higher conductivity and lower resistance than the channel region 131c of the first transistor TR1.

[0104] The semiconductor pattern 132 of the second transistor TR2 may include a channel region 132c of the second transistor TR2, a first source / drain region 132a of the second transistor TR2, and a second source / drain region 132b of the second transistor TR2. The channel region 132c of the second transistor TR2 is overlapped in the thickness direction by the gate electrode 142c covering the second transistor TR2. The first source / drain region 132a and the second source / drain region 132b of the second transistor TR2 are respectively located on one side and the other side of the channel region 132c. The first source / drain region 132a and the second source / drain region 132b of the second transistor TR2 may be conductive regions, and may have higher conductivity and lower resistance than the channel region 132c of the second transistor TR2.

[0105] Semiconductor layer 130 may include an oxide semiconductor. Examples of oxide semiconductors may include binary compounds (AB) comprising indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB) x C y ) and quaternary compounds (AB) x C y D z According to some example embodiments, semiconductor layer 130 may include indium tin zinc oxide (IGZO).

[0106] A gate insulating layer GI is disposed on the semiconductor layer 130. The gate insulating layer GI may be disposed on only a portion of the semiconductor layer 130. That is, the gate insulating layer GI may overlap with a portion of the semiconductor layer 130. The gate insulating layer GI may cover the channel regions 131c and 132c of the semiconductor layer 130, and may expose the first source / drain regions 131a and 132a and the second source / drain regions 131b and 132b of the semiconductor layer 130, as well as the side surfaces.

[0107] The gate insulating layer GI may include a first gate insulating layer region GI1, a second gate insulating layer region GI2, and a third gate insulating layer region GI3. The first gate insulating layer region GI1 may be disposed in a first transistor region TRR1, and the second gate insulating layer region GI2 may be located in a second transistor region TRR2. The third gate insulating layer region GI3 may be located in a capacitor region CPR and may be located in most of the circuit region CA and the emitter region EA of the non-display region NDA and the display region DA. The third gate insulating layer region GI3 may occupy most of the area of ​​the gate insulating layer GI. However, this disclosure is not limited thereto, and the third gate insulating layer region GI3 may be removed according to the process.

[0108] The first gate insulating layer region GI1 may have a planar shape substantially the same as that of the gate electrode 141c of the first transistor TR1 located on the first gate insulating layer region GI1, and the second gate insulating layer region GI2 may have a planar shape substantially the same as that of the gate electrode 142c of the second transistor TR2 located on the second gate insulating layer region GI2. The third gate insulating layer region GI3 may have a planar shape substantially the same as that of the semiconductor dummy portion 133 of the semiconductor layer 130 and the third buffer 123 of the buffer layer 120 located below the third gate insulating layer region GI3. The side surface of the third gate insulating layer region GI3 may be aligned with the side surface of the semiconductor dummy portion 133 and the side surface of the third buffer 123.

[0109] The gate insulating layer GI can include silicon compounds or metal oxides. For example, the gate insulating layer GI can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These materials can be used alone or in combination with each other.

[0110] The second conductive layer 140 is positioned on the gate insulating layer GI. The second conductive layer 140 may include: a first source / drain electrode 141a, a second source / drain electrode 141b, and a gate electrode 141c of the first transistor TR1; a first source / drain electrode 142a, a second source / drain electrode 142b, and a gate electrode 142c of the second transistor TR2; a second electrode 143 (or upper electrode) of the capacitor Cst; and a connection to the scan line SL (see [link to relevant documentation]). Figure 3 The corresponding scan wiring 144.

[0111] The first source / drain electrode 141a, the second source / drain electrode 141b, and the gate electrode 141c of the first transistor TR1 can be located in the first transistor region TRR1, and the first source / drain electrode 142a, the second source / drain electrode 142b, and the gate electrode 142c of the second transistor TR2 can be located in the second transistor region TRR2, and the second electrode 143 of the capacitor Cst can be located in the capacitor region CPR.

[0112] The first source / drain electrode 141a, the second source / drain electrode 141b, and the gate electrode 141c of the first transistor TR1 may overlap with the first semiconductor opening OPS1 and the first buffer opening OPB1, or at least a portion of each of the first source / drain electrode 141a, the second source / drain electrode 141b, and the gate electrode 141c of the first transistor TR1 may be located in the first semiconductor opening OPS1 and the first buffer opening OPB1. Furthermore, the first source / drain electrode 141a and the second source / drain electrode 141b of the first transistor TR1 may cover the upper surface and / or side surface of the semiconductor pattern 131 of the first transistor TR1 while simultaneously covering a portion of the first conductive layer 110 (e.g., the first power wiring 111 and the lower light-blocking pattern 114).

[0113] For example, the first source / drain electrode 141a of the first transistor TR1 can directly contact at least a portion of the upper surface and / or side surface of the first source / drain region 131a of the semiconductor pattern 131 of the first transistor TR1, and can cover at least a portion of the upper surface and / or side surface of the first source / drain region 131a of the semiconductor pattern 131 of the first transistor TR1. The first source / drain electrode 141a of the first transistor TR1 can directly contact the side surface of the first buffer layer 121 of the buffer layer 120, and can cover the side surface of the first buffer layer 121. The first source / drain electrode 141a of the first transistor TR1 can directly contact a portion of the first conductive layer 110, that is, at least a portion of the upper surface and / or side surface of the first power wiring 111, and can cover at least a portion of the upper surface and / or side surface of the first power wiring 111. In addition, the first source / drain electrode 141a of the first transistor TR1 can contact the upper surface of the barrier layer 102, but this disclosure is not limited thereto.

[0114] In other words, the first source / drain electrode 141a of the first transistor TR1 can extend along the side surface of the semiconductor pattern 131 of the first transistor TR1 and the side surface of the first buffer 121, and can directly contact the first source / drain region 131a and the first power supply wiring 111 of the first transistor TR1 without contacting the contact hole, and can electrically connect the first source / drain region 131a of the first transistor TR1 to the first power supply wiring 111.

[0115] The second source / drain electrode 141b of the first transistor TR1 may overlap with at least a portion of the semiconductor pattern 131 of the first transistor TR1, particularly with at least a portion of the second source / drain region 131b of the first transistor TR1, and / or with at least a portion of the first conductive layer 110, particularly with at least a portion of the lower light-blocking pattern 114.

[0116] For example, the second source / drain electrode 141b of the first transistor TR1 can directly contact at least a portion of the upper surface and / or side surface of the second source / drain region 131b of the semiconductor pattern 131 of the first transistor TR1, and can cover at least a portion of the upper surface and / or side surface of the second source / drain region 131b of the semiconductor pattern 131 of the first transistor TR1. The second source / drain electrode 141b of the first transistor TR1 can directly contact the side surface of the first buffer layer 121 of the buffer layer 120, and can cover the side surface of the first buffer layer 121. The second source / drain electrode 141b of the first transistor TR1 can directly contact a portion of the first conductive layer 110, that is, at least a portion of the upper surface and / or side surface of the lower light-blocking pattern 114, and can cover at least a portion of the upper surface and / or side surface of the lower light-blocking pattern 114. In addition, the second source / drain electrode 141b of the first transistor TR1 can contact the upper surface of the blocking layer 102, but this disclosure is not limited thereto.

[0117] In other words, the second source / drain electrode 141b of the first transistor TR1 can extend along the side surface of the semiconductor pattern 131 of the first transistor TR1 and the side surface of the first buffer 121, and can directly contact the second source / drain region 131b of the first transistor TR1 and the lower light-blocking pattern 114 without contacting the contact hole, and can electrically connect the second source / drain region 131b of the first transistor TR1 to the lower light-blocking pattern 114.

[0118] In the plan view, the gate electrode 141c of the first transistor TR1 can protrude from the upper side of the second electrode 143 of the capacitor Cst. The gate electrode 141c of the first transistor TR1 can branch upward from the second electrode 143 of the capacitor Cst in the second direction DR2 to overlap with the channel region 131c of the semiconductor pattern 131 of the first transistor TR1.

[0119] The first source / drain electrode 142a, the second source / drain electrode 142b, and the gate electrode 142c of the second transistor TR2 may overlap with the second semiconductor opening OPS2 and the second buffer opening OPB2, or at least a portion of each of the first source / drain electrode 142a, the second source / drain electrode 142b, and the gate electrode 142c of the second transistor TR2 may be located in the second semiconductor opening OPS2 and the second buffer opening OPB2. Furthermore, the first source / drain electrode 142a and the second source / drain electrode 142b of the second transistor TR2 may cover the upper surface and / or side surface of the semiconductor pattern 132 of the second transistor TR2 while simultaneously covering a portion of the first conductive layer 110 (e.g., data wiring 112).

[0120] The first source / drain electrode 142a of the second transistor TR2 may overlap with at least a portion of the semiconductor pattern 132 of the second transistor TR2, particularly with at least a portion of the first source / drain region 132a of the second transistor TR2, and / or with at least a portion of the first conductive layer 110, particularly with at least a portion of the data wiring 112.

[0121] For example, the first source / drain electrode 142a of the second transistor TR2 can directly contact at least a portion of the upper surface and / or side surface of the first source / drain region 132a of the semiconductor pattern 132 of the second transistor TR2, and can cover at least a portion of the upper surface and / or side surface of the first source / drain region 132a of the semiconductor pattern 132 of the second transistor TR2. The first source / drain electrode 142a of the second transistor TR2 can directly contact the side surface of the second buffer layer 122 of the buffer layer 120, and can cover the side surface of the second buffer layer 122. The first source / drain electrode 142a of the second transistor TR2 can directly contact a portion of the first conductive layer 110, i.e., at least a portion of the upper surface and / or side surface of the data wiring 112, and can cover at least a portion of the upper surface and / or side surface of the data wiring 112. Additionally, the first source / drain electrode 142a of the second transistor TR2 can contact the upper surface of the barrier layer 102, but this disclosure is not limited thereto.

[0122] In other words, the first source / drain electrode 142a of the second transistor TR2 can extend along the side surface of the semiconductor pattern 132 of the second transistor TR2 and the side surface of the second buffer 122, and can directly contact the first source / drain region 132a and the data wiring 112 of the second transistor TR2 without the need for a contact hole, and can electrically connect the first source / drain region 132a of the second transistor TR2 to the data wiring 112.

[0123] The second source / drain electrode 142b of the second transistor TR2 can directly contact at least a portion and / or a side surface of the upper surface of the second source / drain region 132b of the semiconductor pattern 132 of the second transistor TR2, and can cover at least a portion and / or a side surface of the upper surface of the second source / drain region 132b of the semiconductor pattern 132 of the second transistor TR2. The second source / drain electrode 142b of the second transistor TR2 can directly contact the side surface of the second buffer layer 122 of the buffer layer 120, and can cover the side surface of the second buffer layer 122. Additionally, the second source / drain electrode 142b of the second transistor TR2 can contact the upper surface of the barrier layer 102, but this disclosure is not limited thereto.

[0124] The gate electrode 142c of the second transistor TR2 can protrude from the scan wiring 144. The gate electrode 142c of the second transistor TR2 can branch upward from the scan wiring 144 in the second direction DR2 to overlap with the channel region 132c of the semiconductor pattern 132 of the second transistor TR2.

[0125] The second electrode 143 of capacitor Cst may be positioned on the first electrode 113 of capacitor Cst to overlap at least a portion of the first electrode 113 of capacitor Cst. The shape of the second electrode 143 of capacitor Cst may be substantially similar to the shape of the first electrode 113 of capacitor Cst. The second electrode 143 of capacitor Cst may be smaller in area than the first electrode 113 of capacitor Cst to expose a portion of the first electrode 113 of capacitor Cst.

[0126] The second electrode 143 of capacitor Cst can overlap with the first electrode 113 of capacitor Cst, and the third buffer layer 123 of buffer layer 120, the semiconductor dummy portion 133 of semiconductor layer 130, and the third gate insulating layer region GI3 of gate insulating layer GI are located between the second electrode 143 and the first electrode 113 of capacitor Cst, thereby forming capacitor Cst. The third buffer layer 123 of buffer layer 120, the semiconductor dummy portion 133 of semiconductor layer 130, and the third gate insulating layer region GI3 of gate insulating layer GI located between the first electrode 113 and the second electrode 143 of capacitor Cst can be the dielectric of capacitor Cst. However, the third gate insulating layer region GI3 of gate insulating layer GI can be removed according to the process.

[0127] The second electrode 143 of capacitor Cst can be located throughout the entire capacitor region CPR. The second electrode 143 of capacitor Cst can be located throughout the entire capacitor region CPR and can partially extend to connect to the gate electrode 141c of the first transistor TR1 and the second source / drain electrode 142b of the second transistor TR2. For example, the second electrode 143 of capacitor Cst can be located within the capacitor region CPR and can be physically connected and / or electrically connected to the gate electrode 141c of the first transistor TR1 located in the first transistor region TRR1 and the second source / drain electrode 142b of the second transistor TR2 located in the second transistor region TRR2.

[0128] The second electrode 143 of capacitor Cst, the gate electrode 141c of first transistor TR1, and the second source / drain electrode 142b of second transistor TR2 can be integrated into a second conductive layer pattern.

[0129] In the plan view, scan wiring 144 can be positioned below pixel PX (or below circuit region CA). Scan wiring 144 can extend in a first direction DR1. Scan wiring 144 can extend to another pixel PX adjacent to pixel PX in the first direction DR1. Scan wiring 144 can be positioned on a different layer from the first power wiring 111 and data wiring 112, and can be positioned above the first power wiring 111 and data wiring 112. Scan wiring 144 extending in the first direction DR1 can intersect with the first power wiring 111 and data wiring 112 extending in a second direction DR2. However, at the intersection of scan wiring 144 with each of the first power wiring 111 and data wiring 112, one or more insulating layers can be positioned between scan wiring 144 and each of the first power wiring 111 and data wiring 112 to insulate scan wiring 144 from each of the first power wiring 111 and data wiring 112. The scan wiring 144 can be positioned below the second electrode 143 of the capacitor Cst and can be spaced apart from the second electrode 143 of the capacitor Cst.

[0130] The second conductive layer 140 may be made of a material with low resistivity. The second conductive layer 140 may be, but is not limited to, one or more metals selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0131] An interlayer insulating film is positioned on the second conductive layer 140. The interlayer insulating film may include a passivation layer PVX and a via layer VIA. The passivation layer PVX is positioned on the second conductive layer 140. The passivation layer PVX covers the second conductive layer 140 to protect it. The passivation layer PVX may be formed not only on the second conductive layer 140, but also in the first semiconductor opening OPS1, the second semiconductor opening OPS2, the first buffer opening OPB1, and the second buffer opening OPB2.

[0132] For example, the passivation layer PVX can cover not only the upper and side surfaces of the second conductive layer 140, but also the upper and / or side surfaces of the gate insulating layer GI, the upper and / or side surfaces of the semiconductor layer 130, the upper and / or side surfaces of the buffer layer 120, the upper and / or side surfaces of the first conductive layer 110, and the upper surface of the barrier layer 102.

[0133] The passivation layer PVX may comprise an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide. According to some example embodiments, the passivation layer PVX may be formed in the display area DA, but may not be formed in at least a portion of the non-display area NDA.

[0134] The via layer VIA is positioned on the passivation layer PVX. The via layer VIA can be positioned on the passivation layer PVX to completely cover the upper surface of the passivation layer PVX. The via layer VIA can also be positioned within the first semiconductor opening OPS1, the second semiconductor opening OPS2, the first buffer opening OPB1, and the second buffer opening OPB2. When the via layer VIA is made of an organic layer, the upper surface of the via layer VIA can be flat, regardless of any steps beneath the via layer VIA.

[0135] The through-hole layer VIA may include inorganic insulating materials or organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The through-hole layer VIA may also include photosensitive materials, but this disclosure is not limited thereto.

[0136] The anode (ANO) is located on the via layer (VIA). The anode (ANO) can be individually located within each pixel (PX). The anode (ANO) is electrically connected to the second source / drain electrode 141b of the first transistor TR1 via a contact hole (CNT) that penetrates the via layer (VIA) and exposes a portion of the second source / drain electrode 141b of the first transistor TR1. The anode (ANO) can be located in the display area (DA) or not in the non-display area (NDA).

[0137] The anode ANO can have, but is not limited to, a stacked structure in which layers of materials with a high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In₂O₃), are stacked, along with reflective material layers such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof. The high work function material layers can be positioned on top of the reflective material layers close to the light-emitting layer (EL). The anode ANO can have, but is not limited to, a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO.

[0138] The pixel defining layer (PDL) can be positioned on the anode (ANO). The PDL may include openings that partially expose the anode (ANO). The PDL may be made of an organic or inorganic insulating material. For example, the PDL may include at least one of polyimide resin, acrylic resin, silicone compound, and polyacrylic resin.

[0139] The light-emitting layer EL, the cathode CAT, and the thin-film encapsulation layer 150 can be further arranged on the anode ANO exposed by the pixel-defining layer PDL.

[0140] The light-emitting layer (EL) may include an organic material layer. The organic material layer of the EL may include an organic light-emitting layer, and may also include a hole injection / transport layer and / or an electron injection / transport layer.

[0141] The cathode (CAT) can be positioned on the emissive layer (EL). The cathode (CAT) can be a completely positioned common electrode, with no distinction between pixels (PX). The anode (ANO), emissive layer (EL), and cathode (CAT) can constitute an organic light-emitting element (OLED).

[0142] The cathode CAT may comprise a layer of material having a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., mixtures of Ag and Mg). The cathode CAT may also comprise a transparent metal oxide layer positioned on the material layer having a low work function.

[0143] A thin-film encapsulation layer 150 is positioned on the cathode CAT. The thin-film encapsulation layer 150 may include a first inorganic layer 151, a first organic layer 152, and a second inorganic layer 153. According to some example embodiments, the first inorganic layer 151 and the second inorganic layer 153 may be in contact with each other at their ends. The first organic layer 152 may be sealed by the first inorganic layer 151 and the second inorganic layer 153.

[0144] Each of the first inorganic layer 151 and the second inorganic layer 153 may include silicon nitride, silicon oxide, or silicon oxynitride. The first organic layer 152 may include an organic insulating material.

[0145] Now refer to Figures 8 to 18 A method for manufacturing the above-described display device 1 is described.

[0146] Figure 8 This is a flowchart illustrating a method for manufacturing a display device according to some example embodiments. Figures 9 to 18 It shows the manufacturing process. Figure 7 A cross-sectional view of the operation in the method of displaying the device.

[0147] Reference Figure 8 and Figure 9 A barrier layer 102 is formed on the entire surface of the substrate 101, and a patterned first conductive layer 110 is formed on the barrier layer 102 (operation S01: preparing the substrate and depositing and patterning the first conductive layer). The patterned first conductive layer 110 can be formed by a mask process. For example, as... Figure 9 As shown, the material layer for the first conductive layer 110 can be deposited on the entire surface of the barrier layer 102 and then patterned by a photolithography process to form the first conductive layer 110.

[0148] Next, refer to Figures 10 to 14 The buffer layer material 120a, semiconductor layer material 130a, and gate insulating layer material GIa are jointly etched to jointly pattern the buffer layer 120 and semiconductor layer 130 (operation S02: patterning the buffer layer and semiconductor layer), and then the gate insulating layer GI is patterned (operation S03: patterning the gate insulating layer). The above processes (operations S02 and S03) can be performed using a halftone mask (HFM), but this disclosure is not limited thereto. The buffer layer material 120a, semiconductor layer material 130a, and gate insulating layer material GIa can be patterned as the buffer layer 120, semiconductor layer 130, and gate insulating layer GI, respectively.

[0149] For example, buffer layer material 120a, semiconductor layer material 130a and gate insulating layer material GIA are sequentially coated on the entire surface of barrier layer 102 to cover the first conductive layer 110, and photoresist PRO is coated on gate insulating layer material GIA and then exposed to light using halftone mask HFM.

[0150] Based on light transmittance (or transmittance ratio), a halftone mask (HFM) can be divided into a light-blocking portion (BL), a first light-transmitting portion (HT), and a second light-transmitting portion (TR). The transmittance of the second light-transmitting portion (TR) can be greater than that of the first light-transmitting portion (HT).

[0151] The photoresist PRO can be divided into three regions: R1 (first region), R2 (second region), and R3 (third region). R1 ​​corresponds to the first transparent portion (HT) of the halftone mask (HFM), and R2 corresponds to the second transparent portion (TR) of the halftone mask (HFM). R3 corresponds to the light-blocking portion (BL) of the halftone mask (HFM).

[0152] The light-blocking portion BL blocks externally supplied light to prevent or reduce the amount of light reaching the third region R3 of the photoresist PRO. The first light-transmitting portion HT can control the light transmittance to transmit only a portion of the externally supplied light and can allow only a portion of the light to reach the first region R1 of the photoresist PRO. The second light-transmitting portion TR can transmit most of the externally supplied light and can allow most of the light to reach the second region R2 of the photoresist PRO.

[0153] For example, in the case of a positive photoresist exposed to light, the sensitizer can be decomposed and can form an acid. As a result, the area where the sensitizer is decomposed has the characteristic of good melting in the developer. Here, based on the chemical change characteristics of the exposed and unexposed portions, either the light-exposed portion or the unexposed portion of the photoresist in the substrate can be removed using a developer (e.g., a predetermined developer), thereby forming a photoresist pattern.

[0154] However, when using a halftone mask (HFM), a portion of the photoresist in the area corresponding to the portion that only transmits a portion of the light provided from the outside (e.g., the first light-transmitting portion HT) (e.g., the first region R1) can be removed, while other portions of the photoresist can be retained without removal. Therefore, the photoresist PRO in the third region R3 can be retained up to a first height h1, and the photoresist PRO in the first region R1 can be retained up to a second height h2. The first height h1 can be greater than the second height h2. Additionally, the photoresist in the second region R2 can be completely removed to expose a portion of the upper surface of the gate insulating layer material GIA in the second region R2. In the case of a negative photoresist, the photoresist PRO can be retained in the third region R3 and the first region R1 to opposite heights. That is, the photoresist PRO in the third region R3 can be retained up to the second height h2, and the photoresist PRO in the first region R1 can be retained up to the first height h1.

[0155] Next, in the second region R2, from which the photoresist PRO has been completely removed, the gate insulating layer material G1a, the semiconductor layer material 130a, and the buffer layer material 120a are jointly etched.

[0156] For example, in the second region R2, from which the photoresist PRO has been completely removed, the gate insulating layer material GIa, the semiconductor layer material 130a, and the buffer layer material 120a are jointly etched to form the semiconductor layer 130 and the buffer layer 120. In the process of etching the gate insulating layer material GIa, the semiconductor layer material 130a, and the buffer layer material 120a, the etching of the semiconductor layer material 130a can result in the formation of the semiconductor pattern 131 of the first transistor TR1, the semiconductor pattern 132 of the second transistor TR2, the semiconductor dummy portion 133, and the first semiconductor opening OPS1 (see...). Figure 7 ) and the second semiconductor opening OPS2 (see Figure 7 In addition, the etching of the buffer layer material 120a in the above process can lead to the formation of a first buffer 121, a second buffer 122, a third buffer 123, a first buffer opening OPB1, and a second buffer opening OPB2.

[0157] Next, after the gate insulating layer material GIa, the semiconductor layer material 130a, and the buffer layer material 120a are jointly etched, an ashing process is performed. Then, the gate insulating layer GI is patterned.

[0158] For example, the ashing process can completely remove the photoresist PRO in the first region R1 while partially removing the photoresist PRO in the third region R3, leaving a quantity (e.g., a predetermined quantity) of photoresist PRO. Therefore, the gate insulating layer material Gia of the third region R3 may not be exposed, but the gate insulating layer material Gia of the first region R1 may be exposed.

[0159] The exposed gate insulating layer material GIA of the first region R1 can be removed by etching, thereby forming a gate insulating layer GI including a first gate insulating layer region GI1, a second gate insulating layer region GI2, and a third gate insulating layer region GI3.

[0160] As described above, according to some example embodiments, the gate insulating layer GI, the semiconductor layer 130, and the buffer layer 120 can be formed by a single mask process. That is, because a separate mask process is not required for forming each of the gate insulating layer GI, the semiconductor layer 130, and the buffer layer 120, the number of mask processes can be reduced, thereby improving process efficiency.

[0161] Next, refer to Figure 15A patterned second conductive layer 140 is formed on the gate insulating layer GI (operation S04: depositing and patterning the second conductive layer). The patterned second conductive layer 140 can be formed by a mask process. For example, a material layer for the second conductive layer 140 is deposited on the entire surface of the gate insulating layer GI. In the deposition process, the material layer for the second conductive layer 140 can also be deposited on the upper surface and / or side surface of the semiconductor layer 130, the side surface of the buffer layer 120, and the upper surface and / or side surface of the first conductive layer 110. Therefore, the first source / drain electrode 141a and the second source / drain electrode 141b of the first transistor TR1 and the first source / drain electrode 142a and the second source / drain electrode 142b of the second transistor TR2 can be physically connected and / or electrically connected to the semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2, respectively. Furthermore, the first source / drain electrode 141a and the second source / drain electrode 141b of the first transistor TR1 and the first source / drain electrode 142a and the second source / drain electrode 142b of the second transistor TR2 can be physically connected and / or electrically connected to the first power supply wiring 111, the lower light-blocking pattern 114 and the data wiring 112, respectively.

[0162] Next, a photoresist layer is coated onto the material layer for the second conductive layer 140 and exposed and developed to form a photoresist pattern. Then, the photoresist pattern is used as an etching mask to etch the material layer for the second conductive layer 140. Next, as... Figure 15 As shown, the photoresist pattern is removed by a stripping or ashing process to complete the patterned second conductive layer 140.

[0163] Next, refer to Figure 16 A passivation layer PVX and a via layer VIA are formed on the second conductive layer 140, and a contact hole CNT is formed to expose a portion of the second source / drain electrode 141b of the first transistor TR1 (operation S05: depositing the passivation layer and the via layer and then forming the contact hole).

[0164] For example, a passivation layer PVX is deposited on the upper and side surfaces of the second conductive layer 140, the upper and / or side surfaces of the gate insulating layer GI, the upper and / or side surfaces of the semiconductor layer 130, the side surface of the buffer layer 120, the upper and / or side surfaces of the first conductive layer 110, and the upper surface of the barrier layer 102 to cover the second conductive layer 140. After the passivation layer PVX is deposited, a material layer for the via layer VIA is coated to form the via layer VIA. Then, the via layer VIA and the passivation layer PVX are etched to form a contact hole CNT through the via layer VIA and the passivation layer PVX to expose a portion of the second source / drain electrode 141b of the first transistor TR1.

[0165] Next, refer to Figure 17 An anode ANO is formed on the through-hole layer VIA (Operation S06: Forming an anode).

[0166] The anode ANO can be formed using a masking process. For example, a material layer for the anode ANO is deposited on the entire surface of the via layer VIA. In the deposition process, the material layer for the anode ANO can be deposited into the contact hole CNT. Therefore, the anode ANO can be connected to the second source / drain electrode 141b of the first transistor TR1. Next, a photoresist layer is coated on the material layer for the anode ANO and exposed and developed to form a photoresist pattern. Then, the photoresist pattern is used as an etching mask to etch the material layer for the anode ANO. Next, as... Figure 17 As shown, the photoresist pattern is removed by a stripping or ashing process to complete the patterned anodized ANO.

[0167] Next, refer to Figure 18 A patterned pixel-defining layer (PDL) is formed on the via layer (VIA) to cover the anode (ANO) (Operation S07: Forming the pixel-defining layer).

[0168] For example, the pixel-defining layer (PDL) may include an organic material, such as a photosensitive material. In this case, a patterned pixel-defining layer (PDL) can be formed by coating an organic material layer for the PDL and exposing and developing the organic material layer for the PDL.

[0169] The pixel defining layer (PDL) can be formed along the boundary of the pixel (PX) and can partially overlap with the anode (ANO). The PDL can be formed to overlap with the contact hole (CNT). When the anode (ANO) only partially fills the interior space of the contact hole (CNT) instead of completely filling it, the PDL can completely fill the remaining interior space of the contact hole (CNT) that is not filled by the anode (ANO).

[0170] Other embodiments will be described below. In the following embodiments, descriptions of elements identical to those described above will be omitted or briefly given, and the differences will be mainly described.

[0171] Figure 19 This is a layout diagram of buffer layer 120_1 according to some example embodiments. Figure 20 This is a layout diagram of semiconductor layer 130_1 according to some example embodiments. Figure 21 This is a layout diagram of a pixel PX of a display device according to some example embodiments. Figure 22 It is along Figure 21 The cross-sectional view taken from line XXII-XXII'. Figure 23 It is along Figure 21 The cross-sectional view taken from line XXIII-XXIII'.

[0172] Reference Figures 19 to 23 The current embodiment and Figure 4 The difference in the embodiment is that the third buffer 123_1 of the buffer layer 120_1, the semiconductor dummy portion 133_1 of the semiconductor layer 130_1 and the third gate insulating layer region GI3_1 of the gate insulating layer GI_1 arranged in the display panel 10_1 are arranged in only a portion of the circuit region CA.

[0173] For example, buffer layer 120_1 includes a first buffer 121, a second buffer 122, and a third buffer 123_1; semiconductor layer 130_1 includes a semiconductor pattern 131 of a first transistor TR1, a semiconductor pattern 132 of a second transistor TR2, and a semiconductor dummy portion 133_1; and gate insulating layer GI_1 includes a first gate insulating layer region GI1, a second gate insulating layer region GI2, and a third gate insulating layer region GI3_1. Here, the third buffer 123_1, the semiconductor dummy portion 133_1, and the third gate insulating layer region GI3_1 can be arranged only in the capacitor region CPR. That is, the third buffer 123_1, the semiconductor dummy portion 133_1, and the third gate insulating layer region GI3_1 can be arranged outside of the regions other than the first transistor region TRR1, the second transistor region TRR2, and the capacitor region CPR.

[0174] In this configuration, scan wiring 144_1 may be located within only one pixel PX without extending to another pixel PX adjacent to pixel PX in the first direction DR1. Scan wiring 144_1 may not be directly connected to scan wiring 144_1 of adjacent pixel PX, but may be electrically connected to scan wiring 144_1 of adjacent pixel PX via connection wiring CTE located on a different layer than scan wiring 144_1, first power wiring 111, and data wiring 112, as well as contact holes CNT_S1 and CNT_S2.

[0175] The connection wiring CTE can be formed on the via layer VIA and can be electrically connected to the scan wiring 144_1 of pixel PX through contact holes CNT_S1 and CNT_S2 penetrating the via layer VIA and the passivation layer PVX to expose the scan wiring 144_1. Here, a connection wiring CTE can not only be electrically connected to the scan wiring 144_1 of pixel PX, but also to the scan wiring 144_1 of another pixel PX adjacent to pixel PX in the first direction DR1. Therefore, even if the scan wiring 144_1 is only arranged in pixel PX, the scan wiring 144_1 can be electrically connected to the scan wiring 144_1 of the adjacent pixel PX through the connection wiring CTE.

[0176] The connection wiring CTE may intersect with the first power supply wiring 111 and the data wiring 112. A passivation layer PVX and a via layer VIA are disposed between the connection wiring CTE and each of the first power supply wiring 111 and the data wiring 112 to insulate the connection wiring CTE from each of the first power supply wiring 111 and the data wiring 112. That is, even if the third buffer 123_1, the semiconductor dummy portion 133_1, and the third gate insulating layer region GI3_1 are only disposed within the capacitor region CPR, the scan wiring 144_1 of pixel PX can be electrically connected to the scan wiring 144_1 of adjacent pixel PX via the connection wiring CTE, without being shorted (or short-circuited) to the first power supply wiring 111 and the data wiring 112.

[0177] The connection wiring CTE can be formed together with the anode ANO using the same mask. The contact holes CNT_S1 and CNT_S2 of the electrical connection wiring CTE and the scan wiring 144_1 can be formed together with the contact holes CNT of the electrical connection anode ANO and the second source / drain electrode 141b of the first transistor TR1 using the same mask. Therefore, separate masks are not required for forming the connection wiring CTE or the contact holes CNT_S1 and CNT_S2.

[0178] In this case, since there is no need for a separate mask process for forming each of the gate insulating layer GI_1, the semiconductor layer 130_1, and the buffer layer 120_1, the number of mask processes can be reduced, thereby improving process efficiency.

[0179] According to some example embodiments, as described above, the first power supply wiring 111 and data wiring 112 extend to the adjacent pixel PX, the scan wiring 144_1 is located only in pixel PX and does not extend to the adjacent pixel PX, and the scan wiring 144_1 of pixel PX is electrically connected to the scan wiring 144_1 of the adjacent pixel PX via a connection wiring CTE. However, this disclosure is not limited thereto, and the scan wiring 144_1 may also extend to another pixel PX adjacent to pixel PX in the first direction DR1, and the first power supply wiring 111 and data wiring 112 may also be located only in pixel PX and electrically connected to the first power supply wiring 111 and data wiring 112 of the adjacent pixel PX via a connection wiring CTE.

[0180] Figure 24 This is a cross-sectional view of the display panel 10_2 according to some example embodiments.

[0181] Reference Figure 24 The current embodiment and Figure 7 The difference in the embodiment is that a portion of the upper surface of the barrier layer 102_2 disposed in the display panel 10_2 is etched.

[0182] For example, in the etching process used to pattern the buffer layer 120 and the semiconductor layer 130, the buffer layer material 120a can be etched (see...). Figure 11 and Figure 12 The buffer layer 120 is patterned, and the exposed barrier layer 102_2 can then be further etched. In this case, not only the side surfaces of the buffer layer 120 and the semiconductor layer 130, but also the side surfaces of some areas of the etched barrier layer 102_2 can be aligned. Additionally, at the first semiconductor opening OPS1 (see...) Figure 7 ), second semiconductor aperture OPS2 (see Figure 7 ), first buffer opening OPB1 (see Figure 7 ) or the second buffer opening OPB2 (see Figure 7 In the overlapping area, the thickness of at least a portion of the barrier layer 102_2 may be less than the thickness of the other portions of the barrier layer 102_2.

[0183] In this case, since there is no need for a separate mask process for forming each of the gate insulating layer GI, semiconductor layer 130 and buffer layer 120, the number of mask processes can be reduced, thereby improving process efficiency.

[0184] Figure 25 This is a cross-sectional view of the display panel 10_3 according to some example embodiments.

[0185] Reference Figure 25 The current embodiment and Figure 7 The difference in the embodiment is that the buffer layer 120_3 arranged in the display panel 10_3 does not expose the blocking layer 102 located below the buffer layer 120_3.

[0186] For example, in the etching process used for patterning buffer layer 120_3, buffer layer material 120a (see...) Figure 11 and Figure 12 The buffer layer 120_3 can be left unremoved, retaining a small thickness. In this case, the first buffer 121, the second buffer 122, and the third buffer 123 of the buffer layer 120_3 can be connected. However, the thickness of the buffer layer 120_3 arranged between the first buffer 121, the second buffer 122, and the third buffer 123 can be less than the thickness of each of the first buffer 121, the second buffer 122, and the third buffer 123.

[0187] In this case, the upper surface and / or side surface of the first conductive layer 110 may also be partially exposed, and the first conductive layer 110 may also be electrically connected to the semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2 through the second conductive layer 140.

[0188] In this case, since there is no need for a separate mask process for forming each of the gate insulating layer GI, semiconductor layer 130 and buffer layer 120_3, the number of mask processes can be reduced, thereby improving process efficiency.

[0189] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications can be made without departing from the scope of the disclosure and without changing the essential features. Therefore, the above embodiments should be considered in a descriptive sense only and not for limiting purposes.

Claims

1. A display device, comprising: Base; A first conductive layer is located on the substrate and includes a first signal line; An insulating layer pattern is located on the first conductive layer; A semiconductor pattern is located on the insulating layer pattern; A gate insulating layer is located on the semiconductor pattern; as well as The second conductive layer includes a gate electrode located on the gate insulating layer, a first source / drain electrode, and a second source / drain electrode. The first source / drain electrode is one of a source electrode and a drain electrode, and the second source / drain electrode is the other of the source electrode and the drain electrode. The first source / drain electrode and the second source / drain electrode are each located on at least a portion of the semiconductor pattern. The insulating layer pattern and the semiconductor pattern have the same planar shape. The semiconductor pattern includes a channel region overlapping the gate electrode, a first source / drain region located on a first side of the channel region, and a second source / drain region located on a second side of the channel region. The first source / drain region is one of the source region and the drain region, and the second source / drain region is the other of the source region and the drain region. The first source / drain electrode extends along the contour of the first source / drain region and the contour of the insulating layer pattern to electrically connect the first source / drain region and the first signal line.

2. The display device according to claim 1, wherein, The first source / drain electrode directly contacts at least a portion of the first source / drain region, the insulating layer pattern, and at least a portion of the first conductive layer; and / or The gate electrode, the first source / drain electrode, and the second source / drain electrode are composed of the same conductive layer belonging to the second conductive layer and include the same material.

3. The display device according to claim 1, wherein, The side surfaces of the insulating layer pattern and the side surfaces of the semiconductor pattern are aligned with each other.

4. The display device according to claim 3, wherein, The insulating layer pattern and the semiconductor pattern are formed in an island shape.

5. The display device according to claim 1, wherein, The insulating layer pattern and the semiconductor pattern at least partially expose the first signal line, and the first source / drain electrode is located on at least a portion of the side surface of the insulating layer pattern and at least a portion of the side surface of the semiconductor pattern and electrically connects the exposed first signal line and the first source / drain region.

6. The display device according to claim 5, wherein, The first signal line is either a data line or a first power line.

7. The display device according to claim 1, wherein, The display device further includes: An interlayer insulating film is located on the second conductive layer; and The pixel electrode is located on the interlayer insulating film and is electrically connected to the first source / drain region or the second source / drain region.

8. The display device according to claim 7, wherein, The interlayer insulating film is formed on the side surface of the semiconductor pattern and / or the side surface of the insulating layer pattern.

9. The display device according to claim 1, wherein, The display device further includes a passivation layer located on the second conductive layer, wherein the passivation layer covers the upper surface of the gate electrode and at least a portion of the upper surface of the substrate.

10. The display device according to claim 9, wherein, The passivation layer at least partially covers the side surface of the semiconductor pattern and at least partially covers the side surface of the insulating layer pattern.

11. The display device according to claim 1, wherein, The first conductive layer further includes a lower light-blocking pattern, and the lower light-blocking pattern overlaps with the channel region of the semiconductor pattern.

12. The display device according to claim 11, wherein, The lower light-blocking pattern is electrically connected to the first source / drain electrode or the second source / drain electrode.

13. A display device, comprising: Base; A first conductive layer is located on the substrate and includes data wiring and a first power wiring; The first insulating layer pattern and the second insulating layer pattern are located on the first conductive layer; The semiconductor pattern includes a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern is located on the first insulating layer pattern and has the same planar shape as the first insulating layer pattern, and the second semiconductor pattern is located on the second insulating layer pattern and has the same planar shape as the second insulating layer pattern; A gate insulating layer is located on the semiconductor pattern; The second conductive layer includes a first gate electrode and a second gate electrode located on the gate insulating layer, and includes a first source / drain electrode, a second source / drain electrode, a third source / drain electrode, and a fourth source / drain electrode. The first source / drain electrode is one of a first source electrode and a first drain electrode. The second source / drain electrode is the other of the first source electrode and the first drain electrode. The third source / drain electrode is one of a second source electrode and a second drain electrode. The fourth source / drain electrode is the other of the second source electrode and the second drain electrode. The first source / drain electrode, the second source / drain electrode, the third source / drain electrode, and the fourth source / drain electrode are each located on at least a portion of the semiconductor pattern. An interlayer insulating film is located on the second conductive layer; as well as Pixel electrodes are located on the interlayer insulating film. Wherein, the first gate electrode overlaps with the first semiconductor pattern, and the second gate electrode overlaps with the second semiconductor pattern. The first semiconductor pattern includes a first channel region overlapping with the first gate electrode, a first source / drain region located on a first side of the first channel region, and a second source / drain region located on a second side of the first channel region. The second semiconductor pattern includes a second channel region overlapping with the second gate electrode, a third source / drain region located on a first side of the second channel region, and a fourth source / drain region located on a second side of the second channel region. The first source / drain region is one of a first source region and a first drain region. The second source / drain region is the other of the first source region and the first drain region; the third source / drain region is the other of the second source region and the second drain region; the fourth source / drain region is the other of the second source region and the second drain region; the first source / drain electrode is electrically connected to the first source / drain region and the data wiring; the second source / drain electrode is electrically connected to the second source / drain region and the first gate electrode; the third source / drain electrode is electrically connected to the third source / drain region and the first power wiring; and the fourth source / drain electrode is electrically connected to the fourth source / drain region and the pixel electrode.

14. The display device according to claim 13, wherein, The display device further includes: A third insulating layer pattern is located on the same layer as the first and second insulating layer patterns and is spaced apart from them; and The third semiconductor pattern is located on the same layer as the first semiconductor pattern and the second semiconductor pattern and is spaced apart from the first semiconductor pattern and the second semiconductor pattern.

15. The display device according to claim 14, wherein, The first conductive layer further includes a first capacitor electrode of the capacitor, and the second conductive layer further includes a second capacitor electrode of the capacitor.

16. The display device according to claim 15, wherein, At least a portion of the third insulating layer pattern and at least a portion of the third semiconductor pattern are located between the first capacitor electrode and the second capacitor electrode.

17. A method of manufacturing a display device, the display device comprising a plurality of pixels and a first transistor and a second transistor in each of the pixels, the method comprising: A first conductive layer is formed on a substrate. The first conductive layer includes a first power supply wiring electrically connected to a first source / drain electrode of the first transistor, a lower light-blocking pattern electrically connected to a second source / drain electrode of the first transistor, and a data wiring electrically connected to a first source / drain electrode of the second transistor. An insulating layer material, a semiconductor layer material, and a gate insulating layer material are sequentially coated on the substrate to cover the first conductive layer; as well as The gate insulating layer, semiconductor layer, and insulating layer are patterned by etching the gate insulating layer material, the semiconductor layer material, and the insulating layer material using a halftone mask. The gate insulating layer includes the gate insulating layer of the first transistor and the gate insulating layer of the second transistor. The semiconductor layer includes the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor. The insulating layer includes a first insulating pattern having the same planar shape as the semiconductor pattern of the first transistor and a second insulating pattern having the same planar shape as the semiconductor pattern of the second transistor.

18. The method according to claim 17, wherein, In the patterning of the gate insulating layer, the semiconductor layer, and the insulating layer, the gate insulating layer, the semiconductor layer, and the insulating layer are etched to expose at least a portion of the substrate.

19. The method according to claim 18, wherein, The first insulating pattern and the second insulating pattern are formed in an island shape and are spaced apart from each other.

20. The method of claim 17, wherein, The insulating layer further includes a third insulating pattern, which is spaced apart from the first and second insulating patterns and is formed to span the plurality of pixels.

21. The method according to claim 17, wherein, The method further includes: after the patterning of the gate insulating layer, the semiconductor layer and the insulating layer, forming a second conductive layer, the second conductive layer including the first source / drain electrode, the second source / drain electrode and the gate electrode of the first transistor, and the first source / drain electrode, the second source / drain electrode and the gate electrode of the second transistor.

Images