Method for manufacturing conductive pattern, display device, and method for manufacturing display device

Abstract

Disclosed are a method for manufacturing a conductive pattern, a display device, and a method for manufacturing a display device. The method for manufacturing a conductive pattern includes: forming a conductive metal material layer and a conductive covering material layer on a substrate; forming a photoresist pattern as an etching mask on the conductive covering material layer; etching the conductive covering material layer using a first etchant to form a first conductive covering pattern; etching the conductive metal material layer and the first conductive covering pattern using a second etchant to form a conductive metal layer and a second conductive covering pattern; and etching the second conductive covering pattern using a third etchant to form a conductive covering layer. The second conductive covering pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the step of forming the conductive covering layer includes etching the second region of the second conductive covering pattern to form a conductive covering layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0014850 filed in the Korean Intellectual Property Office on February 7, 2020. The entire contents of this Korean Patent Application are incorporated herein by reference. Technical Field

[0002] Disclosed are a method of manufacturing a conductive pattern, a display device, and a method of manufacturing the display device. Background Art

[0003] With the development of multimedia, display devices have become increasingly important, and various types of display devices such as organic light emitting diode (OLED) displays and liquid crystal displays (LCD) have been used.

[0004] A typical display device for displaying an image may include a display panel such as an OLED display panel or an LCD panel. The OLED display panel may include a light-emitting element such as a light-emitting diode (LED), and the LED may be classified into an OLED using an organic material as a fluorescent material and an inorganic LED using an inorganic material as a fluorescent material.

[0005] It will be understood that the technical section of this background technology is intended, in part, to provide a useful background for understanding the technology. However, the technical section of this background technology may also include ideas, concepts or understandings that were not part of what was known or understood by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0006] The embodiment provides a method of manufacturing a data conductive layer with high reliability.

[0007] Embodiments also provide a display device including a data conductive layer having high reliability and a method of manufacturing the display device.

[0008] However, the embodiments are not limited to those set forth herein. The above and other embodiments will become more apparent to those of ordinary skill in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0009] According to an embodiment, a method for manufacturing a conductive pattern may include: forming a conductive metal material layer and a conductive covering material layer on a substrate; forming a photoresist pattern as an etching mask on the conductive covering material layer; etching the conductive covering material layer by using a first etchant to form a first conductive covering pattern; etching the conductive metal material layer and the first conductive covering pattern by using a second etchant to form a conductive metal layer and a second conductive covering pattern; and etching the second conductive covering pattern by using a third etchant to form a conductive covering layer, wherein the second conductive covering pattern may include a first area overlapping the conductive metal layer and a second area not overlapping the conductive metal layer, and the step of forming the conductive covering layer may include etching the second area of ​​the second conductive covering pattern to form the conductive covering layer.

[0010] In an embodiment, the forming of the conductive metal layer may include forming a main metal layer below the conductive cover layer, wherein the main metal layer may contact the conductive cover layer and may include copper (Cu).

[0011] In an embodiment, the conductive cover layer may include at least one of an indium tin oxide (ITO) film, a titanium (Ti) film, an indium zinc oxide (IZO) film, and an indium tin zinc oxide (ITZO) film.

[0012] In an embodiment, the forming step of the conductive cover layer may include aligning a sidewall of the conductive cover layer with a sidewall of the main metal layer, or disposing the sidewall of the conductive cover layer inside the sidewall of the main metal layer.

[0013] In an embodiment, the forming of the conductive metal layer may include forming a conductive base layer below the main metal layer, wherein the conductive base layer may contact the main metal layer and may include titanium (Ti).

[0014] In an embodiment, the step of forming the first conductive covering pattern may include over-etching the conductive covering material layer at an over-etching rate in a range of about 100% to about 200%. The over-etching rate of the conductive covering material layer may be determined based on the thickness of the conductive covering material layer, and the etching rate of the conductive covering material layer by the first etchant may be higher than the etching rate of the conductive metal material layer by the first etchant. The step of forming the first conductive covering pattern may include forming the sidewall of the first conductive covering pattern on the inner side of the sidewall of the photoresist pattern by over-etching the conductive covering material layer.

[0015] In an embodiment, the forming of the conductive capping layer may include over-etching the second conductive capping pattern at an over-etching rate of about 10% or less, and the over-etching rate of the second conductive capping pattern may be determined based on a thickness of the second region of the second conductive capping pattern.

[0016] In an embodiment, the forming step of the conductive metal layer may include over-etching the conductive metal material layer at an over-etching rate of about 50% or less, and the over-etching rate of the conductive metal material layer may be determined based on a thickness of the conductive metal material layer.

[0017] In an embodiment, the forming of the first conductive capping pattern may include exposing a region of the conductive metal material layer that does not overlap the photoresist pattern.

[0018] In an embodiment, an etching rate of the first conductive capping pattern by the second etchant may be lower than an etching rate of the conductive metal material layer by the second etchant.

[0019] In an embodiment, the first etchant and the third etchant may be the same etchant, and an etching duration of etching the conductive capping material layer using the first etchant may be longer than an etching duration of etching the second conductive capping pattern using the third etchant.

[0020] In an embodiment, the first etchant and the third etchant may be different etchants, and an etching rate of the second conductive capping pattern by the third etchant may be lower than an etching rate of the conductive capping material layer by the first etchant.

[0021] In an embodiment, the method of manufacturing a conductive pattern may further include removing the photoresist pattern after forming the conductive capping layer.

[0022] According to an embodiment, a method for manufacturing a display device may include preparing a substrate including a display area and a pad area and forming a data conductive layer, the data conductive layer may include a source electrode and a drain electrode arranged in the display area and a wiring pad arranged in the pad area, a data conductive metal layer arranged on the substrate, and a data cover layer arranged on the data conductive metal layer, wherein the step of forming the data conductive layer may include: forming a material layer for the data conductive metal layer and a material layer for the data cover layer on the substrate; forming a photoresist pattern as an etching mask on the material layer for the data cover layer; forming a first data cover pattern layer by etching the material layer for the data cover layer using a first etchant; etching the material layer for the data conductive metal layer and the first data cover pattern layer on the material layer for the data conductive metal layer using a second etchant to form a data conductive metal layer and a second data cover pattern layer on the data conductive metal layer; and forming the data cover layer by etching the second data cover pattern layer using a third etchant, and wherein the step of forming the first data cover pattern layer may include exposing a portion of the material layer for the data conductive metal layer that does not overlap with the photoresist pattern.

[0023] In an embodiment, the forming of the data conductive metal layer may include forming a data main metal layer under the data cover layer, wherein the data main metal layer may contact the data cover layer and may include copper (Cu).

[0024] In an embodiment, the data cover layer may include at least one of an indium tin oxide (ITO) film, a titanium (Ti) film, an indium zinc oxide (IZO) film, and an indium tin zinc oxide (ITZO) film.

[0025] In an embodiment, an etching rate of the first data capping pattern layer by the second etchant may be lower than an etching rate of the material layer for the data conductive metal layer by the second etchant.

[0026] In an embodiment, the etching step of the material layer for the data conductive metal layer and the first data overlay pattern layer using a second etchant may include forming in the second data overlay pattern layer: a first area overlapping with the data conductive metal layer; and a second area not overlapping with the data conductive metal layer and overlapping with the photoresist pattern.

[0027] In an embodiment, the forming step of the data cover layer may include aligning a sidewall of the data cover layer with a sidewall of the data conductive metal layer, or disposing the sidewall of the data cover layer inside the sidewall of the data conductive metal layer.

[0028] In an embodiment, the forming step of the first data cover pattern layer may include over-etching the material layer for the data cover layer at an over-etching rate in a range of about 100% to about 200%, wherein the over-etching rate of the material layer for the data cover layer may be determined based on the thickness of the material layer for the data cover layer, and the etching rate of the material layer for the data cover layer by the first etchant may be higher than the etching rate of the material layer for the data conductive metal layer by the first etchant. The forming step of the first data cover pattern layer may include forming a sidewall of the first data cover pattern layer on an inner side of a sidewall of the photoresist pattern by over-etching the material layer for the data cover layer.

[0029] In an embodiment, the step of forming the data cover layer may include over-etching the second data cover pattern layer at an over-etching rate of approximately 10% or less, the second data cover pattern layer may include a first area overlapping the data conductive metal layer and a second area not overlapping the data conductive metal layer, and the over-etching rate of the second data cover pattern layer may be determined based on the thickness of the second area of ​​the second data cover pattern layer.

[0030] In an embodiment, the forming step of the data conductive metal layer may include over-etching the material layer for the data conductive metal layer at an over-etching rate of about 50% or less, and the over-etching rate of the material layer for the data conductive metal layer may be determined based on the thickness of the material layer for the data conductive metal layer.

[0031] According to an embodiment, a display device may include: a substrate including a display area and a pad area; a data conductive layer including a source electrode and a drain electrode arranged in the display area and a wiring pad arranged in the pad area and exposed by a pad opening; a passivation layer overlapping the source electrode and the drain electrode; a light emitting element arranged in a pixel; and a driving transistor providing a driving current to the light emitting element, wherein the data conductive layer may also include a data conductive metal layer arranged on the substrate and a data covering layer arranged on the data conductive metal layer, the data conductive metal layer may include copper (Cu), the data covering layer may include a material having an etching rate slower than that of copper (Cu), and a sidewall of the data covering layer may be aligned with the sidewall of the data conductive metal layer or arranged on the inner side of the sidewall of the data conductive metal layer.

[0032] In an embodiment, the data cover layer may include at least one of an indium tin oxide (ITO) film, a titanium (Ti) film, an indium zinc oxide (IZO) film, and an indium tin zinc oxide (ITZO) film.

[0033] According to the foregoing and other embodiments, a data conductive layer is disposed on a substrate including a display area and a pad area. The data conductive layer may include a data conductive metal layer and a data cover layer, the data conductive metal layer may include Cu, and the data cover layer may include a material that is etched more slowly than Cu. The data conductive layer may be patterned to include a source electrode and a drain electrode disposed in the display area and a wiring pad disposed in the pad area. During patterning of the data conductive layer, as a first etching step, the data cover layer may be overetched first so as not to leave a residual data cover layer. In this way, stains may be prevented from being generated due to the data conductive metal layer being overetched in some areas to completely remove the data cover layer.

[0034] Other features and embodiments will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other embodiments and features of the disclosure will become more apparent by describing the disclosed embodiments in detail with reference to the accompanying drawings, in which:

[0036] Figure 1 is a plan view of a display device according to an embodiment;

[0037] Figure 2 yes Figure 1A schematic cross-sectional view of a display device;

[0038] Figure 3 It is shown Figure 1 A layout diagram of a first display substrate of a display device;

[0039] Figure 4 yes Figure 1 An equivalent circuit diagram of a pixel of a display device;

[0040] Figure 5 It is shown Figure 1 A schematic cross-sectional view of a first display substrate of a display device;

[0041] Figures 6 to 10 It shows the manufacturing Figure 5 A schematic cross-sectional view of a method for displaying a device;

[0042] Figures 11 to 14 It shows the manufacturing Figure 5 An enlarged schematic cross-sectional view of a method for forming a data conductive layer; and

[0043] Fig.15 and Fig.16 It shows the manufacturing Figure 5 A schematic cross-sectional view of a method of displaying a device. DETAILED DESCRIPTION

[0044] The disclosure will now be described more fully hereinafter with reference to the accompanying drawings in which embodiments are shown. However, the disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0045] For describing the disclosed embodiments, some components not related to the description may not be provided, and like reference numerals denote like elements throughout the specification.

[0046] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0047] The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or". In the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." for the purpose of its meaning and interpretation. For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0048] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another component. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims.

[0049] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0050] It will also be understood that the terms "includes" and / or "comprising", "having" and their variations are used in this specification, which may indicate the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of other features, integers, steps, operations, elements, components and / or any combination thereof.

[0051] When a layer, film, region, substrate, district or element is referred to as "on" another layer, film, region, substrate, district or element, the layer, film, region, substrate, district or element may be directly on the other layer, film, region, substrate, district or element, or an intermediate layer, film, region, substrate, district or element may be present between them. On the contrary, when a layer, film, region, substrate, district or element is referred to as "directly on" another layer, film, region, substrate, district or element, there may not be an intermediate layer, film, region, substrate, district or element between them. In addition, when a layer, film, region, substrate, district or element is referred to as "below" another layer, film, region, substrate, district or element, the layer, film, region, substrate, district or element may be directly below the other layer, film, region, substrate, district or element, or an intermediate layer, film, region, substrate, district or element may be present between them. In contrast, when a layer, film, region, substrate, area, or element is referred to as being "directly below" another layer, film, region, substrate, area, or element, there may be no intervening layers, films, regions, substrates, areas, or elements therebetween. In addition, "on..." or "over..." may include positioning on or below an object and does not necessarily indicate a direction based on gravity.

[0052] For ease of description, spatially relative terms such as "below", "under", "below", "above", "on", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that in addition to the orientation depicted in the drawings, the spatially relative terms are intended to include different orientations of the device in use or operation. For example, where the device shown in the drawings is flipped, a device that is "below" or "below" another device may be positioned as "above" the other device. Thus, the exemplary term "below" may include both a lower position and an upper position. The device may also be positioned in other directions, so the spatially relative terms may be interpreted differently depending on the orientation.

[0053] For the convenience of explanation, the size of the components in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0054] In addition, the term "superimposed" or "superimposed with ... " represents that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "superimposed" can include stacking, stacking, facing or facing, extending on ..., covering or partially covering or any other suitable term that a person of ordinary skill in the art will appreciate and understand. The terms "facing" and "facing" represent that the first element can be directly or indirectly opposite to the second element. In the case where the third element is between the first element and the second element, the first element and the second element can be understood to be indirectly opposite to each other, although still facing each other. When an element is described as "not "superimposed with" another element or "not superimposed with" another element, it can include that the elements are spaced apart from each other, offset from each other or separated from each other, or any other suitable term that a person of ordinary skill in the art will appreciate and understand.

[0055] In the specification, expressions such as "A and / or B" mean A, B, or A and B. In addition, expressions such as "at least one of A and B" mean A, B, or A and B.

[0056] In the following embodiments, when a component is referred to as "on a plane", it is understood that the component is viewed from the top, and when a component is referred to as "on a schematic cross-section", it is understood that the component is cut vertically and viewed from the side.

[0057] It will be understood that when a layer, region, or component is referred to as being "connected" or "coupled" to another layer, region, or component, the layer, region, or component may be "directly connected" or "directly coupled" to the other layer, region, or component, and / or may be "indirectly connected" or "indirectly coupled" to the other layer, region, or component, with other layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be "directly electrically connected" or "directly electrically coupled" to the other layer, region, or component, and / or may be "indirectly electrically connected" or "indirectly electrically coupled" to the other layer, region, or component, with other layers, regions, or components interposed therebetween.

[0058] In addition, when an element is referred to as being “in contact with” or the like with another element, the element may be “electrically in contact with” or “physically in contact with” the other element, or “indirectly in contact with” or “directly in contact with” the other element.

[0059] As used herein, "about" or "approximately" includes the stated value and the mean of the particular value as determined by one of ordinary skill in the art within an acceptable range of deviation, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0060] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system, but can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the embodiments belong. In addition, it will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an ideal or overly formal sense unless explicitly defined as such herein.

[0062] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0063] Figure 1 is a plan view of a display device according to an embodiment.

[0064] Reference Figure 1, the display device 1 may refer to all electronic devices that may include a display screen. Examples of the display device 1 may include a television (TV), a notebook computer, a monitor, a billboard, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an e-book reader, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, and / or an Internet of Things (IoT) device, all of which may be included in the display device.

[0065] The display device 1 is shown as a TV. The display device 1 may have a high resolution or an ultra-high resolution such as high definition (HD), ultra-high definition (UHD), 4K, or 8K.

[0066] The display device 1 can be classified according to how the display device 1 displays an image. For example, the display device 1 can be classified as an organic light emitting diode (OLED) display device, an inorganic electroluminescent (EL) display device, a quantum dot light emitting diode (QLED) display device, a micro light emitting diode (microLED) display device, a nano light emitting diode (nanoLED) display device, a plasma display device (PDP), a field emission display (FED) device, a cathode ray tube (CRT) display device, a liquid crystal display (LCD) device, or an electrophoretic display (EPD) device. Hereinafter, the display device 1 will be described as, for example, an OLED display device, and the OLED display device may be referred to as the display device 1 for short. However, the disclosure is not limited thereto. Various display devices other than the OLED display device may be used as the display device 1.

[0067] The display device 1 may have a substantially rectangular shape in a plan view. In the case where the display device 1 is a TV, the long side of the display device 1 may be positioned in the horizontal direction, but the disclosure is not limited thereto. Alternatively, the long side of the display device 1 may be positioned in the vertical direction, or the display device 1 may be rotatably mounted so that the long side of the display device 1 may be variably positioned in the horizontal direction or in the vertical direction.

[0068] The display device 1 may include a display area DPA and a non-display area NDA. The display area DPA may be an effective area in which an image may be displayed. The display area DPA may have a shape similar to that of the display device 1 in a plan view (eg, a substantially rectangular shape).

[0069] The display area DPA may include pixels PX. The pixels PX may be arranged in a matrix or set in rows and columns. The pixels PX may have a substantially rectangular shape or a substantially square shape in a plan view, but the disclosure is not limited thereto. Optionally, the pixels PX may have a substantially rhombus shape that is tilted relative to the direction of one side of the display device 1. The pixels PX may include pixels PX of a first color (e.g., red) (hereinafter, first color pixels PX), pixels PX of a second color (e.g., green) (hereinafter, second color pixels PX), and pixels PX of a third color (e.g., blue) (hereinafter, third color pixels PX). The first color pixels PX, the second color pixels PX, and the third color pixels PX may be alternately arranged or set in a stripe manner or a PenTile manner.

[0070] The non-display area NDA may be disposed around the display area DPA, or may be adjacent to the display area DPA. The non-display area NDA may completely or partially surround the display area DPA, or may be completely or partially adjacent to the display area DPA. The display area DPA may have a substantially rectangular shape, and the non-display area NDA may be disposed adjacent to four sides of the display area DPA. The non-display area NDA may form a frame of the display device 1.

[0071] A driving circuit or element that can drive the display area DPA can be disposed in the non-display area NDA. In an embodiment, the first long side and the second long side (eg, Figure 1 In the first non-display area NDA1 and the second non-display area NDA2 adjacent to the first short side (e.g., the lower side and the upper side) of the display device 1, a pad (or referred to as a "pad" or "pad") unit may be provided or set on the display substrate of the display device 1, and the external device EXD may be mounted on the pad electrode in the pad unit. Examples of the external device EXD may include a connection film, a printed circuit board (PCB), a driver integrated circuit (DIC), a connector, and a wiring connection film. ... Figure 1 In the third non-display area NDA3 adjacent to the left side of the display device 1, a scan driver SDR may be provided. The scan driver SDR may be directly formed or provided on the display substrate of the display device 1.

[0072] Figure 2 is a schematic cross-sectional view of a display device.

[0073] Figure 2 The display device 1 is illustrated as a top emission display device that emits light L in a direction away from the first substrate 110 where the emission layer EML may be formed or disposed (eg, in a direction toward the second substrate 21 ), but the disclosure is not limited thereto.

[0074] Reference Figure 2 , the display device 1 may include: an emission layer EML; an encapsulation film ENC, which may cover the emission layer EML or overlap the emission layer EML; and a color control structure (WCL, TPL, and CFL), which may be provided on the encapsulation film ENC. In an embodiment, the display device 1 may include a first display substrate 10 and a second display substrate 20, and the second display substrate 20 may be opposite to the first display substrate 10. The emission layer EML, the encapsulation film ENC, and the color control structure (WCL, TPL, and CFL) may be included in one of the first display substrate 10 and the second display substrate 20.

[0075] For example, the first display substrate 10 may include: a first substrate 110; an emission layer EML, which may be disposed on a first surface of the first substrate 110; and an encapsulation film ENC, which may be disposed on the emission layer EML. For example, the second display substrate 20 may include a second substrate 21 and a color control structure (WCL, TPL, and CFL), and the color control structure (WCL, TPL, and CFL) may be disposed on a first surface of the second substrate 21 that may face the first substrate 110. The color control structure (WCL, TPL, and CFL) may include a color filter layer CFL and a wavelength conversion layer WCL. The color control structure (WCL, TPL, and CFL) may include a light-transmitting layer TPL in some or a predetermined number of pixels PX, and the light-transmitting layer TPL may be disposed on the same layer as the wavelength conversion layer WCL.

[0076] The filling layer 30 may be disposed between the encapsulation film ENC and the color control structure (WCL, TPL, and CFL). The filling layer 30 may fill the space between the first display substrate 10 and the second display substrate 20 and thus may combine the first display substrate 10 and the second display substrate 20 together.

[0077] The first substrate 110 of the first display substrate 10 may be an insulating substrate. The first substrate 110 may include a transparent material. For example, the first substrate 110 may include a transparent insulating material such as glass or quartz. The first substrate 110 may be a rigid substrate, but the disclosure is not limited thereto. Alternatively, the first substrate 110 may include a plastic such as polyimide and may have flexibility such as bendability, foldability, and / or rollability.

[0078] The pixel electrode PXE may be disposed on the first surface of the first substrate 110. The pixel electrode PXE may be disposed in its corresponding pixel PX. The pixel electrodes PXE in a pair of adjacent pixels PX may be separated from each other. A circuit layer CCL that may drive the pixel PX may be disposed on the first substrate 110. The circuit layer CCL may be disposed between the first substrate 110 and the pixel electrode PXE. The circuit layer CCL will be described in detail later.

[0079] The pixel electrode PXE may be a first electrode (eg, an anode electrode) of a light emitting diode (LED). The pixel electrode PXE may have a structure in which indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) and a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. The high work function material layer may be disposed above the reflective material layer, close to the emission layer EML. The pixel electrode PXE may have ITO / Mg, ITO / MgF 2 , ITO / Ag or ITO / Ag / ITO multilayer structures, but the disclosure is not limited thereto.

[0080] The pixel defining film PDL may be disposed on the first surface of the first substrate 110 along the boundary of each pixel PX. The pixel defining film PDL may be disposed on the pixel electrode PXE and may include an opening that may expose the pixel electrode PXE. Due to the pixel defining film PDL and the opening of the pixel defining film PDL, an emission area EMA and a non-emission area NEM may be defined. The pixel defining film PDL may include an organic insulating material, such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB). The pixel defining film PDL may include an inorganic material.

[0081] The emission layer EML may be disposed on the pixel electrode PXE exposed by the pixel definition film PDL. In an embodiment where the display device 1 is an OLED display device, each emission layer EML may include an organic layer, and the organic layer may include an organic material. The organic layer may include an organic light-emitting layer, and may include a hole injection / transport layer and / or an electron injection / transport layer as an auxiliary layer that may assist in the emission of light. In an embodiment where the display device 1 is an LED display device, the emission layer EML may include an inorganic material such as an inorganic semiconductor.

[0082] In an embodiment, each emission layer EML may have a series structure including an organic light-emitting layer and a charge generation layer, the organic light-emitting layers may be arranged to overlap each other in the thickness direction, and the charge generation layer may be arranged between the organic light-emitting layers. The organic light-emitting layers may emit light of the same wavelength or light of different wavelengths. At least some layers or a predetermined number of layers of each emission layer EML may be separated from the corresponding layers in its corresponding adjacent emission layer EML.

[0083] In an embodiment, the wavelength of light emitted by the emission layer EML may be uniform for all pixels PX. For example, the emission layer EML of the pixel PX may all emit blue light or ultraviolet (UV) light, and due to the presence of the wavelength conversion layer WCL of the color control structure (WCL, TPL, and CFL), the pixel PX may display its corresponding color.

[0084] In an embodiment, the wavelength of light emitted by the emission layer EML may vary from the first color pixel PX to the second color pixel PX to the third color pixel PX. For example, the emission layer EML of the first color pixel PX may emit light of a first color, the emission layer EML of the second color pixel PX may emit light of a second color, and the emission layer EML of the third color pixel PX may emit light of a third color.

[0085] The common electrode CME may be disposed on the emission layer EML. The common electrode CME may be in contact not only with the emission layer EML but also with the top surface of the pixel defining layer PDL.

[0086] Portions of the common electrode CME may be all electrically connected without distinguishing the pixels PX. The common electrode CME may be an electrode disposed over the entire surface of the first substrate 110 without distinguishing the pixels PX. The common electrode CME may be a second electrode (eg, a cathode electrode) of the LED.

[0087] The common electrode CME may include Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF 2 The common electrode CME may include a transparent metal oxide layer disposed on the low work function material layer.

[0088] The pixel electrode PXE, the emission layer EML, and the common electrode CME may form a light emitting element (eg, OLED). Light may be emitted upward from the emission layer EML through the common electrode CME.

[0089] The encapsulation film ENC may be disposed on the common electrode CME. The encapsulation film ENC may include at least one layer. For example, the encapsulation film ENC may include a first inorganic film ENC1, an organic film ENC2, and a second inorganic film ENC3. The first inorganic film ENC1 and the second inorganic film ENC3 may include silicon nitride, silicon oxide, or silicon oxynitride. The organic film ENC2 may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, or BCB.

[0090] The second display substrate 20 may be arranged to face the encapsulation film ENC from above the encapsulation film ENC. The second substrate 21 of the second display substrate 20 may include a transparent material. The second substrate 21 may include a transparent insulating material such as glass or quartz. The second substrate 21 may be a rigid substrate, but the disclosure is not limited thereto. Alternatively, the second substrate 21 may include a plastic such as polyimide, and may have flexibility such as bendability, foldability, and / or rollability.

[0091] The same substrate as the first substrate 110 may be used as the second substrate 21, but the second substrate 21 may have a different material, thickness, or transmittance from the first substrate 110. For example, the second substrate 21 may have a transmittance higher than that of the first substrate 110. For example, the second substrate 21 may be thicker or thinner than the first substrate 110.

[0092] The light shielding member BM may be disposed on the first surface of the second substrate 21 facing the first substrate 110 along the boundary of each pixel PX. The light shielding member BM may overlap the pixel definition film PDL of the first display substrate 10 and may be disposed in the non-emission area NEM. The light shielding member BM may include an opening that may expose a portion of the first surface of the second substrate 21 that may overlap the emission area EMA. The light shielding member BM may be formed in a lattice shape in a plan view.

[0093] The light blocking member BM may include an organic material. The light blocking member BM may reduce any color distortion caused by reflection of external light by absorbing external light. The light blocking member BM may prevent light emitted from the emission layer EML of one pixel PX from penetrating into the emission layer EML of another pixel PX.

[0094] In an embodiment, the light blocking member BM may absorb all visible wavelengths. The light blocking member BM may include a light absorbing material. For example, the light blocking member BM may include a material that may be used as a black matrix.

[0095] The color filter layer CFL may be disposed on the first surface of the second substrate 21 where the light blocking member BM may be disposed. The color filter layer CFL may be disposed on a portion of the first surface of the second substrate 21 exposed by the opening of the light blocking member BM. The color filter layer CFL may also be disposed on a portion of the light blocking member BM.

[0096] The color filter layer CFL may include a first color filter layer CFL1 that may be disposed in a first color pixel PX, a second color filter layer CFL2 that may be disposed in a second color pixel PX, and a third color filter layer CFL3 that may be disposed in a third color pixel PX. Each color filter layer CFL may include a colorant (such as a pigment or dye) that may absorb a specific wavelength. The first color filter layer CFL1 may be a red (R) color filter layer, the second color filter layer CFL2 may be a green (G) color filter layer, and the third color filter layer CFL3 may be a blue (B) color filter layer, but the disclosure is not limited thereto. Figure 2 It is shown that a pair of adjacent color filter layers CFL may be spaced apart from each other with respect to the light blocking member BM, but may at least partially overlap each other over the light blocking member BM.

[0097] The first cover layer 22 may be disposed on the color filter layer CFL. The first cover layer 22 may prevent the color filter layer CFL from being damaged or contaminated by impurities such as moisture or air from the outside. The first cover layer 22 may prevent the colorant of the color filter layer CFL from diffusing into other elements.

[0098] The first cover layer 22 may be in contact with the first surface (eg, Figure 2 The first cover layer 22 may include an inorganic material. For example, the first cover layer 22 may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide or silicon oxynitride. The spacer PTL may be disposed on the first cover layer 22. The spacer PTL may be positioned or disposed in the non-emission area NEM. The spacer PTL may be disposed to overlap with the light shielding member BM. The spacer PTL may include an opening that may expose the color filter layer CFL. The spacer PTL may be formed to include a photosensitive organic material, but the disclosure is not limited thereto. The spacer PTL may include a light shielding material.

[0099] The wavelength conversion layer WCL and the light transmission layer TPL may be disposed in the space exposed by the opening of the spacer PTL. The wavelength conversion layer WCL and the light transmission layer TPL may be formed by an inkjet process using the spacer PTL as a bank, but the disclosure is not limited thereto.

[0100] In an embodiment in which the emission layer EML of the pixel PX emits light of a third color, the wavelength conversion layer WCL may include a first wavelength conversion pattern WCL1 and a second wavelength conversion pattern WCL2, the first wavelength conversion pattern WCL1 may be disposed in the first color pixel PX, the second wavelength conversion pattern WCL2 may be disposed in the second color pixel PX, and the light-transmitting layer TPL may be disposed in the third color pixel PX.

[0101] The first wavelength conversion pattern WCL1 may include a first base resin BRS1 and a first wavelength conversion material WCP1, and the first wavelength conversion material WCP1 may be disposed in the first base resin BRS1. The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and a second wavelength conversion material WCP2, and the second wavelength conversion material WCP2 may be disposed in the second base resin BRS2. The light-transmitting layer TPL may include a third base resin BRS3 and a scatterer SCP, and the scatterer SCP may be disposed in the third base resin BRS3.

[0102] The first base resin BRS1, the second base resin BRS2 and the third base resin BRS3 may include a light-transmitting organic material. For example, the first base resin BRS1, the second base resin BRS2 and the third base resin BRS3 may include an epoxy resin, an acrylic resin, a cardo resin or an imide resin. The first base resin BRS1, the second base resin BRS2 and the third base resin BRS3 may all include the same or similar materials, but the disclosure is not limited thereto.

[0103] The scatterers SCP may be particles of metal oxide or organic particles. For example, the metal oxide may be titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 ), zinc oxide (ZnO) or tin oxide (SnO 2 ), the material of the organic particles can be acrylic resin or polyurethane resin.

[0104] The first wavelength conversion material WCP1 may convert the third color into the first color, and the second wavelength conversion material WCP2 may convert the third color into the second color. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 may be quantum dots, quantum rods, or phosphors. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI compound nanocrystals, or a combination thereof. Each of the first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 may include a scatterer SCP that may improve the efficiency of wavelength conversion.

[0105] The light-transmitting layer TPL that may be provided in the third color pixel PX may transmit the third color light incident thereon from the emission layer EML of the third color pixel PX while maintaining the wavelength of the incident light. The scatterer SCP of the light-transmitting layer TPL may control the path of the light emitted through the light-transmitting layer TPL. The light-transmitting layer TPL may not include a wavelength conversion material.

[0106] The second cover layer 23 may be disposed on the wavelength conversion layer WCL and the light-transmitting layer TPL. The second cover layer 23 may include an inorganic material. The second cover layer 23 may include one selected from the above-mentioned materials of the first cover layer 22. The first cover layer 22 and the second cover layer 23 may include the same or similar materials, but the disclosure is not limited thereto.

[0107] The filling layer 30 may be disposed between the first display substrate 10 and the second display substrate 20. The filling layer 30 may fill the space between the first display substrate 10 and the second display substrate 20, and may also combine the first display substrate 10 and the second display substrate 20 together. The filling layer 30 may be disposed between the encapsulation film ENC of the first display substrate 10 and the second cover layer 23 of the second display substrate 20. The filling layer 30 may include a silicon (Si)-based organic material or an epoxy-based organic material, but the disclosure is not limited thereto.

[0108] The circuit layer CCL of the display device 1 will be described below.

[0109] Figure 3 It is shown Figure 1 Layout diagram of a first display substrate of a display device.

[0110] Reference Figure 3 , the wirings may be disposed on the first substrate 110 of the first display substrate 10. The wirings may include a scan line SCL, a sensing signal line SSL, a data line DTL, a reference voltage line RVL, a first power line ELVDL, and a second power line ELVSL.

[0111] The scan lines SCL and the sensing signal lines SSL may extend in the first direction DR1. The scan lines SCL and the sensing signal lines SSL may be electrically connected to a scan driver SDR. The scan driver SDR may include a driving circuit, which may be composed of a circuit layer CCL. The scan driver SDR may be disposed in a third non-display area NDA3 on the first substrate 110, but the disclosure is not limited thereto. Optionally, the scan driver SDR may be disposed in a region that may be adjacent to a second short side (e.g., Figure 1 The scan driver SDR may be electrically connected to the signal connection line CWL, and at least one end of the signal connection line CWL may form a pad WPD_CW in the first non-display area NDA1 and / or in the second non-display area NDA2, and thus may be electrically connected to the first non-display area NDA1 and / or the second non-display area NDA2. Figure 1 External device EXD.

[0112] The data line DTL and the reference voltage line RVL may extend in a second direction DR2, and the second direction DR2 may cross the first direction DR1. The first power line ELVDL and the second power line ELVSL may include a portion extending in the second direction DR2. The first power line ELVDL and the second power line ELVSL may include a portion extending in the first direction DR1. The first power line ELVDL and the second power line ELVSL may have a mesh structure, but the disclosure is not limited thereto.

[0113] The wiring pad WPD may be arranged at least at the first end of the data line DTL, the first end of the reference voltage line RVL, the first end of the first power line ELVDL, and the first end of the second power line ELVSL. The wiring pad WPD may be arranged in the non-display area NDA. In an embodiment, the wiring pad WPD_DT of the data line DTL (hereinafter, the data pad WPD_DT) may be arranged in the first non-display area NDA1, and the wiring pad WPD_RV of the reference voltage line RVL (hereinafter, the reference voltage pad WPD_RV), the wiring pad WPD_ELVD of the first power line ELVDL (hereinafter, the first power pad WPD_ELVD), and the wiring pad WPD_ELVS of the second power line ELVSL (hereinafter, the second power pad WPD_ELVS) may be arranged in the second non-display area NDA2. In an embodiment, the data pad WPD_DT, the reference voltage pad WPD_RV, the first power pad WPD_ELVD, and the second power pad WPD_ELVS may all be arranged in the same area, for example, in the first non-display area NDA1. Figure 1 The external device EXD may be mounted or arranged on the wiring pad WPD. The external device EXD may be mounted or arranged on the wiring pad WPD via an anisotropic conductive film or by ultrasonic bonding.

[0114] The pixel PX on the first substrate 110 may include a pixel driving circuit. The wiring may pass through the pixel PX or bypass the pixel PX to apply a driving signal to the pixel driving circuit. Each pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors in each pixel driving circuit may vary. The pixel driving circuit will be described below as having a "3T1C" structure including, for example, three transistors and one capacitor, but the disclosure is not limited thereto. For example, various variant pixel structures such as a "2T1C" structure, a "7T1C" structure, or a "6T1C" structure may also be applied to the pixel driving circuit of the pixel PX.

[0115] Figure 4 yes Figure 1 An equivalent circuit diagram of a pixel of a display device.

[0116] Reference Figure 4, the pixel PX may include a light emitting element EMD, three transistors (eg, a driving transistor DTR and first and second switching transistors STR1 and STR2 ), and a capacitor (eg, a storage capacitor CST).

[0117] The light emitting element EMD may emit light according to a current applied thereto via the driving transistor DTR. The light emitting element EMD may be implemented as an OLED, a micro-LED, or a nano-LED.

[0118] A first electrode (e.g., an anode electrode) of the light emitting element EMD can be electrically connected to a source electrode of the driving transistor DTR, and a second electrode (e.g., a cathode electrode) of the light emitting element EMD can be electrically connected to a second power line ELVSL, wherein a low potential voltage (or a second power supply voltage) lower than a high potential voltage (or a first power supply voltage) supplied to the first power line ELVDL can be supplied to the second power line ELVSL.

[0119] The driving transistor DTR can adjust the current that can flow from the first power line ELVDL to the light emitting element EMD according to the difference between its gate voltage and source voltage. The gate electrode of the driving transistor DTR can be electrically connected to the second source / drain electrode of the first switching transistor STR1, the source electrode of the driving transistor DTR can be electrically connected to the first electrode of the light emitting element EMD, and the drain electrode of the driving transistor DTR can be electrically connected to the first power line ELVDL.

[0120] The first switching transistor STR1 may be turned on by a scanning signal from a scanning line SCL to electrically connect the data line DTL to the gate electrode of the driving transistor DTR. The gate electrode of the first switching transistor STR1 may be electrically connected to the scanning line SCL, the first source / drain electrode of the first switching transistor STR1 may be electrically connected to the data line DTL, and the second source / drain electrode of the first switching transistor STR1 may be electrically connected to the gate electrode of the driving transistor DTR.

[0121] The second switch transistor STR2 can be turned on by a sensing signal from the sensing signal line SSL to electrically connect the reference voltage line RVL to the source electrode of the drive transistor DTR. The gate electrode of the second switch transistor STR2 can be electrically connected to the sensing signal line SSL, the first source / drain electrode of the second switch transistor STR2 can be electrically connected to the reference voltage line RVL, and the second source / drain electrode of the second switch transistor STR2 can be electrically connected to the source electrode of the drive transistor DTR.

[0122] In an embodiment, the first source / drain electrode of the first switch transistor STR1 and the first source / drain electrode of the second switch transistor STR2 may be a source electrode, and the second source / drain electrode of the first switch transistor STR1 and the second source / drain electrode of the second switch transistor STR2 may be a drain electrode. However, the disclosure is not limited to this embodiment. Alternatively, the first source / drain electrode of the first switch transistor STR1 and the first source / drain electrode of the second switch transistor STR2 may be a drain electrode, and the second source / drain electrode of the first switch transistor STR1 and the second source / drain electrode of the second switch transistor STR2 may be a source electrode.

[0123] The storage capacitor CST may be formed or disposed between the gate electrode and the source electrode of the driving transistor DTR. The storage capacitor CST may store a difference between a gate voltage and a source voltage of the driving transistor DTR.

[0124] The driving transistor DTR and the first and second switching transistors STR1 and STR2 may be formed as thin film transistors (TFTs). Figure 4 It is shown that the driving transistor DTR and the first switching transistor STR1 and the second switching transistor STR2 can be formed as N-type metal oxide semiconductor field effect transistors (MOSFETs), but the disclosure is not limited thereto. Optionally, the driving transistor DTR and the first switching transistor STR1 and the second switching transistor STR2 can be formed as P-type MOSFETs. Optionally, some transistors or a predetermined number of transistors in the driving transistor DTR and the first switching transistor STR1 and the second switching transistor STR2 can be formed as N-type MOSFETs, and the other transistors can be formed as P-type MOSFETs.

[0125] Figure 5 It is shown Figure 1 Schematic cross-sectional view of a first display substrate of a display device.

[0126] Figure 5 A portion of the display area DPA (for example, the transistor region TRR) and a portion of the non-display area NDA (for example, the pad area PDA) are shown. Figure 5 The transistor region TRR may be where one may set Figure 4 region of the driving transistor DTR. Figure 5 The circuit layer CCL of the first display substrate 10 is mainly shown and only a portion of the first display substrate 10 ranging from the first substrate 110 to the pixel defining film PDL is shown.

[0127] Reference Figure 5, the circuit layer CCL may include a semiconductor layer 130, a conductive layer, and an insulating layer that may be disposed on the first substrate 110. The semiconductor layer 130 may include an oxide semiconductor. The conductive layer may include a lower metal layer 120, a gate conductive layer 140, a data conductive layer 150, and a pixel electrode PXE. The insulating layer may include a buffer layer 161, a gate insulating film 162, an interlayer insulating film 163, a passivation layer 164, and a via layer 165.

[0128] As an example, the lower metal layer 120 may be disposed on the first substrate 110. The lower metal layer 120 may be a light shielding layer that may protect the semiconductor layer 130 from external light. The lower metal layer 120 may have a patterned shape. The lower metal layer 120 may be disposed in the transistor region TRR. The lower metal layer 120 may be disposed to cover the semiconductor layer 130 from below or overlap the semiconductor layer 130, and the semiconductor layer 130 may be disposed on the lower metal layer 120. The lower metal layer 120 may be disposed to cover at least the channel region of the semiconductor layer 130 from below the semiconductor layer 130 or overlap at least the channel region of the semiconductor layer 130, or to cover the entire semiconductor layer 130 or overlap the entire semiconductor layer 130. The lower metal layer 120 may be electrically connected to the source electrode SEL of the driving transistor DTR through the first contact hole CNT1 to suppress a change in the voltage of the driving transistor DTR. The lower metal layer 120 may be formed as a titanium (Ti) / copper (Cu) double-layer film in which a Ti layer and a copper (Cu) layer may be stacked, but the disclosure is not limited thereto.

[0129] The buffer layer 161 may be disposed on the lower metal layer 120. The buffer layer 161 may be disposed to cover the entire surface of the first substrate 110 on which the lower metal layer 120 may be formed or to overlap the entire surface of the first substrate 110 on which the lower metal layer 120 may be formed. The buffer layer 161 may include silicon nitride, silicon oxide, or silicon oxynitride. In an embodiment, the buffer layer 161 may include SiN x / SiO x Double layer membrane.

[0130] The semiconductor layer 130 may be disposed on the buffer layer 161. The semiconductor layer 130 may be disposed in the transistor region TRR and may include a channel region of the driving transistor DTR. The semiconductor layer 130 may include an oxide semiconductor. Examples of oxide semiconductors may include a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), or magnesium (Mg). x ), ternary compounds (AB x C y ) or quaternary compound (AB x C y D zIn an embodiment, the semiconductor layer 130 may include indium gallium zinc oxide (IGZO).

[0131] The gate insulating film 162 may be disposed on the semiconductor layer 130. The gate insulating film 162 may be formed in a pattern that is the same as or similar to the gate conductive layer 140. The gate insulating film 162 may be disposed on the semiconductor layer 130, and the gate insulating film 162 may be disposed in the transistor region TRR. The side of the gate insulating film 162 may be substantially aligned with the side of the gate conductive layer 140, but the disclosure is not limited thereto. The gate insulating film 162 may include a silicon compound or a metal oxide. For example, the gate insulating film 162 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. In an embodiment, the gate insulating film 162 may include SiO x membrane.

[0132] The gate conductive layer 140 may be disposed on the gate insulating film 162. The gate conductive layer 140 may include a gate electrode GEL of the driving transistor DTR. The gate conductive layer 140 may include a first electrode (or lower electrode) of a capacitor in the capacitor region, a scan line SCL, and a sensing signal line SSL. The gate conductive layer 140 may not be formed or disposed in the pad region PDA, but the disclosure is not limited thereto.

[0133] The gate conductive layer 140 may be formed as a single layer film, but may also be formed as a multilayer film. In an embodiment, the gate conductive layer 140 may include a gate main metal layer and a gate base layer, and the gate base layer may be disposed below the gate main metal layer. Both the gate main metal layer and the gate base layer may include a conductive material. No insulating layer may be placed or disposed between the films of the gate conductive layer 140 that may overlap each other in the thickness direction. The gate main metal layer and the gate base layer may be patterned by a single mask process.

[0134] The gate base layer may be disposed below the gate main metal layer to improve film forming properties such as adhesion of the gate main metal layer or to prevent reactive materials from entering the gate main metal layer from the underlying gate insulating film 162, which may be disposed below the gate conductive layer 140. The gate base layer may prevent the material of the gate main metal layer (e.g., copper (Cu)) from diffusing into the underlying layer. The gate base layer may include materials such as titanium (Ti), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), or nickel (Ni), but the disclosure is not limited thereto.

[0135] The gate main metal layer may mainly transmit signals and may include a low resistance material. The gate main metal layer may be thicker than the gate base layer and may include a material whose resistance is lower than that of the gate base layer. The gate main metal layer may include a material such as copper (Cu), molybdenum (Mo), aluminum (Al), or silver (Ag), but the disclosure is not limited thereto.

[0136] The interlayer insulating film 163 may be disposed on the gate conductive layer 140. The interlayer insulating film 163 may be disposed on the gate conductive layer 140, on a portion of the semiconductor layer 130 exposed by the gate conductive layer 140, and on a portion of the buffer layer 161 exposed by the gate conductive layer 140 and the semiconductor layer 130. The interlayer insulating film 163 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide. In an embodiment, the interlayer insulating film 163 may include SiON.

[0137] For convenience, the top surface of the interlayer insulating film 163 is shown as being flat in the display area DPA. Alternatively, the interlayer insulating film 163, which may include an inorganic material, may have a surface shape that may reflect any height difference thereunder. The thickness of each portion of the interlayer insulating film 163 may be measured from the same flat reference surface (e.g., the top surface of the buffer layer 161) on which there is no height difference.

[0138] The data conductive layer 150 may be disposed on the interlayer insulating film 163. The data conductive layer 150 may include a source electrode SEL and a drain electrode DEL of the driving transistor DTR in the transistor region TRR and a wiring pad WPD in the pad region PDA. The source electrode SEL and the drain electrode DEL may be electrically connected to the semiconductor layer 130 through a second contact hole CNT2 that may penetrate the interlayer insulating film 163. The source electrode SEL may be electrically connected to the lower metal layer 120 through a first contact hole CNT1 that may penetrate the interlayer insulating film 163 and the buffer layer 161. The data conductive layer 150 may include a second electrode (or upper electrode) of the capacitor in the capacitor region, a data line DTL, a reference voltage line RVL, and a first power line ELVDL.

[0139] The data conductive layer 150 may include a data conductive metal layer 151 and a data cover layer 152, which may be sequentially stacked. The data cover layer 152 may be disposed on the data conductive metal layer 151. The data conductive metal layer 151 may be formed as a single-layer film, but may also be formed as a multi-layer film. In an embodiment, the data conductive metal layer 151 may include a data main metal layer 1511 and a data base layer 1512, and the data base layer 1512 may be disposed below the data main metal layer 1511.

[0140] The data base layer 1512, the data main metal layer 1511, and the data cover layer 152 may all include a conductive material. The data base layer 1512, the data main metal layer 1511, and the data cover layer 152 may be patterned by a single mask process. In an embodiment, the side of the upper layer of the data conductive layer 150 may not protrude outward beyond the side of the lower layer of the data conductive layer 150. In an embodiment, the side of each layer of the data conductive layer 150 (e.g., the side of each of the data base layer 1512, the data main metal layer 1511, and the data cover layer 152) may all be aligned. For example, the data conductive layer 150 may not have a tip structure in which the upper layer of the data conductive layer 150 protrudes. The side of the upper layer of the data conductive layer 150 may be aligned with the side of the lower layer of the data conductive layer 150, or located on the inner side of the side of the lower layer of the data conductive layer 150. For example, a side surface of the data cover layer 152 that may be disposed in an upper portion of the data conductive layer 150 may be aligned with or located on an inner side surface of a side surface of the data main metal layer 1511 that may be disposed in a lower portion of the data conductive layer 150. No insulating layer may be interposed or disposed between layers that may overlap each other in a thickness direction of the data conductive layer 150. A process of forming a stacked structure of the data conductive layer 150 will be described later.

[0141] The data base layer 1512 may improve film forming characteristics such as adhesion of the data main metal layer 1511, or prevent a reactive material from entering the data main metal layer 1511 from an interlayer insulating film 163, which may be disposed below the data conductive layer 150. The data base layer 1512 may prevent a material (e.g., copper (Cu)) of the data main metal layer 1511 from diffusing into a layer below. The data base layer 1512 may include a material such as Ti, Ta, Ca, Cr, Mg, or Ni, but the disclosure is not limited thereto.

[0142] The data main metal layer 1511 may include a low resistance material. The data main metal layer 1511 may be thicker than the data base layer 1512 and the data cover layer 152, and may include a material having a lower resistance than the data base layer 1512 and the data cover layer 152. The data main metal layer 1511 may include a material such as copper (Cu), aluminum (Al), silver (Ag), or molybdenum (Mo), but the disclosure is not limited thereto.

[0143] The data cover layer 152 may cover the data main metal layer 1511 or overlap the data main metal layer 1511, and may protect the data main metal layer 1511 from above the data main metal layer 1511. The data cover layer 152 may protect the data main metal layer 1511 from an etchant or other chemical substances used to form a layer on the data conductive layer 150. The data cover layer 152 may prevent a material of the data main metal layer 1511 (e.g., copper (Cu)) from diffusing into a layer disposed on the data conductive layer 150. The data cover layer 152 may be in direct contact with the data main metal layer 1511.

[0144] The data cover layer 152 may be used as a contact electrode of the wiring pad WPD in the pad area PDA. Therefore, the data cover layer 152 may include a material used as a contact electrode of the wiring pad WPD. The data cover layer 152 may include a transparent conductive material or a low reflectivity conductive material. The data cover layer 152 may include a transparent conductive material such as ITO, IZO, or ITZO. Alternatively, the data cover layer 152 may include a low reflectivity conductive material such as Ti. For example, the data cover layer 152 may be formed as a single-layer film including an ITO film or a Ti film, or may be formed as a multi-layer film.

[0145] In an embodiment, the data conductive layer 150 may include a data base layer 1512 including Ti, a data main metal layer 1511 including copper (Cu), and a data cover layer 152 including ITO. The data conductive layer 150 may include a three-layer film of Ti / Cu / ITO, but the disclosure is not limited thereto. Alternatively, the data conductive layer 150 may have a stack of Ti / Cu / IZO or Ti / Cu / Ti.

[0146] As mentioned above, the thickness of the data main metal layer 1511 may be greater than the thickness of the data base layer 1512 and the data cover layer 152. In the embodiment where the data conductive layer 150 may be formed as a three-layer film of Ti / Cu / ITO, the data main metal layer 1511 may be formed to have a thickness of about To about In the range of To about In the range of To about However, the disclosure is not limited to this embodiment.

[0147] Since the data conductive layer 150 may have a structure in which the side of the upper layer of the data conductive layer 150 may not protrude outward or extend beyond the side of the lower layer of the data conductive layer 150, for example, since the data conductive layer 150 does not have a tip structure in which the upper layer of the data conductive layer 150 protrudes, the occurrence of a step coverage defect due to the tip structure may be prevented, and as a result, cracks may be prevented from being generated in the passivation layer 164 due to such a step coverage defect. Thus, a circuit layer CCL having high reliability may be provided.

[0148] The passivation layer 164 may be disposed on the data conductive layer 150. The passivation layer 164 may be formed or disposed on the entire surface of the display area DPA, and may not be formed in at least a portion of the non-display area NDA. The passivation layer 164 may not be disposed on at least a portion of the wiring pad WPD in the pad area PDA.

[0149] The passivation layer 164 may cover or overlap the data conductive layer 150 and may protect the data conductive layer 150. The passivation layer 164 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide.

[0150] The via layer 165 may be disposed on the passivation layer 164. The via layer 165 may cover the top surface of the passivation layer 164 or overlap the top surface of the passivation layer 164. The via layer 165 may flatten any height difference caused by the drive transistor DTR in the display area DPA. The via layer 165 may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, or BCB. The via layer 165 may include a photosensitive material, but the disclosure is not limited thereto. In an embodiment, the via layer 165 may include polyimide.

[0151] The via layer 165 may have different heights in different regions. The via layer 165 may include a first region 165_1 having a first height and a second region 165_2 having a second height that may be less than the first height. Regardless of the shape and presence of a pattern disposed below the via layer 165, the via layer 165 may have a substantially flat surface. The via layer 165 may have a height difference at a boundary between the first region 165_1 and the second region 165_2.

[0152] The first area 165_1 of the via layer 165 may be disposed in the display area DPA. The second area 165_2 of the via layer 165 may be disposed in the pad area PDA. Since the via layer 165 may have a relatively small height in the pad area PDA, the external device EXD may be smoothly mounted on the wiring pad WPD.

[0153] The via layer 165 may form a pad opening PDOP together with the passivation layer 164, and the pad opening PDOP may expose at least a portion of the wiring pad WPD of the data conductive layer 150 located in the pad area PDA, and the passivation layer 164 may be disposed below the via layer 165. In the pad area PDA, the side of the passivation layer 164 may be aligned with the side of the via layer 165, and the side of the via layer 165 may form an inner sidewall of the pad opening PDOP together with the side of the passivation layer 164, but the disclosure is not limited thereto. The inner sidewall of the pad opening PDOP may be disposed to overlap with the wiring pad WPD of the data conductive layer 150. The passivation layer 164 and the via layer 165 may be formed by a single mask process.

[0154] The pixel electrode PXE may be disposed on the via layer 165. The material of the pixel electrode PXE may be as described above. Figure 2 As has been described, in an embodiment, the pixel electrode PXE may include a three-layer film of ITO / Ag / ITO.

[0155] The pixel electrode PXE may be disposed in the display area DPA but not in the non-display area NDA. The pixel electrode PXE may overlap the transistor area TRR and the capacitor of the display area DPA, but the disclosure is not limited thereto. The pixel electrode PXE may be electrically connected to the source electrode SEL of the driving transistor DTR through the third contact hole CNT3, and the third contact hole CNT3 may penetrate the via layer 165 and the passivation layer 164.

[0156] The pixel definition layer PDL may be disposed on the pixel electrode PXE. The material of the pixel definition layer PDL may be as described above. Figure 2 In an embodiment, the pixel defining layer PDL may include polyimide.

[0157] The pixel defining film PDL may be disposed in the display area DPA but not in the non-display area NDA. The pixel defining film PDL may be disposed to overlap with an edge of the pixel electrode PXE. The pixel defining film PDL may be disposed on a portion of the via layer 165 where the pixel electrode PXE may not be formed or disposed.

[0158] Hereinafter, a method of manufacturing a display device according to an embodiment will be described.

[0159] Figures 6 to 16 It shows the manufacturing Figure 5 A schematic cross-sectional view of a method of displaying a device. Figures 11 to 14 It shows the manufacturing Figure 5 An enlarged schematic cross-sectional view of a method for forming a data conductive layer.

[0160] Reference Figure 6, a lower metal layer 120 that can be patterned can be formed or disposed on the first substrate 110. The lower metal layer 120 can be formed by a mask process. For example, a material layer for the lower metal layer 120 can be deposited on the entire surface of the first substrate 110, and then the material layer can be patterned into Figure 6 The lower metal layer 120 is formed.

[0161] Afterwards, refer to Figure 7 , a buffer layer 161 may be formed or disposed on the entire surface of the first substrate 110 on which the lower metal layer 120 may be formed or disposed. Thereafter, a semiconductor layer 130 may be formed or disposed on the buffer layer 161. The semiconductor layer 130 may be formed by a mask process. For example, an oxide semiconductor may be deposited on the entire surface of the buffer layer 161, and then the oxide semiconductor may be patterned by photolithography. Figure 7 The semiconductor layer 130 is formed by a semiconductor layer 130 of the semiconductor layer 130.

[0162] Afterwards, refer to Figure 8 , a gate insulating film 162 and a gate conductive layer 140 which may be patterned may be formed or provided on the buffer layer 161 where the semiconductor layer 130 may be formed or provided. The gate insulating film 162 and the gate conductive layer 140 may be formed through a single mask process.

[0163] As an example, a material layer for a gate insulating film 162 may be deposited on the entire surface of the buffer layer 161 on which the semiconductor layer 130 may be formed or provided. Thereafter, a material layer for a gate conductive metal layer and a material layer for a gate capping layer may be sequentially deposited on the material layer for the gate insulating film 162. Thereafter, a photoresist layer may be coated on the material layer for the gate capping layer, and the photoresist layer may be exposed and developed to form a photoresist pattern. Thereafter, the photoresist pattern may be used as an etching mask to sequentially etch the material layer for the gate capping layer, the material layer for the gate conductive metal layer, and the material layer for the gate insulating film 162. Thereafter, the photoresist pattern may be removed by a stripping or ashing process. Even in the patterning of the gate insulating film 162, the photoresist pattern may be used as an etching mask. Alternatively, the patterned upper layer may be used as a hard mask that may etch a layer disposed thereunder. The photoresist pattern may be used together with the hard mask as an etching mask. Alternatively, a hard mask may be formed, the photoresist pattern may be removed, and a layer below the hard mask may be etched using the hard mask as an etch mask.

[0164] Afterwards, refer to Fig. 9, an interlayer insulating film 163 may be deposited on the buffer layer 161 where the gate conductive layer 140 may be formed or provided, on the first contact hole CNT1 where a portion of the lower metal layer 120 may be exposed, and on the second contact hole CNT2 where a portion of the semiconductor layer 130 (e.g., the source region and the drain region of the semiconductor layer 130) may be exposed. The first contact hole CNT1 and the second contact hole CNT2 may be formed using the same or similar mask. For example, an insulating layer where the interlayer insulating film 163 may be formed may be deposited on the entire surface of the buffer layer 161 where the gate conductive layer 140 may be formed. Thereafter, a photoresist pattern where a portion of the lower metal layer 120 and the semiconductor layer 130 may be exposed may be formed or provided on the insulating layer where the interlayer insulating film 163 may be formed, and the insulating layer where the interlayer insulating film 163 may be formed may be etched using the photoresist pattern as an etching mask, thereby forming the first contact hole CNT1 and the second contact hole CNT2.

[0165] However, the disclosure is not limited thereto. For example, optionally, the first contact hole CNT1 and the second contact hole CNT2 may be sequentially formed using different masks. For example, a first photoresist pattern that may expose a portion of the lower metal layer 120 may be formed on an insulating layer that may form an interlayer insulating film 163, and the first photoresist pattern may be used as an etching mask to etch the buffer layer 161 and the insulating layer that may form the interlayer insulating film 163, thereby forming the first contact hole CNT1 that may expose a portion of the lower metal layer 120. Thereafter, the first photoresist pattern may be removed, and a second photoresist pattern that may expose a portion of the semiconductor layer 130 (e.g., a source region and a drain region of the semiconductor layer 130) may be formed on the insulating layer that may form the interlayer insulating film 163, and the second photoresist pattern may be used as an etching mask to etch the insulating layer that may form the interlayer insulating film 163, thereby forming the second contact hole CNT2.

[0166] Afterwards, refer to Fig.10 , a data conductive layer 150 that may be patterned may be formed on the interlayer insulating film 163. The data conductive layer 150 may be formed by a single mask process. The data conductive layer 150 may include: a source electrode SEL and a drain electrode DEL that may be disposed in the transistor region TRR of the display region DPA; a first (or lower) electrode (not shown) of a capacitor (not shown) that may be disposed in the capacitor region (not shown); and a wiring pad WPD that may be disposed in the pad region PDA of the non-display region NDA. The data conductive layer 150 may include a second (or upper) electrode (not shown) of a capacitor that may be disposed in the capacitor region, a data line DTL, a reference voltage line RVL, and a first power line ELVDL.

[0167] In the following we will refer to Figures 10 to 14 It is described how to form the data conductive layer 150 , which may be patterned, on the interlayer insulating film 163 . Figures 10 to 14 Only the data conductive layer 150 in the pad area PDA is illustrated, but the data conductive layer 150 may be formed in the display area DPA in the same or similar manner as that in the pad area PDA.

[0168] The data conductive metal layer 151 and the data cover layer 152 of the data conductive layer 150 may be formed using the same or similar masks. In an embodiment, the step of forming the data conductive layer 150, which may be patterned, may include: performing a first etching step of etching a material layer for the data cover layer 152 using a first etchant; performing a second etching step of etching both the material layer for the data conductive metal layer 151 and the material layer for the data cover layer 152 using a second etchant; and performing a third etching step of etching the material layer for the data cover layer 152 using a third etchant.

[0169] First, refer to Fig.10 and Fig.11 , a data conductive material layer in which a material layer 151a and a material layer 152a may be sequentially stacked is prepared on the interlayer insulating film 163, the material layer 151a may form the data conductive metal layer 151, and the material layer 152a may form the data cover layer 152. As an example, a material layer 1512a that may form the data base layer 1512, a material layer 1511a that may form the data main metal layer 1511, and a material layer 152a may be sequentially deposited on the entire surface of the interlayer insulating film 163. During the deposition of the material layers 1512a, 1511a, and 152a, the material layers 1512a and 1511a may even be deposited on the inner sides of the first contact hole CNT1 and the second contact hole CNT2, and thus may be electrically connected to the lower metal layer 120 and the semiconductor layer 130, respectively.

[0170] The thicknesses of the material layers 1512a, 1511a, and 152a, which may be sequentially stacked on the interlayer insulating film 163, may be different. As an example, the thickness d of the material layer 1511a may be 2 can be greater than the thickness d of the material layer 152a 1 and the thickness d of the material layer 1512a 3 For example, the thickness d of the material layer 152a is 1 Can be in about To about Within the range of 2 Can be in about To about Within the range of 3 Can be in about To about However, the disclosure is not limited to this example. In an embodiment, the material layer 1511a may include Cu, the material layer 152a may include at least one of an ITO film, a Ti film, an IZO film, and an ITZO film, and the material layer 1512a may include Ti.

[0171] Thereafter, a photoresist pattern PR that can be used as an etching mask may be formed or disposed on the material layer 152a. The photoresist pattern PR may be used as an etching mask that may etch the material layers 1512a, 1511a, and 152a. The photoresist pattern PR that may be patterned may be formed by coating a photoresist layer and exposing and developing the photoresist layer. The photoresist pattern PR may have a pattern shape similar to a pattern shape of the data conductive layer 150 to be formed. As an example, the photoresist pattern PR may be patterned to overlap with a wiring pad WPD to be formed in a pad area PDA of the non-display area NDA, and overlap with a source electrode SEL and a drain electrode DEL to be formed in a transistor area TRR of the display area DPA.

[0172] Afterwards, the material layer 152a may be etched using the photoresist pattern PR as an etching mask. The material layer 152a may be wet-etched using the first etchant L1. As a result, the portion of the material layer 152a exposed by the photoresist pattern PR may be etched away, so that the portion of the material layer 151a or 1511a that does not overlap with the photoresist pattern PR may be exposed.

[0173] In an embodiment, when the material layers 1512a, 1511a, and 152a are a stack of Ti / Cu / ITO, the first etchant L1 may have a faster etching rate for the material layer 152a than for the material layer 1511a. Alternatively, the first etchant L1 may include an etchant component that may not etch the material layer 1511a. For example, the first etchant L1 may include an etchant component that may etch ITO but not Cu and Ti.

[0174] In an embodiment, when the material layers 1512a, 1511a, and 152a are a stack of Ti / Cu / Ti, the first etchant L1 may have a slower etching rate for the material layer 152a than for the material layer 1511a. For example, the first etchant L1 may include an etchant component that can etch Ti and Cu, and may have a slower etching rate for a material layer including Ti (e.g., material layer 152a) than for a material layer including Cu (e.g., material layer 1511a).

[0175] As used herein, the term "overetching" may mean continuing etching beyond a reference amount of time that typically takes to reach an etching endpoint, which is the point when a target material layer is removed to expose another material layer. The reference amount of time for a target material layer may be represented by equation (1):

[0176]

[0177] The degree to which the target material layer may be overetched will be referred to hereinafter as the overetch rate of the target material layer, and the overetch rate of the target material layer is defined as the ratio of the duration of the etching operation of the target material layer exceeding the reference time amount of the target material layer to the reference time amount of the target material layer. For example, if the target material layer has approximately The thickness is about If the target material layer is etched at an etching rate of about 10 seconds, the reference time amount for the target material layer may be about 10 seconds. In this example, if the duration of etching of the target material layer is about 10 seconds, the over-etching rate of the target material layer may be about 0%. If the duration of etching of the target material layer is about 20 seconds, the over-etching rate of the target material layer may be about 100%.

[0178] Refer again Fig.10 and Fig.11 In order to prevent the material layer 152a from remaining in a region that may not overlap with the photoresist pattern PR after etching the material layer 152a (which may be formed or disposed on the interlayer insulating film 163), the material layer 152a may be over-etched using the first etchant L1. In a non-limiting embodiment, the material layer 152a may be over-etched using the first etchant L1 at an over-etching rate in a range of about 100% to about 200%. In an embodiment, the thickness d of the material layer 152a may be determined based on the thickness of the material layer 152a. 1 To determine a reference amount of time for determining an over-etching rate of the material layer 152 a .

[0179] As a result of etching the material layer 152a, the material layer 152a may be etched not only in a region that may not overlap with the photoresist pattern PR but may also be partially etched in a region that may overlap with the photoresist pattern PR. As a result, a Fig.12 The side of the first data cover pattern layer 152b, which may be obtained by over-etching the material layer 152a, may be located on the inner side of the sidewall of the photoresist pattern PR.

[0180] Afterwards, refer to Fig.10 and Fig.12, both the material layer 151a and the first data overlay pattern layer 152b may be etched simultaneously using the photoresist pattern PR as an etching mask. The material layers 1512a and 1511a and the first data overlay pattern layer 152b may be wet-etched using the second etchant L2.

[0181] The second etchant L2 may have different etching rates for the first data overlay pattern layer 152b and the material layer 1511a. In an embodiment, the etching rate of the second etchant L2 for the first data overlay pattern layer 152b may be slower than the etching rate of the second etchant L2 for the material layer 1511a. In an embodiment, when the material layers 1512a, 1511a, and 152a are a stack of Ti / Cu / ITO, the etching rate of the second etchant L2 for the ITO film may be slower than the etching rate of the second etchant L2 for the Cu film. In an embodiment, when the material layers 1512a, 1511a, and 152a are a stack of Ti / Cu / Ti, the etching rate of the second etchant L2 for the Ti film may be slower than the etching rate of the second etchant L2 for the Cu film.

[0182] Due to the difference between the etching rate of the first data cover pattern layer 152b by the second etchant L2 and the etching rate of the material layer 1511a by the second etchant L2, the first data cover pattern layer 152b may be etched to a different extent than the material layer 1511a. As a result, the first data cover pattern layer 152b and the material layer 1511a may be formed as Fig.13 The second data cover pattern layer 152c and the data main metal layer 1511. Fig.13 , the second data capping pattern layer 152 c may be formed to protrude beyond the data main metal layer 1511 .

[0183] In order to prevent the material layer 151a from remaining in a region that may not overlap with the first data overlay pattern layer 152b during etching of both the material layer 151a and the first data overlay pattern layer 152b that may be formed or disposed on the interlayer insulating film 163, the material layer 1511a may be overetched using the second etchant L2. However, if the material layer 1511a is excessively overetched, the upper layer of the data conductive layer 150 may excessively protrude beyond the lower layer of the data conductive layer 150 due to the difference between the etching rate of the first data overlay pattern layer 152b by the second etchant L2 and the etching rate of the material layer 1511a by the second etchant L2. Therefore, the overetching rate of the material layer 151a and the first data overlay pattern layer 152b needs to be appropriately determined. In a non-limiting embodiment, during etching of the material layer 151a and the first data overlay pattern layer 152b, the material layer 1511a may be overetched using the second etchant L2 at an overetching rate of about 50% or less. In an embodiment, the thickness d of the material layer 1511a may be 2 To determine a reference amount of time for determining an over-etching rate of the material layer 1511 a .

[0184] As a result of etching the material layer 151a and the first data overlay pattern layer 152b, the first data overlay pattern layer 152b may be partially etched (etched only at the edge thereof), thereby forming Fig.13 The second data overlay pattern layer 152c is formed, and a portion of the material layer 151a that may not overlap with the first data overlay pattern layer 152b may be etched, thereby forming Fig.13 The data conductive metal layer 151 is shown in FIG. Fig.13 , a side surface of the second data capping pattern layer 152 c may be located on an inner side of a sidewall of the photoresist pattern PR, and may protrude outward beyond the data conductive metal layer 151 .

[0185] Before etching the material layer 151a and the first data overlay pattern layer 152b, the material layer 152a may be overetched using the first etchant L1 so that the material layer 152a does not remain on the portion of the material layer 151a that may not overlap the photoresist pattern PR. As a result, the material layer 151a may be prevented from being overetched and damaged in some or a predetermined number of regions during etching of the material layer 151a and the first data overlay pattern layer 152b. As an example, if the material layer for the data conductive layer 150 may be etched all together using the second etchant L2 without etching the material layer 152a using the first etchant L1, the material layer 152a may need to be overetched in all regions to sufficiently etch the material layer 152a because the etching rate of the second etchant L2 for the material layer 152a that may include Ti or ITO may be slower than the etching rate of the second etchant L2 for the material layer 151a that may include Cu. Then, the material layer 151a may be overetched in some or a predetermined number of regions. However, if etching of the material layer 152a using the first etchant L1 is performed first, the material layer 152a may be sufficiently etched in advance before etching of the material layer for the data conductive layer 150 using the second etchant L2, and thus an over-etching rate of the material layer for the data conductive layer 150 may be reduced during etching of all the material layers for the data conductive layer 150 using the second etchant L2. As a result, the material layer 151a may be prevented from being damaged in some or a predetermined number of regions.

[0186] Afterwards, refer to Fig.10 and Fig.13 , the second data overlay pattern layer 152c may be etched using the photoresist pattern PR as an etching mask.

[0187] Meanwhile, the second data cover pattern layer 152c may include a first region 152c_T overlapping the data main metal layer 1511, and a second region 152c_M not overlapping the data main metal layer 1511. The first region 152c_T of the second data cover pattern layer 152c may correspond to the data cover layer 152, and the second region 152c_M of the second data cover pattern layer 152c may correspond to a tip structure protruding outward beyond the data main metal layer 1511.

[0188] The second data cover pattern layer 152c may be wet-etched using the third etchant L3. During the etching of the second data cover pattern layer 152c, the second region 152c_M of the second data cover pattern layer 152c may be etched and removed by the third etchant L3. For example, the etching of the second data cover pattern layer 152c may be a step of removing a tip generated in a process of etching all material layers for the data conductive layer 150 using the second etchant L2.

[0189] In order to remove the second area 152c_M of the second data cover pattern layer 152c without removing the first area 152c_T of the second data cover pattern layer 152c during the etching of the second data cover pattern layer 152c, the duration of the etching of the second data cover pattern layer 152c may be appropriately determined. In an embodiment, during the etching of the second data cover pattern layer 152c using the third etchant L3, the second data cover pattern layer 152c may not be over-etched.

[0190] In an embodiment, the second data cover pattern layer 152c may be over-etched at an over-etching rate of about 10% or less. In an embodiment, the thickness d of the second region 152c_M of the second data cover pattern layer 152c may be 4 The reference time amount for determining the over-etching rate of the second data cover pattern layer 152c is determined. The thickness d of the second region 152c_M of the second data cover pattern layer 152c 4 It may be a distance from one side of the data main metal layer 1511 to the outward protrusion of the second data capping pattern layer 152 c beyond the corresponding sidewall of the data main metal layer 1511 .

[0191] In an embodiment, the third etchant L3 may include an etchant component that is the same as or similar to that of the first etchant L1. In an embodiment, in order to selectively remove the second region 152c_M of the second data overlay pattern layer 152c using the third etchant L3, the duration of etching using the third etchant L3 may be much shorter than the duration of etching using the first etchant L1.

[0192] In an embodiment, the third etchant L3 may include an etchant component different from that of the first etchant L1. In an embodiment, in order to easily control the duration of etching for selectively removing the second region 152c_M of the second data overlay pattern layer 152c, the etching rate of the third etchant L3 on the material layer 152a may be slower than the etching rate of the first etchant L1 on the material layer 152a, but the disclosure is not limited thereto.

[0193] Reference Fig.14 As a result of etching of the second data cover pattern layer 152c, the second region 152c_M of the second data cover pattern layer 152c may be removed, thereby forming the data cover layer 152. The data cover layer 152 may correspond to the first region 152c_T of the second data cover pattern layer 152c.

[0194] By etching the tip structure such as the second region 152c_M of the second data cover pattern layer 152c using the third etchant L3, cracks may be prevented from being generated near the second region 152c_M of the second data cover pattern layer 152c during deposition of the passivation layer 164, and as a result, the reliability of the circuit layer CCL may be improved.

[0195] Thereafter, the photoresist pattern PR that may remain on the data cover layer 152 may be removed by an ashing or stripping process, thereby forming Fig.10 The data conductive layer 150 is formed.

[0196] Afterwards, refer to Fig.15 A passivation layer 164 and a via layer 165 may be sequentially deposited on the interlayer insulating film 163 on which the data conductive layer 150 may be formed, and a third contact hole CNT3 may expose a portion of the data conductive layer 150 in the transistor region TRR (e.g., the source electrode SEL) and a pad opening PDOP may be formed, and a portion of the data conductive layer 150 in the pad region PDA (e.g., the wiring pad WPD) may be exposed. The passivation layer 164 and the via layer 165 may be formed using the same or similar mask.

[0197] The via layer 165 may have a substantially flat surface and may have different heights in different regions. For example, the height of the via layer 165 in the pad area PDA may be smaller than the height of the via layer 165 in the display area DPA.

[0198] For example, the via layer 165 may include an organic material including a photosensitive material. In this example, the passivation layer 164 and the via layer 165 may be patterned by coating a material layer for the passivation layer 164 and an organic material layer for the via layer 165 and exposing and developing them to form openings.

[0199] As an example, a material layer for the passivation layer 164 and an organic material layer for the via layer 165 may be deposited on the entire surface of the interlayer insulating film 163 on which the data conductive layer 150 may be formed.

[0200] Afterwards, a photoresist pattern may be formed by forming a photoresist layer on the organic material layer for the via layer 165, and exposing and developing the photoresist layer. The photoresist pattern may include: a first opening exposing a region that may overlap with the source electrode SEL in the transistor region TRR; and a second opening exposing the pad area PDA. The first opening may overlap with the third contact hole CNT3, and the second opening may overlap with the pad opening PDOP.

[0201] Afterwards, the passivation layer 164 and the via layer 165 may be etched using a photoresist pattern located on the organic material layer for the via layer 165 as an etching mask. The via layer 165, which may have different heights in different regions, may be formed using a half-tone mask or a slit mask. As a result of the etching of the passivation layer 164 and the via layer 165, portions of the passivation layer 164 and the via layer 165 exposed by the first opening may be etched so that a third contact hole CNT3 may be formed that may expose the source electrode SEL in the transistor region TRR. Portions of the passivation layer 164 and the via layer 165 exposed by the second opening may be etched so that a pad opening PDOP may be formed that may expose the wiring pad WPD in the pad area PDA. During the etching of the passivation layer 164 and the via layer 165, the data cover layer 152 of the data conductive layer 150 may protect the data conductive metal layer 151 that may be disposed below the data cover layer 152. Afterwards, the photoresist pattern can be removed by a stripping or ashing process to form a Fig.15 A passivation layer 164 and a via layer 165 are provided.

[0202] The third contact hole CNT3 and the pad opening PDOP expose the data conductive layer 150, for example, expose the data cover layer 152 of the data conductive layer 150. The third contact hole CNT3 may expose the data cover layer 152 in the source electrode SEL in the transistor region TRR. Similarly, the pad opening PDOP may expose the data cover layer 152 in the pad area PDA. The side of the via layer 165 where the pad opening PDOP may be formed may be aligned with the side of the passivation layer 164 where the pad opening PDOP is also formed. The portion of the data conductive layer 150 exposed by the pad opening PDOP may be used as a wiring pad WPD.

[0203] The data cover layer 152 formed together with the data conductive metal layer 151 through a single mask process may be used as a contact electrode of the wiring pad WPD. Therefore, since an additional mask process that may form a contact electrode of the wiring pad WPD is not required, process efficiency may be improved.

[0204] Afterwards, refer to Fig.16 , a pixel electrode PXE that may be patterned may be formed or disposed on the via layer 165. The pixel electrode PXE may be formed through a mask process.

[0205] As an example, a material layer for the pixel electrode PXE may be deposited on the entire surface of the via layer 165. During the deposition of the material layer for the pixel electrode PXE, the material layer for the pixel electrode PXE may even be deposited on the inner side of the third contact hole CNT3 and thus may be electrically connected to the source electrode SEL. Thereafter, a photoresist layer may be coated on the material layer for the pixel electrode PXE, and the photoresist layer may be exposed and developed to form a photoresist pattern having a pattern shape that is the same as or similar to the pattern shape of the pixel electrode PXE to be formed. Thereafter, the photoresist pattern may be used as an etching mask to etch the material layer for the pixel electrode PXE. The material layer for the pixel electrode PXE may be wet etched, but the disclosure is not limited thereto.

[0206] Afterwards, refer to Figure 5 , a pixel defining film PDL that can be patterned can be formed or disposed on the via layer 165 where the pixel electrode PXE can be formed or disposed. For example, the pixel defining film PDL can include an organic material containing a photosensitive material. In this example, the pixel defining film PDL can be formed by coating an organic material layer for the pixel defining film PDL and exposing and developing the organic material layer. The pixel defining film PDL can be formed along the boundary of the pixel PX and can partially overlap with the pixel electrode PXE.

[0207] As described above, an additional mask process that may form a contact electrode of a wiring pad may not be required. Therefore, the number of mask processes may be reduced, and as a result, process efficiency may be improved.

[0208] The data conductive layer may be patterned in three etching steps (e.g., first to third etching steps), the data conductive layer being formed by depositing a data main conductive layer (including Cu) and a data conductive cover layer (including a material that can be etched more slowly than Cu for the same or similar etchant). Since the first etching step may be performed using a first etchant so as not to leave a residual data conductive cover film, any stains that may be generated by over-etching the data main conductive layer including Cu may be prevented. The width of the tip structure that needs to be removed in the third etching step may be reduced.

[0209] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles of the disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for a limiting purpose.

Claims

1. A method for manufacturing a conductive pattern, the method comprising the following steps: forming a conductive metal material layer and a conductive covering material layer on a substrate; forming a photoresist pattern as an etching mask on the conductive cover material layer; forming a first conductive covering pattern by etching the conductive covering material layer using a first etchant; forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern using a second etchant; as well as A conductive covering layer is formed by etching the second conductive covering pattern using a third etchant, wherein: The second conductive cover pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and The step of forming the conductive cover layer includes etching the second region of the second conductive cover pattern to form the conductive cover layer.

2. The method according to claim 1, wherein: The step of forming the conductive metal layer comprises: forming a main metal layer below the conductive cover layer, The main metal layer contacts the conductive covering layer and includes copper.

3. The method according to claim 2, wherein: The conductive cover layer includes at least one of an indium tin oxide film, a titanium film, an indium zinc oxide film, and an indium tin zinc oxide film.

4. The method according to claim 3, wherein: The step of forming the conductive covering layer comprises: aligning the sidewalls of the conductive cover layer with the sidewalls of the primary metal layer, or The sidewall of the conductive cover layer is disposed inside the sidewall of the main metal layer.

5. The method according to claim 2, wherein: The step of forming the conductive metal layer comprises: forming a conductive base layer below the main metal layer, Wherein, the conductive base layer contacts the main metal layer and includes titanium.

6. The method according to claim 1, wherein: The step of forming the first conductive covering pattern comprises: Over-etching the conductive covering material layer at an over-etching rate in a range of 100% to 200%, wherein the over-etching rate of the conductive covering material layer is determined based on a thickness of the conductive covering material layer, and an etching rate of the conductive covering material layer by the first etchant is higher than an etching rate of the conductive metal material layer by the first etchant; and The sidewall of the first conductive capping pattern is formed inside the sidewall of the photoresist pattern by an over-etching step performed on the conductive capping material layer.

7. The method according to claim 6, wherein: The step of forming the conductive cover layer includes over-etching the second conductive cover pattern at an over-etching rate of 10% or less, and The over-etching rate of the second conductive capping pattern is determined based on a thickness of the second region of the second conductive capping pattern.

8. The method according to claim 6, wherein: The step of forming the conductive metal layer includes over-etching the conductive metal material layer at an over-etching rate of 50% or less, and The over-etching rate of the conductive metal material layer is determined based on the thickness of the conductive metal material layer.

9. The method according to claim 6, wherein: The step of forming the first conductive covering pattern comprises: A region of the conductive metal material layer that does not overlap the photoresist pattern is exposed.

10. The method according to claim 1, wherein: An etching rate of the first conductive capping pattern by the second etchant is lower than an etching rate of the conductive metal material layer by the second etchant.

11. The method according to claim 10, wherein: The first etchant and the third etchant are the same etchant, and An etching duration of an etching step performed on the conductive capping material layer using the first etchant is longer than an etching duration of an etching step performed on the second conductive capping pattern using the third etchant.

12. The method according to claim 10, wherein: The first etchant and the third etchant are different etchants, and An etching rate of the second conductive capping pattern by the third etchant is lower than an etching rate of the conductive capping material layer by the first etchant.

13. The method according to claim 1, further comprising: The photoresist pattern is removed after forming the conductive capping layer.

14. A method for manufacturing a display device, the method comprising the following steps: preparing a substrate including a display region and a pad region; as well as forming a data conductive layer, the data conductive layer comprising: a source electrode and a drain electrode, arranged in the display area; a wiring pad, arranged in the pad area; a data conductive metal layer, arranged on the substrate; and a data cover layer, arranged on the data conductive metal layer, The step of forming the data conductive layer includes: forming a material layer for the data conductive metal layer and a material layer for the data cover layer on the substrate; forming a photoresist pattern as an etching mask on the material layer for the data cover layer; etching the material layer for the data cover layer by using a first etchant to form a first data cover pattern layer; etching the material layer for the data conductive metal layer and the first data cover pattern layer on the material layer for the data conductive metal layer by using a second etchant to form the data conductive metal layer and a second data cover pattern layer on the data conductive metal layer; and etching the second data cover pattern layer by using a third etchant to form the data cover layer, and The step of forming the first data cover pattern layer includes exposing a portion of the material layer for the data conductive metal layer that does not overlap with the photoresist pattern.

15. The method according to claim 14, wherein: The step of forming the data conductive metal layer comprises: forming a data main metal layer below the data cover layer, The data main metal layer contacts the data cover layer and includes copper.

16. The method according to claim 15, wherein: The data cover layer includes at least one of an indium tin oxide film, a titanium film, an indium zinc oxide film and an indium tin zinc oxide film.

17. The method according to claim 15, wherein: An etching rate of the first data cover pattern layer by the second etchant is lower than an etching rate of the material layer for the data conductive metal layer by the second etchant.

18. The method according to claim 17, wherein: The step of etching the material layer for the data conductive metal layer and the first data cover pattern layer using the second etchant includes: forming in the second data cover pattern layer: A first region overlapping the data conductive metal layer; and The second region does not overlap the data conductive metal layer and overlaps the photoresist pattern.

19. The method according to claim 14, wherein: The step of forming the data cover layer comprises: aligning the sidewall of the data cover layer with the sidewall of the data conductive metal layer, or The sidewall of the data cover layer is disposed inside the sidewall of the data conductive metal layer.

20. The method according to claim 14, wherein: The step of forming the first data overlay pattern layer comprises: over-etching the material layer for the data cover layer at an over-etching rate in a range of 100% to 200%, wherein the over-etching rate of the material layer for the data cover layer is determined based on a thickness of the material layer for the data cover layer, and an etching rate of the material layer for the data cover layer by the first etchant is higher than an etching rate of the material layer for the data conductive metal layer by the first etchant; and By over-etching the material layer for the data cover layer, a sidewall of the first data cover pattern layer is formed inside the sidewall of the photoresist pattern.

21. The method according to claim 20, wherein: The step of forming the data cover layer includes over-etching the second data cover pattern layer at an over-etching rate of 10% or less, The second data cover pattern layer includes: a first area overlapping the data conductive metal layer; and a second area not overlapping the data conductive metal layer, and The over-etching rate of the second data cover pattern layer is determined based on a thickness of the second region of the second data cover pattern layer.

22. The method according to claim 20, wherein: The step of forming the data conductive metal layer includes over-etching the material layer for the data conductive metal layer at an over-etching rate of 50% or less, and The over-etching rate of the material layer for the data conductive metal layer is determined based on the thickness of the material layer for the data conductive metal layer.

23. A display device, comprising: a substrate, including a display area and a pad area; A data conductive layer including: a source electrode and a drain electrode disposed in the display region; and a wiring pad disposed in the pad region and exposed by the pad opening; a passivation layer, overlapping the source electrode and the drain electrode; A light emitting element is disposed in the pixel; and A driving transistor is provided to provide a driving current to the light emitting element, wherein: The data conductive layer further comprises: a data conductive metal layer disposed on the substrate; and a data cover layer disposed on the data conductive metal layer. The data conductive metal layer includes copper, The data cover layer includes a material having an etching rate slower than that of copper, and The sidewall of the data cover layer is aligned with the sidewall of the data conductive metal layer or is disposed inside the sidewall of the data conductive metal layer.

24. The display device according to claim 23, wherein: The data cover layer includes at least one of an indium tin oxide film, a titanium film, an indium zinc oxide film and an indium tin zinc oxide film.

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