Display device

Abstract

An embodiment of the present application discloses a display device, the display device includes: a substrate including a display area and a non-display area; a circuit portion configured on the non-display area and including a first circuit portion and a second circuit portion; a valley portion separating the first circuit portion and the second circuit portion; and a thin film encapsulation layer sealing the display area and extending from the display area to the valley portion, the first circuit portion is configured between the valley portion and the display area, the second circuit portion is configured outside the valley portion, an inner layer configured on the first circuit portion includes a plurality of island-shaped portions spaced apart from each other in a first direction and a second direction intersecting the first direction, and an outer layer configured on the second circuit portion has at least one groove extending in the first direction.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a display device including a thin film encapsulation layer. BACKGROUND

[0002] As the development of an information society, the demand for a display device for displaying an image is continuously increasing in various forms. The field of display devices has rapidly changed to enable a flat panel display device (FPD) which is thin, light, and large in area, instead of a cathode ray tube (CRT) which is large in volume. Among the flat panel display devices are a liquid crystal display device (LCD), a plasma display panel (PDP), an organic light emitting display device (OLED), and an electrophoretic display device (EPD), etc.

[0003] The display device can include a display area in which an image is realized and a non-display area in which an image is not realized. Recently, research is actively conducted to enlarge the display area by reducing the area of the non-display area of the display device in which a circuit portion or the like is disposed.

[0004] Meanwhile, the display device can include a thin film encapsulation layer which seals the display area, and the thin film encapsulation layer can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. SUMMARY

[0005] Embodiments of the present application provide a display device which prevents or checks overflow of the organic encapsulation layer.

[0006] In addition, embodiments of the present application reduce the area of the non-display area and enlarge the display area by disposing at least one groove which prevents or checks overflow of the organic encapsulation layer on a circuit portion of the non-display area.

[0007] An embodiment of the present invention discloses a display device including a substrate including a display area and a non-display area, a circuit portion disposed on the non-display area and including a first circuit portion and a second circuit portion, a valley portion separating the first circuit portion and the second circuit portion, and a thin film encapsulation layer sealing the display area and extending from the display area to the valley portion, the first circuit portion being disposed between the valley portion and the display area, an inner layer disposed on the first circuit portion including a plurality of island portions spaced apart from each other in a first direction and a second direction intersecting the first direction, and an outer layer disposed on the second circuit portion having at least one groove extending in the first direction.

[0008] In an embodiment, a display element including a pixel electrode and a counter electrode can be disposed on the display area, a connection conductive layer including the same substance as the pixel electrode can extend from the first circuit portion to the second circuit portion, and the connection conductive layer can include a plurality of holes.

[0009] In an embodiment, the outer layer can cover the plurality of holes.

[0010] In an embodiment, the outer layer can be separated into a plurality of pattern portions by the at least one groove, and the plurality of pattern portions can cover the plurality of holes.

[0011] In an embodiment, the outer layer can define a light emitting area of the display element and include the same substance as a pixel defining film covering an end portion of the pixel electrode, and an upper outer layer can be further disposed on the outer layer.

[0012] In an embodiment, the inner layer and the outer layer can be separated by the valley portion.

[0013] In an embodiment, a first outer insulating layer covering the second circuit portion can be disposed between the second circuit portion and the outer layer.

[0014] In an embodiment, a second outer insulating layer can be disposed between the first outer insulating layer and the outer layer.

[0015] In an embodiment, a third outer insulating layer can be disposed between the second outer insulating layer and the outer layer.

[0016] In an embodiment, the display device can further include a dam portion surrounding the valley portion.

[0017] In an embodiment, the dam portion can include a plurality of dams extending in the second direction.

[0018] In one embodiment, it can be that the at least one groove of the outer layer surrounds the valley portion.

[0019] In one embodiment, it can be that the thin film encapsulation layer includes at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0020] In one embodiment, it can be that the display device further includes an input sensing portion on the thin film encapsulation layer.

[0021] In one embodiment, it can be that the input sensing portion includes a touch wiring on the non-display area.

[0022] Another embodiment of the present application discloses a display device including a substrate including a display area and a non-display area, a valley portion configured to surround the display area on the non-display area and including a first valley area and a second valley area facing each other, a circuit portion configured outside at least any one of the first valley area and the second valley area and extending in a first direction, an outer layer having at least one groove extending on the circuit portion in the first direction, a plurality of dams configured outside the valley portion between the first valley area and the second valley area in the valley portion and extending in a second direction intersecting the first direction, and a thin film encapsulation layer sealing the display area and extending to the non-display area.

[0023] In one embodiment, it can be that a display element including a pixel electrode and a counter electrode is configured on the display area, a connection conductive layer including the same substance as the pixel electrode is configured on the circuit portion, and the connection conductive layer includes a plurality of holes.

[0024] In one embodiment, it can be that the outer layer covers the plurality of holes.

[0025] In one embodiment, it can be that the outer layer is separated into a plurality of pattern portions by the at least one groove.

[0026] In one embodiment, it can be that the plurality of pattern portions cover the plurality of holes.

[0027] (EFFECTS OF THE INVENTION)

[0028] As described above, embodiments of the present application can prevent or check overflow of the organic encapsulation layer by having at least one groove extending in a first direction in the non-display area.

[0029] In addition, the area of the non-display area can be reduced and the display area can be enlarged by configuring the at least one groove on the circuit portion. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a perspective view schematically showing a display device according to an embodiment of the present application.

[0031] Figure 2 is a cross-sectional view schematically showing a display panel according to an embodiment of the present application.

[0032] Figure 3 is a plan view schematically showing an input sensing portion according to an embodiment of the present application.

[0033] Figure 4 is a cross-sectional view showing a stack structure of an input sensing portion according to an embodiment of the present application.

[0034] Figure 5a and Figure 5b is an equivalent circuit diagram of any one pixel included in a display device according to an embodiment of the present application.

[0035] Figure 6 is a plan view schematically showing a display panel according to an embodiment of the present application.

[0036] Figure 7 is a cross-sectional view taken along the line A-A' of Figure 6 .

[0037] Figure 8 is a cross-sectional view taken along the line B-B' of Figure 6 .

[0038] Figure 9 is a cross-sectional view taken along the line C-C' of Figure 6 .

[0039] Figure 10 is a cross-sectional view taken along the line D-D' of Figure 6 .

[0040] Figure 11 is a cross-sectional view schematically showing a part of a non-display region according to another embodiment of the present application.

[0041] Figure 12 is a cross-sectional view schematically showing a part of a non-display region according to still another embodiment of the present application.

[0042] Figure 13 is a cross-sectional view schematically showing a part of a non-display region according to still another embodiment of the present application.

[0043] Figure 14 is a cross-sectional view taken along the line D-D' of Figure 6 according to still another embodiment of the present application.

[0044] REFERENCE NUMERALS

[0045] BL1: first boundary line

[0046] BL2: second boundary line

[0047] BL3: third boundary line

[0048] BL4: fourth boundary line

[0049] CL1: first connection conductive layer

[0050] CL2: second connection conductive layer

[0051] CL3: third connection conductive layer

[0052] CP: circuit portion

[0053] CP1: first circuit portion

[0054] CP2: second circuit portion

[0055] CP1-TFT: first thin film transistor

[0056] CP2-TFT: second thin film transistor

[0057] DAM, DAM-1: dam portion

[0058] VA1: first valley region

[0059] VA2: second valley region

[0060] VP: valley portion

[0061] 1: display device

[0062] 100: substrate

[0063] 118: pixel definition film

[0064] 118A: inner layer

[0065] 118B: outer layer

[0066] 118B-1: first pattern portion

[0067] 118B-2: second pattern portion

[0068] 118B-3: third pattern portion

[0069] 119B: upper outer layer

[0070] 211: pixel electrode

[0071] 213: counter electrode

[0072] 310: first inorganic encapsulation layer

[0073] 330: second inorganic encapsulation layer

[0074] 320: organic encapsulation layer DETAILED DESCRIPTION

[0075] The present application can be variously changed and can have various embodiments, and specific embodiments are illustrated in the drawings and are described in detail in the detailed description. The effects, features, and methods of achieving them of the present application will become apparent through the embodiments described below in detail with reference to the accompanying drawings. However, the present application is not limited to the embodiments disclosed herein and can be implemented in various forms.

[0076] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings. In the description, the same or similar components are designated by the same reference numerals, and repetitive description of the same or similar components will be omitted.

[0077] In the following embodiments, the first, second, and the like terms do not have a limiting meaning, and the purpose of their use is to distinguish one component from other components.

[0078] In the following embodiments, the singular expression includes the plural expression unless the context clearly dictates otherwise.

[0079] In the following embodiments, the including or having terms mean that the features or components described in the specification are present, and do not exclude the possibility of addition of one or more other features or components in advance.

[0080] In the following embodiments, when a film, a region, a component, or the like is described as being located on or above another part, not only a case in which it is directly located on the other part is included, but also a case in which another film, region, component, or the like is interposed therebetween is included.

[0081] In the drawings, the size of the components can be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present application is not necessarily limited to the case shown in the drawings.

[0082] When a certain embodiment can be implemented in different forms, a specific process sequence can also be performed differently from the order described. For example, two processes described in succession can be performed substantially simultaneously or in the opposite order.

[0083] In the following embodiments, when a film, a region, a component, or the like is described as being connected, not only a case in which the film, the region, the component, or the like is directly connected is included, but also a case in which other films, regions, components, or the like are interposed between the film, the region, the component, or the like to indirectly connect the film, the region, the component, or the like. For example, in the present specification, when a film, a region, a component, or the like is described as being electrically connected, not only a case in which the film, the region, the component, or the like is directly electrically connected is included, but also a case in which other films, regions, components, or the like are interposed therebetween to indirectly electrically connect the film, the region, the component, or the like.

[0084] The display device 1 can be a game machine, a multimedia device, a portable mobile device such as a subminiature PC, as a device that displays an image. The display device 1 to be described later can include a liquid crystal display, an electrophoretic display, an organic light emitting display, an inorganic EL display, a field emission display, a surface-conduction electron-emitter display, a quantum dot display, a plasma display, a cathode ray tube display, or the like. Hereinafter, as the display device 1 according to an embodiment of the present application, an organic light emitting display will be described as an example, but an embodiment of the present application can use a display device of various modes as described above.

[0085] Figure 1 is a perspective view schematically showing the display device 1 according to an embodiment of the present application. Figure 2 is a cross-sectional view schematically showing the display panel 10 according to an embodiment of the present application.

[0086] Referring to Figure 1 , the display device 1 can include a display panel 10 that realizes an image. The display panel 10 includes a display area DA in which pixels P are arranged to realize an image, and a non-display area NDA in which an image is not realized. A circuit portion or the like including at least one thin film transistor can be arranged on the non-display area NDA. The display panel 10 can provide an image using light emitted from a plurality of pixels P arranged in the display area DA. Each pixel P can emit light of red, green, blue, or white, respectively.

[0087] Referring to Figure 2The display panel 10 can include a pixel circuit layer PCL including pixel circuits and insulating layers on the substrate 100, and a display element layer DEL including a plurality of display elements on the pixel circuit layer PCL.

[0088] The substrate 100 can include glass or a high molecular resin such as polyethersulfone, polyarylate, polyetherimide, polyethylenenaphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate (PC), triacetyl cellulose (TAC), cellulose acetate propionate, or the like.

[0089] A barrier layer (not shown) can be further included between the pixel circuit layer PCL and the substrate 100. The barrier layer, which serves as a barrier layer for preventing penetration of external foreign substances, can be a single layer or a plurality of layers including inorganic substances such as silicon nitride (SiN X ), silicon oxide (SiO X ).

[0090] The display element layer DEL can include display elements, for example, organic light emitting diodes. The pixel circuit layer PCL can include pixel circuits and insulating layers connected to each of the organic light emitting diodes. The pixel circuit layer PCL can include a plurality of transistors, a storage capacitor, and insulating layers interposed therebetween.

[0091] The display elements can be covered with an encapsulation member such as a thin film encapsulation layer TFE. The thin film encapsulation layer TFE can include at least one inorganic encapsulation layer and at least one organic encapsulation layer covering the display element layer DEL. The inorganic encapsulation layer can include one or more inorganic substances among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride. The organic encapsulation layer can include a substance of a polymer series. As a material of the polymer series, an acrylic resin, an epoxy resin, a polyimide, and polyethylene, or the like can be included. As an embodiment, the organic encapsulation layer can include acrylate.

[0092] The input sensing portion TSL including a touch electrode can be disposed on the thin film encapsulation layer TFE, and the optical functional layer OFL can be disposed on the input sensing portion TSL. The input sensing portion TSL can acquire an input from the outside, for example, coordinate information according to a touch event. The optical functional layer OFL can reduce reflectance of light (external light) incident from the outside toward the display device 1, and / or can improve color purity of light emitted from the display device 1. As an embodiment, the optical functional layer OFL can include a phase retarder and a polarizer. The phase retarder can be of a film type or a liquid crystal coating type, and can include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer can also be of a film type or a liquid crystal coating type. The film type can include a stretched synthetic resin film, and the liquid crystal coating type can include liquid crystals arranged in a predetermined arrangement. The phase retarder and the polarizer can further include a protective film.

[0093] As another embodiment, the optical functional layer OFL can include a black matrix and a color filter. The color filter can be arranged in consideration of colors of light emitted from each of the pixels of the display device 1. Each of the color filters can include a red, green, or blue pigment or dye. Alternatively, each of the color filters can further include a quantum dot in addition to the above-described pigments or dyes. Alternatively, a part of the color filters can not include the above-described pigments or dyes, and can include scattering particles such as titanium oxide.

[0094] As another embodiment, the optical functional layer OFL can include a destructive interference structure. The destructive interference structure can include a first reflection layer and a second reflection layer disposed on different layers from each other. First reflected light and second reflected light reflected from the first reflection layer and the second reflection layer, respectively, can destructively interfere, whereby external light reflectance can be reduced.

[0095] A bonding member can be disposed between the input sensing portion TSL and the optical functional layer OFL. The bonding member can be used without limitation from conventional bonding members known in the technical field. The bonding member can be a pressure sensitive adhesive (PSA).

[0096] Figure 3 FIG. 1 is a schematic view illustrating a display device according to an embodiment of the present application.

[0097] Referring to Figure 3The input sensing part TSL can include a first sensing electrode 410, first traces lines (415-1 to 415-4) connected to the first sensing electrode 410, a second sensing electrode 420, and second traces lines (425-1 to 425-5) connected to the second sensing electrode 420. The first sensing electrode 410 and the second sensing electrode 420 can be disposed in the display area DA, and the first traces lines (415-1 to 415-4) and the second traces lines (425-1 to 425-5) can be disposed in the non-display area NDA.

[0098] The first sensing electrode 410 can be arranged in ±y direction, and the second sensing electrode 420 can be arranged in ±x direction crossing the ±y direction. The first sensing electrode 410 arranged in the ±y direction can be connected to each other by a first connection electrode 411 between adjacent first sensing electrodes 410, and can form respective first sensing lines (410C1 to 410C4). The second sensing electrode 420 arranged in the ±x direction can be connected to each other by a second connection electrode 421 between adjacent second sensing electrodes 420, and can form respective second sensing lines (420R1 to 420R5). The first sensing lines (410C1 to 410C4) and the second sensing lines (420R1 to 420R5) can cross each other. For example, the first sensing lines (410C1 to 410C4) and the second sensing lines (420R1 to 420R5) can cross each other perpendicularly.

[0099] The first sensing lines (410C1 to 410C4) can be connected to pads of the sensing signal pad part 440 through the first traces lines (415-1 to 415-4) disposed in the non-display area NDA. For example, each of the first traces lines (415-1 to 415-4) can be a double routing structure connected to upper sides and lower sides of the first sensing lines (410C1 to 410C4), respectively. The first traces lines (415-1 to 415-4) connected to the upper sides and the lower sides of the first sensing lines (410C1 to 410C4), respectively, can be connected to corresponding pads, respectively. Such a structure can improve sensing sensitivity. In another embodiment, the first traces lines (415-1 to 415-4) can be a single routing structure connected to the upper sides or the lower sides of the first sensing lines (410C1 to 410C4).

[0100] The second sensing lines (420R1 to 420R5) can be connected to pads of the sensing signal pad part 440 through the second traces lines (425-1 to 425-5) disposed in the non-display area NDA. For example, the second traces lines (425-1 to 425-5) can be connected to corresponding pads, respectively.

[0101] Figure 4 is a cross-sectional view illustrating a stack structure of an input sensing part TSL according to an embodiment of the present application.

[0102] Referring to Figure 4 , the input sensing part TSL can include a first conductive layer CML1 and a second conductive layer CML2. A first touch insulation layer 43 can be disposed between the first conductive layer CML1 and the second conductive layer CML2, and a second touch insulation layer 45 can be disposed on the second conductive layer CML2. Referring to Figure 3 Each of the first sensing electrode 410, the first connection electrode 411, the second sensing electrode 420, and the second connection electrode 421 described above can be included in one of the first conductive layer CML1 or the second conductive layer CML2.

[0103] The first conductive layer CML1 or the second conductive layer CML2 can include a metal layer or a transparent conductive layer. The metal layer can include molybdenum (Mo), molybdenum (Md), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), and alloys thereof. The transparent conductive layer can include a transparent conductive oxide such as ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc. In addition thereto, the transparent conductive layer can include a conductive polymer such as PEDOT, a metal nanowire, graphene, etc.

[0104] The first conductive layer CML1 or the second conductive layer CML2 can be a single layer or a plurality of layers. The single-layer first conductive layer CML1 or the second conductive layer CML2 can include a metal layer or a transparent conductive layer, and the materials of the metal layer and the transparent conductive layer are as described above. One of the first conductive layer CML1 and the second conductive layer CML2 can include a single metal layer. One of the first conductive layer CML1 and the second conductive layer CML2 can include a plurality of metal layers. For example, the plurality of metal layers can include three layers of a titanium layer / aluminum layer / titanium layer, or can include two layers of a molybdenum layer / molybdenum layer. Alternatively, the plurality of metal layers can include a metal layer and a transparent conductive layer. The first conductive layer CML1 and the second conductive layer CML2 can have different stack structures from each other, or can have the same stack structure. For example, the first conductive layer CML1 can include a metal layer, and the second conductive layer CML2 can include a transparent conductive layer. Alternatively, the first conductive layer CML1 and the second conductive layer CML2 can include the same metal layer.

[0105] The sensing sensitivity can be considered to determine the substance of the first conductive layer CML1 and the second conductive layer CML2 and the configuration of the sensing electrodes provided in the first conductive layer CML1 and the second conductive layer CML2. The RC delay can affect the sensing sensitivity, but the resistance of the sensing electrodes including the metal layer is small compared to the transparent conductive layer, so the RC value can be reduced, and thus the charging time of the capacitor defined between the sensing electrodes can be reduced. The sensing electrodes including the transparent conductive layer are invisible to the user compared to the metal layer, and can increase the input area to increase the capacitance.

[0106] The first touch insulating layer 43 and the second touch insulating layer 45 can include inorganic insulating substances and / or organic insulating substances, respectively. The inorganic insulating substances can include silicon oxide, silicon nitride, or silicon oxynitride, etc., and the organic insulating substances can include high molecular organic substances.

[0107] In Figure 4 The input sensing part TSL includes the first conductive layer CML1, the first touch insulating layer 43, the second conductive layer CML2, and the second touch insulating layer 45 is shown in FIG. 1, but in another embodiment, a buffer layer including inorganic insulating substances or organic insulating substances can be further configured under the first conductive layer CML1.

[0108] Figure 5a And Figure 5b is an equivalent circuit diagram of any one pixel P included in a display device according to an embodiment of the present application.

[0109] Referring to Figure 5a , the pixel P can include a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC.

[0110] The pixel circuit PC can include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. For example, each pixel P can emit red, green, or blue light through the organic light emitting diode OLED, or emit red, green, blue, or white light.

[0111] The switching thin film transistor T2 can be connected to a scan line SL and a data line DL, and can transmit a data voltage input from the data line DL to the driving thin film transistor T1 based on a switching voltage input from the scan line SL. The storage capacitor Cst can be connected to the switching thin film transistor T2 and a driving voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the switching thin film transistor T2 and the first power voltage ELVDD supplied to the driving voltage line PL.

[0112] The drive thin film transistor T1 can be connected with the drive voltage line PL and the storage capacitor Cst, and can control a drive current flowing through the organic light emitting diode OLED from the drive voltage line PL in response to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light having a predetermined brightness by the drive current. The counter electrode (e.g., cathode) of the organic light emitting diode OLED can receive the second power voltage ELVSS.

[0113] Referring to Figure 5b , the pixel circuit PC can include the drive thin film transistor T1, the switch thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the light emission control thin film transistor T6, and the second initialization thin film transistor T7.

[0114] In Figure 5b , it is shown that each of the pixel circuits PC is provided with the signal lines (SL, SL-1, SL+1, EL, DL), the initialization voltage line VL, and the drive voltage line PL, but in yet another embodiment, at least any one of the signal lines (SL, SL-1, SL+1, EL, DL) and / or the initialization voltage line VL can be shared in adjacent pixel circuits PC.

[0115] The drain electrode of the drive thin film transistor T1 can be electrically connected with the organic light emitting diode OLED via the light emission control thin film transistor T6. The drive thin film transistor T1 can supply the drive current to the organic light emitting diode OLED in response to the data signal Dm received according to the switching operation of the switch thin film transistor T2.

[0116] The gate electrode of the switch thin film transistor T2 can be connected with the scan line SL, and the source electrode can be connected with the data line DL. The drain electrode of the switch thin film transistor T2 can be connected with the source electrode of the drive thin film transistor T1 while being connected with the drive voltage line PL via the operation control thin film transistor T5.

[0117] The switch thin film transistor T2 can be turned on according to the scan signal Sn received through the scan line SL to perform the switching operation of transferring the data signal Dm transferred to the data line DL to the source electrode of the drive thin film transistor T1.

[0118] The gate electrode of the compensation thin film transistor T3 can be connected with the scan line SL. The source electrode of the compensation thin film transistor T3 can be connected with the drain electrode of the driving thin film transistor Tl while being connected with the pixel electrode of the organic light emitting diode OLED via the light emitting control thin film transistor T6. The drain electrode of the compensation thin film transistor T3 can be connected with any one of the electrodes of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor Tl. The compensation thin film transistor T3 can be turned on according to the scan signal Sn received through the scan line SL to connect the gate electrode and the drain electrode of the driving thin film transistor Tl to each other, thereby making the driving thin film transistor Tl diode-connection.

[0119] The gate electrode of the first initialization thin film transistor T4 can be connected with the previous scan line SL-1. The drain electrode of the first initialization thin film transistor T4 can be connected with the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 can be connected with any one of the electrodes of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor Tl. The first initialization thin film transistor T4 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1 to transmit the initialization voltage Vint to the gate electrode of the driving thin film transistor Tl, thereby performing an initialization operation of initializing the voltage of the gate electrode of the driving thin film transistor Tl.

[0120] The gate electrode of the operation control thin film transistor T5 can be connected with the light emitting control line EL. The source electrode of the operation control thin film transistor T5 can be connected with the driving voltage line PL. The drain electrode of the operation control thin film transistor T5 can be connected with the source electrode of the driving thin film transistor Tl and the drain electrode of the switching thin film transistor T2.

[0121] The gate electrode of the light emitting control thin film transistor T6 can be connected with the light emitting control line EL. The source electrode of the light emitting control thin film transistor T6 can be connected with the drain electrode of the driving thin film transistor Tl and the source electrode of the compensation thin film transistor T3. The drain electrode of the light emitting control thin film transistor T6 can be connected with the pixel electrode of the organic light emitting diode OLED. The operation control thin film transistor T5 and the light emitting control thin film transistor T6 are simultaneously turned on according to the light emitting control signal En received through the light emitting control line EL to transmit the first power voltage ELVDD to the organic light emitting diode OLED, and a driving current flows through the organic light emitting diode OLED.

[0122] The gate electrode of the second initialization thin film transistor T7 can be connected with the next scan line SL+1. The source electrode of the second initialization thin film transistor T7 can be connected with the pixel electrode of the organic light emitting diode OLED. The drain electrode of the second initialization thin film transistor T7 can be connected with the initialization voltage line VL. The second initialization thin film transistor T7 can be turned on according to the next scan signal Sn+1 received through the next scan line SL+1, to initialize the pixel electrode of the organic light emitting diode OLED.

[0123] In Figure 5b , the case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected with the previous scan line SL-1 and the next scan line SL+1 respectively is shown, but as still another embodiment, the first initialization thin film transistor T4 and the second initialization thin film transistor T7 can both be connected with the previous scan line SL-1 and driven according to the previous scan signal Sn-1.

[0124] The other electrode of the storage capacitor Cst can be connected with the drive voltage line PL. Any one of the electrodes of the storage capacitor Cst can be connected together with the gate electrode of the drive thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4.

[0125] The counter electrode (e.g., cathode) of the organic light emitting diode OLED receives the second power supply voltage ELVSS. The organic light emitting diode OLED can emit light from the drive current received from the drive thin film transistor T1.

[0126] The pixel circuit PC is not limited to the one described with reference to Figure 5a and Figure 5b The number and the circuit design of the thin film transistors and the storage capacitor described are subject to various changes.

[0127] Figure 6 is a plan view schematically showing a display panel 10 according to an embodiment of the present application.

[0128] With reference to Figure 6 , the display panel 10 can be provided with a substrate 100 including a display area DA and a non-display area NDA. The pixel P can be arranged in the display area DA, and the circuit portion CP, the valley portion VP, the voltage wiring portion WP, and the pad portion PADP can be included in the non-display area NDA.

[0129] In one embodiment, the display region DA can be a polygonal shape. In another embodiment, the display region DA can be a polygonal shape including a curvature. In yet another embodiment, the display region DA can be a circular shape. Hereinafter, a case where the display region DA is a polygonal shape will be described in detail with emphasis. In particular, a case where the display region DA is a rectangular shape will be described in detail with emphasis.

[0130] The non-display region NDA can be configured to surround the display region DA. At this time, a virtual boundary line dividing the display region DA and the non-display region NDA can be defined. For example, the virtual boundary line can include a first boundary line BL1, a second boundary line BL2, a third boundary line BL3, and a fourth boundary line BL4. The first boundary line BL1 and the third boundary line BL3 can extend in a first direction (for example, a y direction). In addition, the first boundary line BL1 and the third boundary line BL3 can be configured to be spaced apart from each other. The second boundary line BL2 and the fourth boundary line BL4 can extend in a second direction (for example, an x direction). In addition, the second boundary line BL2 and the fourth boundary line BL4 can be configured to be spaced apart from each other.

[0131] The pixel P can be connected with a data line DL extending in a first direction (for example, a y direction) and a scan line SL and an emission control line EL extending in a second direction (for example, an x direction). In addition, although not shown, the pixel P can also be connected with a driving voltage line PL (refer to FIG. 1). Figure 5a ).

[0132] The circuit portion CP can apply a signal to the pixel P in connection with the scan line SL or the emission control line EL. The circuit portion CP can be configured in the non-display region NDA. Specifically, the circuit portion CP can be configured corresponding to a part of the virtual boundary line of the display region DA and the non-display region NDA. In one embodiment, the circuit portion CP can be configured corresponding to a part of the first boundary line BL1 and / or the third boundary line BL3. Accordingly, the circuit portion CP can extend in the first direction (for example, a y direction). In this case, the circuit portion CP can be configured corresponding to the first boundary line BL1 and / or the third boundary line BL3, and not configured corresponding to the second boundary line BL2. The circuit portion CP can include a first circuit portion CP1 and a second circuit portion CP2.

[0133] The first circuit portion CP1 can be disposed between the valley portion VP and the display area DA. That is, the first circuit portion CP1 can be disposed closer to the display area DA than the second circuit portion CP2. The first circuit portion CP1 can include at least one first thin film transistor. In an embodiment, the first circuit portion CP1 can transmit a scan signal to the pixel P disposed in the display area DA. At this time, the first circuit portion CP1 can be connected with the scan line SL. In another embodiment, the first circuit portion CP1 can transmit an emission control signal to the pixel P disposed in the display area DA. At this time, the first circuit portion CP1 can be connected with the emission control line EL.

[0134] In the present embodiment, an inner layer can be disposed on the first circuit portion CP1. The inner layer can be an insulating layer including an organic substance or an inorganic substance. At this time, the inner layer can include a plurality of island portions IP disposed on the first circuit portion CP1, and the plurality of island portions IP can be disposed apart from each other. Specifically, the plurality of island portions IP can be disposed apart from each other in a first direction (for example, the y direction) and / or a second direction (for example, the x direction) intersecting the first direction.

[0135] The second circuit portion CP2 can be disposed outside the valley portion VP. That is, the second circuit portion CP2 can be disposed farther from the display area DA than the first circuit portion CP1. The second circuit portion CP2 can include at least one second thin film transistor. In an embodiment, the second circuit portion CP2 can transmit an emission control signal to the pixel P disposed in the display area DA. At this time, the second circuit portion CP2 can be connected with the emission control line EL. Hereinafter, a case in which the first circuit portion CP1 is connected with the scan line SL and the second circuit portion CP2 is connected with the emission control line EL will be described in detail.

[0136] In the present embodiment, an outer layer can be disposed on the second circuit portion CP2. The outer layer can be an insulating layer including an organic substance or an inorganic substance. At this time, the outer layer can have at least one groove VH extending in the first direction (for example, the y direction). That is, the outer layer can include at least one groove VH extending corresponding to the first boundary line BL1 or the third boundary line BL3. Accordingly, the at least one groove VH can be disposed to extend along one side of the display area DA.

[0137] In an embodiment, the at least one groove VH can include a plurality of grooves VH. For example, the plurality of grooves VH can include a first groove VH1 and a second groove VH2. At this time, the first groove VH1 can be disposed closer to the display area DA than the second groove VH2. As another example, the plurality of grooves VH can include three or more grooves VH.

[0138] The valley portion VP can be configured to separate the first circuit portion CP1 and the second circuit portion CP2. The valley portion VP can be configured to surround the display area DA in the non-display area NDA. Specifically, the valley portion VP can include the first valley area VA1 and the second valley area VA2 facing each other with the display area DA in between. At this time, the first valley area VA1 and the second valley area VA2 can extend in the first direction (for example, the y direction). In addition, the valley portion VP can include the third valley area VA3 and the fourth valley area VA4 facing each other with the display area DA in between. At this time, the third valley area VA3 and the fourth valley area VA4 can extend in the second direction (for example, the x direction). The first valley area VA1 and the second valley area VA2 can be connected to the third valley area VA3. In addition, the first valley area VA1 and the second valley area VA2 can be connected to the fourth valley area VA4.

[0139] The valley portion VP can separate the insulating layer laminated on the display panel 10. Therefore, it is possible to prevent moisture or foreign matter generated from an area outside the valley portion VP configured in the non-display area NDA from penetrating into the display area DA.

[0140] In the present embodiment, the valley portion VP can separate the circuit portion CP into the first circuit portion CP1 and the second circuit portion CP2. The valley portion VP separating the circuit portion CP into the first circuit portion CP1 and the second circuit portion CP2 means that the first circuit portion CP1 and the second circuit portion CP2 are spaced apart. A plurality of island portions IP can be configured to be spaced apart from each other in the first direction (for example, the y direction) and / or the second direction (for example, the x direction) between the valley portion VP and the display area DA, and at least one groove VH extending in the first direction (for example, the y direction) can be included outside the valley portion VP.

[0141] The voltage wiring portion WP can transmit a power voltage to the pixels P of the display area DA. The voltage wiring portion WP can be configured to surround the display area DA. The voltage wiring portion WP can also be connected to the pads PAD of the pad portion PADP. The voltage wiring portion WP can include the first voltage wiring portion WP1 and the second voltage wiring portion WP2. At this time, it can be that the first voltage wiring portion WP1 transmits the first power voltage ELVDD (refer to FIG. 1) to the pixels P of the display area DA, and the second voltage wiring portion WP2 transmits the second power voltage ELVSS (refer to FIG. 1) to the pixels P of the display area DA. Figure 5a ) to the pixels P of the display area DA, and the second voltage wiring portion WP2 transmits the second power voltage ELVSS (refer to Figure 5a

[0142] The first voltage wiring portion WP1 can extend in the second direction (for example, the x direction). In this case, the first voltage wiring portion WP1 can extend corresponding to the fourth boundary line BL4. In an embodiment, the first voltage wiring portion WP1 can be configured between the display area DA and the pad portion PADP.​

[0143] The second voltage wiring part WP2 can be configured to surround at least a portion of the display area DA. In an embodiment, the second voltage wiring part WP2 can extend along the remaining virtual boundary lines except for the virtual boundary line adjacent to the first voltage wiring part WP1. For example, the second voltage wiring part WP2 can extend corresponding to the first boundary line BL1, the second boundary line BL2, and the third boundary line BL3. In an aspect, the second circuit part CP2 can be configured between the second voltage wiring part WP2 and the valley part VP.

[0144] The pad part PADP can be configured at one end of the substrate 100 and include a plurality of pads PAD. Specifically, the pad part PADP can be configured corresponding to the fourth boundary line BL4. The pad part PADP can be exposed without being covered by the insulating layer to be electrically connected with a control part (not shown) such as a flexible printed circuit substrate or a driving driver IC chip, etc.

[0145] The control part can change a plurality of signals transmitted from the outside to a plurality of image data signals, and transmit the changed signals to the display area DA through a portion of the plurality of pads PAD. In addition, the control part can supply a first power voltage ELVDD (refer to Figure 5a ) to the first voltage wiring part WP1 through a first pad PAD1 of the plurality of pads PAD, and can supply a second power voltage ELVSS (refer to Figure 5a ) to the second voltage wiring part WP2 through a second pad PAD2 of the plurality of pads PAD.

[0146] In addition, although not shown, in the non-display area NDA, a data circuit part that supplies a data signal to a data line DL can be further configured in each pixel P.

[0147] In the present embodiment, as described above, at least one groove VH configured outside the valley part VP in the non-display area NDA can be used to prevent overflow of an organic encapsulation layer in a thin film encapsulation layer (not shown) that seals the display area DA and extends from the display area DA to the valley part VP or to inspect the overflowed organic encapsulation layer. In this regard, a detailed description will be given below with reference to Figure 8 and Figure 9 , and first, a detailed description will be given with reference to Figure 7 of the stack structure configured on the display area DA in the display panel 10.

[0148] Figure 7 is a cross-sectional view taken along the A-A' line of Figure 6 .

[0149] With reference to Figure 7The display panel 10 can include a substrate 100, a pixel circuit layer PCL, a display element layer DEL, and a thin film encapsulation layer TFE.

[0150] The pixel circuit layer PCL can be disposed on the substrate 100. The pixel circuit layer PCL can include a thin film transistor TFT and a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 114, a first planarization insulating layer 115, and a second planarization insulating layer 116 disposed below and / or above constituent elements of the thin film transistor TFT.

[0151] The buffer layer 111 can include an inorganic insulator such as silicon nitride, silicon oxynitride, and silicon oxide, and can be a single layer or a plurality of layers including the above-described inorganic insulator.

[0152] The thin film transistor TFT can include a semiconductor layer Act, and the semiconductor layer Act can include polycrystalline silicon. Alternatively, the semiconductor layer Act can include amorphous silicon, or an oxide semiconductor, or an organic semiconductor, etc. The semiconductor layer Act can include a channel region and a drain region and a source region respectively disposed on both sides of the channel region. A gate electrode GE can overlap the channel region.

[0153] The gate electrode GE can include a low-resistance metal material. The gate electrode GE can include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can be formed as a single layer or a plurality of layers including the material.

[0154] The first gate insulating layer 112 between the semiconductor layer Act and the gate electrode GE can include an inorganic insulator such as silicon oxide (SiO2), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0155] The second gate insulating layer 113 can be provided to cover the gate electrode GE. The second gate insulating layer 113 can include an inorganic insulator such as silicon oxide (SiO2), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc., similarly to the first gate insulating layer 112.

[0156] An upper electrode Cst2 of the storage capacitor Cst can be provided above the second gate insulating layer 113. The upper electrode Cst2 can overlap the gate electrode GE thereunder. At this time, the gate electrode GE and the upper electrode Cst2 overlapping with the second gate insulating layer 113 interposed therebetween can form the storage capacitor Cst. That is, the gate electrode GE can serve as a lower electrode Cst1 of the storage capacitor Cst.

[0157] In this way, the storage capacitor Cst and the thin film transistor TFT can be formed to overlap. In some embodiments, the storage capacitor Cst can also be formed not to overlap the thin film transistor TFT.

[0158] The upper electrode Cst2 can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and can be a single layer or multiple layers of the above-described substances.

[0159] The interlayer insulating layer 114 can cover the upper electrode Cst2. The interlayer insulating layer 114 can include silicon oxide (SiO2), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc. The interlayer insulating layer 114 can be a single layer or multiple layers including the above-described inorganic insulating substances.

[0160] The drain electrode DE and the source electrode SE can be respectively positioned on the interlayer insulating layer 114. The drain electrode DE and the source electrode SE can include a material having excellent conductivity. The drain electrode DE and the source electrode SE can include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can be formed to include multiple layers or a single layer of the material. As an embodiment, the drain electrode DE and the source electrode SE can have a multi-layer structure of Ti / Al / Ti.

[0161] The first planarization insulating layer 115 can be provided to cover the drain electrode DE and the source electrode SE. The first planarization insulating layer 115 can include an organic insulating layer. The first planarization insulating layer 115 can include a general-purpose high molecule such as polymethylmethacrylate (PMMA) or polystyrene (PS), an organic insulating substance such as a high molecule derivative having a phenol group, an acrylic high molecule, an imide high molecule, an aryl ether high molecule, an amide high molecule, a fluorine high molecule, a p-xylene high molecule, a vinyl alcohol high molecule, and a mixture thereof, etc.

[0162] The connection electrode CM can be disposed on the first planarization insulating layer 115. At this time, the connection electrode CM can be connected with the drain electrode DE or the source electrode SE through a contact hole of the first planarization insulating layer 115. The connection electrode CM can include a material having excellent conductivity. The connection electrode CM can include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and can be formed as a single layer or a plurality of layers including the material. As an embodiment, the connection electrode CM can have a multi-layer structure of Ti / Al / Ti.

[0163] The second planarization insulating layer 116 can be disposed to cover the connection electrode CM. The first planarization insulating layer 115 can include an organic insulating layer. The second planarization insulating layer 116 can include a general-purpose polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), an organic insulating material such as a polymer derivative having a phenol group, an enoic acid-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a mixture thereof.

[0164] The display element layer DEL can be disposed on the pixel circuit layer PCL. The display element layer DEL can include an organic light emitting diode OLED, and a pixel electrode 211 of the organic light emitting diode OLED can be electrically connected with the connection electrode CM through a contact hole of the second planarization insulating layer 116.

[0165] The pixel P can include an organic light emitting diode OLED and a thin film transistor TFT. For example, each pixel P can emit red, green, or blue light, or emit red, green, blue, or white light through the organic light emitting diode OLED.

[0166] The pixel electrode 211 can include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). As another example, the pixel electrode 211 can include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. As yet another example, the pixel electrode 211 can further include a film formed of ITO, IZO, ZnO, or In2O3 above / below the reflective film described above.

[0167] The pixel electrode 211 can be configured with a pixel definition film 118 having an opening 118OP exposing a central portion of the pixel electrode 211. The pixel definition film 118 can include an organic insulator and / or an inorganic insulator. The opening 118OP can define a light emitting area EA (hereinafter, referred to as a light emitting area) of light emitted from the organic light emitting diode OLED. For example, the width of the opening 118OP can correspond to the width of the light emitting area EA.

[0168] The pixel definition film 118 can be configured with a spacer 119. The spacer 119 can be used to prevent breakage of the substrate 100 in a manufacturing method of manufacturing a display device. In the case of the method of manufacturing a display device, a mask sheet can be used, at this time, the mask sheet enters inside the opening 118OP of the pixel definition film 118 or is attached to the pixel definition film 118, so that the mask sheet can prevent a bad phenomenon of damage or breakage of a portion of the substrate 100 when evaporating a material on the substrate 100.

[0169] The spacer 119 can include an organic insulator such as polyimide. Alternatively, the spacer 119 can include an inorganic insulator such as silicon nitride (SiN X ) or silicon oxide (SiO2), or can include an organic insulator and an inorganic insulator.

[0170] In one embodiment, the spacer 119 can include a different substance from the pixel defining film 118. Alternatively, in another embodiment, the spacer 119 can include the same substance as the pixel defining film 118, in which case the pixel defining film 118 and the spacer 119 can be formed together in a mask process using a half-tone mask or the like. Hereinafter, a case where the pixel defining film 118 and the spacer 119 include an organic insulator will be described in detail as a focus.

[0171] The intermediate layer 212 can be provided on the pixel defining film 118. The intermediate layer 212 can include a light emitting layer 212b provided in the opening 118OP of the pixel defining film 118. The light emitting layer 212b can include a high molecular or low molecular organic substance that emits light of a predetermined color.

[0172] A first functional layer 212a and a second functional layer 212c can be provided below and above the light emitting layer 212b, respectively. The first functional layer 212a can include a hole transport layer (HTL), or can include a hole transport layer and a hole injection layer (HIL), for example. The second functional layer 212c is optional as a constituent element provided above the light emitting layer 212b. The second functional layer 212c can include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 212a and / or the second functional layer 212c can be a common layer formed to cover the substrate 100 as a whole, like the counter electrode 213 to be described later.

[0173] The counter electrode 213 can be composed of a conductive substance having a low work function. For example, the counter electrode 213 can include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof, or the like. Alternatively, the counter electrode 213 can further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the above-described substance.

[0174] In some embodiments, a capping layer (not shown) can be further provided on the counter electrode 213. The capping layer can include LiF, an inorganic substance, and / or an organic substance.

[0175] A thin film encapsulation layer TFE can be provided on the counter electrode 213. In one embodiment, the thin film encapsulation layer TFE includes at least one inorganic encapsulation layer and at least one organic encapsulation layer, in which caseFigure 7 The thin film encapsulation layer TFE includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330, which are sequentially stacked.

[0176] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include one or more inorganic substances among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 can include a substance of a polymer series. As a material of the polymer series, an acrylic resin, an epoxy resin, a polyimide, a polyethylene, and the like can be included. As an embodiment, the organic encapsulation layer 320 can include an acrylate.

[0177] The input sensing part TSL can be disposed on the thin film encapsulation layer TFE. Insulating layers and conductive layers can be alternately stacked in the input sensing part TSL. For example, the input sensing part TSL can include a first conductive layer CML1 and a second conductive layer CML2. At this time, it can be that a first touch insulating layer 43 is disposed between the first conductive layer CML1 and the second conductive layer CML2, and a second touch insulating layer 45 is disposed on the second conductive layer CML2. Referring to Figure 3 Each of the first sensing electrode 410, the first connection electrode 411, the second sensing electrode 420, and the second connection electrode 421 described above can be included in one of the first conductive layer CML1 or the second conductive layer CML2.

[0178] Figure 8 is a cross-sectional view taken along the B-B' line of Figure 6 is a cross-sectional view taken along the C-C' line of Figure 9 is a cross-sectional view taken along the C-C' line of Figure 6 Referring to

[0179] and Figure 8 , the circuit part CP, the valley part VP, the second voltage wiring part WP2, and the dam part DAM can be disposed in the non-display area NDA. Figure 9 The circuit part CP can be separated into a first circuit part and a second circuit part by the valley part VP. The first circuit part can include at least one first thin film transistor CP1-TFT, and the second circuit part can include at least one second thin film transistor CP2-TFT.

[0180] The first internal insulating layer 115A, the second internal insulating layer 116A, and the internal layer 118A can be disposed on the first thin film transistor CP1-TFT. The first internal insulating layer 115A can include the same material as the first planarization insulating layer 115 (refer to

[0181] Figure 7 ​) the same substance as the first planarization insulating layer 115 (refer to Figure 7 ) and can be formed at the same time as the second planarization insulating layer 116 (refer to Figure 7 ) the same substance as the second planarization insulating layer 116 (refer to Figure 7 ) and can be formed at the same time as the second planarization insulating layer 116 (refer to

[0182] A first connection conductive layer CL1 having a plurality of first holes H1 can be disposed between the first internal insulating layer 115A and the second internal insulating layer 116A. In an embodiment, the first connection conductive layer CL1 can extend from the first thin film transistor CP1-TFT to the second thin film transistor CP2-TFT. The first connection conductive layer CL1 can include the same substance as the connection electrode CM (refer to Figure 7 ) and can be formed at the same time as the connection electrode CM (refer to Figure 7 ). The plurality of first holes H1 can become a passage for discharging gas generated from the first internal insulating layer 115A at the time of manufacturing the display device. Thus, it is possible to prevent or reduce the problem that the gas generated from the first internal insulating layer 115A penetrates into the display area to degrade the quality of an image realized in the display area. In some embodiments, the first connection conductive layer CL1 can be omitted.

[0183] A second connection conductive layer CL2 can be disposed on the second internal insulating layer 116A. The second connection conductive layer CL2 can have a plurality of second holes H2. In an embodiment, the plurality of second holes H2 can be disposed to be spaced apart from the plurality of first holes H1. In addition, the second connection conductive layer CL2 can extend from the first thin film transistor CP1-TFT to the second thin film transistor CP2-TFT.

[0184] The second connection conductive layer CL2 can include the same substance as the pixel electrode 211 (refer to Figure 7 ) and can be formed at the same time as the pixel electrode 211 (refer to Figure 7 ). The plurality of second holes H2 can become a passage for discharging gas generated from the first internal insulating layer 115A and / or the second internal insulating layer 116A at the time of manufacturing the display device. Thus, it is possible to prevent or reduce the problem that the gas generated from the first internal insulating layer 115A and / or the second internal insulating layer 116A penetrates into the display area to degrade the quality of an image realized in the display area.

[0185] In this embodiment, the internal layer 118A can include a plurality of island portions IP on the second internal insulating layer 116A. At this time, the plurality of island portions IP can be configured to be spaced apart from each other and can correspond to the plurality of second holes H2, respectively. Accordingly, the plurality of island portions IP can be configured to fill the plurality of second holes H2. The plurality of island portions IP can prevent deterioration of the side surface of the second connection conductive layer CL2 exposed by the plurality of second holes H2. For example, when the second connection conductive layer CL2 has a multi-layer structure of ITO / Ag / ITO, the Ag layer can be exposed by the second hole H2. In this case, the ITO layer and the Ag layer can be etched according to a subsequent process of manufacturing the display device, and the degree of etching of the Ag layer is greater than that of the ITO layer, and thus more of the Ag layer is etched. In this embodiment, since the plurality of island portions IP are configured to fill the plurality of second holes H2, these problems can be prevented.

[0186] The first external insulating layer 115B, the second external insulating layer 116B, and the external layer 118B can be configured on the second thin film transistor CP2-TFT. The first external insulating layer 115B can include the same substance as the first internal insulating layer 115A and can be formed at the same time as the first internal insulating layer 115A. The second external insulating layer 116B can include the same substance as the second internal insulating layer 116A and can be formed at the same time as the second internal insulating layer 116A.

[0187] The first connection conductive layer CL1 having a plurality of first holes H1 can be configured between the first external insulating layer 115B and the second external insulating layer 116B. In an embodiment, the first connection conductive layer CL1 can extend from the second thin film transistor CP2-TFT to the second voltage wiring portion WP2. The plurality of first holes H1 can become a passage for discharging gas generated from the first external insulating layer 115B at the time of manufacturing the display device.

[0188] The second connection conductive layer CL2 can be configured on the second external insulating layer 116B. In addition, in an embodiment, the second connection conductive layer CL2 can extend from the second thin film transistor CP2-TFT to the second voltage wiring portion WP2.

[0189] The plurality of second holes H2 can become a passage for discharging gas generated from the first external insulating layer 115B and / or the second external insulating layer 116B at the time of manufacturing the display device.

[0190] In the present embodiment, the outer layer 118B can have at least one groove VH extending in the first direction (for example, the y direction). That is, the outer layer 118B can have at least one groove VH extending in correspondence with the virtual boundary line of the non-display region NDA. In this case, the outer layer 118B can be separated into a plurality of pattern portions by the at least one groove VH. For example, when the outer layer 118B has a first groove VH1 and a second groove VH2, the outer layer 118B can be separated into a first pattern portion 118B-1, a second pattern portion 118B-2, and a third pattern portion 118B-3 by the first groove VH1 and the second groove VH2. Since the outer layer 118B described above is formed at the same time as the pixel definition film is formed, the outer layer 118B described above can be formed without adding a mask used when the display device is manufactured.

[0191] The plurality of pattern portions can be arranged in correspondence with the plurality of second holes H2. For example, the first pattern portion 118B-1, the second pattern portion 118B-2, and the third pattern portion 118B-3 can be arranged in correspondence with the second holes H2, respectively, and can be arranged to fill the second holes H2. The plurality of pattern portions can prevent the side surface of the second connection conductive layer CL2 exposed by the plurality of second holes H2 from deteriorating.

[0192] In the present embodiment, the valley portion VP can separate the inner layer 118A and the outer layer 118B. In addition, the valley portion VP can separate the first inner insulating layer 115A and the first outer insulating layer 115B, and can separate the second inner insulating layer 116A and the second outer insulating layer 116B. Therefore, it is possible to prevent moisture or foreign matter generated from a region arranged outside the valley portion VP of the non-display region NDA from penetrating into the display region DA through the organic insulating layer.

[0193] The second voltage wiring portion WP2 can be arranged to surround the valley portion VP, and the second thin film transistor CP2-TFT can be arranged between the second voltage wiring portion WP2 and the valley portion VP. The second voltage wiring portion WP2 can include a wiring WL. In an embodiment, the first connection conductive layer CL1 and the second connection conductive layer CL2 can overlap the wiring WL, and the wiring WL, the first connection conductive layer CL1, and the second connection conductive layer CL2 can be electrically connected. Therefore, the first connection conductive layer CL1 and the second connection conductive layer CL2 can transmit the second power supply voltage ELVSS (refer to FIG. 1) applied to the wiring WL. Figure 5a ) to the wiring WL.

[0194] The wiring WL can include the same substance as the drain electrode DE (refer to Figure 7 ) or the source electrode SE (refer to Figure 7 ), and can be electrically connected to the drain electrode DE (refer to Figure 7 ) or the source electrode SE (refer toFigure 7 ) simultaneously formed.

[0195] In the present embodiment, the dam portion DAM can prevent overflow of the organic encapsulation layer 320. At this time, the dam portion DAM can include at least one dam. The dam portion DAM can be configured to surround the valley portion VP. That is, the dam portion DAM can be configured outside the valley portion VP. In an embodiment, the dam portion DAM can be configured to overlap at least a portion of the wiring WL. Accordingly, a phenomenon in which an end portion of the wiring WL is deteriorated due to a subsequent process can be prevented.

[0196] The dam portion DAM can include at least one of a first portion 115C, a second portion 116C, a third portion 118C, and a fourth portion 119C. At this time, the first portion 115C can include the same substance as the first inner insulating layer 115A or the first outer insulating layer 115B, and can be simultaneously formed with the first inner insulating layer 115A or the first outer insulating layer 115B. The second portion 116C can include the same substance as the second inner insulating layer 116A or the second outer insulating layer 116B, and can be simultaneously formed with the second inner insulating layer 116A or the second outer insulating layer 116B. The third portion 118C can include the same substance as the inner layer 118A or the outer layer 118B, and can be simultaneously formed with the inner layer 118A or the outer layer 118B. The fourth portion 119C can include the same substance as the spacer 119 (refer to Figure 7 ) and can be simultaneously formed with the spacer 119 (refer to Figure 7 ).

[0197] In an embodiment, the functional layer 212-1 including the first functional layer and the second functional layer, and the counter electrode 213 can be configured to extend to the non-display area NDA. For example, the functional layer 212-1 and the counter electrode 213 can cover the inner layer 118A and the valley portion VP, and can cover a portion of the outer layer 118B. As another example, the functional layer 212-1 and the counter electrode 213 can cover the inner layer 118A and a portion of the valley portion VP. As still another example, the functional layer 212-1 and the counter electrode 213 can be configured only on the inner layer 118A.

[0198] The thin film encapsulation layer TFE sealing the display area DA can extend to the valley portion VP. In particular, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can extend to the dam portion DAM. The organic encapsulation layer 320 can be configured to fill the valley portion VP.

[0199] The input sensing portion can be configured on the thin film encapsulation layer TFE. The input sensing portion can include a first touch insulating layer 43, a touch wiring TW, and a second touch insulating layer 45. At this time, the touch wiring TW can be Figure 3at least one of the first traces (415-1 to 415-4) and the second traces (425-1 to 425-5).

[0200] Like the first inorganic encapsulation layer 310 or the second inorganic encapsulation layer 330, the first touch insulating layer 43 and the second touch insulating layer 45 can extend to the dam portion DAM of the non-display area NDA. In one aspect, the touch wiring TW can be configured to correspond to the first circuit portion or the valley portion VP.

[0201] In the present embodiment, at least one groove VH of the external layer 118B can be used to prevent overflow of the organic encapsulation layer 320 and can be used to check overflow of the organic encapsulation layer 320 in the manufacturing of the display device. If it is a case where the organic encapsulation layer 320 does not sufficiently fill the valley portion VP, a part of the touch wiring TW can not be configured in the same plane as the other part of the touch wiring TW. If the touch wiring TW is not configured in the same plane, a characteristic of the input sensing portion can be degraded, and a short circuit can occur between the touch wiring TW. If it is a case where the organic encapsulation layer 320 fills all of the valley portions VP but overflows in the direction from the valley portion VP to the dam portion DAM, moisture or foreign substances can be propagated inside the display area DA due to the organic encapsulation layer 320, thereby causing a decrease in reliability of the display device. Therefore, it is important to form the organic encapsulation layer 320 in an appropriate amount.

[0202] Unlike the present embodiment, if the plurality of island portions IP are also configured on the second circuit portion, like the first circuit portion, it is not possible to check whether the organic encapsulation layer 320 overflows the valley portion VP. However, at least one groove VH of the present embodiment can be configured to extend in the first direction (for example, the y direction) on the second circuit portion. Therefore, if the organic encapsulation layer 320 overflows the valley portion VP when the organic encapsulation layer 320 is formed, at least one groove VH can be filled. In this case, it is possible to check whether the organic encapsulation layer 320 overflows by checking at least one groove VH. Thereby, it is possible to form the organic encapsulation layer 320 in an appropriate amount, and the reliability of the display device can be improved.

[0203] In addition, at least one groove VH can be configured on the circuit portion CP. Thereby, it is possible to reduce the area of the non-display area NDA to enlarge the display area DA. For example, if at least one groove VH is not configured on the circuit portion CP, the area occupied by the non-display area NDA in the display device can increase. In addition, in a case where a part of the thin film transistor that drives a pixel includes an oxide semiconductor, the area occupied by the circuit portion CP in the non-display area NDA can further expand. In the case of the present embodiment, since at least one groove VH is configured on the circuit portion CP while functioning as a dam, the area of the entire non-display area NDA can be reduced.

[0204] Figure 10 is a cross-sectional view taken along a D-D' line in Figure 6 . In Figure 10 , the same reference characters denote the same parts, and repetitive explanation will be omitted. Figure 8 Figure 9

[0205] Referring to Figure 10 , the valley portion VP, the second voltage wiring portion WP2, and the dam portion DAM can be arranged in the non-display region NDA.

[0206] The valley portion VP can separate the inner layer 118A and the outer layer 118B. In addition, the valley portion VP can separate the first inner insulating layer 115A and the first outer insulating layer 115B, and can separate the second inner insulating layer 116A and the second outer insulating layer 116B. Thus, penetration of moisture or foreign matter generated in a region outside the valley portion VP arranged in the non-display region NDA toward the display region DA can be prevented.

[0207] The first inner insulating layer 115A, the second inner insulating layer 116A, and the inner layer 118A can be stacked on the non-display region NDA, and in an embodiment, the first circuit portion can not be arranged between the substrate 100 and the first inner insulating layer 115A. The first outer insulating layer 115B, the second outer insulating layer 116B, and the outer layer 118B can be stacked on the non-display region NDA, and in an embodiment, the second circuit portion can not be arranged between the substrate 100 and the first outer insulating layer 115B.

[0208] In the present embodiment, the dam portion DAM can include a plurality of dams. For example, the dam portion DAM can include a first dam DAM1 and a second dam DAM2 arranged side by side with each other. At this time, the first dam DAM1 and the second dam DAM2 can extend in the second direction (for example, the x direction). Specifically, the first dam DAM1 and the second dam DAM2 can be arranged outside the valley portion VP between the first valley region VA1 (refer to Figure 6 ) and the second valley region VA2 (refer to Figure 6 ). That is, the circuit portion CP (refer to Figure 6 ) can be arranged outside at least any one of the first valley region VA1 (refer to Figure 6 ) and the second valley region VA2 (refer to Figure 6 ), and the first dam DAM1 and the second dam DAM2 can be arranged outside at least any one of the third valley region VA3 (refer to Figure 6 ) and the fourth valley region VA4 (refer to Figure 6 ). Thus, in the present embodiment, the first dam DAM1 and the second dam DAM2 can be arranged outside the third valley region VA3 (refer to Figure 6 ​​) and the second valley region VA2 (refer to Figure 6 ) can be provided with one dam, and the third valley region VA3 (refer to Figure 6 ) and the fourth valley region VA4 (refer to Figure 6 ) can be provided with a plurality of dams. At this time, the dam provided at the outer side of at least any one of the first valley region VA1 (refer to Figure 6 ) and the second valley region VA2 (refer to Figure 6 ) can be connected to the plurality of dams provided at the outer side of at least any one of the third valley region VA3 (refer to Figure 6 ) and the fourth valley region VA4 (refer to Figure 6 ).

[0209] In an embodiment, the first dam DAM1 can include a first inner portion 116D1 and a second inner portion 118D1 on the first inner portion 116D1. The first inner portion 116D1 can include the same material as the second inner insulating layer 116A or the second outer insulating layer 116B, and can be formed at the same time as the second inner insulating layer 116A or the second outer insulating layer 116B. The second inner portion 118D1 can include the same material as the inner layer 118A or the outer layer 118B, and can be formed at the same time as the inner layer 118A or the outer layer 118B.

[0210] In an embodiment, the second dam DAM2 can include at least one of a first outer portion 115D2, a second outer portion 116D2, a third outer portion 118D2, and a fourth outer portion 119D2. At this time, the first outer portion 115D2 can include the same material as the first inner insulating layer 115A or the first outer insulating layer 115B, and can be formed at the same time as the first inner insulating layer 115A or the first outer insulating layer 115B. The second outer portion 116D2 can include the same material as the second inner insulating layer 116A or the second outer insulating layer 116B, and can be formed at the same time as the second inner insulating layer 116A or the second outer insulating layer 116B. The third outer portion 118D2 can include the same material as the inner layer 118A or the outer layer 118B, and can be formed at the same time as the inner layer 118A or the outer layer 118B. The fourth outer portion 119D2 can include the same material as the spacer 119 (refer to Figure 7 ), and can be formed at the same time as the spacer 119 (refer to Figure 7 ).

[0211] The thin film encapsulation layer TFE sealing the display area DA can extend to the valley portion VP. In particular, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can extend to the second dam DAM2. The organic encapsulation layer 320 can be configured to fill the valley portion VP. Like the first inorganic encapsulation layer 310 or the second inorganic encapsulation layer 330, the first touch insulating layer 43 and the second touch insulating layer 45 of the input sensing portion can extend to the second dam DAM2 of the non-display area NDA.

[0212] Figure 11 FIG. 31 is a cross-sectional view schematically illustrating a portion of a non-display area NDA according to another embodiment of the present application.

[0213] Referring to Figure 11 , the display panel can include a substrate including a display area and a non-display area, a circuit portion configured on the non-display area and including a first circuit portion and a second circuit portion, a valley portion separating the first circuit portion and the second circuit portion, and a thin film encapsulation layer TFE sealing the display area and extending from the display area to the valley portion.

[0214] The second circuit portion can include at least one second thin film transistor CP2-TFT, and an external layer 118B having at least one groove VH extending in the first direction can be configured on the second thin film transistor CP2-TFT. At this time, the external layer 118B can include the same substance as the pixel definition film.

[0215] In the present embodiment, an upper external layer 119B can be configured on the external layer 118B. The upper external layer 119B can include the same substance as the spacer 119 (refer to Figure 7 ) and can be formed at the same time as the spacer 119 (refer to Figure 7 ).

[0216] The upper external layer 119B can include a plurality of upper pattern portions spaced apart from each other. For example, the upper external layer 119B can include a first upper pattern portion 119B-1, a second upper pattern portion 119B-2, and a third upper pattern portion 119B-3 spaced apart from each other. At this time, the first upper pattern portion 119B-1, the second upper pattern portion 119B-2, and the third upper pattern portion 119B-3 can be respectively configured on the first pattern portion 118B-1, the second pattern portion 118B-2, and the third pattern portion 118B-3.

[0217] In the present embodiment, since the upper external layer 119B is further configured on the external layer 118B, the depth of the at least one groove VH can be deepened.

[0218] Figure 12is a cross-sectional view schematically illustrating a portion of a non-display area NDA according to yet another embodiment of the present application. Figure 13 is a cross-sectional view schematically illustrating a portion of a non-display area NDA according to yet another embodiment of the present application.

[0219] Referring to Figure 12 and Figure 13 The display panel can include a substrate including a display area and a non-display area, a circuit portion disposed on the non-display area and including a first circuit portion and a second circuit portion, a valley portion separating the first circuit portion and the second circuit portion, and a thin film encapsulation layer TFE sealing the display area and extending from the display area to the valley portion.

[0220] The second circuit portion can include at least one second thin film transistor CP2-TFT, and an external layer 118B having at least one groove VH extending in the first direction can be disposed on the second thin film transistor CP2-TFT. At this time, the external layer 118B can include the same substance as the pixel definition film.

[0221] Referring to Figure 12 A third external insulating layer 117B can be further disposed between the second external insulating layer 116B and the external layer 118B. The third external insulating layer 117B can include an organic insulating layer. The third external insulating layer 117B can include a general-purpose polymer such as Polymethylmethacrylate (PMMA) or Polystyrene (PS), an organic insulating material such as a phenol-based polymer derivative, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and a mixture thereof.

[0222] A third connection conductive layer CL3 having a plurality of third holes H3 can be disposed between the third external insulating layer 117B and the second external insulating layer 116B. In an embodiment, the third connection conductive layer CL3 can extend from the first thin film transistor to the second thin film transistor CP2-TFT. The third connection conductive layer CL3 can include a material having excellent conductivity. The third connection conductive layer CL3 can include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and can be formed as a single layer or a plurality of layers including the material. As an embodiment, the third connection conductive layer CL3 can have a multi-layer structure of Ti / Al / Ti. The plurality of third holes H3 can become a passage for discharging gas generated from the second external insulating layer 116B when manufacturing the display device. In some embodiments, the third connection conductive layer CL3 can be omitted.

[0223] Referring to Figure 13 A first external insulating layer 115B can be disposed between the second thin film transistor CP2-TFT and the external layer 118B. At this time, the second external insulating layer 116B and the first connection conductive layer CL1 can be omitted compared to Figure 8 Thus, the organic insulating layer can be stacked on the second thin film transistor CP2-TFT by various methods.

[0224] Figure 14 is a cross-sectional view taken along a D-D' line of FIG. 1 according to still another embodiment of the present application. In Figure 6 the same reference numerals are used to refer to the same components as those of Figure 14 the same reference numerals are used to refer to the same components as those of Figure 10 the same reference numerals are used to refer to the same components as those of

[0225] Referring to Figure 14 The display panel can include a substrate including a display area and a non-display area, a circuit portion disposed on the non-display area and including a first circuit portion and a second circuit portion, a valley portion separating the first circuit portion and the second circuit portion, and a thin film encapsulation layer TFE sealing the display area and extending from the display area to the valley portion.

[0226] The second circuit portion can include at least one second thin film transistor CP2-TFT, and an external layer 118B having at least one groove VH extending in a first direction can be disposed on the second thin film transistor CP2-TFT. At this time, the external layer 118B can include the same substance as a pixel definition film.

[0227] The valley portion VP can separate the internal layer 118A and the external layer 118B. In addition, the valley portion VP can separate the first internal insulating layer 115A and the first external insulating layer 115B, and can separate the second internal insulating layer 116A and the second external insulating layer 116B. Thus, penetration of moisture or foreign matter generated from an area outside the valley portion VP disposed in the non-display area NDA to the display area DA can be prevented.

[0228] The first internal insulating layer 115A, the second internal insulating layer 116A, and the internal layer 118A can be stacked on the non-display area NDA, and in an embodiment, the first circuit portion can not be disposed between the substrate 100 and the first internal insulating layer 115A. The first external insulating layer 115B, the second external insulating layer 116B, and the external layer 118B can be stacked on the non-display area NDA, and in an embodiment, the second circuit portion can not be disposed between the substrate 100 and the first external insulating layer 115B.

[0229] In this embodiment, at least one groove VH of the outer layer 118B can be configured to surround the valley VP. Specifically, at least one groove VH of the outer layer 118B can be configured to extend along a second direction (e.g., the x-direction). That is, at least one groove VH of the outer layer 118B can be configured in the third valley region VA3 (refer to...). Figure 6 The outer side of the outer layer 118B. In this case, the outer layer 118B can be separated into multiple patterned portions by at least one groove VH. For example, when the outer layer 118B has a third groove VH3 and a fourth groove VH4, the outer layer 118B can be separated into a fourth patterned portion 118B-4, a fifth patterned portion 118B-5, and a sixth patterned portion 118B-6 by the third groove VH3 and the fourth groove VH4. In this case, Figure 14 The third groove VH3, the fourth groove VH4, the fourth pattern part 118B-4, the fifth pattern part 118B-5, and the sixth pattern part 118B-6 are respectively with Figure 8 The first groove VH1, the second groove VH2, the first pattern part 118B-1, the second pattern part 118B-2, and the third pattern part 118B-3 are similar, and detailed descriptions will be omitted.

[0230] The dam section DAM-1 may include at least one of the following: a first part 115D-1, a second part 116D-1, a third part 118D-1, and a fourth part 119D-1. In this case, the dam section DAM-1, the first part 115D-1, the second part 116D-1, the third part 118D-1, and the fourth part 119D-1 are respectively connected with... Figure 8 The dam section DAM, Part 1 115C, Part 2 116C, Part 3 118C, and Part 4 119C are similar, and detailed descriptions will be omitted.

[0231] In this embodiment, the outer layer 118B may also have at least one recess VH in the area where no circuitry is configured. In this case, since the dam section DAM-1 can be configured as a dam, the area of ​​the non-display area NDA can be reduced.

[0232] As described above, the present invention has been illustrated with reference to one embodiment shown in the accompanying drawings, but this is merely exemplary, and it will be understood by those skilled in the art that various modifications and variations of the embodiments can be made therefrom. Therefore, the true scope of protection of the present invention should be determined by the technical concept of the appended claims.

Claims

1. A display device, wherein, include: The substrate includes a display area and a non-display area; A circuit section is disposed on the non-display area and includes a first circuit section and a second circuit section; Valley section, separating the first circuit section and the second circuit section; as well as A thin-film encapsulation layer seals the display area and extends from the display area to the valley. The first circuit section is disposed between the valley and the display area, and the second circuit section is disposed outside the valley. The inner layer disposed on the first circuit portion includes a plurality of grooves extending in a first direction and a second direction intersecting the first direction, and a plurality of island-shaped portions including respective upper surfaces spaced apart from each other along the first direction and the second direction. The outer layer disposed on the second circuit portion has at least one groove extending in the first direction, and includes a plurality of pattern portions separated by the at least one groove. The planar area of ​​the upper surface of one of the multiple patterned portions is larger than the planar area of ​​the upper surface of one of the multiple island portions.

2. The display device according to claim 1, wherein, The display area is provided with display elements including pixel electrodes and counter electrodes. A conductive layer, comprising the same material as the pixel electrode, extends from the first circuit section to the second circuit section. The conductive layer includes multiple holes.

3. The display device according to claim 2, wherein, The outer layer covers the plurality of holes.

4. The display device according to claim 2, wherein, The outer layer is separated into multiple patterned portions by the at least one groove. The plurality of patterned portions cover the plurality of holes.

5. The display device according to claim 2, wherein, The outer layer defines the light-emitting area of ​​the display element and includes the same material as the pixel-defining film covering the ends of the pixel electrodes. An upper outer layer is also disposed on the outer layer.

6. The display device according to claim 1, wherein, The inner layer and the outer layer are separated by the valley.

7. The display device according to claim 1, wherein, A first external insulating layer covering the second circuit section is disposed between the second circuit section and the outer layer.

8. The display device according to claim 7, wherein, A second outer insulating layer is disposed between the first outer insulating layer and the outer layer.

9. The display device according to claim 8, wherein, A third outer insulating layer is disposed between the second outer insulating layer and the outer layer.

10. The display device according to claim 1, wherein, The display device further includes a dam section surrounding the valley section.

11. The display device according to claim 10, wherein, The dam section includes multiple dams. The plurality of dams are configured to extend in the second direction.

12. The display device according to claim 1, wherein, The valley is surrounded by at least one groove in the outer layer.

13. The display device according to claim 1, wherein, The thin-film encapsulation layer includes at least one inorganic encapsulation layer and at least one organic encapsulation layer.

14. The display device according to claim 1, wherein, The display device further includes an input sensing unit on the thin-film encapsulation layer.

15. The display device according to claim 14, wherein, The input sensing unit includes touch wiring on the non-display area.

16. A display device, wherein, include: The substrate includes a display area and a non-display area; The valley is configured to surround the display area over the non-display area and includes a first valley area and a second valley area facing each other. A first circuit section is disposed inside at least one of the first valley region and the second valley region and extends in a first direction; The second circuit section is disposed on the outside of at least one of the first valley region and the second valley region, and extends in the first direction; The outer layer has at least one groove extending along the first direction on the second circuit portion, and includes a plurality of pattern portions separated by the at least one groove; An inner layer is disposed on the first circuit portion and includes a plurality of grooves extending in the first direction and a second direction intersecting the first direction, and a plurality of island portions including respective upper surfaces spaced apart from each other along the first direction and the second direction. Multiple dams are disposed outside the valley between the first valley region and the second valley region in the valley and extend in a second direction intersecting the first direction; as well as A thin-film encapsulation layer seals the display area and extends into the non-display area. The planar area of ​​the upper surface of one of the multiple patterned portions is larger than the planar area of ​​the upper surface of one of the multiple island portions.

17. The display device according to claim 16, wherein, The display area is provided with display elements including pixel electrodes and counter electrodes. A conductive layer comprising the same material as the pixel electrode is disposed on the circuit section. The conductive layer includes multiple holes.

18. The display device according to claim 17, wherein, The outer layer covers the plurality of holes.

19. The display device according to claim 17, wherein, The outer layer is separated into multiple patterned sections by the at least one groove.

20. The display device according to claim 19, wherein, The plurality of patterned portions cover the plurality of holes.

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