Elastic Neural Network

Abstract

A spiking neural network for classifying input signals is disclosed. The spiking neural network includes a plurality of spiking neurons and a plurality of synaptic elements that interconnect them to form a network. Each synaptic element receives a synaptic input signal and applies a weight to generate a synaptic output signal, and the synaptic element is configurable to adjust the weight applied by each synaptic element. Each spiking neuron is adapted to receive the synaptic output signal from the synaptic element and generate a spatio-temporal spike train output signal in response thereto. The spiking neural network is divided into a plurality of sub-networks, which include a subset of spiking neurons connected to receive the synaptic output signal from a subset of synaptic elements. The sub-network is adapted to generate a sub-network output pattern signal in response to a sub-network input pattern signal. In addition, each sub-network forms part of one or more cores in a core array, and each core consists of a programmable network of spiking neurons implemented in hardware or a combination of hardware and software. Communication between cores in the core array is arranged through a programmable interconnect structure.

Description

Technical Field

[0001] The present disclosure generally relates to automatic signal recognition technology, and more particularly, to systems and methods for a hardware resilient deep learning inference accelerator using spiking neurons. Background Art

[0002] Automatic signal recognition (ASR) refers to recognizing a signal by identifying its constituent features. ASR is utilized in a range of applications, for example, recognizing a speaker's speech and uttered words in a speech / sound recognition system, recognizing arrhythmias in an electrocardiogram (ECG) to determine the shape of a gesture in an action-controlled system, and so on. ASR typically performs by characterizing patterns present in short samples of the input signal, and thus an accurate pattern recognition function is crucial for an effective ASR system.

[0003] Measuring some physical quantities to derive the input signal for an ASR system may require fusing data from multiple types of sensors. For example, recognizing a gesture using a handheld input device may require fusing data from an accelerometer (for measuring motion) and data from a gyroscope (for measuring orientation). By combining data from the two sensors, gestures in three-dimensional space can be detected.

[0004] Generally, data fusion refers to the integration of data collected from different and potentially heterogeneous sources in order to reduce the uncertainty in the interpretation of data from those individual sources. Importantly, during the fusion process, the fundamental features in different input signals are fully represented in the fused signal.

[0005] Pattern recognition and fusion are typically performed using a microprocessor and / or a digital signal processor, both of which implement a stored program architecture. For the analysis of streaming data, this architecture is inherently inefficient. On a single processor, patterns are sequentially extracted and recognized. This is because pattern extraction and recognition are implemented according to a general and simple instruction set (such as a RISC or CISC instruction set), resulting in a long execution sequence for each pattern in the signal sample. Complex patterns in the input signal require the use of more complex signal processing algorithms, and in systems that require a real-time response from the pattern recognition engine, a higher clock frequency further needs to be used for the processor. This is not feasible in power-constrained devices (such as portable electronic devices, wearable devices, etc.). In addition, due to the sequential execution paradigm, the latency and power consumption of pattern recognition operations on a microprocessor increase significantly with the increase in pattern complexity and the library. The presence of noise in the input signal further increases the complexity of the analysis and adversely affects performance and efficiency.

[0006] Data fusion is a non-local operation for a microprocessor. This means that before input signals or data streams can be fused, their information content must first be extracted and then combined with corresponding content in other streams. Thus, in a microprocessor implementation, each input signal / data source for fusion is processed separately by an independent pattern recognition pipeline, and then different pattern recognition results are combined by a rule-based framework. This method requires multiple calls to the pattern recognition infrastructure for each input signal or data stream, resulting in increased power consumption. Additionally, the limitations of load-store architecture microprocessors and digital signal processors (DSPs) used for pattern recognition mean that as pattern complexity increases, the power consumption and latency cost of recognizing these patterns also increase. While the latency cost can be reduced by increasing the clock frequency, this comes at the expense of further increasing power consumption. Similarly, the quality of fusion is limited by the processing and complexity of ASR performed on the input signals, the number of signals being fused, and the computational capabilities of the microprocessor or DSP. The sequential nature of the processing reduces the throughput of fusion-based ASR, and thus, as the complexity of the signal patterns increases, the number of input signals that can be fused using a microprocessor or DSP decreases.

[0007] Artificial neural networks in the form of deep neural networks (DNNs) have been proposed to replace microprocessor implementations. DNNs form the basis for a large number of machine learning applications; starting from speech and image recognition, the number of applications leveraging DNNs has grown exponentially, but these applications have inherent limitations, mainly in processing large amounts of data or quickly adapting to changing environments.

[0008] Initially, hardware deep network accelerators have been implemented on standard synchronous digital logic. In the (usually) serial and time-division multiplexed processing of digital systems, the high-level parallelism of neural networks cannot be replicated; instead, computational primitives of hardware DNN emulators implemented as analog computing nodes (where memory and processing elements are co-located) offer significant improvements in speed, size, and power consumption.

[0009] In biological neural network models, each individual neuron communicates asynchronously and through sparse events or spikes. In such event-based spiking neural networks (SNNs), only neurons that change state generate spikes and may trigger signal processing in subsequent layers, thus saving computational resources. Spiking neural networks (SNNs) are a promising approach for implementing ASR for many different applications.

[0010] The SNN encodes information in the form of one or more precisely timed (voltage) pulses rather than in the form of integer or real-valued vectors. Computations for inference (i.e., inferring the presence of a certain feature in the input signal) are performed efficiently in the analog and time domains. Thus, SNNs are typically implemented in hardware as fully custom mixed-signal integrated circuits. In addition to having a smaller network size, this also enables them to perform the inference function with an energy consumption that is several orders of magnitude lower than that of their artificial neural network counterparts.

[0011] The SNN consists of a network of spiking neurons interconnected by synapses, which indicate the connection strength between the spiking neurons. This strength is represented as a weight, which modulates the effect of the output of the presynaptic neuron on the input of the postsynaptic neuron. Typically, these weights are set during a training process, which involves exposing the network to a large amount of labeled input data and then gradually adjusting the weights of the synapses until the desired network output is achieved.

[0012] Relying on the principle that amplitude-domain, time-domain, and frequency-domain features in the input signal can be encoded as a unique spatio-temporal encoded spike train, the SNN can be directly applied to pattern recognition and sensor data fusion.

[0013] The generation of these spike trains relies on the use of one or more ensembles of spiking neurons, where an ensemble is a collaborative group of neurons. Each ensemble performs a specific signal processing function, i.e., for example, feature encoding, conditioning, filtering, data fusion, classification. Each ensemble consists of one or more interconnected layers of spiking neurons, and the connectivity between and within these layers follows a specific topology. The size (number of neurons) of each ensemble, its connectivity (topology and number of synapses), and its configuration (weights and number of layers) depend on the characteristics of the input signal, such as dynamic range, bandwidth, time scale, or the complexity of the features in the input signal. Thus, the ensemble used in the case of a speech pattern matching system may be different from the one used in a handwritten recognition system.

[0014] Typically, as the complexity of the features to be recognized in the input signal increases, the size of the ensemble required to process them also increases. Spiking neural network hardware can utilize configurable arrays of spiking neurons and synapses, which are connected using programmable interconnect structures, thus facilitating the implementation of any arbitrary connection topology. However, to implement a larger ensemble, the underlying SNN hardware must have at least the required number of neurons and synapses.

[0015] Although the basic operations required for SNNs are very effectively implemented by analog electronic circuits, inevitable variations in microelectronic circuits due to the manufacturing process can cause distortion of their functional characteristics, such as resistance, capacitance, gain, time response, and so on. Especially in the case of smaller manufacturing process geometries and lower operating currents, these circuits are increasingly vulnerable to quantum effects and external noise, effectively reducing the signal-to-noise ratio and limiting the processing performance. These undesirable effects increase in large arrays where drivers, biases, encoder / decoder circuits are shared by a larger number of devices over longer interconnects. Summary of the Invention

[0016] To address the drawbacks of the prior art discussed above, according to a first aspect of the present disclosure, a spiking neural network for classifying input signals is proposed. The spiking neural network includes a plurality of spiking neurons and a plurality of synaptic elements that interconnect the spiking neurons to form a network, where each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, and the synaptic element is configurable to adjust the weight applied by each synaptic element. Each of the spiking neurons is adapted to receive one or more synaptic output signals from one or more synaptic elements and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals. The network is divided into a plurality of sub-networks, where each sub-network includes a subset of the spiking neurons that are connected to receive synaptic output signals from a subset of the synaptic elements. The sub-network is adapted to generate a sub-network output pattern signal in response to a sub-network input pattern signal applied to the sub-network. Additionally, each sub-network forms part of one or more cores in a core array, each core consisting of a programmable network of spiking neurons implemented in hardware or a combination of hardware and software, and communication between the cores in the core array is arranged through a programmable interconnect structure.

[0017] In an embodiment, the programmable interconnect structure includes a switch matrix.

[0018] In an embodiment, the switch matrix includes a plurality of routers adapted to route a plurality of output signals from a first core in the core array to a plurality of inputs of a second core in the core array.

[0019] In an embodiment, the programmable interconnect structure forms a packet-switched network between the cores in the core array. In an embodiment, the programmable interconnect structure uses address event representation. In an embodiment, the programmable interconnect structure uses synchronous or asynchronous communication. In an embodiment, the core array is implemented in an integrated circuit, and the programmable interconnect structure includes a network-on-chip.

[0020] In an embodiment, the network-on-chip is real-time configurable.

[0021] In an embodiment, a learning rule, weight storage mechanism, or communication protocol for a synaptic element is heterogeneously applied to a single core of a core array. In an embodiment, a learning rule, weight storage mechanism, or communication protocol for a synaptic element is heterogeneously applied to multiple cores in a core array. In an embodiment, a learning rule block is used to implement the learning rule configuration of one or more cores in a core array. In an embodiment, cores using the same learning rule use a common learning rule block that implements the learning rule.

[0022] In an embodiment, the distribution of the learning rule within each core and / or across cores in a core array is dynamically configurable at runtime.

[0023] In an embodiment, one of the sub-networks is part of a classifier for classifying an input signal of the sub-network.

[0024] In an embodiment, one of the sub-networks is part of a set of classifiers for classifying an input signal of the sub-network. In an embodiment, random weight updates are used to configure the weights of the synaptic elements.

[0025] In an embodiment, the weight of a synaptic element is bound by a binding value, where the binding value is a random value.

[0026] According to a second aspect of the present disclosure, an integrated circuit is disclosed that includes a spiking neural network implemented in the core array of the first aspect of the present disclosure.

[0027] According to a third aspect of the present disclosure, a method of partitioning and mapping a spiking neural network onto a core array is disclosed. Here, the spiking neural network includes a plurality of spiking neurons and a plurality of synaptic elements that interconnect the spiking neurons to form a network, where each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, the synaptic element is configurable to adjust the weight applied by each synaptic element, and where each of the spiking neurons is adapted to receive one or more synaptic output signals from one or more synaptic elements and, in response to the received one or more synaptic output signals, generate a spatio-temporal spike train output signal. Further, the core array includes a plurality of cores, where each core consists of a programmable network of spiking neurons implemented in hardware or a combination of hardware and software, and where communication between the cores in the core array is arranged through a programmable interconnect structure. Here, the method includes partitioning the network into a plurality of sub-networks, where each sub-network includes a subset of spiking neurons that are connected to receive synaptic output signals from a subset of synaptic elements. The sub-network is adapted to generate a sub-network output pattern signal from the subset of spiking neurons in response to a sub-network input pattern signal applied to the subset of synaptic elements, where each sub-network is mapped onto one or more cores.

[0028] In an embodiment, a mapping method is used to determine the partitioning of a spiking neural network into subnetworks implemented in one or more cores. The mapping method includes constraint-driven partitioning. The constraints are performance metrics linked to the functionality of each corresponding subnetwork.

[0029] According to a fourth aspect of the present disclosure, a spiking neural network is disclosed. The spiking neural network includes a plurality of spiking neurons implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements interconnecting the spiking neurons to form a network, wherein each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, the synaptic element being configurable to adjust the weight applied by each synaptic element, and wherein each of the spiking neurons is adapted to receive one or more synaptic output signals from one or more synaptic elements and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals. Further, learning rules, weight storage mechanisms, and / or communication protocols are applied heterogeneously on neurons and / or synaptic elements in the spiking neural network.

[0030] According to a fifth aspect of the present disclosure, a spiking neural network is disclosed, which includes spiking neurons and synaptic elements connected to the spiking neurons. Here, the synaptic element includes first and second receptors adapted to receive a synaptic input signal, wherein the first and second receptors generate first and second receptor signals respectively based on the synaptic input signal. The synaptic element applies a weight to the first receptor signal to generate a synaptic output signal, the synaptic element being configurable to adjust the weight applied by the synaptic element based at least on the second receptor signal. The spiking neuron is adapted to receive the synaptic output signal from the synaptic element and generate a spatio-temporal spike train output signal at least in response to the received synaptic output signal.

[0031] In an embodiment, the neuron issues a control signal, wherein the control signal, together with the second receptor signal, adjusts the weight applied by the synaptic element.

[0032] In an embodiment, the control signal is a backpropagation signal.

[0033] In an embodiment, the neuron includes dendrites, an axon, and a soma, wherein the control signal originates from the dendrites and / or axon and / or soma of the neuron.

[0034] In an embodiment, the control signal includes one or more spikes generated by action potentials in the neuron. In an embodiment, the decay time of the first receptor is faster than the decay time of the second receptor. In an embodiment, the first receptor generates a sink current or an absorption current for the spiking neuron.

[0035] In an embodiment, the first receptor includes a low-pass filter. In an embodiment, the second receptor forms a voltage-gated receptor. In an embodiment, the second receptor includes a low-pass filter, a band-pass filter, a high-pass filter, and / or an amplifier. In an embodiment, the first receptor is an AMPA receptor, or a GABA receptor, or an NMDA receptor.

[0036] According to a sixth aspect of the present disclosure, a method for adjusting the weight of a synaptic element in a spiking neural network is disclosed. The spiking neural network includes spiking neurons connected to the synaptic element. The synaptic element includes first and second receptors adapted to receive synaptic input signals, wherein the first and second receptors receive the synaptic input signals and generate first and second receptor signals respectively based on the synaptic input signals. The synaptic element applies a weight to the first receptor signal to generate a synaptic output signal. The weight of the synaptic element is adjusted based at least on the second receptor signal, and the spiking neuron receives the synaptic output signal from the synaptic element and generates a spatio-temporal spike train output signal at least in response to the received synaptic output signal.

[0037] In an embodiment, the neuron emits a control signal, wherein the control signal, together with the second receptor signal, adjusts the weight applied by the synaptic element.

[0038] In an embodiment, the control signal is a backpropagation signal.

[0039] In an embodiment, the neuron includes a dendrite, an axon, and a soma, wherein the control signal originates from the dendrite and / or axon and / or soma of the neuron.

[0040] In an embodiment, the control signal includes one or more spikes generated by action potentials in the neuron. In an embodiment, the decay time of the first receptor is faster than the decay time of the second receptor. In an embodiment, the first receptor generates a pulling current or an absorption current for the spiking neuron.

[0041] In an embodiment, the first receptor includes a low-pass filter. In an embodiment, the second receptor forms a voltage-gated receptor. In an embodiment, the second receptor includes a low-pass filter, a band-pass filter, a high-pass filter, and / or an amplifier. In an embodiment, the first receptor is an AMPA receptor, or a GABA receptor, or an NMDA receptor.

[0042] According to a seventh aspect of the present disclosure, an integrated circuit including the spiking neural network of the fifth aspect of the present disclosure is disclosed.

[0043] According to an eighth aspect of the present disclosure, a method for configuring a spiking neural network to reduce the influence of noise in the spiking neural network is disclosed. The spiking neural network includes a plurality of spiking neurons implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements that interconnect the spiking neurons to form a network. Each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, and the synaptic element is configurable to adjust the weight applied by each synaptic element. Each of the spiking neurons is adapted to receive one or more synaptic output signals from one or more synaptic elements and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals. The synaptic drive Γ of one of the spiking neurons i in the spiking neural network i is a time-dependent function that describes the total transfer function of all synaptic elements connected to the neuron. The method includes obtaining an expression for the variance of each synaptic drive in the synaptic drive Γ i , and the expression for the variance depends on a control parameter. The variance of each synaptic drive in the synaptic drive Γ i can be adjusted by adjusting the control parameter. The control parameter is adjusted such that the variance of each synaptic drive in the synaptic drive Г i is lower than a predetermined value, such that the synaptic drive Г of each neuron in the neuron i in the spiking neural network i is bound around the equilibrium point Г i of the synaptic drive Γ with the least noise influence i * .

[0044] In an embodiment, the synaptic drive Γ of the spiking neuron i in the spiking neural network i can be written in vector form for all neurons in the spiking neural network as Γ = (Γ1,..., Γ n ), T where n is the number of neurons in the spiking neural network, and where Γ satisfies the following formula:

[0045] dΓ = N(Γ(t))dt + σ(Γ(t))dω(t),

[0046] where N(Γ(t)) is the nominal matrix part, and σ(Γ) is the state-dependent noise matrix of the Gaussian white noise process dω(t), where ω is the Wiener process describing the noise in the spiking neural network, and where, according to the variance-covariance matrix K(t) of Г(t) that satisfies the following continuous-time algebraic Lyapunov equation, the expression for dΓ can be rewritten:

[0047] N(Γ(t))K(t) + K(t)[N(Г(t))] T + σ(Г(t))[σ(Γ(t))] T = 0,

[0048] Among them, obtaining the synaptic drive Γ i The steps of obtaining the expression of the variance of each synaptic drive in include determining the diagonal values of the variance-covariance matrix K(t).

[0049] In an embodiment, the synaptic drive Г i The equilibrium point Γ i * Can be written in vector form for all neurons in the spiking neural network as Where the noise matrix σ is zero, i.e., σ(Γ * ) = 0.

[0050] In an embodiment, the control parameters are adjusted by means of computer simulation.

[0051] According to a ninth aspect of the present disclosure, a spiking neural network is disclosed, which includes a plurality of spiking neurons implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements that interconnect the spiking neurons to form a network. Each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, and the synaptic element can be configured to adjust the weight applied by each synaptic element. Each of the spiking neurons is adapted to receive one or more synaptic output signals from one or more synaptic elements and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals. The synaptic drive Γ of one of the spiking neurons i in the spiking neural network i Is a time-dependent function that describes the total transfer function of all synaptic elements connected to the neuron. The variance of each synaptic drive in the synaptic drive Γ i Is lower than a predetermined value, such that the synaptic drive Γ of each neuron in the neuron i in the spiking neural network i Is bound around the equilibrium point Γ of the synaptic drive Γ with the least influence of noise i Of i * Surrounding. Brief Description of the Drawings

[0052] Now, embodiments will be described only by way of example, with reference to the accompanying schematic diagrams, in which corresponding reference numerals indicate corresponding parts, and wherein:

[0053] Figure 1 Shows an exemplary neural network composed of neurons and synaptic elements;

[0054] Figure 2 Schematically shows a spiking neural network within a microcontroller integrated circuit;

[0055] Figure 3 Shows a high-level architecture of a learning system with a neuromorphic core array;

[0056] Figure 4 A graphical representation showing an enhanced algorithm within a single core;

[0057] Figure 5 A graphical representation showing the combination of multiple set systems within a single core;

[0058] Figure 6 A graphical representation showing the combination of multiple set systems across multiple cores in a multi - core implementation;

[0059] Figure 7A A conceptual diagram showing a synaptic structure;

[0060] Figure 7B A conceptual diagram showing a neural synaptic structure;

[0061] Figure 8 Shows the net activity of an unbound network; and

[0062] Figure 9 Shows the net activity of a bound network.

[0063] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting the scope or protection defined by the claims. Detailed Description of the Invention

[0064] In the following, certain embodiments will be described in more detail. However, it should be understood that these embodiments are not to be construed as limiting the scope of the present disclosure.

[0065] Figure 1 is a simplified diagram of a neural network 100. Neurons 1 are connected to each other via synaptic elements 2. To avoid cluttering the drawing, only a small number of neurons and synaptic elements are shown (and only some with reference numerals attached to them). Figure 1 The connection topology shown (the way in which synaptic elements 2 are connected to neurons 1) is merely an example, and many other topologies may be employed. Each synaptic element 2 can send a signal to the input of a neuron 1, and each neuron 1 that receives the signal can process the signal and can then generate an output, which is sent to other neurons 1 via additional synaptic elements 2. Each synaptic element 2 has a certain weight assigned to it, which is applied to each synaptic input signal received and sent by the synaptic element to produce a weighted synaptic output signal. Thus, the weight of a synaptic element is a measure of the type of causal relationship between the two neurons 1 connected by the synaptic element 2. The relationship can be causal (positive weight), anti - causal (negative weight), or non - existent (zero weight).

[0066] The neuron 1 and the synaptic element 2 can be implemented in hardware, for example, using analog circuit elements or digital hardwired logic circuits. They can also be implemented partly in hardware, partly in software or entirely in software. It is preferred to implement in hardware or at least partly in hardware, that is, using hardware circuits or elements to perform the functions of a single neuron, rather than using a large processor to execute software that mimics a single neuron. These (partial) hardware implementation methods can achieve faster processing, such as achieving faster pattern recognition and event-driven processing, where only the blocks of neurons and synaptic elements are activated when needed.

[0067] The neural network 100 can be a spiking neural network. Then, the neuron 1 is a spiking neuron that generates a neuron output signal in the form of one or more spikes or events generated by the neuron. The spiking neuron 1 can be configured to trigger (i.e., generate an output spike) only when the membrane potential (e.g., energy potential, or voltage or current level) within the neuron reaches a predetermined threshold. The membrane potential of the spiking neuron changes due to the received input signals, that is, the synaptic output signals received by the neuron from the synaptic element are accumulated, integrated or otherwise processed to change the membrane potential. When the weight of the synaptic element 2 is positive, the synaptic output signal received from this synaptic element excites the spiking neuron 1 that receives the signal, thereby increasing its membrane potential. When the weight of the synaptic element 2 is negative, the synaptic output signal received from this synaptic element inhibits the synaptic neuron 1 that receives the signal, thereby decreasing its membrane potential. When the weight of the synaptic element 2 is zero, the synaptic output signal received from this synaptic element has no effect on the synaptic neuron 1 that receives the signal.

[0068] When the membrane potential of the spiking neuron 1 reaches the threshold, the neuron triggers, generating a spike at the time of triggering, and the membrane potential decreases due to the triggering. If the membrane potential reaches the threshold again subsequently, the neuron will trigger again, thereby generating a second spike. Therefore, each spiking neuron 1 is configured to generate one or more spikes in response to the input signals received from the connected synaptic element 2, and these spikes form a spatio-temporal spike train. Since the spiking neuron 1 only triggers when its membrane potential reaches a predetermined threshold, the encoding and processing of time information are incorporated into the neural network 100. In this way, spatio-temporal spike trains are generated in the spiking neural network 100, which are the time sequences of the spikes generated by the spiking neurons 1 of the network 100.

[0069] The temporal characteristics of the spike train encode the amplitude and frequency characteristics of the input signal. The temporal characteristics include: the waiting time between the start of the stimulus (e.g., the input signal from the synaptic element) and the generation of the spike at the neuron output; the waiting time between consecutive spikes from the same neuron; and the number of spikes triggered by the neuron during the duration of the applied input stimulus.

[0070] The synaptic element 2 can be configurable such that, for example, by training the neural network 100, the corresponding weights of the synaptic elements can be changed. The neurons 1 can be configured in the way they respond to the signals from the synaptic elements. For example, in the case of a spiking neural network, the neurons 1 can be configured in such a way that a certain signal increases or decreases: the membrane potential, the time required for the membrane potential to decay naturally to the resting potential, the value of the resting potential, the threshold for triggering a spike of the neuron 1. The configuration of the neurons 1 can, for example, remain constant during training, or be variable and set when training the neural network 100 on a specific training set.

[0071] The input signal 11 is, for example, a plurality of different sampled input signals or a spatio-temporal pulse sequence. The input can be the analog-to-digital conversion value of a signal sample, or in the case of, for example, an analog or digital integrator, it can be the digital value of a sample, or in the case of an analog integrator, it can be the analog value of a sample.

[0072] The output signal 12 of the neural network 100 is, for example, a spatio-temporal pulse sequence, from which they can be read out from the output neurons 1 and further classified and converted into a set of digital values corresponding to the output code type selected by the user through an output conversion stage.

[0073] Figure 2 An embodiment showing a high-level architecture of a microcontroller integrated circuit 100 including a spiking neural network 110 is presented. In this case, the microcontroller 110 is an economical means for data collection, sensing, pattern recognition, and actuating physical signals.

[0074] The spiking neural network 110 is connected to one or more streaming input data ports 111, which provide an input to the spiking neural network 110 that will be converted into a spatio-temporal pulse sequence. The spiking neural network 110 is connected to one or more output ports 112. The memory-mapped control and configuration interface 113 controls the configuration parameters of the spiking neural network 110, such as synaptic weights and / or neuron configurations, and can further include peripherals (e.g., A / D converters, D / A converters, bandgaps, PLLs) and circuits for controlling and regulating neurons, synapses, and plasticity (learning) circuits, etc. The interface 113 reads a memory device 102, in which the settings for the spiking neural network 110 are stored, and sends signals to the spiking neural network 110 to set the hardware accordingly. The interface 113 can send analog signals to the spiking neural network 110. The settings can include the configuration parameters of each neuron 1 or synaptic element 2 of the spiking neural network 110, or the network topology.

[0075] Each neuron 1 can have a set of configuration parameters that control the precise firing behavior of the neuron 1. For example, a neuron can be designed to have a firing threshold, which represents a threshold of voltage, energy, or other variable that accumulates in the neuron due to received inputs, and when the accumulated variable meets or exceeds the firing threshold, the neuron generates an output spike (e.g., a voltage, current, or energy spike). The neuron can implement an integration function that integrates the inputs to the neuron to determine the adjustment of the accumulated variable. Additionally, the neuron can be designed with: (a) a leakage rate, which represents the rate at which the accumulated variable in the neuron decays over time; (b) a resting value of the accumulated variable, which represents the value to which the accumulated variable will decay over time in the absence of any input signal to the neuron; (c) an integration time constant, which represents the time during which input signals are integrated to determine any increase in the accumulated variable in the neuron; (d) a refractory level, which represents the value of the accumulated variable in the neuron immediately after firing the neuron; (e) a refractory period, which represents the time period during which the accumulated variable in the neuron rises to the resting value after the neuron fires. For each neuron, these parameters can be predetermined and / or configurable and / or adjustable. By adjusting, for example, the firing threshold, leakage rate, integration time constant, and refractory period of the neuron, as well as the refractory period of the neuron for matching the energy content of key input signal features, when neuron 1 is stimulated by an input signal containing the feature, it will generate one or more precisely timed pulses.

[0076] The configuration parameters of the synaptic element 2 include the weight and gain of the synaptic element 2. The weight of the synaptic element 2 is typically used to adjust the synaptic element 2, while the gain of the synaptic element 2 is used for signal amplification in hardware and typically involves the implementation manner of a low-pass filter. Generally, the gain is fixed when the network 110 is initialized, while the weight can vary based on the evolution / training of the spiking neural network 110.

[0077] The microcontroller integrated circuit 100 further includes a microprocessor core 101 to perform the calculations and controls of the integrated circuit 100. For example, the microprocessor core 101 can supervise the communication between the memory-mapped control and configuration interface 113 and the memory device 102.

[0078] The memory device 102 can be any computer-readable storage medium. The memory device 102 can be a non-transitory storage medium. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media on which information can be permanently stored (e.g., read-only memory devices within a computer, such as CD-ROM disks readable by a CD-ROM drive, ROM chips, or any type of solid-state non-volatile semiconductor memory); (ii) writable storage media on which variable information can be stored, such as hard disk drives or any type of solid-state random-access semiconductor memory, flash memory.

[0079] The external bus 104 is connected to one or more sensors or other data sources 103. The microcontroller integrated circuit 100 can also be directly attached to the sensor 105. The sensor can first pass through the analog-to-digital converter 106. One or more serial input / output ports 107 and general-purpose input / output ports 108 can be present on the microcontroller integrated circuit 100. Direct access to the memory of the microcontroller integrated circuit 100 by external devices can be arranged through direct memory access (DMA) 109.

[0080] Figure 3 An advanced architecture for a learning system is shown, the learning system having a plurality of synaptic cores 210 arranged in a core array 200. Each core 210 includes a neuron network 1 implemented in hardware, the neurons being interconnected by synaptic elements 2. A single core 210 can implement a complete spiking neural network or form part of a spiking neural network that forms a separate subnetwork. Thus, a large spiking neural network can be divided into a plurality of smaller subnetworks, each subnetwork being implemented in one of the cores 210 of the array 200. In one embodiment, the core 210 can implement Figure 2 the spiking neural network 110 shown in with associated input data port 111, output port 112, and / or control and configuration interface 113.

[0081] By dividing a large spiking neural network 110 into smaller subnetworks and implementing each subnetwork on one or more cores 210, each core having its own essential circuitry, some of the non-idealities in the circuitry will operate under smaller processing geometries and draw lower operating currents, especially for large arrays. Thus, the core-based implementation reduces the impact of physical non-idealities.

[0082] Subnetworks or collections of neurons that form a cooperation group can form, for example, classifiers, collections of classifiers, process data transformation, feature encoding, or groups of neurons that only classify, etc.

[0083] In such cases, a large collective network is divided and mapped onto a core array, each core containing a programmable network of spiking neurons. Thus, each core implements a single collective, multiple small collectives (related to the number of neurons and synapses in the core), or in the case of a large collective, only a part of a single collective, with other parts being implemented on other cores of the array. The method of how the collective is divided and mapped to the cores is determined by the mapping method. The mapping method can include constraint-driven partitioning. The constraint can be a performance metric linked to the function of each corresponding subnetwork. The performance metric can depend on power consumption area limits, memory structure, memory access, time constants, offsets, technology limitations, resilience, acceptable mismatch levels, and network or physical artifacts.

[0084] The periphery of the array 200 includes rows of synaptic circuits that mimic the actions of the soma and axon hillock of biological neurons. Additionally, each neurosynaptic core 210 in the array 200 has a local router 202 that communicates with the routers 202 of other cores 210 within a dedicated real-time reconfigurable network-on-chip.

[0085] The local router 202 and its connections 201 form a programmable interconnect structure between the cores 210 of the core array 200. The cores 210 are connected via a switchable matrix. Different cores 210 of the core array 200 are thus connected via the programmable interconnect structure. In particular, different parts of the spiking neural network implemented on different cores 210 of the core array 200 are interconnected via the programmable interconnect structure. In this way, quantum effects and external noise act only on each core separately, rather than on the entire network. Thus, these effects are mitigated.

[0086] In the sense that the spiking neural network 110 has dense connections between neurons within the core 210 but sparse connections between different cores 210, the spiking neural network 110 implemented on the core array 200 can have high modularity. In this way, noise and quantum effects between cores can be even further reduced, while still allowing sub-networks to increase, for example, classification accuracy by allowing a high degree of complexity.

[0087] The programmable interconnect structure can form a packet-switched network between the cores 210 in the core array 200. For example, the local router 202 can packetize data into packets and then send them via the connections 201. These connections 201 can form a digital network. Packets can consist of a header and a payload. The data in the header is used by the local router 202 to direct the packet to its destination core 210, where the payload within the packet is extracted and used. The data can be, for example, the output of one of the sub-networks of the spiking neural network partitioned and implemented on one or more cores 210 of the core array 200. The data can also be input from a sensor or another external device.

[0088] The programmable interconnect structure can also use address-event representation, where the addresses of the neurons to be connected are sent to different cores.

[0089] Additionally, synchronous or asynchronous communication can be used. Examples of synchronous communication are any clock-based communication, and examples of asynchronous communication are, for example, handshake protocols.

[0090] The cores in the core array can form a network-on-chip on the microcontroller integrated circuit 100. The network-on-chip improves the scalability and power efficiency of the microcontroller integrated circuit 100.

[0091] The topology of the network-on-chip is selected based on system parameters, such as mesh, torus, tree, ring, star. The routing algorithm in use depends on the topology and characteristics of the network 110. The complexity of the routing algorithm can be increased by, for example, considering multiple shortest paths to a destination and then randomly selecting one of these paths for each migration (resulting in a better network load). Additional efficiency can be obtained by using heuristics and information about network load at any given time. There are other types of routing methods, including static routing tables or source-based routing.

[0092] The network-on-chip can be reconfigurable in real time or statically defined during the production phase. When the network-on-chip is reconfigurable in real time, the settings of the cores 210 in the core array 200 and their interconnect structure settings can be changed. For example, this change can be made based on changes in the input or output of the microcontroller integrated circuit, different requirements for classification accuracy or stability, network development based on its learning rules, and changes in communication protocols.

[0093] The present invention encompasses that the synaptic core 210 can apply a uniform learning rule, weight storage type, and / or communication protocol to the synaptic matrix. In other words, homogeneous learning rules, weight storage types, and / or communication protocols can be set within one core.

[0094] The entire spiking neural network 110 can be implemented as a single entity implemented within one core 210 (e.g., implemented as an intersection structure of neurons 1 and synapses 2, with all feedback connections in place to implement any recurrent neural network structure, or a simple feedforward network without any feedback signals). Alternatively, the entire spiking neural network 110 can be distributed across multiple cores 210, where each core 210 implements a specific layer or part of a layer in the context of, for example, a deep neural network. The decision on how to split the network completely is based entirely on the application case (e.g., radar, lidar, image, ultrasound, biopotential sensing).

[0095] In an embodiment, all synaptic cores 210 can apply the same learning rule, weight storage type, and / or communication protocol to each of their synaptic matrices.

[0096] In an embodiment, synaptic cores 210 can apply different learning rules, weight storage types, and / or communication protocols to each of their synaptic matrices.

[0097] In an embodiment, the synaptic array of the entire spiking neural network 110 can be organized as a single core 210 that implements heterogeneous learning rules depending on the optimal performance-power-area trade-off.

[0098] In another embodiment, different regions of the synaptic matrix within the core 210 can be configured with the same learning rule, which can be implemented by a common learning rule block driven by the same configuration register. The size of this region of the synaptic matrix within the core 210 can be configured at design time to create dedicated circuitry, or dynamically configured at runtime, where the synaptic matrix within the core 210 will have heterogeneous synaptic circuit clusters, each cluster implementing a different learning rule. This heterogeneous clustering may require special mapping or synthesis algorithms to map each neuron unit to a determined cluster of the synaptic matrix within the core 210 based on the applied learning rule.

[0099] The learning rule block can be implemented for each synaptic element, each group of synaptic elements, or each core 210 of the core array 200. The learning rule block can consist of circuitry implemented, for example, in the configuration interface 113.

[0100] In another embodiment, one or more cores 210 of different groups within the core array 200 can be configured with the same learning rule, which can be implemented by a common learning rule block driven by the same configuration register. The size of this group of cores 210 within the core array 200 can be configured at design time to create a dedicated group of cores 210, or dynamically configured at runtime, where the core array 200 will have heterogeneous clusters of cores 210, each cluster implementing a different learning rule. This heterogeneous clustering may also require special mapping or synthesis algorithms to map each neuron unit to a determined cluster of cores 210 based on the applied learning rule.

[0101] Different / heterogeneous learning rules can also be implemented within a single core 210 and not only across cores 210.

[0102] Because different groups of cores 210 of the core array 200 and different regions of the synaptic matrix within the core 210 can implement different learning rules, the design is more flexible. Additionally, by applying different learning rules, a specific input will have different effects on specific regions of the core array 200. In this way, different regions that implement different learning rules can be optimized to achieve better operation of the entire network 110. Finally, for different input signals, different learning rules may work better, enabling the network to be customized according to which part of the network requires which learning rule.

[0103] Furthermore, in an embodiment, each region of the synaptic matrix within a core 210 or each region of a group of one or more cores 210 within the core array 200 can also implement different weight storage mechanisms, such as digital memory, capacitive storage, bistable mechanisms, where each region will have different power requirements.

[0104] A set of cores 210 within the core array 200 can implement different communication protocols. This makes the design more flexible. Thus, the cores 210 of the core array 200 allow for a practical and flexible implementation of the spiking neural network 110 as hardware, especially since they allow the application of the same or different learning rules, weight storage types, and / or communication protocols to each of their synaptic matrices.

[0105] The cognitive ability of the brain comes from the computational or collective form of neuronal activity, i.e., a collaborative group (subnetwork or ensemble) of neurons generates a functional neural state that triggers learning and enhances the comprehensive perceptual ability and compensates for sensory-deprived modalities, where the collective activity of the neuronal group overcomes the unreliable random nature triggered by individual neurons.

[0106] Subsequently, numerous architectures that attempt to reflect various aspects of biology can be used: multiple (parallel) classifiers that act on the same stimulus or on various parts or features of the stimulus to remedy various machine learning complexities such as feature selection, confidence estimation, missing features, incremental learning, error correction, etc. Multiple classifiers can partition the feature space of the input signal. An ensemble of similarly configured neural networks can be utilized to improve classification performance. Through boosting procedures, a powerful classifier (with a small error on binary classification problems) can be formed from an ensemble of classifiers; the error of any of these classifiers that make up the ensemble is only marginally better than random guessing.

[0107] Thus, multiple ensemble systems can be designed based on (i) the selection of training data for individual classifiers, (ii) the specific procedures for generating ensemble members, and / or (iii) the combination rules for obtaining ensemble decisions, including for example bagging, random forests (ensembles of decision trees), composite classifier systems, mixture of experts (MoE), stacked generalization, consensus aggregation, combination of multiple classifiers, dynamic classifier selection, classifier fusion, committee of neural networks, and classifier ensembles.

[0108] Figure 4 A graphical representation of the boosting algorithm within a single core 210 of the core array 200 is shown. In Figure 4 it shows multiple classifiers 300 implemented within a single core 210 of the core array 200. The classifiers 300 form an ensemble of classifiers 300.

[0109] An ensemble 300 of classifiers is an example of a subnetwork of the spiking neural network 110, which can be implemented on a single core 210 of the core array 200.

[0110] Suppose classifier 300 has a set of output neurons (one for each class), and each output neuron triggers an event (a spike) according to its firing probability distribution. A particular classifier 300 may include different layers 301, 302, 303 of neurons 1 (or neurons 1 and synaptic elements 2) connected by synaptic elements 2. Each layer may have a different function. For example, layer 301 may perform data transformation, layer 302 may perform feature encoding, and layer 303 may perform classification. An output layer may also exist in each classifier 300. This output layer may be connected to the local router 202 of a particular core 210 of the core array 200. Using the connections 201 between the local routers 202, the output of a particular classifier 300 or a set of classifiers 300 can be directed to other cores 210 in the core array 200 and, in this way, to other sub-networks of the spiking neural network 110.

[0111] Figure 5 A graphical representation showing the combination of multiple set classifier systems within a single core 210 of the core array 200.

[0112] First, a set 401 of classifiers 300 implemented based on the boosting algorithm receives an input 404 and then sends its output to a second set 402 implemented based on the mixture of experts algorithm. The synaptic elements 410 between the layers can be trained using the triplet-based spike-timing-dependent plasticity (T-STDP) as the learning rule. When using STDP, if, on average, the input spikes of neuron 1 tend to occur immediately before the output spikes of that neuron 1, that particular input becomes stronger. On average, if the input spikes tend to occur immediately after the output spikes, that particular input can be made weaker by adjusting the weights. Thus, by increasing the weight of a particular synaptic element 2, an input that may be the cause of the postsynaptic neuron 1 firing will be more likely to contribute in the future, while an input that is not the cause of the postsynaptic spike will be less likely to contribute in the future by decreasing the weight of a particular synaptic element 2. This STDP method is based on pairs because it uses a pair of spikes. T-STDP differs from ordinary STDP in that it uses triplets.

[0113] Using the gating network 408, a data division is set among the experts during training and the outputs are combined. The gating network 408 can be used as a so-called "golden reference" during training, which defines a filter or transfer function for pooling the results of different experts and acts as a teacher signal. The experts compete to learn the training pattern, while the gating network 408 coordinates the competition. The pooling and combining system 409 pools and combines the outputs of all different experts into one output 406 and outputs the output 406 of the expert mixing layer as an input to a third set 403 of the classifier 300 implemented based on the boosting algorithm. The output 407 of the third set 403 can be output to the local router 202 of the core 210 and can be sent via the interconnect 201 to other cores 210 of the core array 200 or to the output port 112 of the spiking neural network 110.

[0114] Figure 6 A graphical representation showing the combination of multiple set systems on multiple cores in a multi-core implementation.

[0115] First, in the first core 510A, a set 401 of the classifier 300 implemented based on the boosting algorithm receives the input 404 and subsequently sends its output to a second set 402, which is implemented based on the expert mixing algorithm. The pooling and combining system 409 of the second set 402 outputs its output to the first local router 502A of the first core 510A, and then the first local router 502A sends this output to the second local router 502B of the second core 510B via the interconnects 501A, 501B. Then, this data is used as an input to the third set 403 existing on the second core 510B. Thus, this system is different from Figure 5 the system shown in that the spiking neural network 110 is divided in a certain way and mapped to the core array 200 in a different way. That is, in this embodiment, the sets are divided into two different cores 510A, 510B; each has its own necessary circuitry.

[0116] Design a dynamic model that represents the subsequent merging of classifier outputs, forcing a scheme for assigning each unique unlabeled pattern to the most suitable classifier. The classifier is defined as a random winner-takes-all, where only a single neuron can spike for any data presented at the input. A trainable combiner can determine which classifiers are accurate in which parts of the feature space and can then combine accordingly.

[0117] Without loss of generality, in the boosting algorithm, the equality of the weak and strong probably approximately correct (PAC) learning models is a prerequisite, that is, different distributions are generated when training different sub-hypotheses. Probably approximately correct (PAC) learning is a mathematical analysis framework in computational learning theory in machine learning. Here, the learner receives samples and must select a generalization function from a class of possible functions. The aim is to make the selected function have a high probability (the "probably" part) of having a low generalization error (the "approximately correct" part).

[0118] Conversely, the adaptive mixture of experts obtains enhanced performance by assigning different subtasks to different learners. Most ensemble learning algorithms (such as stacking) first train the base predictors and then try to tune the combined model.

[0119] The mixture of experts and boosting are designed for different classes of problems, which results in different advantages and disadvantages. For boosting, the distribution is mainly specified so that each classifier can develop into an expert in terms of data patterns where the previous classifier was wrong or disagreed. However, in the mixture of experts, the data patterns are divided into basic but consistent subsets; subsequently, the learning processes required for each subset are not as complex as the original data pattern.

[0120] Both employ the same gating function to set the data partition among the experts during training and combine the outputs. The gating network is usually trained using the expectation maximization (EM) algorithm on the original training data.

[0121] Each ensemble or combination of ensembles can be implemented in one or more cores 210.

[0122] In Figure 7A the embodiment shown, a hardware implementation of a synaptic matrix with synaptic elements 652A - D within the core 210 is shown. Each of the synaptic elements 652A - D has a corresponding weight 653A - D attributed to them. The first weight 653A can be written as w 2，1 , the second weight 653B can be written as w 1，1 , the third weight 653C can be written as w 2，2 , and the fourth weight 653D can be written as w 1，2 .

[0123] The input signal 650A to synaptic elements 652A, 652B can be written as X1, while the input signal 650B to synaptic elements 652C, 652D can be written as X2. As part of a spatio-temporal spike train, this could be a voltage spike. In each of the synaptic elements 652A, 652B, the input signal 650A is multiplied by the corresponding weights 653A, 653B. In each of the synaptic elements 652C, 652D, the input signal 650B is multiplied by the corresponding weights 653C, 653D. Then the output signal 651A can be written as ∑ i W 1，i X i , and the output signal 651B can be written as ∑ i w 2，i X i . These output signals 651A, 651B can be sent to one or more neurons.

[0124] The weights 653A-D of the synaptic elements 652A-D can be set by using one or more enable lines 654 and error lines 655. The enable lines 654 implement the weights 653A-D and set the correct values known to the system, while the error lines 655 update the weights 653A-D based on the perceived error in the weight setting. These signals can be analog or digital.

[0125] In another embodiment, each of the neural synapse assemblies can be implemented as a combination of multiple (synaptic) receptors of a biological neuron with dendrites (inputs) and the soma (output). This is shown in Figure 7B .

[0126] Figure 7B One or more synaptic elements 602 are shown. The pulse 606 portion of the spatio-temporal pulse train enters the synaptic element 602. At the input of the computing element, three receptors are accessible: the NMDA receptor (rNMDA) 607A provides activity-dependent modification of the synaptic weight w, while the AMPA receptor (rAMPA) 607B facilitates fast synaptic current to drive the soma by pulling current, and finally the GABA receptor (rGABA) 607C can facilitate fast or slow inhibitory synaptic current by absorbing current, depending on whether the GABAA or GABAB receptor is used. The output of rAMPA 607A and / or rGABA 607C can be used as the input to an amplifier 608.

[0127] In this embodiment, rNMDA 607A and rAMPA 607B or rGABA 607C may also be present. Importantly, receptors 607A-C with different time components can be used. rAMPA 607B and rGABA 607C can be implemented as low-pass filters. Meanwhile, rNMDA 607A can be implemented as a voltage-gated receptor with amplification and filtering functions, which is connected to the presynaptic circuit implementing the learning rule. This filtering can consist of band-pass, low-pass, and high-pass filters.

[0128] The output of amplifier 608 is sent to dendrite 601A, which forms part of a neuron that connects to synaptic element 602. Then, the outputs from all synaptic elements 602 are integrated over time by integrator 609. The integrated signal is sent via receptor 610 into the axon soma 601B of the neuron, which consists of axon 603 and soma 604. Signals from other clusters 605, 606 of synaptic elements can also enter axon soma 601B at this time. Different integrators 611 can be placed in axon soma 601B. When axon 603 releases a pulse to generate an action potential, it leaves axon soma 601B and can be sent, for example, as a pulse in a spatio-temporal pulse sequence to other synaptic elements.

[0129] Receptors 612 and 613 obtain backpropagating signals from dendrite 601A and axon soma 601B respectively. They are added to, for example, the synaptic element to complete the time derivative 614, and the resulting signal is multiplied by the rNMDA 607A signal to modify amplifier 608 and thus modify the weight of each synaptic element 602.

[0130] This increase in size allows for more states and transitions (and time constants), providing greater flexibility for the implementation of homeostatic plasticity and metaplastic interactions, i.e., providing a mechanism to adapt to environmental changes and thus providing a means to implement and maintain robust neural computations.

[0131] In engineering terms, homeostatic plasticity is a form of control by backpropagating signals that balances the effects of neuronal activity or internal connectivity drift caused by changes in external conditions or temperature variations.

[0132] Although this concept plays a crucial role in the hardware design of spiking neural network 110 as it provides robustness against changes in operating conditions, the limited number of previous implementations has mainly been due to the technical constraints involved in implementing long-term constants in silicon and thus includes homeostatic plasticity.

[0133] The implemented synaptic element 602 allows for the implementation of a variety of computational capabilities, e.g., a wide range of receptor time constants and conductance values g m, axonal and dendritic delays, optimal synaptic transfer function.

[0134] Activity-dependent plasticity of synaptic transmission, which is the basis of learning and memory, is mainly attributed to postsynaptic changes in the biophysical properties of receptors.

[0135] To regulate the flow of synaptic current, each receptor is referred to as a multi-(trans)conductance channel, which models non-linear properties such as the multi-binding cooperativity of neurotransmitters with receptors. The synaptic current mediated by the NMDA receptor 607A is regulated by synaptic activity. Through the formation, stability, morphology, and density of synaptic contacts, rapid changes in the number of receptors on the synaptic element 602 play a control mechanism for activity-dependent changes in synaptic efficacy. If a group (burst) of dendritic spikes is sufficient to exceed the threshold, the axon 603 will generate an action potential; then the subsequent spikes will backpropagate into the dendrite 601A and subsequently generate weight control together with the somatic 604 signal that multiplies and adds to the NMDA receptor 607A signal. This quasi-local homeostatic framework provides a normalization function without disrupting Hebbian plasticity and can effectively keep the net synaptic activation constant by hierarchically regulating the postsynaptic strength.

[0136] Figure 7A and Figure 7B The two hardware implementation methods of and are not necessarily used in the multi-core implementation of the present invention, but any spiking neural network 110 can be implemented in this way in any hardware.

[0137] Each in the combined ensemble system operates according to a biologically plausible mechanism. For example, the expert mixture non-linear gating mechanism is based on spike-timing-dependent plasticity (STDP), and the combination of STDP and activity-dependent changes in neuronal excitability induces Bayesian information processing (referred to as the spike-expectation maximization (SEM) network).

[0138] The proposed ensemble architecture can utilize an SEM network such as a single ensemble unit (classifier). The learning rule used in SEM is the weight-dependent Hebbian triplet TSTDP rule. Assume that the classifier has a set of output neurons (one for each class), and each output neuron triggers an event (spike) according to its firing probability distribution. The classifier follows a stochastic winner-takes-all (sWTA) mechanism, in which, for any presented input data, only a single neuron 1 can trigger.

[0139] If its output (postsynaptic neuron) triggers, then each synapse w ij will aggregate its input y i(Pre-synaptic neuron) activation statistics. These statistics can be collected at runtime from samples of the augmented input distribution. From this data, each weight can be interpreted as the log product of two local virtual counters in each synapse, i.e., one representing the number of events, and one representing the local learning rate η ij .

[0140] Thus, we can derive a spike event-triggered stochastic online learning rule:

[0141]

[0142] This approximates the logarithm of the running average of the spike time output of neuron z ij in synapse w i .

[0143] The (stochastic) variables used to set the stochastic weight updates in the spiking neural network 110 are independent and identically distributed. Due to the randomness introduced in the transition, the classifier learns various representations of the target class. Subsequently, the classifier responses are combined into a pooled improved classifier. Additionally, by adding uncertainty to the bound values of the synaptic weights, the level of activation of the classifier decisions can be controlled.

[0144] Neuron 1 communicates mainly through fast all-or-none events (i.e., spikes in its membrane potential) in the spiking neural network 110. The relative spike trigger times in the neuron population are assumed to be the information code, while the synchronization between neuron populations is assumed to be the signal for encoding and decoding the information. Thus, the neuroelectric properties of excitatory and inhibitory neuron networks can be expressed by the following formula:

[0145]

[0146] Here, Γ i (t) is the i-th synaptic drive at time t, which essentially represents the synaptic strength and is defined according to the synaptic weight and the gain function, λ i is the gain, which regulates the exponential decay of the synaptic voltage and simulates the spike-time-dependent scaling of the input conductance, the function f i (...) represents the firing rate of the i-th neuron, w ji is the constant specifying the coupling between the j-th neuron on the i-th neuron, and v r，i (t) represents the input voltage of the i-th neuron, e.g., a nerve impulse from a sensory receptor. The i-th neuron is the post-synaptic neuron, while the j-th neuron is the pre-synaptic neuron of the synaptic element with connection weight w ji . The synaptic drive Γ iis regarded as the total transfer function of all synaptic elements driving neuron i, which can be, for example, a function of the exponential decay value, weight, and gain of the synaptic elements driving neuron i, etc.

[0147] However, in both the generation of spikes and the transmission of synaptic signals, neurons are noisy. The noise stems from the quantal release of neurotransmitters, the random opening of ion channels, the coupling of background neural activity, etc.

[0148] Subsequently, the noise induces neuronal variability, increases the sensitivity of neurons to environmental stimuli, affects the synchronization between neurons, and facilitates probabilistic inference.

[0149] We derive the uncertainty model as a Markov process, where the stochastic integral is interpreted as the system of a stochastic differential equation; thus, we extend the time delay and stochastic input uncertainty to the above formula (1):

[0150]

[0151] The first two terms on the right - hand side of formula (2) are the deterministic drift part and the stochastic diffusion part of the stochastic differential equation, where we define and

[0152] Here, ω(t)=[ω1(t), ω2(t),..., ω n (t)] T describes the noise in the input voltage and is represented by Brownian motion, i.e., an n - dimensional standard Wiener process, and σ(Γ)=diag([σ1(Γ1), σ2(Γ2),..., σ n (Γ n )] T ) represents the state - dependent noise matrix of the Gaussian white noise process dω(t). The time - varying function δ ji (t) represents the continuous time - varying time delay of the signal from the j - th neuron to the i - th neuron at time t, where δ ji (t)≥0, t≥0.

[0153] Make the following assumption: Each entry of the matrices ψ and w of the mean dynamics is synchronously perturbed, e.g., (where v r，i (t)=0).

[0154] The assumption that synaptic inputs are similar to triangular current pulses and can subsequently be modeled as Gaussian white noise is valid for fast AMPA (decay of about 2 ms) and GABAA currents (decay of about 5 - 10 ms); however, for slower currents such as NMDA or GABAB currents (decay of about 50 - 100 ms), this assumption may not hold. Therefore, they are modeled as colored noise, including non-zero synaptic time constants within the steady-state firing rate, requiring complex 3-D Fokker-Planck expressions.

[0155] Although such methods are feasible, more efficient methods include replacing the variance with a rescaled variance, i.e., noting that the synaptic time constant τ s mainly affects the magnitude of the variance. Therefore, from the ratio of the voltage variances of colored noise and white noise, a reduction factor for the synaptic time correlation constant can be derived where where τ m is the membrane time constant, and is the standard deviation of the synaptic current. Therefore, the Gaussian white noise theory remains valid, simply replacing the variance with σ red instead of the variance

[0156] The goal is to find the variance-covariance matrix of Γ(t). Equation 2 is a set of stochastic differential equations. From there, the variance-covariance matrix of Γ(t) is derived, which is essentially a system of linear ordinary differential equations with time-varying coefficients. To solve, discretization is performed using the backward Euler, and thus the continuous-time algebraic Lyapunov shown in Equation 5 below is obtained. These problems can be solved by iterative methods, and the solution is given in Equation 6.

[0157] The goal is to find an expression for the variance of the synaptic drive Γ i (t) for all neurons i, as it can measure how far the stochastic values of Г i (t) are spread from its mean. The variance of the synaptic drive is the expectation of the squared deviation of the synaptic drive from its mean. By finding such an expression, the spiking neural network can be bounded. That is, the spread of the synaptic drive values caused by noise in the spiking neural network can be restricted by adjusting the parameters that make up the variance expression, such that the variance is small, and in particular, minimized in a specific hardware implementation.

[0158] The diagonal elements K of the variance-covariance matrix K(t) of Γ(t) i，i (t) are given by the variance of the synaptic drive Γ i (t) respectively. Therefore, solving the variance-covariance matrix K(t) of Γ(t) will provide the synaptic drive Г of all neurons i iExpression for the variance of (t).

[0159] Solving (2) requires first finding σ(Γ), and then obtaining its matrix square root. We use the static statistics of the open channels in the Markov channel model to define the noise process in the conductance model. A general method for constructing σ(Γ) according to the deterministic drift and M ion channels (or the number of synaptic elements in a spiking neural network) using the Goldwyn method can be expressed as:

[0160]

[0161] Here, N is the number of states, I N×1 is an N×1 column vector with all entries equal to 1, and I N×N is the N×N identity matrix. At the equilibrium point Γ * where σ(Γ * ) = 0, the noise part of equation (2) is zero. Using the above expression (4), we can find the equilibrium point Γ * of the system. At the equilibrium point Γ * , the spiking neural network will remain stable, i.e., the noise does not affect the behavior of the spiking neural network. Next, the boundaries of the network are determined by finding the expression for the variance of the synaptic drive Γ i (t) for all neurons i.

[0162] Apply the stochastic differential theorem, and then apply the backward Euler. The variance-covariance matrix K(t) of Γ(t) (with an initial value of K(0) = E[ΓΓ T )) can be expressed as a continuous-time algebraic Lyapunov equation:

[0163]

[0164] By solving the system in (5), K(t) at a specific time t r is calculated. The Bartels-Stewart method or the Hammarling method can be used to efficiently calculate small and dense Lyapunov equations. Alternatively, large and dense Lyapunov equations can be calculated by techniques based on the sign function. Generally, the matrix of the deterministic drift in a neural network is not a full-rank matrix; therefore, we rewrite (5) as a sparse linear matrix-vector system in standard form and solve it using the adjusted alternating direction method:

[0165]

[0166] Here, for iteration j = 1, 2,..., K j has a rank of j×n, and n is [σ(Γ)]r The number of medium vectors.

[0167] To stabilize the network in (2) to the equilibrium point Γ * , for example, the point where σ(Γ * ) = 0, where the random perturbation decreases, we transform Θ(t) = Γ(t) - Γ * to move the equilibrium point Γ * to the origin,

[0168]

[0169] where g(Θ(t)) = f(Γ(t) + Γ * ) - f(Γ(t)), and the controller u(t) is set to

[0170]

[0171] where |Θ(t)|γ = (|Θ1(t)|γ, |Θ2(t)|γ,..., |Θ n (t)|γ) T , sign(Θ(t)) = diag(sign(Θ1(t)), sign(Θ2(t)),..., sign(Θ n (t))), is the gain coefficient, and γ satisfies 0 < γ < 1. For γ = 0, u(t) is discontinuous; when 0 < γ < 1, the controller is a continuous function of Θ; for γ = 1, u(t) is set to be asymptotically stable.

[0172] Without loss of generality, Figure 8 and Figure 9 show the network activity and thus show the average network activity histograms of the unbound and bound networks, respectively.

[0173] In both figures, the input signals of the spiking neural network 110 are the same. However, by making the synaptic drive Γ i (t) of all neurons i in the spiking neural network 110 fall within a specific range around the equilibrium point Γ i * to bind the network, the bound neural network is not troubled by noise as the unbound network. The equilibrium point Γ i (t) is set by selecting the parameters that appear in the variance expression of the synaptic drive Γ i * around a specific range. Each synaptic drive Γ iThe variances are all below a certain value, which depends on the maximum admissible value of the amount of noise in network 110. This value can be predefined and depends on the specific application, the input signal, the accuracy requirements for the classification performed by spiking neural network 110, etc.

[0174] In practice, network 110 can be bounded, for example, by simulating the network in hardware or software and then restricting the network and evaluating the effects as described above. The bounding of network 110 can be performed during the learning process of setting weights. Noise can be artificially added or simulated to test the stability of the network when affected by noise.

[0175] The above can be implemented in any spiking neural network 110, can be implemented in a multi-core solution in a specific core 210 of core array 200, or can be implemented within the general hardware implementation of spiking neural network 110.

[0176] The present invention can be implemented as the implementation of a reconfigurable multi-layer computing network, which is a collection of multi-receptor multi-dendritic synapse structures, where each collection implements a unique input-output transfer function, such as filtering, amplification, multiplication, addition.

[0177] In an embodiment, a method is designed to set the reliability and uncertainty bounding for synapse structures or a collection of such structures for the control and adaptation of classifier responses and activation functions.

[0178] In an embodiment, an increase in the size of synapse structures is achieved, allowing for more states and transitions, providing greater flexibility in the implementation of plasticity and metaplasia interactions and various neuronal properties (such as delays or synaptic transfer functions).

[0179] In an embodiment, multiple learning rules can be implemented, where each synapse structure in a collection or a group of collections implements a unique learning rule.

[0180] In an embodiment, a unique input-output transfer function can be generated by adaptively controlling the amount of charge or representative chemical substances (such as calcium, potassium, sodium).

[0181] In an embodiment, fine-grained time accuracy can be achieved to drive precise learning behavior and improve the learning ability of synapse structures.

[0182] In an embodiment, multiple time control mechanisms can be implemented to allow for steady-state regulation in the resulting network.

[0183] In an embodiment, multiple signals can be implemented to model local and global postsynaptic effects.

[0184] In an embodiment, a set of collections can be organized as a reconfigurable synaptic array.

[0185] In an embodiment, a reconfigurable synaptic structure can be organized as a computing / signal processing core, where each core can be organized as a single heterogeneous or homogeneous type implementing a specific learning rule, weight storage, etc., depending on the optimal performance-power-area trade-off.

[0186] The vast difference in energy efficiency and cognitive performance between biological nervous systems and traditional computing is profoundly illustrated in tasks related to real-time interaction with the physical environment, especially in the presence of uncontrolled or noisy sensory inputs. However, due to the ability to learn (such as parallelism of operations, associative memory, multi-factor optimization, and scalability), neuromorphic event-based neural networks are an inherent choice for compact and low-power cognitive systems that learn and adapt to statistical changes in complex sensory signals. This new hardware resilience approach for neuromorphic networks allows for the design of energy-efficient solutions for applications such as detecting patterns in biomedical signals (e.g., pulse classification, disease onset detection, etc.), classifying images (e.g., handwritten digits), voice commands, and can be widely applied to various devices, including smart sensors or wearable devices in cyber-physical systems and the Internet of Things.

[0187] One or more embodiments can be implemented as a computer program product for use with a computer system. The program of the program product can define the functions of the embodiments (including the methods described herein) and can be contained on various computer-readable storage media. The computer-readable storage media can be non-transitory storage media. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media on which information can be permanently stored (e.g., read-only storage devices within a computer, such as a CD-ROM disk readable by a CD-ROM drive, a ROM chip, or any type of solid-state non-volatile semiconductor memory); (ii) writable storage media on which variable information can be stored, such as a hard disk drive or any type of solid-state random-access semiconductor memory, flash memory.

[0188] Two or more of the above-described embodiments can be combined in any suitable manner.

Claims

1. A spiking neural network (110) for classifying an input signal, comprising a plurality of spiking neurons (1) implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements (2) interconnecting the spiking neurons (1) to form a network (110). wherein, Each synaptic element (2) is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, and the synaptic element (2) can be configured to adjust the weight applied by each synaptic element (2), and wherein each of the spiking neurons (1) is adapted to receive one or more of the synaptic output signals from one or more of the synaptic elements (2) and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals, wherein the weights of the synaptic elements (2) are bound by a binding value, and wherein the binding value is a random value; wherein, in a multi-core solution, the spiking neural network (110) is in the cores of a core array, each core consisting of a programmable network (110) of spiking neurons (1) implemented in hardware or a combination of hardware and software, and wherein communication between cores in the core array is arranged through a programmable interconnect structure.

2. The spiking neural network (110) according to claim 1, wherein, Random weight updates are used to configure the weights of the synaptic elements (2), wherein the random variables used to set the random weight updates in the spiking neural network (110) are independent and identically distributed.

3. The spiking neural network (110) according to claim 1 or 2, wherein, If the output of each synaptic element (2) fires, each synaptic element (2) aggregates the activation statistics of its inputs, the output of each synaptic element (2) being a postsynaptic neuron (1) and the input of each synaptic element (2) being a presynaptic neuron (1), wherein the activation statistics are collected from samples of the input distribution at runtime, and / or wherein the weights are updated according to a stochastic online learning rule triggered by a spike event given by: w ij is the old weight of the synaptic element (2) from the input neuron i to the output neuron j of the spiking neural network (110), η ij is the local learning rate, y i is the input of the presynaptic input neuron i, z i is the output of the spike time of neuron i.

4. The spiking neural network (110) according to claim 1, wherein, The weight of the synaptic element (2) connected to the spiking neuron i is bound by binding the synaptic drive Γ of the spiking neuron i in the spiking neural network (110) i and the binding Among them, the synaptic drive Γ of one of the spiking neurons i in the spiking neural network (110) i is a time-dependent function that describes the total transfer function of all synaptic elements (2) connected to the neuron.

5. The spiking neural network (110) according to claim 4, wherein, The variance can be adjusted by the following means: obtaining the synaptic drive Γ i the expression of the variance of each synaptic drive in i , the expression of the variance depending on a control parameter, where the synaptic drive Γ i the variance of each synaptic drive in i can be adjusted by adjusting the control parameter Among them, adjust the control parameter so that the synaptic drive Γ i The variance of each synaptic drive in is lower than a predetermined value, so that for each neuron i in the spiking neural network (110), the synaptic drive Γ i is bound around the equilibrium point Γ i of the synaptic drive Γ i * with the least influence of noise. Among them, the synaptic drive Γ i The equilibrium point Γ i * Can be written in vector form for all neurons in the spiking neural network (110) as Where the noise matrix σ is zero, i.e., σ(Γ * ) = 0.

6. The spiking neural network according to claim 5, wherein, The synaptic drive Γ of the spiking neuron i in the spiking neural network (110) i can be written in vector form for all neurons in the spiking neural network (110) as Γ = (Γ1,…,Γ n ) T , where n is the number of neurons in the spiking neural network (110), and where Γ satisfies the following formula: dΓ = N(Γ(t))dt + σ(Γ(t))dω(t), where N(Γ(t)) is the nominal matrix part and σ(Γ) is the state-dependent noise matrix of the Gaussian white noise process dω(t), where ω is the Wiener process describing the noise in the spiking neural network (110), wherein, according to the variance-covariance matrix K(t) of Γ(t) that satisfies the following continuous-time algebraic Lyapunov equation, the expression for dΓ can be rewritten: N(Γ(t))K(t)+K(t)[N(Γ(t))] T +σ(Γ(t))[σ(Γ(t))] T =0, wherein, obtaining the synaptic drive Γ i The steps of obtaining the expression of the variance of each synaptic drive in i include determining the diagonal values of the variance-covariance matrix K(t).

7. The spiking neural network (110) according to claim 1, wherein the spiking neural network (110) is a sub-network obtained by dividing a large spiking neural network (110) into a plurality of sub-networks, each of the sub-networks including a subset of the spiking neurons (1), the subset being connected to receive synaptic output signals from a subset of the synaptic elements (2), wherein the sub-network is adapted to generate a sub-network output pattern signal in response to a sub-network input pattern signal applied to the sub-network, wherein each sub-network forms part of one or more cores in a core array, each core being composed of a programmable network of spiking neurons (1) implemented in hardware or a combination of hardware and software, and wherein communication between the cores in the core array is arranged through a programmable interconnect structure.

8. An integrated circuit comprising a spiking neural network (110) according to any one of the preceding claims.

9. A method for configuring a spiking neural network (110) to reduce the influence of noise in the spiking neural network (110), wherein, The spiking neural network (110) includes a plurality of spiking neurons (1) implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements (2) interconnecting the spiking neurons (1) to form a network (110), wherein each synaptic element (2) is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, and the synaptic element (2) can be configured to adjust the weight applied by each synaptic element (2), and wherein each of the spiking neurons (1) is adapted to receive one or more of the synaptic output signals from one or more of the synaptic elements (2) and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals, the method comprising: binding the weights of the synaptic elements (2) by a binding value, wherein the binding value is a random value; Among them, in the multi-core solution, the spiking neural network (110) is in the core of the core array, each core consists of a programmable network (110) of spiking neurons (1) implemented in hardware or a combination of hardware and software, and the communication between cores in the core array is arranged through a programmable interconnect structure.

10. The method according to claim 9, wherein, Random weight updates are used to configure the weights of the synaptic elements (2), where the random variables used to set the random weight updates in the spiking neural network (110) are independent and identically distributed.

11. The method according to claim 9 or 10, wherein, If the output of each synaptic element (2) fires, each synaptic element (2) aggregates the activation statistics of its inputs, the output of each synaptic element (2) is a postsynaptic neuron, and the input of each synaptic element (2) is a presynaptic neuron, where the activation statistics are collected from samples of the input distribution at runtime, and / or where the weights are updated according to a stochastic online learning rule triggered by spike events given by the following formula: w ij is the old weight of the synaptic element (2) from the input neuron i to the output neuron j of the spiking neural network (110), η ij is the local learning rate, y i is the input of the presynaptic input neuron i, z i is the output of the spike time of neuron i.

12. The method according to claim 9, wherein, The weight of the synaptic element (2) connected to the spiking neuron i is bound by binding the synaptic drive Γ of the spiking neuron i in the spiking neural network (110). i The binding is performed by binding the synaptic drive Γ of one of the spiking neurons i in the spiking neural network (110), i where the synaptic drive Γ is a time-dependent function that describes the total transfer function of all the synaptic elements (2) connected to the neuron.

13. The method according to claim 12, wherein, The variance can be adjusted by the following method: obtaining the synaptic drive Γ i an expression of the variance of each synaptic drive in i , the expression of the variance depending on a control parameter, wherein i the variance of each synaptic drive in i can be adjusted by adjusting the control parameter Among them, adjust the control parameter so that the synaptic drive Γ i The variance of each synaptic drive in is lower than a predetermined value, so that for each neuron i in the spiking neural network (110), the synaptic drive Γ i is bound around the equilibrium point Γ i of the synaptic drive Γ i * with the least influence of noise, Among them, the synaptic drive Γ i The equilibrium point Γ i * Can be written in vector form for all neurons in the spiking neural network (110) as Where the noise matrix σ is zero, i.e., σ(Γ * ) = 0.

14. The method according to claim 13, wherein, The synaptic drive Γ of the spiking neuron i in the spiking neural network (110) i can be written in vector form for all neurons in the spiking neural network (110) as Γ = (Γ1,…,Γ n ) T , where n is the number of neurons in the spiking neural network (110), and where Γ satisfies the following formula: dΓ = N(Γ(t))dt + σ(Γ(t))dω(t), where N(Γ(t)) is the nominal matrix part, and σ(Γ) is the state-dependent noise matrix of the Gaussian white noise process dω(t), where ω is the Wiener process describing the noise in the spiking neural network (110), where, according to the variance-covariance matrix K(t) of Γ(t) that satisfies the following continuous-time algebraic Lyapunov equation, the expression of dΓ can be rewritten: N(Γ(t))K(t)+K(t)[N(Γ(t))] T +σ(Γ(t))[σ(Γ(t))] T =0, wherein, obtaining the synaptic drive Γ i The steps of obtaining the expression of the variance of each synaptic drive in i include determining the diagonal values of the variance-covariance matrix K(t).

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