Display device and method for manufacturing the same

Abstract

The present application relates to a display device and a method for manufacturing the display device. The display device includes a first substrate, the first substrate including a first region and a second region located at an edge of the first region. A first electrode and a second electrode are arranged on the first substrate and are spaced apart from each other. A light-emitting element is arranged between the first electrode and the second electrode in the first region. A first conductive layer is arranged on the first electrode in the second region. A pixel circuit layer is arranged on the first conductive layer in the second region and includes a transistor connected to the first conductive layer. A second substrate is arranged on the pixel circuit layer.

Description

Technical Field

[0001] Various embodiments of the present disclosure are directed to a display device and a method of manufacturing the display device. Background Art

[0002] Recently, a technology for manufacturing ultra-small light-emitting elements using materials having a reliable inorganic crystal structure and manufacturing light-emitting devices using the light-emitting elements has been developed. For example, a technology for forming a light source of a light-emitting device using ultra-small light-emitting elements having a small size ranging from nanometers to micrometers is being developed. Such a light-emitting device can be used in various electronic devices, such as display devices or lighting devices. Summary of the invention

[0003] Technical issues

[0004] The display device is manufactured by forming a circuit element on a substrate and forming a light emitting element on the circuit element. When any one of the circuit element and the light emitting element is actually defective, the display device may be classified as a defective product.

[0005] Furthermore, when a light emitting element is formed on a circuit element, an electromagnetic shielding layer may be formed between the circuit element and the light emitting element to prevent interference by the circuit element, but this may complicate the process.

[0006] A technical object of the present disclosure is to provide a display device that can be manufactured with an improved yield while having a simpler structure.

[0007] The technical purpose of the present disclosure is to provide a method for manufacturing a display device capable of improving yield through a more simplified process.

[0008] Technical Solution

[0009] In order to achieve the purpose of the present disclosure, a display device according to an embodiment of the present disclosure includes a first substrate, a first electrode and a second electrode, a light-emitting element, a first conductive layer, a pixel circuit layer and a second substrate, the first substrate including a first region and a second region located at an edge of the first region, the first electrode and the second electrode are arranged on the first substrate and are spaced apart from each other, the light-emitting element is arranged between the first electrode and the second electrode in the first region, the first conductive layer is arranged on the first electrode in the second region, the pixel circuit layer is arranged on the first conductive layer in the second region and includes a transistor connected to the first conductive layer, and the second substrate is arranged on the pixel circuit layer.

[0010] According to an embodiment, the display device may further include a first dam pattern, a second dam pattern and a third dam pattern, the first dam pattern being inserted between the first substrate and the first electrode in the first region, the second dam pattern being inserted between the first substrate and the second electrode in the first region, the third dam pattern being inserted between the first substrate and the first electrode in the second region, and the light-emitting element may be arranged between the first dam pattern and the second dam pattern.

[0011] According to an embodiment, the pixel circuit layer may further include a transmission component disposed to overlap the first region of the first substrate and configured to transmit at least some of the light emitted from the light emitting element.

[0012] According to an embodiment, the display device may further include a first contact electrode configured to couple a first end of each of the light emitting elements to the first electrode and a second contact electrode configured to couple a second end of each of the light emitting elements to the second electrode.

[0013] According to an embodiment, the first contact electrode may be interposed between the first electrode and the first conductive layer in the second region.

[0014] According to an embodiment, the display device may further include an insulating layer disposed on the first contact electrode and the second contact electrode, and the insulating layer may not overlap with the first conductive layer.

[0015] According to an embodiment, the thickness of the first conductive layer may be greater than an average thickness of the insulating layer.

[0016] According to an embodiment, the pixel circuit layer may also include a through-hole layer arranged on the first conductive layer, a first transistor electrode arranged on the through-hole layer, and a semiconductor pattern arranged on the first transistor electrode, the first transistor electrode and the semiconductor pattern may form a transistor, and the first conductive layer may contact the first transistor electrode through a contact hole, which exposes the first transistor electrode by passing through the through-hole layer.

[0017] According to an embodiment, the via layer may include a light blocking material that absorbs or blocks light emitted from the light emitting element.

[0018] According to an embodiment, the display device may further include a second conductive layer, which is arranged on the second electrode in the second region and is separated from the first conductive layer, and the pixel circuit layer may further include a power line arranged on the second conductive layer in the second region and connected to the second conductive layer.

[0019] In order to achieve the purpose of the present disclosure, the display device according to the embodiment of the present disclosure is configured so that the first substrate includes a plurality of pixel areas configured to display different monochrome colors, each of the plurality of pixel areas includes a first area and a second area, a first conductive layer is independently arranged in each of the plurality of pixel areas, and the second conductive layer is arranged to span at least two pixel areas among the plurality of pixel areas.

[0020] According to an embodiment, the transmissive member may cover the second electrode in the second region.

[0021] According to an embodiment, the first substrate may further include a display area in which an image is displayed and a non-display area located on one side of the display area, the display area may include a plurality of pixel areas configured to display different monochrome colors, each of the plurality of pixel areas includes a first area and a second area, the second electrode may extend to the non-display area, and the pixel circuit layer may further include a power line and a second conductive layer, the power line is arranged in the non-display area, the second conductive layer is arranged between the second electrode and the power line in the non-display area, and is configured to connect the second electrode to the power line.

[0022] According to an embodiment, the first conductive layer may cover the transistor.

[0023] According to an embodiment, the transmission component may include a color filter material configured to block light of some wavelength bands among the light emitted from the light emitting element.

[0024] According to an embodiment, the transmissive component may include quantum dots configured to convert the color of light emitted from the light emitting element.

[0025] According to an embodiment, the display device may further include a bank disposed on the first substrate in the second region along an edge of the first region and configured to define the first region, and the bank may not overlap the first conductive layer.

[0026] According to an embodiment, a sum of a thickness of the first conductive layer and a thickness of the third bank pattern may be greater than a thickness of the bank.

[0027] According to an embodiment, each of the light emitting elements may be a rod-type light emitting diode having a size ranging from a nanometer scale to a micrometer scale.

[0028] In order to achieve the purpose of the present disclosure, a method for manufacturing a display device according to an embodiment of the present disclosure includes preparing a first panel including a light-emitting element layer formed on a first substrate; preparing a second panel including a pixel circuit layer formed on a second substrate; and combining the first panel and the second panel so that the light-emitting element layer and the pixel circuit layer are in contact with each other, the light-emitting element layer may include a first substrate, a first electrode and a second electrode arranged to be spaced apart from each other on the first substrate, and a plurality of light-emitting elements arranged between the first electrode and the second electrode, and the pixel circuit layer may include a second substrate, a transistor arranged on the second substrate, and a first conductive layer arranged on the transistor.

[0029] According to an embodiment, the pixel circuit layer may further include a transmission component overlapping the light emitting element of the first panel and configured to transmit at least some of the light emitted from the light emitting element.

[0030] According to an embodiment, preparing the second panel may include forming a transistor on a second substrate; forming a first conductive layer on the transistor; forming a groove in a pixel circuit layer corresponding to the transmission component; and forming the transmission component by supplying a transparent organic material to the groove.

[0031] Beneficial Effects

[0032] The display device according to the embodiment of the present disclosure may have a simpler structure by including a circuit element disposed on a light emitting element.

[0033] The method for manufacturing a display device according to an embodiment of the present disclosure enables manufacturing a display device by separately manufacturing a first panel including a light emitting element and a second panel including a circuit element and a conductive layer formed on the circuit element, and by combining the first panel and the second panel so that the circuit element is connected to the light emitting element through the conductive layer. Therefore, the yield rate of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1a and Figure 1b are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0035] Figure 2a and Figure 2b are a perspective view and a cross-sectional view showing a light emitting element according to another embodiment of the present disclosure.

[0036] Figure 3a and Figure 3b are a perspective view and a cross-sectional view showing a light emitting element according to still another embodiment of the present disclosure.

[0037] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure.

[0038] Figure 5a to Figure 5c It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a display device.

[0039] Figure 6 It is shown Figure 4 A cross-sectional view of an example of a display device.

[0040] Figure 7 It is shown that the Figure 6 A plan view of an example of a first panel in a display device.

[0041] Figures 8a to 8d It is shown along Figure 7 A cross-sectional view of an example of the first panel taken along line II'.

[0042] Fig. 9 It is shown that the Figure 6 A plan view of an example of a second panel in a display device.

[0043] Fig.10 It is shown along Fig. 9 A cross-sectional view of an example of the second panel taken along line II-II'.

[0044] Fig.11 It is shown Figure 6 A cross-sectional view of an example of a display device.

[0045] Fig.12 It is shown that the Figure 6 A plan view of another example of a first panel in a display device.

[0046] Fig.13 It is shown along Fig.12 A cross-sectional view of another example of the first panel taken along line III-III'.

[0047] Fig.14 It is shown Figure 6 A cross-sectional view of another example of a display device.

[0048] Fig.15 It is shown along Figure 7 FIG. 1 is a cross-sectional view of yet another example of the first panel taken along line II′.

[0049] Fig.16 It is shown Figure 6 A cross-sectional view of yet another example of a display device.

[0050] Fig.17 It is shown that the Figure 6 A plan view of another example of a second panel in a display device.

[0051] Fig.18 It is shown along Fig.17 A cross-sectional view of another example of the second panel taken along line IV-IV'.

[0052] Fig.19 It is shown Figure 6 A cross-sectional view of yet another example of a display device.

[0053] Fig. 20 is a plan view showing a display device according to another embodiment of the present disclosure.

[0054] Fig.21 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0055] Figures 22a to 22d It is used to explain the Fig.21 A view of the process of preparing the first panel of the method.

[0056] Figures 23a to 23g It is used to explain the Fig.21 A view of a process of preparing a second panel. DETAILED DESCRIPTION

[0057] Since the present disclosure allows various changes and multiple embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, the present disclosure is not limited to the embodiments disclosed below and can be implemented in various forms.

[0058] Meanwhile, in order to clearly illustrate the present disclosure, some components that are not directly related to the characteristics of the present disclosure may be omitted in the drawings. In addition, the sizes or proportions of some components in the drawings may be exaggerated. In all the drawings, although the same or similar components are shown in different drawings, the same or similar components are given the same reference numerals and symbols as much as possible, and repeated descriptions will be omitted.

[0059] Figure 1a and Figure 1b 1 is a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure. Figure 1a and Figure 1b , a rod-type light emitting element LD having a cylindrical shape is shown, but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0060] refer to Figure 1a and Figure 1b, the light emitting element LD may include a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. For example, the light emitting element LD may be formed of a stacked body in which the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13 are sequentially stacked in one direction.

[0061] According to an embodiment, the light emitting element LD may be provided in a rod shape extending in one direction. The light emitting element LD may have a first end portion and a second end portion in one direction.

[0062] According to an embodiment, one of the first and second conductive semiconductor layers 11 and 13 may be disposed on the first end portion of the light emitting element LD, and the other of the first and second conductive semiconductor layers 11 and 13 may be disposed on the second end portion of the light emitting element LD.

[0063] According to an embodiment, the light emitting element LD may be a rod-type light emitting diode manufactured in a rod shape. Here, the rod shape includes a rod-like shape or a rod-like shape having a longitudinal length greater than a lateral length (i.e., having an aspect ratio greater than 1), such as a cylinder, a polygonal column, etc., and the shape of its cross section is not particularly limited. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0064] The first conductive semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer including one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant such as Si, Ge, Sn, etc. However, the material forming the first conductive semiconductor layer 11 is not limited thereto, and various materials other than these may also form the first conductive semiconductor layer 11.

[0065] The active layer 12 may be disposed on the first conductive semiconductor layer 11, and may be formed as a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on the active layer 12 and / or may be formed under the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. According to an embodiment, materials such as AlGaN, AlInGaN, etc. may be used to form the active layer 12, and various materials other than these may form the active layer 12.

[0066] When a voltage equal to or higher than the threshold voltage is applied to opposite ends of the light emitting element LD, electron-hole pairs are recombined in the active layer 12, whereby the light emitting element LD can emit light. The light emission of the light emitting element LD is controlled using this principle, whereby the light emitting element LD can be used as a light source for pixels of various light emitting devices and display devices.

[0067] The second conductive semiconductor layer 13 may be disposed on the active layer 12, and may include a semiconductor layer having a type different from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a p-type semiconductor layer including at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the material forming the second conductive semiconductor layer 13 is not limited thereto, and various materials other than these may form the second conductive semiconductor layer 13.

[0068] According to an embodiment, the light emitting element LD may further include an insulating film INF disposed on a surface thereof. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer peripheral surface of the active layer 12, and in addition to this, the insulating film INF may also surround a portion of the first conductive semiconductor layer 11 and a portion of the second conductive semiconductor layer 13. However, the insulating film INF may expose opposite ends of the light emitting element LD having different polarities. For example, the insulating film INF may expose, rather than cover, respective one ends of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 located at opposite ends of the light emitting element LD in the longitudinal direction, for example, two bases (i.e., the top surface and the bottom surface) of a cylinder.

[0069] According to an embodiment, the insulating film INF may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) and titanium oxide (TiO 2 ) is at least one insulating material, but is not limited thereto. That is, the material forming the insulating film INF is not particularly limited, and the insulating film INF can be formed of various insulating materials currently known.

[0070] In an embodiment, the light emitting element LD may further include additional components in addition to the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, and / or the insulating film INF. For example, the light emitting element LD may further include one or more fluorescent layers, active layers, semiconductor layers, and / or electrode layers disposed on one end of each of the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0071] Figure 2a and Figure 2b are a perspective view and a cross-sectional view showing a light emitting element according to another embodiment of the present disclosure. Figure 3a and Figure 3b are a perspective view and a cross-sectional view showing a light emitting element according to still another embodiment of the present disclosure.

[0072] refer to Figure 2a and Figure 2b The light emitting element LD may further include at least one electrode layer 14 disposed on one end portion of the second conductive semiconductor layer 13 .

[0073] refer to Figure 3a and Figure 3b The light emitting element LD may further include at least one additional electrode layer 15 disposed on one end portion of the first conductive semiconductor layer 11 .

[0074] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a conductive metal oxide, and may be formed of, for example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), its oxide, its alloy, a transparent electrode material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or zinc indium tin oxide (ITZO), etc. (the above materials alone or in combination). The electrode layers 14 and 15 may be substantially transparent or translucent. Therefore, the light generated in the light emitting element LD passes through the electrode layers 14 and 15 and is emitted from the light emitting element LD.

[0075] According to an embodiment, the insulating film INF may at least partially surround the outer peripheral surfaces of the electrode layers 14 and 15, or may not surround the outer peripheral surfaces of the electrode layers 14 and 15. That is, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different polarities, and may expose, for example, at least parts of the electrode layers 14 and 15. However, this is not limited thereto, and the insulating film INF may not be provided.

[0076] The insulating film INF is provided on the surface of the light emitting element LD, for example, on the surface of the active layer 12, thereby preventing the active layer 12 from being short-circuited with at least one electrode (for example, at least one of the contact electrodes connected to the opposite ends of the light emitting element LD), etc. Therefore, the electrical stability of the light emitting element LD can be ensured.

[0077] In addition, since the insulating film INF is formed on the surface of the light emitting element LD, defects on the surface of the light emitting element LD can be minimized, and the life and efficiency of the light emitting element LD can be improved. In addition, since the insulating film INF is formed on the surface of the light emitting element LD, even when a plurality of light emitting elements LD are disposed adjacent to each other, an undesirable short circuit between the light emitting elements LD can be prevented.

[0078] In an embodiment, the light emitting element LD may be manufactured after a surface treatment process (e.g., coating). For example, when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and supplied to each emission region (e.g., the emission region of each pixel), the light emitting elements LD may be uniformly distributed rather than unevenly aggregated in the solution. Here, the emission region is a region where light is emitted by the light emitting element LD, and may be different from a non-emission region where no light is emitted.

[0079] According to an embodiment, the insulating film INF itself is formed of a hydrophobic film using a hydrophobic material, or a hydrophobic film made of a hydrophobic material may be additionally formed on the insulating film INF. According to an embodiment, the hydrophobic material may be a material including fluorine to exhibit hydrophobic properties. In addition, according to an embodiment, a hydrophobic material in the form of a self-assembled monolayer (SAM) may be applied to the light emitting element LD. In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. In addition, the hydrophobic material may be a commercial material including fluorine, such as Teflon. TM or Cytop TM Or the corresponding materials.

[0080] The light-emitting device including the light-emitting element LD can be used in various devices and display devices that require a light source. For example, at least one ultra-small light-emitting element LD (for example, a plurality of ultra-small light-emitting elements LD each having a nanometer or micrometer size) is provided in each pixel region of the display panel, and the light source (or light source unit) of each pixel can be formed using the ultra-small light-emitting element LD. However, in the present disclosure, the application field of the light-emitting element LD is not limited to the display device. For example, the light-emitting element LD can also be used in other types of devices that require a light source, such as, lighting devices, etc.

[0081] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. According to an embodiment, Figure 4 The display device (specifically, the display panel PNL provided in the display device) is shown as a display device that can be used Figures 1a to 3b According to the embodiment, in Figure 4The structure of the display panel PNL is simply shown with emphasis on the display area DA. However, according to an embodiment, although not shown, at least one driving circuit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further provided in the display panel PNL.

[0082] refer to Figure 4 The display panel PNL may include a first substrate SUB1 (or base layer) and pixels PXL disposed on the first substrate SUB1. Specifically, the display panel PNL and the first substrate SUB1 may include a display area DA in which an image is displayed and a non-display area NDA except the display area DA.

[0083] According to an embodiment, the display area DA may be disposed in the central area of ​​the display panel PNL, and the non-display area NDA may be disposed along the edge of the display panel PNL to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may vary.

[0084] The first substrate SUB1 may configure a base member of the display panel PNL. For example, the first substrate SUB1 may configure a base member of a lower panel (eg, a lower plate of the display panel PNL).

[0085] According to an embodiment, the first substrate SUB1 may be a rigid substrate or a flexible substrate, and its material and properties are not particularly limited. For example, the first substrate SUB1 may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the first substrate SUB1 may be a transparent substrate, but is not limited thereto. For example, the first substrate SUB1 may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0086] One area on the first substrate SUB1 is defined as a display area DA in which the pixels PXL are disposed, and the remaining area is defined as a non-display area NDA. For example, the first substrate SUB1 may include a display area DA including a plurality of pixel areas in which the pixels PXL are formed, and a non-display area NDA disposed around the display area DA. Various lines and / or embedded circuits connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA.

[0087] The pixel PXL may include at least one light emitting element LD driven by corresponding scan signals and data signals, for example, according to Figures 1a to 3b At least one rod-type light emitting diode of any one of the embodiments of the present invention. For example, the pixel PXL may include a plurality of rod-type light emitting diodes having a small size ranging from nanometer level to micrometer level and connected in parallel to each other. The plurality of rod-type light emitting diodes may form a light source of the pixel PXL.

[0088] In addition, the pixel PXL may include a plurality of sub-pixels. For example, the pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0089] According to an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may emit light of different colors. For example, the first sub-pixel SPX1 may be a red sub-pixel emitting red light, the second sub-pixel SPX2 may be a green sub-pixel emitting green light, and the third sub-pixel SPX3 may be a blue sub-pixel emitting blue light. However, the color, type, and / or number of sub-pixels forming the pixel PXL are not particularly limited, and, for example, the color of light emitted by each of the sub-pixels may be changed differently. In addition, in Figure 4 2 shows an embodiment in which the pixels PXL are arranged in the display area DA in a stripe form, but the present disclosure is not limited thereto. For example, the pixels PXL may be arranged to have various pixel arrangement forms currently known.

[0090] In an embodiment, the pixel PXL (or each of the sub-pixels) may be formed by an active pixel. However, the type, structure and / or driving method of the pixel PXL applicable to the display device of the present disclosure are not particularly limited. For example, the pixel PXL may be formed by a pixel of a display device having various currently known passive or active structures.

[0091] Figure 5a to Figure 5c It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a display device. Figure 5a to Figure 5c The sub-pixel SPX shown in FIG. 1 may be arranged in Figure 4 Any one of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 in the display panel PNL, and the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have substantially the same or similar structures. Therefore, the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 are Figure 5a to Figure 5c They are collectively referred to as sub-pixels SPX.

[0092] First, refer to Figure 5a The sub-pixel SPX includes a light source unit LSU configured to emit light having a brightness corresponding to the data signal. In addition, the sub-pixel SPX may further selectively include a pixel circuit PXC for driving the light source unit LSU.

[0093] According to an embodiment, the light source unit LSU may include a plurality of light emitting elements LD electrically connected between a first power source VDD and a second power source VSS. In an embodiment, the light emitting elements LD may be connected in parallel with each other, but are not limited thereto. For example, the plurality of light emitting elements LD may be connected between the first power source VDD and the second power source VSS in a series-parallel combination structure.

[0094] The first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD can emit light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, at least during the emission period of the sub-pixel SPX, the potential difference between the first power supply VDD and the second power supply VSS may be set to be equal to or higher than the threshold voltage of the light emitting element LD.

[0095] At the same time, Figure 5a , an embodiment in which the light emitting elements LD are connected in parallel with each other in the same direction (e.g., forward direction) between the first power supply VDD and the second power supply VSS, is shown, but the present disclosure is not limited thereto. For example, some of the light emitting elements LD are connected between the first power supply VDD and the second power supply VSS in the forward direction and form each effective light source, and other light emitting elements LD may be connected in the reverse direction. In another example, at least one sub-pixel SPX may include only a single light emitting element LD (e.g., a single effective light source connected between the first power supply VDD and the second power supply VSS in the forward direction).

[0096] According to an embodiment, the first end of each light emitting element LD may be commonly coupled to the corresponding pixel circuit PXC through the first electrode, and may be commonly coupled to the first power supply VDD through the pixel circuit PXC and the first power line PL1. The second end of each light emitting element LD may be commonly coupled to the second power supply VSS through the second electrode and the second power line PL2.

[0097] The light source unit LSU may emit light having brightness corresponding to the driving current supplied through the corresponding pixel circuit PXC. Thus, a predetermined image may be displayed in the display area DA.

[0098] The pixel circuit PXC may be coupled to the scan line Si and the data line Dj of the corresponding sub-pixel SPX. For example, when the sub-pixel SPX is disposed in the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the sub-pixel SPX may be coupled to the i-th scan line Si and the j-th data line Dj of the display area DA. The pixel circuit PXC may include first and second transistors T1 and T2 and a storage capacitor Cst.

[0099] The first transistor T1 (or driving transistor) may be coupled between the first power source VDD and the light source unit LSU. A gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control a driving current supplied to the light source unit LSU in response to a voltage of the first node N1.

[0100] The second transistor T2 (or the switching transistor) may be coupled between the data line Dj and the first node N1. A gate electrode of the second transistor T2 may be coupled to the scan line Si.

[0101] The second transistor T2 is turned on in response to a scan signal having a gate-on voltage (eg, a low voltage) from the scan line Si, thereby electrically coupling the data line Dj to the first node N1.

[0102] For each frame period, a data signal of a corresponding frame is supplied to the data line Dj, and the data signal may be transmitted to the first node N1 via the second transistor T2. Therefore, the storage capacitor Cst may be charged with a voltage corresponding to the data signal.

[0103] A first electrode of the storage capacitor Cst may be coupled to the first power source VDD, and a second electrode of the storage capacitor Cst may be coupled to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal supplied to the first node N1 during each frame period, and may maintain the charged voltage until a data signal of a next frame is supplied.

[0104] At the same time, all transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are Figure 5a , but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0105] For example, Figure 5b As shown in FIG. 1 , all of the first transistor T1 and the second transistor T2 may be N-type transistors. In this case, the gate-on voltage of the scanning signal for writing the data signal supplied to the data line Dj to the sub-pixel SPX in each frame period may be a high-level voltage. Similarly, the voltage of the data signal for turning on the first transistor T1 may be a voltage having a voltage with a value similar to that of FIG. Figure 5a The waveform of the voltage in the embodiment is opposite to the waveform of the voltage. For example, in Figure 5b In the embodiment, as the grayscale value to be represented is larger, a data signal having a higher voltage level may be supplied.

[0106] In addition to the locations where some circuit elements are connected and the voltage levels of control signals (eg, scan signals and data signals) are changed according to the types of transistors, Figure 5bThe sub-pixel SPX shown in FIG. 1 is similar in configuration and operation to the Figure 5a The sub-pixels SPX are basically similar. For example, Figure 5b In the sub-pixel SPX shown in FIG. 1 , the light emitting unit LSU is connected between the first power source VDD and the first electrode of the first transistor T1, the first transistor T1 is connected between the light emitting unit LSU and the second power source VSS, and the storage capacitor Cst is connected between the first node N1 and the second electrode of the first transistor T1. Therefore, the description of Figure 5b Detailed description of the sub-pixel SPX.

[0107] Meanwhile, the structure of the pixel circuit PXC is not limited to Figure 5a and Figure 5b That is, the pixel circuit PXC may be formed by a pixel circuit having various structures and / or driving methods currently known. For example, the pixel circuit PXC may be formed by Figure 5c The embodiment shown in FIG.

[0108] refer to Figure 5c , in addition to the corresponding scan line Si, the pixel circuit PXC may also be coupled to at least one additional scan line (or control line). For example, the pixel circuit PXC of the sub-pixel SPX disposed in the i-th row of the display area DA may also be coupled to the (i-1)th scan line Si-1 and / or the (i+1)th scan line Si+1. In addition, according to an embodiment, the pixel circuit PXC may also be coupled to a power source other than the first power source VDD and the second power source VSS. For example, the pixel circuit PXC may also be coupled to an initialization power source Vint. According to an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0109] The first transistor T1 may be coupled between the first power source VDD and the light source unit LSU. The first electrode (e.g., source electrode) of the first transistor T1 may be coupled to the first power source VDD through the fifth transistor T5 and the first power line PL1, and the second electrode (e.g., drain electrode) of the first transistor T1 may be coupled to the first electrode of the light source unit LSU (e.g., the first electrode of the corresponding sub-pixel SPX) via the sixth transistor T6. The gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control the driving current supplied to the light source unit LSU in response to the voltage of the first node N1.

[0110] The second transistor T2 may be coupled between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be coupled to the corresponding scan line Si. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the scan line Si, the second transistor T2 is turned on, thereby electrically coupling the data line Dj to the first electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the data line Dj may be transmitted to the first transistor T1 (e.g., the first transistor T1 may be diode-connected).

[0111] The third transistor T3 may be coupled between the second electrode (e.g., drain electrode) of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be coupled to the corresponding scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the third transistor T3 is turned on, thereby coupling the first transistor T1 in a diode form.

[0112] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be coupled to a previous scan line, for example, the (i-1)th scan line Si-1. When a scan signal having a gate-on voltage is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 is turned on, thereby transmitting the voltage of the initialization power supply Vint to the first node N1. Here, the voltage of the initialization power supply Vint may be equal to or lower than the lowest voltage of the data signal.

[0113] The fifth transistor T5 may be coupled between the first power supply VDD and the first transistor T1. A gate electrode of the fifth transistor T5 may be coupled to a corresponding emission control line, for example, the i-th emission control line Ei. When an emission control signal having a gate-off voltage (for example, a high voltage) is supplied to the emission control line Ei, the fifth transistor T5 is turned off, and when an emission control signal having a gate-on voltage (for example, a low voltage) is supplied to the emission control line Ei, the fifth transistor T5 may be turned on.

[0114] The sixth transistor T6 may be coupled between the first transistor T1 and the first electrode of the light source unit LSU. A gate electrode of the sixth transistor T6 may be coupled to a corresponding emission control line, for example, an i-th emission control line Ei. When an emission control signal having a gate-off voltage is supplied to the emission control line Ei, the sixth transistor T6 is turned off, and when an emission control signal having a gate-on voltage (for example, a low voltage) is supplied to the emission control line Ei, the sixth transistor T6 may be turned on.

[0115] The seventh transistor T7 may be coupled between the first electrode of the light source unit LSU and the initialization power supply Vint. The gate electrode of the seventh transistor T7 may be coupled to any one of the scan lines of the next stage, for example, the (i+1)th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the (i+1)th scan line Si+1, the seventh transistor T7 is turned on, thereby supplying the voltage of the initialization power supply Vint to the first electrode of the light source unit LSU. In this case, for each initialization period during which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode of the light source unit LSU may be initialized.

[0116] The control signal for controlling the operation of the seventh transistor T7 may be changed variously. For example, the gate electrode of the seventh transistor T7 is alternatively coupled to the scan line of the corresponding horizontal line, that is, the i-th scan line Si. In this case, when the scan signal having the gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 is turned on, thereby supplying the voltage of the initialization power supply Vint to the first electrode of the light source unit LSU.

[0117] The storage capacitor Cst may be coupled between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal supplied to the first node N1 in each frame period and a threshold voltage of the first transistor T1.

[0118] At the same time, all transistors (eg, the first transistor T1 to the seventh transistor T7) included in the pixel circuit PXC are turned on. Figure 5c , but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0119] In addition, the structure of the sub-pixel SPX applicable to the present disclosure is not limited to Figure 5a to Figure 5c , and the sub-pixel SPX may have various structures currently known. For example, the pixel circuit PXC included in the sub-pixel SPX may be formed by a pixel circuit having various structures and / or driving methods currently known. In addition, the sub-pixel SPX may be formed in a passive light emitting display device or the like. In this case, the pixel circuit PXC is omitted, and each of the first electrode and the second electrode of the light source unit LSU may be directly connected to the scan line Si, the data line Dj, the power line, and / or the control line.

[0120] Figure 6 It is shown Figure 4 A cross-sectional view of an example of a display device.

[0121] refer to Figure 6 , display device (or Figure 4The display panel PNL) may include a first substrate SUB1, a light emitting element layer LDL (or a display element layer), a pixel circuit layer PCL (or a circuit element layer), and a second substrate SUB2. Hereinafter, a surface of the display device on which an image is displayed (e.g., the second substrate SUB2) is defined as an upper surface, and another surface facing the upper surface (e.g., the first substrate SUB1) is defined as a lower surface. In this case, the third direction DR3 may be a direction from the lower surface to the upper surface of the display device, that is, a direction toward the upper portion of the display device.

[0122] The light emitting element layer LDL may be disposed on the first substrate SUB1, the pixel circuit layer PCL may be disposed on the light emitting element layer LDL, and the second substrate SUB2 may be disposed on the pixel circuit layer PCL. Here, the light emitting element layer LDL may include a reference Figure 5a to Figure 5c The light source unit LSU (or light emitting element LD) described above, and the pixel circuit layer PCL may include reference Figure 5a to Figure 5c A pixel circuit PXC is described.

[0123] As will be described later, the first substrate SUB1 and the light emitting element layer LDL may form a first panel STR1 (or a first structure, a lower panel), and the pixel circuit layer PCL and the second substrate SUB2 may form a second panel STR2 (or a second structure, an upper panel). The first panel STR1 and the second panel STR2 may be manufactured independently of each other and may be formed into a single display device by a bonding process.

[0124] Hereinafter, the first panel STR1 , the second panel STR2 , and the display panel PNL in which the first panel STR1 and the second panel STR2 are combined will be described in sequence.

[0125] Figure 7 It is shown that the Figure 6 A plan view of an example of a first panel in a display device. Figure 7 In, based on and included in Figure 4 The light emitting element layer LDL corresponding to the sub-pixel SPX (for example, the first sub-pixel SPX1) in the display device shows the structure of the sub-pixel SPX.

[0126] refer to Figure 7 , the sub-pixel SPX may include first and second electrodes ELT1 and ELT2 disposed to be spaced apart from each other in the sub-pixel area SPA, and at least one light emitting element LD coupled between the first and second electrodes ELT1 and ELT2.

[0127] According to an embodiment, the first electrode ELT1 and the second electrode ELT2 may be arranged to be spaced apart from each other in the sub-pixel area SPA, and may be arranged so that they at least partially face each other. For example, the first electrode ELT1 and the second electrode ELT2 may extend along the first direction DR1, respectively, and may be parallel to each other while being spaced apart from each other by a predetermined distance along the second direction DR2, and the second direction DR2 is substantially perpendicular to or intersects the first direction DR1. However, the present disclosure is not limited thereto. For example, the shape and / or arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed variously.

[0128] The first electrode ELT1 may be electrically coupled to a first connection electrode CONT1 (or a first connection line) extending in the second direction DR2. The first connection electrode CONT1 may be coupled to a reference electrode. Figure 5a to Figure 5c The pixel circuit PXC (eg, the first transistor T1 ) is described.

[0129] The second electrode ELT2 may be electrically coupled to a second connection electrode CONT2 (or a second connection line) extending in the second direction DR2. The second connection electrode CONT2 extends to an adjacent sub-pixel (eg, based on the reference Figure 4 The first sub-pixel SPX1 described above extends to the second sub-pixel SPX2 and the third sub-pixel SPX3), and may also extend to the non-display area NDA (see Figure 4 ).

[0130] The sub-pixel area SPA may include an emission area EMA in which at least one pair of first and second electrodes ELT1 and ELT2 and at least one light emitting element LD coupled between the first and second electrodes ELT1 and ELT2 are disposed. According to an embodiment, the emission area EMA is a unit area that emits light of a single color, which is different from an emission area in which light of another single color is emitted, and may be formed by a bank described later (see Fig.12 ) etc. to limit.

[0131] According to an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer structure or a multi-layer structure. For example, the first electrode ELT1 may have a multi-layer structure including a first reflective electrode and a first conductive capping layer, and the second electrode ELT2 may have a multi-layer structure including a second reflective electrode and a second conductive capping layer.

[0132] According to an embodiment, the first electrode ELT1 may be coupled to the first connection electrode CONT1. The first electrode ELT1 may be integrally coupled to the first connection electrode CONT1. For example, the first electrode ELT1 may be formed as at least one branch deviating from the first connection electrode CONT1. When the first electrode ELT1 and the first connection electrode CONT1 are formed as a single body, the first connection electrode CONT1 may be considered as a part of the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the first electrode ELT1 and the first connection electrode CONT1 are separately formed and may be electrically coupled to each other through at least one contact hole or through hole not shown.

[0133] According to an embodiment, the first connection electrode CONT1 may have a single-layer structure or a multi-layer structure. For example, the first connection electrode CONT1 may include a first sub-connection electrode integrally coupled to the first reflective electrode of the first electrode ELT1 and a second sub-connection electrode integrally coupled to the first conductive capping layer of the first electrode ELT1. According to an embodiment, the first connection electrode CONT1 may have the same cross-sectional structure (or stacked structure) as the first electrode ELT1, but is not limited thereto.

[0134] According to an embodiment, the second electrode ELT2 may be coupled to the second connection electrode CONT2. For example, the second electrode ELT2 may be integrally coupled to the second connection electrode CONT2. For example, the second electrode ELT2 may be formed as at least one branch deviating from the second connection electrode CONT2. When the second electrode ELT2 and the second connection electrode CONT2 are formed as a single body, the second connection electrode CONT2 may be considered as part of the second electrode ELT2. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the second electrode ELT2 and the second connection electrode CONT2 are separately formed and may be electrically coupled to each other through at least one contact hole or through hole not shown.

[0135] According to an embodiment, similar to the first connection electrode CONT1 , the second connection electrode CONT2 may have a single-layer structure or a multi-layer structure.

[0136] The first embankment pattern PW1 may be disposed under the first electrode ELT1 while overlapping a portion of the first electrode ELT1, and the second embankment pattern PW2 may be disposed under the second electrode ELT2 while overlapping a portion of the second electrode ELT2. The first embankment pattern PW1 and the second embankment pattern PW2 are disposed to be spaced apart from each other in the emission area EMA, and portions of the first electrode ELT1 and the second electrode ELT2 may be made to protrude in an upward direction. For example, the first electrode ELT1 may be disposed on the first embankment pattern PW1, and thereby protrude in a direction of a height of the first substrate SUB1 (or in a third direction DR3 (thickness direction)) through the first embankment pattern PW1, and the second electrode ELT2 may be disposed on the second embankment pattern PW2, and thereby protrude in a direction of a height of the first substrate SUB1 through the second embankment pattern PW2.

[0137] The third bank pattern PW3 may be disposed under the first and second connection electrodes CONT1 and CONT2 while overlapping the first and second connection electrodes CONT1 and CONT2. The third bank pattern PW3 may protrude portions of the first and second connection electrodes CONT1 and CONT2 in an upward direction (or in the third direction DR3).

[0138] In an embodiment, a width W1 of each of the first connection electrode CONT1 and the second connection electrode CONT2 (e.g., a width of the first connection electrode CONT1 and the second connection electrode CONT2 in the first direction DR1) may be greater than a width of each of the first electrode ELT1 and the second electrode ELT2 (e.g., a width of each of the first electrode ELT1 and the second electrode ELT2 in the second direction DR2).

[0139] As will be described later, the first and second connection electrodes CONT1 and CONT2 are in direct contact with the pixel circuit layer PCL of the second panel STR2 through a bonding process, and each of the first and second connection electrodes CONT1 and CONT2 may have a relatively large width so that even when the reference Figure 6 When an alignment error occurs between the first panel STR1 and the second panel STR2 as described above, the first connection electrode CONT1 and the second connection electrode CONT2 are also coupled to the pixel circuit layer PCL of the second panel STR2. For example, because each of the first connection electrode CONT1 and the second connection electrode CONT2 has a relatively large width, the total area occupied by the first connection electrode CONT1 and the second connection electrode CONT2 in the sub-pixel area SPA may be larger than the area occupied by the pixel circuit PXC (see Figure 5a ) occupies an area in the pixel circuit layer PCL and may cover the pixel circuit PXC in a plan view.

[0140] At the same time, Figure 7 , the light emitting element LD is shown to be aligned between the first electrode ELT1 and the second electrode ELT2 in the second direction DR2 (eg, in the horizontal direction), but the direction in which the light emitting element LD is arranged is not limited thereto. For example, at least one of the light emitting elements LD may be arranged in a diagonal direction.

[0141] Each of the light emitting elements LD may be electrically coupled between the first electrode ELT1 and the second electrode ELT2 of the subpixel SPX. For example, a first end of each of the light emitting elements LD may be electrically coupled to the first electrode ELT1, and a second end of each of the light emitting elements LD may be electrically coupled to the second electrode ELT2.

[0142] In an embodiment, the first end of each of the light emitting elements LD may be electrically coupled to the first electrode ELT1 via at least one contact electrode (e.g., the first contact electrode CNE1) rather than being directly disposed on the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the first end of the light emitting element LD is in direct contact with the first electrode ELT1, thereby being electrically coupled to the first electrode ELT1.

[0143] Similarly, the second end of each of the light emitting elements LD may be electrically coupled to the second electrode ELT2 via at least one contact electrode (e.g., the second contact electrode CNE2) rather than being directly disposed on the second electrode ELT2. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the second end of each of the light emitting elements LD is in direct contact with the second electrode ELT2, thereby being electrically coupled to the second electrode ELT2.

[0144] According to an embodiment, each of the light emitting elements LD may be a light emitting diode using a material of an inorganic crystal structure and having an ultra-small size (eg, a small size ranging from a nanometer scale to a micrometer scale). Figures 1a to 3b The ultra-small rod-type light-emitting diode shown in any one of the above, having a size ranging from nanometer to micrometer. However, the type of light-emitting element LD applicable to the present disclosure is not limited thereto. For example, the light-emitting element LD is formed using a growth method, and the light-emitting element LD may be, for example, a light-emitting diode of a core-shell structure having a size ranging from nanometer to micrometer.

[0145] According to an embodiment, the light emitting element LD may be prepared in a dispersed form in a predetermined solution, and then supplied to the emission area EMA of each sub-pixel SPX by an inkjet printing method, a slit coating method, or the like. For example, the light emitting element LD may be supplied to the emission area EMA in a state where it is mixed with a volatile solvent. Here, when a predetermined voltage is supplied to the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light emitting element LD is self-aligned between the first electrode ELT1 and the second electrode ELT2. After the light emitting element LD is aligned, the solvent is removed by volatilizing the solvent or using another method, whereby the light emitting element LD can be stably arranged between the first electrode ELT1 and the second electrode ELT2. In addition, the first contact electrode CNE1 and the second contact electrode CNE2 are formed on the first end and the second end of the light emitting element LD, whereby the light emitting element LD can be stably connected between the first electrode ELT1 and the second electrode ELT2.

[0146] Since neither circuit elements nor wires are disposed between the first substrate SUB1 and the first and second electrodes ELT1 and ELT2, when an electric field is formed between the first and second electrodes ELT1 and ELT2, interference caused by circuit elements, conductive patterns, etc. can be eliminated. Therefore, the efficiency of alignment of the light emitting element LD can be relatively improved.

[0147] According to an embodiment, the first contact electrode CNE1 is formed on the first end portion of the light emitting element LD and at least a portion of the first electrode ELT1 corresponding thereto, thereby physically and / or electrically coupling the first end portion of the light emitting element LD to the first electrode ELT1. Similarly, the second contact electrode CNE2 is formed on the second end portion of the light emitting element LD and at least a portion of the second electrode ELT2 corresponding thereto, thereby physically and / or electrically coupling the second end portion of the light emitting element LD to the second electrode ELT2.

[0148] The light emitting elements LD disposed in the sub-pixel area SPA are gathered to form a light source of the corresponding sub-pixel SPX. For example, when a driving current flows into at least one sub-pixel SPX during each frame period, the light emitting element LD coupled between the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX in the forward direction emits light, thereby emitting light having a brightness corresponding to the driving current.

[0149] Figures 8a to 8d It is shown along Figure 7 A cross-sectional view of an example of the first panel taken along line II'. Figures 8a to 8dIn FIG. 1 , any one sub-pixel region SPA (eg, first sub-pixel region SPA1) formed on the first panel STR1 is shown. According to an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have substantially the same or similar cross-sectional structures. Figures 8a to 8d In order to facilitate description, the structure of the sub-pixel SPX including the first sub-pixel SPX1, the second sub-pixel SPX2 and the third sub-pixel SPX3 will be described emphatically.

[0150] First, refer to Figure 8a , the light emitting element layer LDL may be disposed on the first substrate SUB1. According to an embodiment, the light emitting element layer LDL may be formed in the entire display area DA of the display panel PNL. For example, the light emitting element layer LDL may be formed on one surface of the first substrate SUB1.

[0151] The light emitting element layer LDL may include a first embankment pattern PW1, a second embankment pattern PW2, and a third embankment pattern PW3, first and second electrodes ELT1 and ELT2, a first insulating layer INS1, a light emitting element LD, a second insulating layer INS2, first and second contact electrodes CNE1 and CNE2, and a third insulating layer INS3, which are sequentially arranged and / or formed on a first substrate SUB1.

[0152] The first bank pattern PW1 and the second bank pattern PW2 may be disposed on the first substrate SUB1 in the emission area EMA. The first bank pattern PW1 and the second bank pattern PW2 may be disposed to be spaced apart from each other in the emission area EMA.

[0153] The third bank pattern PW3 may be disposed on the first substrate SUB1 in the non-emission areas NEMA1 and NEMA2. The third bank pattern PW3 is spaced apart from the first and second bank patterns PW1 and PW2, but is not limited thereto.

[0154] The first dam pattern PW1, the second dam pattern PW2, and the third dam pattern PW3 may protrude in the third direction DR3 (i.e., in the height direction) on the first substrate SUB1. According to an embodiment, the first dam pattern PW1 and the second dam pattern PW2 may have substantially the same height, but are not limited thereto. For example, the third dam pattern PW3 may have a height greater than that of the first dam pattern PW1 and the second dam pattern PW2.

[0155] According to an embodiment, the first embankment pattern PW1 may be disposed between the first substrate SUB1 and the first electrode ELT1. The first embankment pattern PW1 may be disposed adjacent to the first end portion EP1 of the light emitting element LD. For example, one side surface of the first embankment pattern PW1 is located at a certain distance close to the first end portion EP1 of the light emitting element LD and may be disposed to face the first end portion EP1.

[0156] According to an embodiment, the second embankment pattern PW2 may be disposed between the first substrate SUB1 and the second electrode ELT2. The second embankment pattern PW2 may be disposed adjacent to the second end EP2 of the light emitting element LD. For example, one side surface of the second embankment pattern PW2 is located at a certain distance close to the second end EP2 of the light emitting element LD and may be disposed to face the second end EP2.

[0157] According to an embodiment, the third bank pattern PW3 may be disposed between the first substrate SUB1 and the first electrode ELT1 in the first non-emission area NEMA1, and may be disposed between the first substrate SUB1 and the second electrode ELT2 in the second non-emission area NEMA2.

[0158] According to the implementation mode, Figure 8a As shown in , the first embankment pattern PW1, the second embankment pattern PW2, and the third embankment pattern PW3 may have various shapes. For example, the first embankment pattern PW1 and the second embankment pattern PW2 may have a trapezoidal cross-sectional shape whose width decreases as it approaches its top. In this case, each of the first embankment pattern PW1 and the second embankment pattern PW2 may have a slope in at least one side surface thereof. In another example, as Figure 8b As shown in , the first embankment pattern PW1 and the second embankment pattern PW2 may have a semicircular or semi-elliptical cross-section whose width decreases as it approaches its top. In this case, each of the first embankment pattern PW1 and the second embankment pattern PW2 may have a curved surface in at least one side surface thereof. That is, the shapes of the first embankment pattern PW1, the second embankment pattern PW2, and the third embankment pattern PW3 are not particularly limited in the present disclosure and may be variously changed. In addition, according to the embodiment, at least one of the first embankment pattern PW1 and the second embankment pattern PW2 may be omitted, or its position may be changed.

[0159] Reference again Figure 8a The first bank pattern PW1, the second bank pattern PW2 and the third bank pattern PW3 may include an insulating material, and the insulating material includes an inorganic material and / or an organic material. For example, the first bank pattern PW1, the second bank pattern PW2 and the third bank pattern PW3 may include at least one layer of an inorganic film, and the inorganic film includes various inorganic insulating materials currently known, such as SiN x 、SiO x Etc. Alternatively, the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may include at least one layer of an organic film including various organic insulating materials and / or photoresist films known at present, or may be formed of a single-layer insulator or a multi-layer insulator compositely including organic materials / inorganic materials. That is, the materials forming the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may be changed variously.

[0160] In an embodiment, the first and second bank patterns PW1 and PW2 may be used as reflective members. For example, the first and second bank patterns PW1 and PW2 and the first and second electrodes ELT1 and ELT2 disposed thereon may be used as reflective members, thereby improving the light efficiency of the pixel PXL by guiding the light emitted from the corresponding light emitting element LD to travel in a desired direction.

[0161] The first electrode ELT1 and the second electrode ELT2 may be disposed on the first bank pattern PW1 and the second bank pattern PW2, respectively. The first electrode ELT1 and the second electrode ELT2 may be disposed to be spaced apart from each other in the emission area EMA. In addition, the first electrode ELT1 and the second electrode ELT2 (or the first connection electrode CONT1 and the second connection electrode CONT2, see Figure 7 ) may be disposed on the third bank pattern PW3.

[0162] According to an embodiment, the first electrode ELT1 and the second electrode ELT2 respectively disposed on the first bank pattern PW1 and the second bank pattern PW2 may have shapes corresponding to the corresponding shapes of the first bank pattern PW1 and the second bank pattern PW2. For example, the first electrode ELT1 and the second electrode ELT2 may protrude in the direction of the height of the light emitting element layer LDL (or in the thickness direction) while having an inclined surface or a curved surface corresponding to the first bank pattern PW1 and the second bank pattern PW2, respectively. Similarly, the first electrode ELT1 and the second electrode ELT2 disposed on the third bank pattern PW3 may have a shape corresponding to the shape of the third bank pattern PW3.

[0163] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one material of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti) and an alloy thereof, a conductive oxide (such as ITO, IZO, ZnO and ITZO) and a conductive polymer (such as PEDOT), but is not limited thereto.

[0164] In addition, each of the first electrode ELT1 and the second electrode ELT2 may be formed of a single layer or multiple layers. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one reflective electrode layer. In addition, each of the first electrode ELT1 and the second electrode ELT2 may also selectively include at least one of at least one transparent electrode layer and at least one conductive capping layer, wherein at least one transparent electrode layer is disposed on the reflective electrode layer and / or under the reflective electrode layer, and at least one conductive capping layer covers the upper portion of the transparent electrode layer and / or the reflective electrode layer.

[0165] According to an embodiment, the reflective electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be made of a conductive material having uniform reflectivity. For example, the reflective electrode layer may include at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr) and an alloy thereof, but is not limited thereto. That is, the reflective electrode layer may be made of various reflective conductive materials. When each of the first electrode ELT1 and the second electrode ELT2 includes a reflective electrode layer, light emitted from the opposite ends of each of the light emitting elements LD (i.e., the first end EP1 and the second end EP2) may be further advanced in the direction in which an image is displayed (e.g., in the forward direction). Specifically, when the first electrode ELT1 and the second electrode ELT2 are disposed to face the first end EP1 and the second end EP2 of the light emitting element LD while having an inclined surface or a curved surface corresponding to the shape of the first dyke pattern PW1 and the second dyke pattern PW2, light emitted from the first end EP1 and the second end EP2 of each of the light emitting elements LD can be further traveled in the third direction DR3 (i.e., in the forward direction of the display panel PNL) by being reflected by the first electrode ELT1 and the second electrode ELT2. Therefore, the efficiency of the light emitted from the light emitting element LD can be improved.

[0166] In addition, the transparent electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be made of various transparent electrode materials. For example, the transparent electrode layer may include ITO, IZO or ITZO, but is not limited thereto. In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may be formed of three layers having a stacked structure of ITO / Ag / ITO. As described above, when the first electrode ELT1 and the second electrode ELT2 are formed of a multilayer including at least two layers, the voltage drop caused by the signal delay (RC delay) may be minimized. Therefore, the desired voltage may be efficiently transmitted to the light emitting element LD.

[0167] In addition, when each of the first electrode ELT1 and the second electrode ELT2 includes a conductive capping layer configured to cover the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer of the first electrode ELT1 and the second electrode ELT2, etc., can be prevented from being damaged due to defects caused in the process of manufacturing the pixel PXL, etc. However, the conductive capping layer may be selectively included in the first electrode ELT1 and the second electrode ELT2, and may be omitted according to the embodiment. In addition, the conductive capping layer may be considered as a component of each of the first electrode ELT1 and the second electrode ELT2, or may be considered as a separate component provided on the first electrode ELT1 and the second electrode ELT2.

[0168] The first insulating layer INS1 may be disposed on portions of the first and second electrodes ELT1 and ELT2. For example, the first insulating layer INS1 may be formed to cover portions of the first and second electrodes ELT1 and ELT2, and may include openings exposing other portions of the first and second electrodes ELT1 and ELT2.

[0169] In an embodiment, the first insulating layer INS1 may be first formed to completely cover the first electrode ELT1 and the second electrode ELT2. Figure 8a As shown in , after the light emitting element LD is supplied to the first insulating layer INS1 between the first electrode ELT1 and the second electrode ELT2 and aligned on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose the first electrode ELT1 and the second electrode ELT2 in the predetermined first contact portion and the second contact portion. Alternatively, after the supply and alignment of the light emitting element LD are completed, the first insulating layer INS1 may be patterned in the form of a separate pattern locally disposed under the light emitting element LD.

[0170] That is, the first insulating layer INS1 is interposed between the first and second electrodes ELT1 and ELT2 and the light emitting element LD, and may expose at least a portion of each of the first and second electrodes ELT1 and ELT2. After forming the first and second electrodes ELT1 and ELT2, the first insulating layer INS1 is formed to cover the first and second electrodes ELT1 and ELT2, thereby preventing the first and second electrodes ELT1 and ELT2 from being damaged or preventing metal from being extracted in a subsequent process. In addition, the first insulating layer INS1 may stably support the corresponding light emitting element LD. According to an embodiment, the first insulating layer INS1 may be omitted.

[0171] In the emission area EMA in which the first insulating layer INS1 is formed, the light emitting element LD may be supplied and aligned. For example, the light emitting element LD may be supplied to the emission area EMA by an inkjet method or the like, and the light emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2 by a predetermined alignment voltage (or alignment signal) applied to the first electrode ELT1 and the second electrode ELT2. In order to align the light emitting element LD, a reference voltage (for example, a ground voltage) may be applied to the first electrode ELT1, and an AC voltage (or alignment voltage) may be applied to the second electrode ELT2. In this case, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light emitting element LD may be self-aligned between the first electrode ELT1 and the second electrode ELT2 in the emission area EMA.

[0172] The second insulating layer INS2 is disposed on the light emitting element LD (specifically, the light emitting element LD aligned between the first electrode ELT1 and the second electrode ELT2) to expose the first end EP1 and the second end EP2 of the light emitting element LD. For example, the second insulating layer INS2 may be only partially disposed on a portion of the light emitting element LD without covering the first end EP1 and the second end EP2 of the light emitting element LD. The second insulating layer INS2 may be formed as an independent pattern in each emission area EMA, but is not limited thereto. In addition, as Figure 8a As shown in FIG. 1 , when there is a gap space between the first insulating layer INS1 and the light emitting element LD before forming the second insulating layer INS2 , the space may be filled with the second insulating layer INS2 . Therefore, the light emitting element LD may be supported more stably.

[0173] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the first electrode ELT1 and the second electrode ELT2 and the first end portion EP1 and the second end portion EP2 of the light emitting element LD. Figure 8a As shown in , the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed in the same process using the same conductive material, but are not limited thereto.

[0174] The first and second contact electrodes CNE1 and CNE2 may electrically couple the first and second end portions EP1 and EP2 of the light emitting element LD to the first and second electrodes ELT1 and ELT2 , respectively.

[0175] For example, the first contact electrode CNE1 may be disposed on the first electrode ELT1 to contact the first electrode ELT1. For example, the first contact electrode CNE1 may be disposed on a portion of the first electrode ELT1 that is not covered by the first insulating layer INS1 (e.g., a first contact portion) to contact the first electrode ELT1. In addition, in order to make the first contact electrode CNE1 contact at least one light emitting element LD (e.g., a first end portion EP1 of a plurality of light emitting elements LD adjacent to the first electrode ELT1), the first contact electrode CNE1 may be disposed on the first end portion EP1. That is, the first contact electrode CNE1 may be disposed to cover the first end portion EP1 of the light emitting element LD and at least a portion of the first electrode ELT1 corresponding thereto. Therefore, the first end portion EP1 of the light emitting element LD may be electrically coupled to the first electrode ELT1.

[0176] Similarly, the second contact electrode CNE2 may be disposed on the second electrode ELT2 to contact the second electrode ELT2. For example, the second contact electrode CNE2 may be disposed on a portion of the second electrode ELT2 that is not covered by the first insulating layer INS1 (e.g., a second contact portion) to contact the second electrode ELT2. In addition, in order to make the second contact electrode CNE2 contact at least one light emitting element LD (e.g., a second end portion EP2 of a plurality of light emitting elements LD adjacent to the second electrode ELT2), the second contact electrode CNE2 may be disposed on the second end portion EP2. That is, the second contact electrode CNE2 may be disposed to cover the second end portion EP2 of the light emitting element LD and at least a portion of the second electrode ELT2 corresponding thereto. Therefore, the second end portion EP2 of the light emitting element LD may be electrically coupled to the second electrode ELT2.

[0177] The third insulating layer INS3 may be formed and / or disposed on one surface of the first substrate SUB1 on which the first and second bank patterns PW1 and PW2, the first and second electrodes ELT1 and ELT2, the light emitting element LD, and the first and second contact electrodes CNE1 and CNE2 are formed, so as to cover the first and second bank patterns PW1 and PW2, the first and second electrodes ELT1 and ELT2, the light emitting element LD, and the first and second contact electrodes CNE1 and CNE2. The third insulating layer INS3 may include a thin film encapsulation layer including at least one layer of an inorganic film and / or an organic film, but is not limited thereto. In addition, according to an embodiment, at least one outer coating layer not shown may be further disposed on the third insulating layer INS3.

[0178] According to an embodiment, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may be formed of a single layer or a multilayer, and may include at least one inorganic insulating material and / or an organic insulating material. For example, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include various types of organic insulating materials / inorganic insulating materials currently known (such as SiN x ), and the material forming each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 is not particularly limited. In addition, the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include different insulating materials, or at least some of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include the same insulating material.

[0179] In an implementation, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on different layers.

[0180] refer to Figure 8c, the first contact electrode CNE1 may be disposed in the sub-pixel area SPA in which the second insulating layer INS2 is disposed. According to an embodiment, the first contact electrode CNE1 may be disposed on the first electrode ELT1 to contact a portion of the first electrode ELT1 disposed in the corresponding sub-pixel area SPA. In addition, the first contact electrode CNE1 may be disposed on the first end portion EP1 of at least one light emitting element LD disposed in the corresponding sub-pixel area SPA to contact the first end portion EP1. Through the first contact electrode CNE1, the first end portion EP1 of the at least one light emitting element LD disposed in the sub-pixel area SPA may be electrically coupled to the first electrode ELT1 disposed in the corresponding sub-pixel area SPA.

[0181] The fourth insulating layer INS4 may be disposed in the sub-pixel area SPA in which the first contact electrode CNE1 is disposed. According to an embodiment, the fourth insulating layer INS4 may cover the second insulating layer INS2 and the first contact electrode CNE1 disposed in the corresponding sub-pixel area SPA.

[0182] According to an embodiment, similar to the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3, the fourth insulating layer INS4 may be formed of a single layer or multiple layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the fourth insulating layer INS4 may include various types of currently known organic insulating materials / inorganic insulating materials (such as SiN x ). In addition, the fourth insulating layer INS4 may include an insulating material different from those of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3, or may include the same insulating material as at least some of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0183] The second contact electrode CNE2 may be disposed in each sub-pixel region SPA in which the fourth insulating layer INS4 is disposed. For example, the fourth insulating layer INS4 may have a portion disposed between the first contact electrode CNE1 and the second contact electrode CNE2 to insulate the first contact electrode CNE1 from the second contact electrode CNE2. According to an embodiment, the second contact electrode CNE2 may be disposed on the second electrode ELT2 to contact a portion of the second electrode ELT2 disposed in the corresponding sub-pixel region SPA. In addition, the second contact electrode CNE2 may be disposed on the second end portion EP2 of at least one light emitting element LD disposed in the corresponding sub-pixel region SPA to contact the second end portion EP2. Through the second contact electrode CNE2, the second end portion EP2 of at least one light emitting element LD disposed in each sub-pixel region SPA may be electrically coupled to the second electrode ELT2 disposed in the corresponding sub-pixel region SPA.

[0184] According to the implementation mode, Figure 8c As shown in , the first bank pattern PW1 and the second bank pattern PW2 may have various shapes. For example, the first bank pattern PW1 and the second bank pattern PW2 may have a trapezoidal cross-sectional shape, the width of which decreases as it approaches its top. In another example, as shown in Figure 8d As shown in FIG. 1 , the first bank pattern PW1 and the second bank pattern PW2 may have a semicircular or semi-elliptical cross-section whose width decreases toward the top thereof.

[0185] Fig. 9 It is shown that the Figure 6 A plan view of an example of a second panel in a display device of FIG. Fig. 9 In, focus on Figure 7 The pixel circuit layer PCL corresponding to the sub-pixel SPX (eg, the first sub-pixel SPX1 ) shown in FIG. 1 shows the structure of the sub-pixel SPX.

[0186] refer to Fig. 9 The sub-pixel SPX (or pixel circuit layer PCL) may include a first conductive layer SPACER1 (or a first conductive pattern) and a second conductive layer SPACER2 (or a second conductive pattern) respectively arranged in a first non-emissive area NEMA1 and a second non-emissive area NEMA2 in a sub-pixel area SPA of a second substrate SUB2, and a transmissive component PR (or a light-transmitting component, an opening) arranged in the emissive area EMA.

[0187] The transmissive member PR is disposed to correspond to the emission area EMA of the light emitting element layer LDL and has an area equal to or larger than an area occupied by the emission area EMA in the sub-pixel area SPA, and, for example, may cover the emission area EMA.

[0188] The first conductive layer SPACER1 (or the first conductive pattern) may be formed to be aligned with the reference Figure 7 The first connection electrode CONT1 described corresponds to and may have an area substantially the same as that of the first connection electrode CONT1 (or an area of ​​the third bank pattern PW3 in the first non-emission area NEMA1). The first conductive layer SPACER1 (and the second conductive layer SPACER2) may be used as a spacer configured to separate the light emitting element layer LDL from the pixel circuit layer PCL (e.g., the pixel circuit layer PCL not including the first conductive layer SPACER1 and the second conductive layer SPACER2) by a fixed distance or configured to support the light emitting element layer LDL.

[0189] Similarly, the second conductive layer SPACER2 (or the second conductive pattern) may be formed to be aligned with the reference Figure 7The described second connection electrode CONT2 corresponds and may have substantially the same area as that of the second connection electrode CONT2 (or that of the third bank pattern PW3 in the second non-emission area NEMA2). The second conductive layer SPACER2 may be disposed on the same layer as the first conductive layer SPACER1.

[0190] In an embodiment, the second conductive layer SPACER2 may extend to an adjacent sub-pixel region (eg, based on Figure 4 The first sub-pixel SPX1 extends to the second sub-pixel SPX2 and the third sub-pixel SPX3, and can also extend to the non-display area NDA (see Figure 4 ).

[0191] Fig.10 It is shown along Fig. 9 A cross-sectional view of an example of the second panel taken along line II-II'. Fig.10 In the figure, it is shown that Figure 8a The cross section of the first panel corresponds to the cross section of the second panel. That is, Fig. 9 The line II-II' shown in Figure 7 Meanwhile, for the convenience of description, the second panel is shown inverted. As will be described later, in the manufacturing process, the second panel may first be Fig.10 , after which the second panel can be joined to the first panel (e.g., Figure 8a ), wherein the second panel is flipped over so that the positions of the top surface and the bottom surface thereof are swapped.

[0192] The pixel circuit layer PCL may be disposed on one surface of the second substrate SUB2. According to an embodiment, the pixel circuit layer PCL may be formed in the entire display area DA of the display panel PNL.

[0193] According to an embodiment, the pixel circuit layer PCL may include a plurality of circuit elements disposed in the non-emission regions NEMA1 and NEMA2. For example, the pixel circuit layer PCL may include a plurality of circuit elements that form a pixel circuit PXC of a sub-pixel SPX by being formed in the non-emission regions NEMA1 and NEMA2. For example, the pixel circuit layer PCL may include a plurality of transistors disposed in the first non-emission region NEMA1, for example, referring to Figure 5a and Figure 5b The first transistor T1 is described. In addition, although Fig.10 , but the pixel circuit layer PCL may include a storage capacitor Cst disposed in the non-emission regions NEMA1 and NEMA2, various signal lines (eg, reference lines) coupled to the pixel circuit PXC, Figure 5a and Figure 5bThe scan lines Si and data lines Dj described above) and various power lines (eg, reference lines 1 and 2) connected to the pixel circuit PXC and / or the light emitting element LD Figure 5a and Figure 5b The first power line PL1 and the second power line PL2 described above respectively transmit the voltage of the first power source VDD and the voltage of the second power source VSS).

[0194] According to an embodiment, a plurality of transistors provided in the pixel circuit PXC may have a cross-sectional structure substantially the same as or similar to that of the first transistor T1 or the second transistor T2. However, the present disclosure is not limited thereto, and in another embodiment, at least some of the plurality of transistors may have different types and / or structures.

[0195] According to an embodiment, the pixel circuit layer PCL may include a transmissive component PR formed in the emission area EMA. The transmissive component PR may transmit Figure 8a At least some of the light emitted by the light emitting element LD of the described light emitting element layer LDL.

[0196] In an implementation, the transmission component PR may include, for example, a resin that is a transparent light-transmitting organic material such as polyethylene terephthalate (PET), polyacrylate, polyimide (PI), polycarbonate (PC), or the like.

[0197] In an embodiment, the transmission component PR may include a color filter material that transmits or blocks only light having a specific wavelength. For example, sub-pixels SPX adjacent to each other (eg, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, see Figure 4 ) may include a red color filter material (or red transmissive material) that transmits only red light, a green color filter material (or green transmissive material) that transmits only green light, and a blue color filter material (or blue transmissive material) that transmits only blue light.

[0198] In an embodiment, the transmission component PR may include quantum dots. The quantum dots may convert light having a specific wavelength into light having a different wavelength, may be configured with a core, a shell, and a ligand, and may be included in a transparent resin or the like of the transmission component PR in a dispersed form. For example, when the light emitting element LD of the first panel emits blue light, the sub-pixels SPX adjacent to each other (for example, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, see Figure 4) may include a transmissive component PR of one sub-pixel (e.g., a first sub-pixel SPX1) configured to convert blue light into red light, a transmissive component PR of another sub-pixel (e.g., a second sub-pixel SPX2) may include a green quantum dot configured to convert blue light into green light, and a transmissive component PR of yet another sub-pixel (e.g., a third sub-pixel SPX3) may not include quantum dots.

[0199] The pixel circuit layer PCL may include a plurality of insulating layers disposed in the non-emission regions NEMA1 and NEMA2. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV (or a through-hole layer) sequentially stacked on one surface of the second substrate SUB2 in the non-emission regions NEMA1 and NEMA2.

[0200] According to an embodiment, the buffer layer BFL may prevent impurities from diffusing into the circuit element. The buffer layer BFL may be formed of a single layer, but may also be formed of a multilayer including at least two layers. When the buffer layer BFL is provided as a multilayer, the respective layers may be made of the same material or may be made of different materials. Meanwhile, according to an embodiment, the buffer layer BFL may be omitted.

[0201] According to an embodiment, the first transistor T1 may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. Fig.10 , the first transistor T1 is shown to include a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL, but the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, each of the first transistor electrode ET1 and the second transistor electrode ET2 provided in at least one transistor provided in each sub-pixel area SPA may be formed by integration with the semiconductor layer SCL.

[0202] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the second substrate SUB2 on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region between the first region and the second region. According to an embodiment, one of the first region and the second region is a source region, and the other may be a drain region.

[0203] According to an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. In addition, the channel region of the semiconductor layer SCL may be an intrinsic semiconductor as a semiconductor pattern not doped with impurities, and the first and second regions of the semiconductor layer SCL may be respective semiconductor patterns doped with predetermined impurities.

[0204] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD while overlapping at least a portion of the semiconductor layer SCL.

[0205] The first transistor electrode ET1 and the second transistor electrode ET2 may be disposed on the semiconductor layer SCL and the gate electrode GE, while at least one interlayer insulating layer ILD is interposed therebetween. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be disposed between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically coupled to the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be coupled to the first region and the second region of the semiconductor layer SCL, respectively, through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0206] In an embodiment, the first conductive layer SPACER1 may be disposed on the passivation layer PSV in the first non-emission area NEMA1. The first conductive layer SPACER1 may be electrically coupled to one (eg, the first transistor electrode ET1) of the first and second transistor electrodes ET1 and ET2 through a first contact hole CH1 passing through the passivation layer PSV.

[0207] According to an embodiment, at least one signal line and / or a power line coupled to the sub-pixel SPX may be disposed on the same layer as one electrode of a circuit element forming the pixel circuit PXC.

[0208] For example, in the second non-emission area NEMA2, the power line PL (for example, the second power line PL2 for supplying the voltage of the second power supply VSS) may be set on the same layer as the gate electrode GE of each of the first transistor T1 and the second transistor T2, and may be electrically connected to the second conductive layer SPACER2 via a bridge pattern BRP and at least one second contact hole CH2 passing through the passivation layer PSV, wherein the bridge pattern BRP is set on the same layer as the first transistor electrode ET1 and the second transistor electrode ET2.

[0209] However, the structure and / or position, etc. of the power line PL may be variously changed.

[0210] Each of the first conductive layer SPACER1 and the second conductive layer SPACER2, the gate electrode GE, the power line PL, the first transistor electrode ET1 and the second transistor electrode ET2, and the bridge pattern BRP may include at least one conductive material. For example, each of the first conductive layer SPACER1 and the second conductive layer SPACER2, the gate electrode GE, the power line PL, the first transistor electrode ET1 and the second transistor electrode ET2, and the bridge pattern BRP may include at least one material of metals (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti) and alloys thereof, conductive oxides (such as ITO, IZO, ZnO, and ITZO), and conductive polymers (such as PEDOT), but is not limited thereto.

[0211] Fig.11 It is shown Figure 6 A cross-sectional view of an example of a display device. Fig.11 , as a cross-section of a display device based on a sub-pixel area SPA, Fig.10 The second panel is flipped (or inverted) and Figure 8a The state of the first panel combination.

[0212] refer to Fig.11 , the first substrate SUB1, the light emitting element layer LDL, the pixel circuit layer PCL, and the second substrate SUB2 may be sequentially stacked along the third direction DR3. That is, the light emitting element layer LDL may be disposed on the first substrate SUB1, the pixel circuit layer PCL may be disposed on the light emitting element layer LDL, and the second substrate SUB2 may be disposed on the pixel circuit layer PCL.

[0213] The first substrate SUB1 and the light emitting element layer LDL are connected to the reference Figure 8a The described first substrate SUB1 and light emitting element layer LDL are substantially the same, and thus redundant descriptions will not be repeated.

[0214] In the first non-emission area NEMA1, the first conductive layer SPACER1 may be disposed on the first electrode ELT1. The first conductive layer SPACER1 may have a size (or area) corresponding to a portion of the first electrode ELT1 protruding in the third direction DR3 (i.e., upward direction) through the third bank pattern PW3, and for example, the size of the first conductive layer SPACER1 may be substantially the same as a size of a portion of the first electrode ELT1 protruding through the third bank pattern PW3.

[0215] In an embodiment, the thickness of the first conductive layer SPACER1 may be greater than the thickness (or average thickness) of the third insulating layer INS3 (and the outer coating) of the light emitting element layer LDL. That is, the first conductive layer SPACER1 may have a sufficient thickness so that the third insulating layer INS3 and the components thereunder are not compressed by the transmissive component PR in the emission area EMA. For example, the first conductive layer SPACER1 may have a thickness equal to or greater than 2 μm.

[0216] In an embodiment, the first conductive layer SPACER1 may not overlap the third insulating layer INS3. That is, the third insulating layer INS3 may expose the first electrode ELT1 in the first non-emission area NEMA1 (eg, referring to FIG. 1 ). Figure 7 The first conductive layer SPACER1 may be in direct contact with the protruding portion of the first electrode ELT1 or may be combined with the protruding portion of the first electrode ELT1. For example, the first conductive layer SPACER1 may be combined with the first electrode ELT1 by ultrasonic bonding, anisotropic conductive film, etc.

[0217] The passivation layer PSV, the first transistor electrode ET1 and the second transistor electrode ET2, the interlayer insulating layer ILD, the gate electrode GE, the gate insulating layer GI, the semiconductor layer SCL (or the semiconductor pattern), and the buffer layer BFL may be sequentially disposed on the first conductive layer SPACER1. As described above, the first transistor electrode ET1 and the second transistor electrode ET2, the gate electrode GE, and the semiconductor layer SCL may form the first transistor T1. The first conductive layer SPACER1 may contact the first transistor T1 (or the first transistor electrode ET1) through the first contact hole CH1 (or the first through hole) passing through the passivation layer PSV (or the through hole layer).

[0218] Similar to the first non-emission area NEMA1, the second conductive layer SPACER2 may be disposed on the second electrode ELT2 in the second non-emission area NEMA2. The second conductive layer SPACER2 may have a size (or area) corresponding to a portion of the second electrode ELT2 protruding in the third direction DR3 (i.e., the upward direction) through the third embankment pattern PW3, and for example, the size of the second conductive layer SPACER2 may be substantially the same as the size of a portion of the second electrode ELT2 protruding through the third embankment pattern PW3.

[0219] The thickness of the second conductive layer SPACER2 may be substantially the same as the thickness of the first conductive layer SPACER1. The second conductive layer SPACER2 may not overlap with the third insulating layer INS3. That is, the third insulating layer INS3 may expose the second electrode ELT2 in the second non-emission region NEMA2 (eg, reference Figure 7The second conductive layer SPACER2 may be in direct contact with the protruding portion of the second electrode ELT2 or may be combined with the protruding portion of the second electrode ELT2.

[0220] The passivation layer PSV, the bridge pattern BRP, the interlayer insulating layer ILD, the power line PL, the gate insulating layer GI and the buffer layer BFL may be sequentially disposed on the second conductive layer SPACER2. The second conductive layer SPACER2 may be coupled to the bridge pattern BRP and the power line PL through a second contact hole CH2 (or second through hole) passing through the passivation layer PSV (or through hole layer).

[0221] In the emission area EMA, the transmissive component PR of the pixel circuit layer PCL may be disposed on the third insulating layer INS3. The transmissive component PR may be disposed to be spaced apart from the third insulating layer INS3, but is not limited thereto. The transmissive component PR transmits light generally emitted from the light emitting element LD in the third direction DR3, and thus, an image may be displayed through one surface of the second substrate SUB2 (i.e., the surface of the display device in the third direction DR3). That is, the display device may emit light from the back side based on the pixel circuit layer PCL.

[0222] At the same time, Fig.11 , the thickness of the transmission component PR is shown to be the same as the total thickness of the passivation layer PSV, the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BFL, but is not limited thereto. For example, the thickness of the transmission component PR may be less than the total thickness of the passivation layer PSV, the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BFL. In another example, the thickness of the transmission component PR may be greater than the total thickness of the passivation layer PSV, the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BFL, and the top surface of the transmission component PR may not be flat.

[0223] Fig.12 It is shown that the Figure 6 A plan view of another example of a first panel in a display device of FIG. Fig.12 In the figure, it is shown that Figure 7 The sub-pixel SPX shown in FIG. 1 corresponds to the sub-pixel SPX. Fig.13 It is shown along Fig.12 A cross-sectional view of another example of the first panel taken along line III-III'. Fig.13 In the figure, it is shown that Figure 8a The sub-pixel SPX shown in FIG. 1 corresponds to the sub-pixel SPX.

[0224] refer to Figure 7 , Figure 8a , Fig.12 and Fig.13 , Fig.12The sub-pixel SPX (or the first panel) and Figure 7 The sub-pixels of SPX differ in that: Fig.12 The sub-pixel SPX also includes a bank BANK. In addition to the bank BANK, Fig.12 The sub-pixel SPX and Figure 7 The sub-pixels SPX are substantially the same, and therefore a redundant description will not be repeated.

[0225] The bank BANK is disposed along the edge of the emission area EMA and may surround the emission area EMA. For example, in order to surround the emission area EMA of the sub-pixel SPX, the bank BANK may be disposed between the sub-pixel SPX and another sub-pixel SPX (or between other sub-pixels SPX). That is, the emission area EMA may be defined by the bank BANK, or the bank BANK may be configured as a pixel defining layer for dividing the emission area EMA of the sub-pixel SPX.

[0226] In an embodiment, the bank BANK may not overlap the first conductive layer SPACER1 and the second conductive layer SPACER2. For example, the bank BANK may be disposed between the first conductive layer SPACER1 and the emission area EMA, and may also be disposed between the second conductive layer SPACER2 and the emission area EMA.

[0227] According to an embodiment, in the step of supplying the light emitting element LD to each emission area EMA, the embankment BANK may prevent the solution mixed with the light emitting element LD from flowing into the emission area EMA of the adjacent sub-pixel SPX, or may be used as a dam structure for performing control so that a fixed amount of solution is supplied to each emission area EMA.

[0228] According to an embodiment, the bank BANK may be formed to prevent light emitted from each emission area EMA from leaking to an adjacent emission area EMA and generating light interference. To this end, the bank BANK may be formed to prevent light emitted from the light emitting element LD of each subpixel SPX from penetrating the bank BANK.

[0229] refer to Fig.13 The bank BANK may be disposed on the first substrate SUB1. For example, the bank BANK may be interposed between the first insulating layer INS1 and the third insulating layer INS3.

[0230] Fig.14 It is shown Figure 6 A cross-sectional view of another example of a display device. Fig.14 In, as Fig.11 The corresponding display device shows Fig.10 The second panel is flipped (or inverted) and Fig.13 The state of the first panel combination.

[0231] refer to Fig.11 and Fig.14 , Fig.14 The display device and Fig.11 The display devices differ in that: Fig.14 The display device further includes a bank portion BANK. In addition to the bank portion BANK, Fig.14 The display device and Fig.11 The display devices are basically the same, and therefore redundant descriptions will not be repeated.

[0232] According to an embodiment, the total thickness of the first conductive layer SPACER1 (or the second conductive layer SPACER2) and the third bank pattern PW3 may be greater than the thickness of the bank BANK. For example, when the thickness of the bank BANK is equal to or greater than 2.5 μm and when the thickness of the third bank pattern PW3 is 2 μm, the thickness of the first conductive layer SPACER1 may be equal to or greater than 1 μm.

[0233] Fig.15 It is shown along Figure 7 FIG. 1 is a cross-sectional view of yet another example of the first panel taken along line II′.

[0234] refer to Figure 7 , Figure 8a and Fig.15 , except for the first contact electrode CNE1 and the second contact electrode CNE2, Fig.15 The first panel can be Figure 8a The first panel of FIG. 1 is substantially the same. Therefore, a redundant description will not be repeated.

[0235] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the first electrode ELT1 and the second electrode ELT2, and may be aligned with the third bank pattern PW3 (or reference electrode PW4). Figure 7 The first connection electrode CONT1 and the second connection electrode CONT2 are described to overlap.

[0236] For example, the first contact electrode CNE1 may be disposed on the first electrode ELT1 in the first non-emission area NEMA1, and may overlap with the third bank pattern PW3 in the third direction DR3. That is, the first contact electrode CNE1 may cover the first electrode ELT1 in the first non-emission area NEMA1, and may protrude in the third direction DR3 through the third bank pattern PW3 in the first non-emission area NEMA1. Similarly, the second contact electrode CNE2 may be disposed on the second electrode ELT2 in the second non-emission area NEMA2, and may overlap with the third bank pattern PW3 in the third direction DR3. That is, the second contact electrode CNE2 may cover the second electrode ELT2 in the second non-emission area NEMA2, and may protrude in the third direction DR3 through the third bank pattern PW3 in the second non-emission area NEMA2.

[0237] Fig.16 It is shown Figure 6 A cross-sectional view of another example of a display device. Fig.16 , as a cross-section of a display device based on a sub-pixel area SPA, Fig.10 The second panel is flipped (or inverted) and Fig.15 The state of the first panel combination.

[0238] refer to Fig.11 and Fig.16 , except for the first contact electrode CNE1 and the second contact electrode CNE2, Fig.16 The display device and Fig.11 The display devices are basically the same, and therefore redundant descriptions will not be repeated.

[0239] In the first non-emission area NEMA1, the first electrode ELT1 may be disposed on the third bank pattern PW3, the first contact electrode CNE1 may be disposed on the first electrode ELT1, and the first conductive layer SPACER1 may be disposed on the first contact electrode CNE1. That is, in the first non-emission area NEMA1, the first contact electrode CNE1 may be interposed between the first electrode ELT1 and the first conductive layer SPACER1.

[0240] The first conductive layer SPACER1 has a size (or area) corresponding to a portion of the first contact electrode CNE1 protruding in the third direction DR3 (i.e., in an upward direction) through the third embankment pattern PW3, and for example, the size of the first conductive layer SPACER1 may be substantially the same as the size of the first contact electrode CNE1 protruding through the third embankment pattern PW3, but is not limited thereto.

[0241] The first contact electrode CNE1 may be directly coupled to the first end EP1 of the light emitting element LD in the emission area EMA, and may be electrically coupled to the first transistor T1 of the pixel circuit layer PCL through the first conductive layer SPACER1 in the first non-emission area NEMA1. That is, the first contact electrode CNE1 may electrically couple the light emitting element LD to the first transistor T1.

[0242] Similarly, in the second non-emission area NEMA2, the second electrode ELT2 may be disposed on the third bank pattern PW3, the second contact electrode CNE2 may be disposed on the second electrode ELT2, and the second conductive layer SPACER2 may be disposed on the second contact electrode CNE2. That is, in the second non-emission area NEMA2, the second contact electrode CNE2 may be interposed between the second electrode ELT2 and the second conductive layer SPACER2.

[0243] The second contact electrode CNE2 may be directly coupled to the second end EP2 of the light emitting element LD in the emission area EMA, and may be electrically coupled to the power line PL (e.g., the second power line PL2 to which the voltage of the second power supply VSS is applied) of the pixel circuit layer PCL through the second conductive layer SPACER2 and the bridge pattern BRP in the second non-emission area NEMA2. That is, the second contact electrode CNE2 may electrically couple the light emitting element LD to the power line PL.

[0244] Fig.17 It is shown that the Figure 6 A plan view of another example of a second panel in a display device of FIG. Fig.17 In, based on Figure 7 The structure of the sub-pixel SPX is shown by referring to the pixel circuit layer PCL corresponding to the sub-pixel SPX (eg, the first sub-pixel SPX1 ) shown in FIG.

[0245] First, refer to Figure 6 , Figure 7 and Fig.17 , the sub-pixel SPX (or the pixel circuit layer PCL) may include a first conductive layer SPACER1 disposed in a first non-emission area NEMA1 of the second substrate SUB2 and a transmissive component PR disposed in an emission area EMA and a second non-emission area NEMA2.

[0246] The first conductive layer SPACER1 can be connected to the reference Fig. 9 The first conductive layer SPACER1 described above is substantially the same as or similar to the first conductive layer SPACER1 described above, and except for the size (or shape, the position where the transmission component PR is disposed), the transmission component PR may be the same as the first conductive layer SPACER1 described above. Fig. 9 The transmissive components PR described are substantially the same or similar, and therefore, redundant descriptions will not be repeated.

[0247] Fig.18It is shown along Fig.17 A cross-sectional view of another example of the second panel taken along line IV-IV'. Fig.18 In the figure, it is shown that Figure 8a The cross section of the first panel corresponds to the cross section of the second panel. That is, Fig.18 The line IV-IV' shown in Figure 7 Meanwhile, for the convenience of description, the second panel is shown inverted. As described above, in the manufacturing process, the second panel is Fig.18 , and then the second panel can be bonded to the first panel in a state where it is turned over (so that the positions of the top surface and the bottom surface of the second panel are exchanged).

[0248] refer to Fig.10 and Fig.18 , in addition to the setting of the transmission component PR, Fig.18 The second panel with Fig.10 The second panel is substantially the same or similar, and therefore a redundant description will not be repeated.

[0249] The pixel circuit layer PCL may include a transmissive component PR formed in the emission area EMA and the second non-emission area NEMA2. The transmissive component PR may transmit at least some of emission light incident from a lower portion to an upper portion.

[0250] Fig.19 It is shown Figure 6 A cross-sectional view of another example of a display device. Fig.19 , as a cross-section of a display device based on a sub-pixel area SPA, Fig.18 The second panel is flipped (or inverted) and Figure 8a The state of the first panel combination.

[0251] refer to Fig.11 and Fig.19 , except for the stacked structure in the second non-emitting area NEMA2, Fig.19 The display device and Fig.11 The display devices are substantially the same or similar, and therefore redundant descriptions will not be repeated.

[0252] In the second non-emission area NEMA2, the transmission component PR may be disposed on the light emitting element layer LDL. For example, the transmission component PR may be disposed to be spaced apart from the light emitting element layer LDL, but is not limited thereto. For example, the third insulating layer INS3 (and / or the outer coating) of the light emitting element layer LDL may be disposed on the second electrode ELT2 in the second non-emission area NEMA2, and may also support the transmission component PR while contacting with the transmission component PR.

[0253] Meanwhile, the second electrode ELT2 may be coupled to the non-display area NDA (see Figure 4 ) in the pixel circuit layer PCL (not in the pixel area) (eg, the second power line PL2 to which the voltage of the second power source VSS is applied).

[0254] For reference Fig. 20 , to illustrate the configuration of the electric power line connecting the second electrode ELT2 to the pixel circuit layer PCL.

[0255] Fig. 20 is a plan view showing a display device according to another embodiment of the present disclosure. Fig. 20 , a display panel PNL provided in a display device is briefly shown.

[0256] refer to Figure 4 and Fig. 20 , in addition to the power line PL and the second conductive layer SPACER2, Fig. 20 The display panel PNL and Figure 4 The display panels PNL of the embodiment of the present invention are substantially the same or similar. Therefore, a redundant description will not be repeated.

[0257] The display panel PNL includes sub-pixels SPX1, SPX2, and SPX3, and at least some of the sub-pixels SPX1, SPX2, and SPX3 may have reference Fig.19 Describe the cross-sectional structure.

[0258] The display panel PNL may include power lines PL and a second conductive layer SPACER2 formed in the non-display area NDA.

[0259] The power lines PL may be disposed along the edge of the display area DA and may form a closed loop, but are not limited thereto. The power lines PL may be reference Figure 5a The second power line PL2 described or reference Figure 5b A first power line PL1 is described.

[0260] The second conductive layer SPACER2 may be repeatedly disposed at regular intervals along the edge of the display area DA and may be electrically coupled to the power line PL.

[0261] In an embodiment, the second conductive layer SPACER2 may be electrically coupled to the second electrode ELT2 in the non-display area NDA (see Fig.11 ).

[0262] Along Fig. 20 The cross section of the display panel PNL taken along the line V-V' may be Fig.11 The cross-section of the second non-emitting area NEMA2 shown in FIG. 1 is substantially the same.

[0263] As reference Figure 7 As described above, the second electrode ELT2 may extend to the adjacent sub-pixel SPX and may also extend to the non-display area NDA. Fig.11 Similar to the second conductive layer SPACER2 in the second non-emissive region NEMA2 shown in FIG. Fig. 20 The second conductive layer SPACER2 shown in the figure can be electrically coupled to the power line PL through at least one second contact hole CH2 passing through the passivation layer PSV of the pixel circuit layer PCL. That is, the sub-pixels SPX1, SPX2 and SPX3 can be electrically coupled to the power line PL through the second electrode ELT2 and the second conductive layer SPACER2 (or the contact hole CH2 corresponding to the second conductive layer SPACER2) extending to the non-display area NDA.

[0264] As reference Figures 17 to 20 As described, the sub-pixel SPX may be connected to the circuit elements of the pixel circuit layer PCL through the first conductive layer SPACER1 disposed in the first non-emission area NEMA1 of the sub-pixel area SPA, and may be electrically connected to the power line PL through the second conductive layer SPACER2 disposed in the non-display area NDA. Since the second conductive layer SPACER2 is not disposed in the sub-pixel area SPA having a limited area, the area of ​​at least one of the first conductive layer SPACER1 and the transmission component PR may be relatively increased. For example, the area of ​​the first conductive layer SPACER1 may be increased, in which case the bonding force, conductivity, etc. between the pixel circuit in the pixel circuit layer PCL and the first electrode ELT1 may be improved. In another example, the area of ​​the transmission component PR may be increased, in which case the emission area EMA is set large to correspond to the transmission component PR, and the increase in the number of light emitting elements LD disposed in the emission area EMA may result in an improvement in the maximum brightness.

[0265] Fig.21 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0266] refer to Figure 4 , Figure 6 and Fig.21 , Fig.21 The method enables the production of Figure 4 Display device (or display panel PNL).

[0267] exist Fig.21 In the method, the following steps can be respectively prepared in steps S2010 and S2020: Figure 6 The first panel STR1 and the second panel STR2 are shown in FIG.

[0268] The first panel STR1 may be Figures 8a to 8d , Fig.13 and Fig.15 The second panel STR2 may be one of the first panels shown in FIG. Fig.10 and Fig.18 The one in the second panel shown in .

[0269] Will refer to it later Figures 22a to 22d as well as Figures 23a to 23g A process of preparing the first panel STR1 and the second panel STR2 is described.

[0270] Then, in Fig.21 In the method, in step S2030, the first panel STR1 and the second panel STR2 may be combined with each other so that the light emitting element layer LDL of the first substrate SUB1 and the pixel circuit layer PCL of the second substrate SUB2 contact each other.

[0271] For example, in Fig.21 In the method, the second panel STR2 (for example, Fig.10 The second panel STR2 of the display device STR2 is flipped or rotated 180 degrees so that the top and bottom surfaces thereof are exchanged, the second panel STR2 is aligned on the first panel STR1 so that the first conductive layer SPACER1 of the second panel STR2 faces the first electrode ELT1 of the first panel STR1 (i.e., the first electrode ELT1 of the first non-emission area NEMA1), and the second conductive layer SPACER2 of the second panel STR2 faces the second electrode ELT2 of the first panel STR1 (i.e., the second electrode ELT2 of the second non-emission area NEMA2), and then the second panel STR2 can be combined with the first panel STR1. In this case, the display device can have Fig.11 cross-sectional structure.

[0272] In another example, Fig.21 In the method, the first panel STR1 is turned over and aligned on the second panel STR2, and then the first panel STR1 may be combined with the second panel STR2.

[0273] Figures 22a to 22d It is used to explain the Fig.21 A view of the process of preparing the first panel of the method.

[0274] refer to Figures 22a to 22d , which shows by way of example Fig.21 In the method for manufacturing a display device, step S2010 is to prepare Figure 8a FIG. 1 is a cross-sectional structure of a first panel STR1 of the process.

[0275] exist Fig.21 In the method, such as Fig.22aAs shown in FIG. 1 , a first bank pattern PW1 , a second bank pattern PW2 , and a third bank pattern PW3 may be formed on a first substrate SUB1 .

[0276] For example, in Fig.21 In the method, a dam pattern layer for forming a first dam pattern PW1, a second dam pattern PW2 and a third dam pattern PW3 is formed on the entire first substrate SUB1, after which the first dam pattern PW1, the second dam pattern PW2 and the third dam pattern PW3 can be formed by an etching process or the like.

[0277] As reference Figure 7 and Figure 8a As described, the first embankment pattern PW1 and the second embankment pattern PW2 may be formed so that one side surface of the first embankment pattern PW1 and one side surface of the second embankment pattern PW2 face each other in the emission area EMA of the first substrate SUB1, and the third embankment pattern PW3 may be formed in the first non-emission area NEMA1 and the second non-emission area NEMA2.

[0278] Then, in Fig.21 In the method, such as Figure 22b As shown in FIG. 1 , first and second electrodes ELT1 and ELT2 may be formed on a first substrate SUB1 and first, second, and third bank patterns PW1 , PW2 , and PW3 .

[0279] For example, in Fig.21 In the method, a first conductive layer may be formed on the entire first substrate SUB1, and the first conductive layer may be patterned to form the first electrode ELT1 and the second electrode ELT2.

[0280] As reference Figure 7 and Figure 8a As described, the first electrode ELT1 may be formed as the third bank pattern PW3 covering the first bank pattern PW1 and the first non-emission area NEMA1, and the second electrode ELT2 may be formed as the third bank pattern PW3 covering the second bank pattern PW2 and the second non-emission area NEMA2.

[0281] Then, in Fig.21 In the method, such as Fig.22c As shown in FIG. 1 , a first insulating layer INS1 may be formed to cover portions of the first electrode ELT1 and the second electrode ELT2. Fig.21 In the method, an insulating layer is formed on the entire first substrate SUB1, and thereafter, the first insulating layer INS1 may be formed by an etching process, etc. In an embodiment, the first insulating layer INS1 may be omitted.

[0282] Then, in Fig.21In the method, the light emitting element LD may be disposed between the first electrode ELT1 and the second electrode ELT2 in the emission area EMA.

[0283] For example, in Fig.21 In the method, the light emitting element LD may be supplied to the emission area EMA by an inkjet method or the like, and a predetermined alignment voltage (or alignment signal) may be applied between the first electrode ELT1 and the second electrode ELT2. In this case, an electric field may be formed between the first electrode ELT1 and the second electrode ELT2, and the light emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2 according to the electric field.

[0284] Then, if Fig.22d As shown in Fig.21 In the method, a second insulating layer INS2 may be formed on the light emitting element LD so as to expose the first end EP1 and the second end EP2 of the light emitting element LD. Similar to the process of forming the first insulating layer INS1, Fig.21 The method enables forming the second insulating layer INS2 by applying an insulating material and etching. When there is a gap space between the first insulating layer INS1 and the light emitting element LD, the space may be filled with the second insulating layer INS2.

[0285] Then, in Fig.21 In the method, the first and second contact electrodes CNE1 and CNE2 may be formed on the first and second electrodes ELT1 and ELT2 and the first and second end portions EP1 and EP2 of the light emitting element LD.

[0286] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer, but are not limited thereto. Fig.21 In the method, such as Figure 8c and Figure 8d As shown in FIG. 1 , a first contact electrode CNE1 may be formed, a fourth insulating layer INS4 may be formed to cover the first contact electrode CNE1, and a second contact electrode CNE2 may be formed. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed on different layers.

[0287] According to an embodiment, in Fig.21 In the method, as referenced Fig.15 As described, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed to overlap the third bank pattern PW3 .

[0288] Then, in Fig.21In the method, a third insulating layer INS3 may be formed on a surface of the first substrate SUB1 on which the first and second bank patterns PW1 and PW2, the first and second electrodes ELT1 and ELT2, the light emitting element LD, and the first and second contact electrodes CNE1 and CNE2 are formed to cover the first and second bank patterns PW1 and PW2, the first and second electrodes ELT1 and ELT2, the light emitting element LD, and the first and second contact electrodes CNE1 and CNE2. Therefore, the first panel STR1 may have Figure 8a cross-sectional structure.

[0289] For example, in Fig.21 In the method, the third insulating layer INS3 may be formed by forming an insulating layer on the entire first substrate SUB1 and removing a portion overlapping the third bank pattern PW3 from the insulating layer through an etching process or the like.

[0290] According to an embodiment, in Fig.21 In the method, at least one outer coating layer may be further formed on the third insulating layer INS3.

[0291] Figures 23a to 23g It is used to explain the Fig.21 A method of preparing a second panel process is shown in FIG.

[0292] refer to Figures 23a to 23g , which shows by way of example Fig.21 In step S2020 of the display device manufacturing process, a Fig.10 The process of the second panel STR2 of the cross-sectional structure.

[0293] exist Fig.21 In the method, such as Fig.23a As shown in FIG. 1 , a semiconductor layer SCL may be formed in the non-emitting region NEMA1 of the second substrate SUB2. Fig.21 In the method, a reference may be formed in the first non-emitting area NEMA1 Fig.10 The semiconductor layer SCL of the first transistor T1 is described.

[0294] Then, in Fig.21 In the method, such as Figure 23b As shown in , a gate insulating layer GI may be formed over the entire second substrate SUB2, and a first conductive pattern may be formed on the gate insulating layer GI. Here, the first conductive pattern may include a gate electrode GE and a power line PL. For example, in Fig.21 In the method, the gate electrode GE may be formed in the first non-emission area NEMA1, and the power line PL may be formed in the second non-emission area NEMA2.

[0295] Then, in Fig.21In the method, such as Fig.23c As shown in , an interlayer insulating layer ILD may be formed over the entire second substrate SUB2, and a contact hole exposing at least one of the first conductive patterns and the semiconductor layer SCL may be formed. For example, the contact hole may expose a first region and a second region (e.g., a source region and a drain region) of the semiconductor layer SCL and a portion of the power line PL.

[0296] Then, in Fig.21 In the method, such as Fig.23d As shown in , a second conductive pattern may be formed on the interlayer insulating layer ILD. Here, the second conductive pattern may include a first transistor electrode ET1 and a second transistor electrode ET2 and a bridge pattern BRP. The first transistor electrode ET1 and the second transistor electrode ET2 may contact the first region and the second region of the semiconductor layer SCL through contact holes, respectively, and the bridge pattern BRP may contact the power line PL through the contact hole.

[0297] Then, in Fig.21 In the method, such as Fig.23e As shown in FIG. 1 , a passivation layer PSV may be formed over the entire second substrate SUB2 to cover the second conductive patterns and the interlayer insulating layer ILD, and contact holes CH1 and CH2 (or through holes) exposing at least some of the second conductive patterns may be formed.

[0298] Then, in Fig.21 In the method, such as Figure 23f As shown in, a first conductive layer SPACER1 and a second conductive layer SPACER2 may be formed on the passivation layer PSV in the first non-emission area NEMA1 and the second non-emission area NEMA2. The first conductive layer SPACER1 may be formed in the first non-emission area NEMA1 and may contact the first transistor electrode ET1 through the first contact hole CH1. The second conductive layer SPACER2 may be formed in the second non-emission area NEMA2 and may contact the bridge pattern BRP through the second contact hole CH2.

[0299] Then, in Fig.21 In the method, such as Figure 23g As shown in FIG. 1 , a trench may be formed by removing the insulating layers (i.e., the buffer layer BFL, the gate insulating layer GI, the interlayer insulating layer ILD, and the passivation layer PSV) in the emission area EMA of the second substrate SUB2 through an etching process or the like, and a transmissive component PR may be formed in the trench (refer to FIG. Fig.10 ). For example, in Fig.21 In the method, the transmissive component PR can be formed by supplying a transparent organic material to the groove by an inkjet printing method. Fig.10 A second panel STR2 of the cross-sectional structure.

[0300] At the same time, Fig.10 as well as Figures 23a to 23g , it is shown that the transmission component PR is formed by forming a trench in the emission area EMA of the second substrate SUB2 after forming insulating layers (ie, a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV), but the present disclosure is not limited thereto.

[0301] For example, Fig.21 The method is configured so that, in the corresponding processes of forming a contact hole of an interlayer insulating layer ILD and a first contact hole CH1 and a second contact hole CH2 of a passivation layer PSV, a groove is formed by removing corresponding insulating layers (e.g., the interlayer insulating layer ILD and the passivation layer PSV) in an emission area EMA of a second substrate SUB2, after which a transmissive component PR can be formed in the groove.

[0302] Although the technical spirit of the present disclosure is specifically described according to the above embodiments, it should be noted that the above embodiments are only for illustrative purposes and do not limit the technical spirit of the present disclosure. In addition, those skilled in the art to which the present disclosure belongs should understand that various replacements can be made herein without departing from the technical spirit of the present disclosure.

[0303] The scope of the present disclosure is not limited by the detailed description of this specification, and should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A display device, comprising: A first substrate including a first region and a second region located at an edge of the first region; A first electrode and a second electrode, disposed on the first substrate and spaced apart from each other; a light emitting element, disposed between the first electrode and the second electrode in the first region; a first conductive layer disposed on the first electrode in the second region; a pixel circuit layer disposed on the first conductive layer in the second region and comprising a transistor coupled to the first conductive layer; A second substrate, disposed on the pixel circuit layer; a first contact electrode configured to couple a first end of each of the light emitting elements to the first electrode; a second contact electrode configured to couple a second end of each of the light emitting elements to the second electrode; as well as an insulating layer, disposed on the first contact electrode and the second contact electrode, Wherein, the thickness of the first conductive layer is greater than the average thickness of the insulating layer.

2. The display device according to claim 1, further comprising: a first bank pattern interposed between the first substrate and the first electrode in the first region; a second bank pattern interposed between the first substrate and the second electrode in the first region; as well as a third bank pattern interposed between the first substrate and the first electrode in the second region, Wherein, the light emitting element is disposed between the first bank pattern and the second bank pattern.

3. The display device according to claim 2, wherein: The pixel circuit layer also includes a transmissive component disposed to overlap the first region of the first substrate and configured to transmit at least some of the light emitted from the light emitting element.

4. The display device according to claim 1, wherein: The first contact electrode is interposed between the first electrode and the first conductive layer in the second region.

5. The display device according to claim 4, wherein: The insulating layer does not overlap with the first conductive layer.

6. The display device according to claim 3, wherein: The pixel circuit layer further includes: A through-hole layer, disposed on the first conductive layer; A first transistor electrode is disposed on the via layer; and a semiconductor pattern, disposed on the first transistor electrode, The first transistor electrode and the semiconductor pattern form the transistor, and The first conductive layer contacts the first transistor electrode through a contact hole, and the contact hole exposes the first transistor electrode by passing through the via layer.

7. The display device according to claim 6, wherein: The via layer includes a light-blocking material that absorbs or blocks the light emitted from the light-emitting element.

8. The display device according to claim 3, further comprising: a second conductive layer disposed on the second electrode in the second region and spaced apart from the first conductive layer, The pixel circuit layer further includes a power line, which is disposed on the second conductive layer in the second region and connected to the second conductive layer.

9. The display device according to claim 8, wherein: The first substrate includes a plurality of pixel regions configured to display different monochromatic colors, each of the plurality of pixel regions including the first region and the second region, The first conductive layer is independently disposed in each of the plurality of pixel regions, and The second conductive layer is disposed across at least two pixel regions among the plurality of pixel regions.

10. The display device according to claim 3, wherein: The transmissive component covers the second electrode in the second region.

11. The display device according to claim 10, wherein: The first substrate further includes a display area for displaying an image and a non-display area located on one side of the display area. The display area includes a plurality of pixel areas, the plurality of pixel areas are configured to display different monochrome colors, each of the plurality of pixel areas includes the first area and the second area, The second electrode extends to the non-display area, and The pixel circuit layer further includes: A power line is arranged in the non-display area; and A second conductive layer is disposed between the second electrode and the power line in the non-display area and is configured to couple the second electrode to the power line.

12. The display device according to claim 3, wherein: The first conductive layer covers the transistor.

13. The display device according to claim 3, wherein: The transmissive component includes a color filter material configured to block light of some wavelength bands among the light emitted from the light emitting element.

14. The display device according to claim 3, wherein: The transmissive component includes quantum dots configured to convert the color of the light emitted from the light emitting element.

15. The display device according to claim 2, further comprising: a bank disposed on the first substrate in the second region along an edge of the first region and configured to define the first region, The embankment does not overlap with the first conductive layer.

16. The display device according to claim 15, wherein: A sum of a thickness of the first conductive layer and a thickness of the third bank pattern is greater than a thickness of the bank portion.

17. The display device according to claim 1, wherein: Each of the light emitting elements is a rod-type light emitting diode having a size ranging from a nanometer scale to a micrometer scale.

18. A method for manufacturing a display device, comprising: preparing a first panel including a light emitting element layer formed on a first substrate; preparing a second panel including a pixel circuit layer formed on a second substrate; as well as combining the first panel and the second panel so that the light emitting element layer and the pixel circuit layer are in contact with each other, in: The light emitting element layer includes a first substrate, a first electrode and a second electrode disposed on the first substrate to be spaced apart from each other, a plurality of light emitting elements disposed between the first electrode and the second electrode, a first contact electrode configured to couple a first end of each of the light emitting elements to the first electrode, a second contact electrode configured to couple a second end of each of the light emitting elements to the second electrode, and an insulating layer disposed on the first contact electrode and the second contact electrode. The pixel circuit layer includes a second substrate, a transistor disposed on the second substrate, and a first conductive layer disposed on the transistor, and Wherein, the thickness of the first conductive layer is greater than the average thickness of the insulating layer.

19. The method according to claim 18, wherein: The pixel circuit layer also includes a transmissive component that overlaps the light emitting element of the first panel and is configured to transmit at least some of the light emitted from the light emitting element.

20. The method according to claim 19, wherein: Preparing the second panel includes: forming the transistor on the second substrate; forming the first conductive layer on the transistor; forming a groove in the pixel circuit layer corresponding to the transmission component; and The transmissive component is formed by supplying a transparent organic material to the groove.

Images