Interface circuit and information processing system

Abstract

The present disclosure relates to an interface circuit and an information processing system. In the present invention, a signal is transmitted at a high speed in a direction opposite to the transmission direction of a main large-capacity channel. A differential signal consisting of a first signal containing a clock component is transmitted to an external device via a channel through a first transmission unit. A second transmission unit transmits the common mode signal to the external device by superimposing a common mode signal on the channel, the common mode signal consisting of a second signal containing a clock component. A status notification unit communicates with the external device via a pair of differential channels included in the above-mentioned channel, and notifies the external device of the connection status of the device including the first transmission unit, the second transmission unit and the status notification unit through a DC bias potential of at least one of the pair of differential channels.

Description

[0001] This application is a divisional application of the invention patent application with application number 201580029798.5, application date March 24, 2015, and name “Interface circuit and information processing system”. Technical Field

[0002] The present technology relates to an interface circuit. Specifically, the present technology relates to an interface circuit for transmitting digital signals such as audio signals and video signals between a device and an information processing system. Background Art

[0003] Currently, with the prevalence of audio-visual (AV) devices that handle digital signals such as audio signals and video signals, various types of interfaces for transmitting digital signals between AV devices are proposed. As such interfaces, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard and the High-Definition Multimedia Interface (HDMI) (TM) standard are widely known. In this interface, a technology for transmitting an audio signal in a direction opposite to the transmission direction of a main large-capacity channel is known. For example, an interface circuit for transmitting a bi-phase modulated signal called SPDIF in a direction opposite to the transmission direction of a serial transmission path called TMDS is proposed in the HDMI standard (for example, refer to Patent Document 1).

[0004] Citation list

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application No. 2009-130606 Summary of the invention

[0007] Problems to be solved by the present invention

[0008] However, the bi-phase modulation signal of SPDIF assumes transmission of an audio signal of substantially about 3 Mbps, so that this is not suitable for transmission of high-quality audio signals such as so-called high bit rate audio (HBR), etc. If the bi-phase modulation signal is transmitted at a high speed, then since it is an in-phase signal at a fixed bit rate, unnecessary radiation is generated and this may affect another signal in the cable.

[0009] The present technology has been achieved in view of this situation, and an object of the present technology is to transmit a signal at a high speed in a direction opposite to the transmission direction of a main large-capacity channel.

[0010] Solution to the problem

[0011] The present technology is implemented to solve the above-mentioned problems, and its first aspect is an interface circuit provided with: a first transmission unit that transmits a first signal containing a clock component as a differential signal to an external device via a transmission path; a second transmission unit that superimposes a second signal containing a clock component as an in-phase signal on the transmission path to transmit to the external device; and a state notification unit that communicates with the external device via a pair of differential transmission paths included in the transmission path, and notifies the external device of the connection state of its own device through a DC bias potential of at least one of the pair of differential transmission paths. According to this situation, there is an effect of superimposing a first signal transmitted by differential transmission and a second signal transmitted by in-phase transmission on the same transmission path to transmit the first signal and the second signal.

[0012] Furthermore, in the first aspect, the first signal may be an audio signal, for example, using the MLT-3 method and the NRZ method as modulation during transmission.

[0013] Furthermore, the first aspect may be further provided with a communication unit, wherein the communication unit performs communication with an external device for encrypting and decrypting the first signal via a second transmission path different from the transmission path. According to this situation, there is an effect of transmitting the encrypted first signal. Furthermore, the utility line and the hot plug detection line forming the HDMI cable may be used as the above-mentioned transmission path, and the display data channel forming the HDMI cable may be used as the above-mentioned second transmission path.

[0014] Furthermore, a second aspect of the present technology is an interface circuit provided with: a first transmission unit that transmits a first signal including a clock component as a differential signal to an external device via a transmission path; a second transmission unit that superimposes a second signal for decrypting the first signal as an in-phase signal on the transmission path to transmit the superimposed signal to the external device; and a status notification unit that communicates with the external device via a pair of differential transmission paths included in the transmission path, and notifies the external device of the connection state of its own device through a DC bias potential of at least one of the pair of differential transmission paths. According to this situation, there is an effect of superimposing the first signal transmitted by differential transmission and the second signal for decrypting the first signal transmitted by in-phase transmission on the same transmission path to transmit the superimposed signal.

[0015] Furthermore, in the second aspect, the above-mentioned first signal may be an audio signal. Furthermore, a utility line and a hot plug detection line forming an HDMI cable may be used as a transmission path.

[0016] Furthermore, a third aspect of the present technology is an interface circuit provided with: a first receiving unit that extracts a first signal including a clock component from a differential signal received from an external device via a transmission path; a second receiving unit that extracts a second signal including a clock component from an in-phase signal received from an external device via the transmission path; and a state receiving unit that communicates with an external device via a pair of differential transmission paths included in the transmission path, and is notified of a connection state by the external device through a DC bias potential of at least one of the pair of differential transmission paths. According to this situation, there is an effect of receiving a first signal transmitted by differential transmission and a second signal transmitted by in-phase transmission via the same transmission path.

[0017] Furthermore, in the third aspect, the first signal may be an audio signal.

[0018] Furthermore, the third aspect may be further provided with a communication unit, wherein the communication unit performs communication with an external device for encrypting and decrypting the first signal via a second transmission path different from the transmission path. According to this situation, there is an effect of receiving the encrypted first signal. Furthermore, the utility line and the hot plug detection line forming the HDMI cable may be used as the above-mentioned transmission path, and the display data channel forming the HDMI cable may be used as the above-mentioned second transmission path.

[0019] Furthermore, a fourth aspect of the present technology is an interface circuit provided with: a first receiving unit that extracts a first signal including a clock component from a differential signal received from an external device via a transmission path; a second receiving unit that extracts a second signal for decrypting the first signal from an in-phase signal received from an external device via the transmission path; and a state receiving unit that communicates with an external device via a pair of differential transmission paths included in the transmission path, and is notified of a connection state by the external device through a DC bias potential of at least one of the pair of differential transmission paths. According to this situation, there is an effect of receiving a first signal transmitted by differential transmission and a second signal for decrypting the first signal transmitted by in-phase transmission via the same transmission path.

[0020] Furthermore, in the fourth aspect, the above-mentioned first signal may be an audio signal. Furthermore, a utility line and a hot plug detection line forming an HDMI cable may be used as a transmission path.

[0021] Furthermore, a fifth aspect of the present technology is an information processing system obtained by connecting a first interface circuit and a second interface circuit to each other via a transmission path, wherein the first interface circuit is provided with: a first transmission unit that transmits a first signal containing a clock component as a differential signal to the second interface circuit via the transmission path; a second transmission unit that superimposes a second signal containing a clock component as an in-phase signal on the transmission path to transmit the superimposed signal to the second interface circuit; and a status notification unit that communicates with the second interface circuit via a pair of differential transmission paths included in the transmission path, and transmits the status notification unit to the second interface circuit via the pair of differential transmission paths. The first interface circuit is notified of the connection state of the first interface circuit to the second interface circuit by the DC bias potential of at least one of the pair of differential transmission paths, and the second interface circuit is provided with: a first receiving unit that extracts a first signal containing a clock component from a differential signal received from the first interface circuit via a transmission path; a second receiving unit that extracts a second signal containing a clock component from an in-phase signal received from the first interface circuit via the transmission path; and a state receiving unit that communicates with the first interface circuit via the pair of differential transmission paths included in the transmission path, and is notified of the connection state by the first interface circuit through the DC bias potential of at least one of the pair of differential transmission paths. According to this situation, there is an effect of superimposing the first signal transmitted by differential transmission and the second signal transmitted by in-phase transmission on the same transmission path for transmission and reception.

[0022] Effects of the Invention

[0023] According to the present technology, an excellent effect of being able to transmit signals at high speed in the direction opposite to the transmission direction of the main large-capacity channel can be obtained. Meanwhile, the effect is not necessarily limited to the effect described here, and may be any effect described in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic configuration diagram of an interface compliant with the HDMI standard.

[0025] Figure 2 is a view illustrating an example of a pin arrangement of a connector conforming to the HDMI standard.

[0026] Figure 3 1 is a diagram illustrating an internal configuration example of the source device 100 and the sink device 200 in the embodiment of the present invention.

[0027] Figure 4 1 is a diagram illustrating a configuration example of the source-side reception circuit 140 and the sink-side transmission circuit 250 in the embodiment of the present technology.

[0028] Figure 5is a view illustrating an overview of operations in the embodiment of the present technology.

[0029] Figure 6 1 is a diagram illustrating a configuration example of the sink device model detection circuit 110 and the source device model detection circuit 210 in the embodiment of the present technology.

[0030] Figure 7 is a view illustrating a configuration example of the plug connection detection circuit 120 and the plug connection transmission circuit 220 in the embodiment of the present technology.

[0031] Figure 8 is a view illustrating an overview of a copyright protection technology application system in general high-quality content transmission.

[0032] Fig. 9 is a diagram illustrating a configuration example of the source device 100 in the second embodiment of the present technology.

[0033] Fig.10 : is a diagram illustrating a configuration example of the sink device 200 in the second embodiment of the present technology.

[0034] Fig.11 is a sequence diagram illustrating an example of an authentication and key exchange process in the second embodiment of the present technology.

[0035] Fig.12 is a view illustrating a configuration example of the optical disc player 500 in the embodiment of the present technology.

[0036] Fig.13 is a view illustrating a configuration example of a television receiver 600 in the embodiment of the present technology.

[0037] Fig.14 is a view illustrating a configuration example of a digital camera 700 in the embodiment of the present technology. DETAILED DESCRIPTION

[0038] Modes for carrying out the present technology (hereinafter, referred to as embodiments) are described below. The description is made in the following order.

[0039] 1. First Embodiment (Example of Transmitting Signals in Reverse Directions)

[0040] 2. Second Embodiment (Example of Transmitting a Key for Copyright Protection)

[0041] 3. Third Embodiment (Example of Transmitting Clock Signal by In-Phase Signal)

[0042] 4. Application Examples

[0043] <1. First Embodiment>

[0044] [HDMI-compliant interface]

[0045] Figure 1 3 is a schematic configuration diagram of an interface conforming to the HDMI standard. In the HDMI standard, the transmission direction of the basic high-speed transmission line is determined in one direction; the device on the transmission side is called a source device, and the device on the receiving side is called a sink device. In this example, the source device 100 and the sink device 200 are connected to each other via an HDMI cable 300. Next, the source device 100 includes a transmitter 101 that performs a transmission operation, and the sink device 200 includes a receiver 201 that performs a reception operation.

[0046] A serial transmission method called transition minimized differential signaling (TMDS) is used for transmission between the transmitter 101 and the receiver 201. In the HDMI standard, video signals and audio signals are transmitted by using three TMDS channels 310 to 330. That is, in an active image segment (which is a segment obtained by removing a horizontal blanking interval and a vertical blanking interval from a segment from a certain vertical synchronization signal to a next vertical communication signal), a differential signal corresponding to uncompressed pixel data of a single screen image is unidirectionally transmitted toward the sink device 200 via the TMDS channels 310 to 330. And, in a horizontal blanking interval or a vertical blanking interval, a differential signal corresponding to audio data, control data, other auxiliary data, etc. is unidirectionally transmitted toward the sink device 200 via the TMDS channels 310 to 330.

[0047] Also, in the HDMI standard, a clock signal is transmitted via the TMDS clock channel 340. In each of the TMDS channels 310 to 330, 10-bit pixel data may be transmitted during one clock transmitted via the TMDS clock channel 340.

[0048] Also, in the HDMI standard, a display data channel (DDC) 350 is provided. The display data channel 350 is basically used by the source device 100 to read the E-EDID information stored in the EDID ROM 282 in the sink device 200. When the sink device 200 is a display device, the enhanced extended display identification data (E-EDID) information indicates information about settings and performance, such as model, resolution, color characteristics, and timing. The E-EDID information is maintained in the EDID ROM 282 of the sink device 200.

[0049] In addition, in the HDMI standard, a consumer electronics control (CEC) line 361, a utility line 362, a hot plug detection (HPD) line 363, etc. are set. The CEC line 361 is a line for performing bidirectional communication of device control signals. Although the display data channel 350 connects devices on a one-to-one basis, the CEC line 361 is shared by all devices connected to the HDMI to perform communication.

[0050] The HPD line 363 is a line for detecting connection (hot plug) to another device via the HDMI cable. In the HDMI 1.4 standard, an audio return channel (ARC) is defined, wherein the audio return channel (ARC) is used to transmit an audio signal as an in-phase signal from the sink device 200 to the source device 100 by using the utility line 362 and the HPD line 363. In the embodiment of the present invention, the audio signal is transmitted at a high speed as a differential signal for transmitting a high-quality audio signal from the sink device 200 to the source device 100 by using the utility line 362 and the HPD line 363.

[0051] The audio format standardized by the International Electrotechnical Commission (IEC) and the like is extended to a 1536KHz frame rate. Its data rate is a maximum of 49.152Mbps. On the other hand, the HEC channel using the utility line 362 and the HPD line 363 defined in the HDMI 1.4 standard corresponds to the transmission of a 100Base-T signal, and its transmission speed is 125Mbps. Therefore, the transmission of the maximum data rate of the currently adopted audio can be performed by using this transmission path.

[0052] Figure 2 3 is a diagram illustrating an example of a pin arrangement of a connector conforming to the HDMI standard. Here, the correspondence between a pin number 301 and a signal name 302 in a pin arrangement called type A is illustrated.

[0053] Each of the TMDS channels 310 to 330 and the TMDS clock channel 340 is formed by three pins, namely a positive electrode, a shielding electrode and a negative electrode; pins 1 to 3, pins 4 to 6, pins 7 to 9 and pins 10 to 12 correspond to TMDS channels 330, 320 and 310 and the TMDS clock channel 340 respectively.

[0054] And, pins 13, 14 and 19 correspond to the CEC line 361, the utility line 362 and the HPD line 363, respectively. And, the display data channel 350 is formed by three pins, namely, the serial clock (SCL), the serial data (SDA) and the ground (ground), which pins 15 to 17 correspond to, respectively. Meanwhile, the ground (pin 17) of the display data channel 350 is shared by the ground of the CEC line 361. Pin 18 corresponds to the power supply line (+5V).

[0055] [Source device and sink device]

[0056] Figure 3 1 is a diagram illustrating an internal configuration example of the source device 100 and the sink device 200 in the embodiment of the present invention. Here, the configuration of the utility line 362 and the HPD line 363, which are the essential parts of the embodiment of the present technology, is described. The source device 100 is provided with a sink device model detection circuit 110, a plug connection detection circuit 120, a source side reception circuit 140, an in-phase signal reception circuit 160, and a differential signal reception circuit 170. And, the sink device 200 is provided with a source device model detection circuit 210, a plug connection transmission circuit 220, a sink side transmission circuit 250, an in-phase signal transmission circuit 260, and a differential signal transmission circuit 270.

[0057] The utility line 362 is a line used in the HDMI 1.4 standard and subsequent standards. The sink device model detection circuit 110 in the source device 100 detects the model of the sink device 200 via the utility line 362. Also, the source device model detection circuit 210 in the sink device 200 detects the model of the source device 100 via the utility line 362. Here, for example, a model configured to transmit ARC via the utility line 362 and the HPD line 363 as in the HDMI 1.4 standard (hereinafter, referred to as an ARC support model) can be taken as the model.

[0058] The HPD line 363 is a line for detecting connection to another device via the HDMI cable as described above. The plug connection transmission circuit 220 in the sink device 200 transmits the fact that the sink device 200 is connected by biasing the terminal connected to the HPD line 363 to a predetermined voltage. The plug connection detection circuit 120 in the source device 100 compares the potential at the terminal connected to the HPD line 363 with the reference potential to detect the connection of the sink device 200.

[0059] In the embodiment of the present technology, the source side reception circuit 140 and the sink side transmission circuit 250 are connected to the utility line 362 and the HPD line 363 having these functions. That is, the source side reception circuit 140 in the source device 100 is connected to the utility line 362 and the HPD line 363 via the capacitors 131 and 132 and the resistor 133. And, that is, the source side reception circuit 140 in the sink device 200 is connected to the utility line 362 and the HPD line 363 via the capacitors 231 and 232 and the resistor 233.

[0060] The source-side reception circuit 140 connects the in-phase signal and the differential signal transmitted from the sink device 200 by using the utility line 362 and the HPD line 363 to the in-phase signal reception circuit 160 and the differential signal reception circuit 170 , respectively.

[0061] The sink-side transmission circuit 250 connects the in-phase signal and the differential signal transmitted from the source device 100 by using the utility line 362 and the HPD line 363 to the in-phase signal transmission circuit 260 and the differential signal transmission circuit 270 , respectively.

[0062] Meanwhile, in this embodiment, a differential signal is expected to be transmitted between the sink-side transmission circuit 250 and the source-side reception circuit 140 through AC coupling.

[0063] The in-phase signal receiving circuit 160 and the in-phase signal transmission circuit 260 perform unidirectional communication in accordance with the SPDIF standard. Here, the SPDIF standard, which is an interface standard for transmitting digital audio signals in real time, is standardized by IEC as "IEC60958". The SPDIF signal transmitted in the SPDIF standard is subjected to bi-phase mark modulation so that this contains a clock component. Meanwhile, the in-phase signal receiving circuit 160 and the in-phase signal transmission circuit 260 are implemented by conventional technology.

[0064] In this embodiment, the differential signal receiving circuit 170 and the differential signal transmission circuit 270 perform unidirectional communication of the audio signal. As for the differential signal, data and a clock synchronized with the data are transmitted. As for the modulation during transmission, the MLT-3 method and the NRZ method are adopted.

[0065] The MLT-3 method for transmission at three voltage levels is defined as a code by which data "0" does not change and data "1" changes. The MLT-3 method is used in the HEC channel in the HDMI 1.4 standard, and a differential signal can be transmitted in this embodiment by driving a similar physical layer at a frequency required for audio transmission. And, when the MLT-3 method is used, a clock can be extracted from the transmission data. Just like 100Base-T, the audio signal can be subjected to Manchester encoding to achieve a DC-free property.

[0066] The NRZ method is a method in which the potential does not return to 0 for each bit transmission; when the data is "0", a zero potential is obtained, and when the data is "1", a positive potential is obtained. Although this is a simple method, encoding such as 8B10B is required to achieve a DC-free property and embed clock information into the data. 8B10B is a method of embedding a clock into 8-bit data and converting 10 bits to transmit the converted data.

[0067] Meanwhile, the in-phase signal receiving circuit 160 is an example of the second receiving unit described in the claims. Also, the differential signal receiving circuit 170 is an example of the first receiving unit described in the claims. Also, the in-phase signal transmission circuit 260 is an example of the second transmission unit described in the claims. Also, the differential signal transmission circuit 270 is an example of the first transmission unit described in the claims. Also, the plug-in connection detection circuit 120 is an example of the state receiving unit described in the claims. Also, the plug-in connection transmission circuit 220 is an example of the state notification unit described in the claims.

[0068] Figure 4 1 is a diagram illustrating a configuration example of the source-side reception circuit 140 and the sink-side transmission circuit 250 in the embodiment of the present technology.

[0069] like Figure 4 As shown in FIG. 1 a , the sink-side transmission circuit 250 includes an amplifier 251 and adders 252 and 253 .

[0070] The amplifier 251 is an amplifier that amplifies the signal supplied from the differential signal transmission circuit 270. The output of the amplifier 251 is a differential signal, and the signal at the positive electrode and the signal at the negative electrode are supplied to adders 252 and 253, respectively.

[0071] The adder 252 adds the signal supplied from the in-phase signal transmission circuit 260 to the positive electrode output of the amplifier 251. The adder 253 adds the signal supplied from the in-phase signal transmission circuit 260 to the negative electrode output of the amplifier 251.

[0072] That is, the signal superimposed by the adders 252 and 253 is an in-phase signal, and the signal output from the amplifier 251 is a differential signal. According to this situation, two signals can be transmitted via the same pair of signal lines (utility line 362 and HPD line 363).

[0073] like Figure 4 As shown in FIG. 2 b , the source side receiving circuit 140 includes an amplifier 141 and an adder 142 .

[0074] The amplifier 141 is an amplifier that amplifies signals from the utility line 362 and the HPD line 363. The signals transmitted via the utility line 362 and the HPD line 363 are differential signals, and the amplifier 141 operates by differential input.

[0075] The adder 142 is a circuit that adds the signal at the positive electrode and the signal at the negative electrode of the output of the amplifier 141 .

[0076] That is, of the signals transmitted via the utility line 362 and the HPD line 363 , the differential signal is extracted by the amplifier 141 , and the in-phase signal is extracted by the adder 142 .

[0077] Figure 5 362, and the HPD line 363. In devices prior to the HDMI 1.4 standard, neither the in-phase signal nor the differential signal is transmitted via the utility line 362 and the HPD line 363. When the in-phase signal is transmitted as in the HDMI 1.4 standard, the positive electrode signal is superimposed on pins 14 and 19. When the differential signal is transmitted as in this embodiment, the positive electrode signal is superimposed on pin 14, and the negative electrode signal is superimposed on pin 19. In this embodiment, the in-phase signal and the differential signal can also be transmitted simultaneously.

[0078] Therefore, the in-phase signal and the differential signal can be independently transmitted via the utility line 362 and the HPD line 363, and the following conditions can be supported: both signals are transmitted, or only one of the signals is transmitted, without requiring a special mechanism on the receiving side (source side receiving circuit 140).

[0079] When the user desires high-quality audio transmission from the sink device 200 side, the source device 100 or the sink device 200 requests activation of the transmission function by using a command of the CEC line 361 or the like and communication of the DDC 350. For example, a situation in which the user selects a function by using a remote controller of a display as the sink device 200 or selects a transmission function by activating an audio player as the source device 100 corresponds to this situation. The source device 100 or the sink device 200 receiving the activation request transmits a response of whether the transmission function is supported as a response to the activation request by a similar method in consideration of the current use status of the TMDS channel or the like. Upon receiving a response to the activation request or a transmission response, both devices change their configurations to start high-quality audio transmission. Similarly, when canceling or stopping the transmission function, this can be achieved by conveying a similar command or the like.

[0080] [Model detection]

[0081] Figure 6 1 is a diagram illustrating a configuration example of the sink device model detection circuit 110 and the source device model detection circuit 210 in the embodiment of the present technology.

[0082] like Figure 6As shown in a of FIG. 1 , the sink device model detection circuit 110 is provided with resistors 111 and 112, a capacitor 113, and a comparator 116. The resistor 111 pulls up the utility line 362 to +5V. The resistor 111 exists only when the source device 100 is a specific model, and when the source device 100 is not a specific model, the pull-up is not performed. The resistor 112 and the capacitor 113 form a low-pass filter. The output of the low-pass filter is supplied to the signal line 114. The comparator 116 compares the DC potential supplied from the low-pass filter to the signal line 114 with the reference potential supplied to the signal line 115.

[0083] And, if Figure 6 As shown in FIG. 2 , the source device model detection circuit 210 is provided with resistors 211 and 212, a capacitor 213, and a comparator 216. The resistor 211 pulls down the utility line 362 to the ground potential. The resistor 211 exists only when the sink device 200 is a specific model, and when the sink device 200 is not a specific model, the pull-down is not performed. The resistor 212 and the capacitor 213 form a low-pass filter. The output of the low-pass filter is supplied to the signal line 215. The comparator 216 compares the DC potential supplied from the low-pass filter to the signal line 215 with the reference potential supplied to the signal line 214.

[0084] When the sink device 200 is a specific model, the pull-down by the resistor 211 is performed, and the potential of the utility line 362 reaches 2.5 V; when the sink device 200 is not a specific model, the sink device 200 is turned on, and 5 V is obtained. Therefore, for example, when the reference potential of the signal line 115 is set to 3.75 V, the model of the sink device 200 can be distinguished by the source device 100 based on the output of the signal line 117.

[0085] Similarly, when the source device 100 is a specific model, pull-up by the resistor 111 is performed and the potential of the utility line 362 reaches 2.5 V, and when the source device 100 is not a specific model, 0 V is obtained. Therefore, for example, when the reference potential of the signal line 214 is set to 1.25 V, the model of the source device 100 can be distinguished by the sink device 200 based on the output of the signal line 217.

[0086] The signal for detecting the model number is transmitted through a DC bias potential so that this does not affect the in-phase signal and the differential signal transmitted as an AC signal.

[0087] [Connection Detection]

[0088] Figure 7 is a view illustrating a configuration example of the plug connection detection circuit 120 and the plug connection transmission circuit 220 in the embodiment of the present technology.

[0089] like Figure 7 As shown in a of FIG. 1 , the plug connection transmission circuit 220 is provided with a choke coil 221 and resistors 222 and 223. The choke coil 221 and the resistors 222 and 223 bias the HPD line 363 to about 4V, for example.

[0090] And, if Figure 7 As shown in FIG. 1 , the plug connection detection circuit 120 is provided with resistors 121 and 122, a capacitor 123, and a comparator 126. The resistor 121 pulls down the HPD line 363 to the ground potential. The resistor 122 and the capacitor 123 form a low-pass filter. The output of the low-pass filter is supplied to the signal line 124. The comparator 126 compares the DC potential supplied from the low-pass filter to the signal line 124 with the reference potential supplied to the signal line 125.

[0091] Here, for example, 1.4 V is supplied as a reference potential to the signal line 125. When the source device 100 is not connected to the HPD line 363, the input potential is pulled down by the resistor 121, and the potential of the signal line 124 becomes lower than the reference potential of the signal line 125. On the other hand, when the source device 100 is connected to the HPD line 363, since this is biased to about 4 V, the potential of the signal line 124 becomes higher than the reference potential of the signal line 125. Therefore, it is possible to detect whether the sink device 200 is connected by the source device 100 based on the output of the signal line 127.

[0092] The signal for detecting the plug connection is transmitted via a DC bias potential so that this does not affect the in-phase signal and the differential signal transmitted as an AC signal.

[0093] In this way, according to the first embodiment of the present technology, a high-quality audio transmission path independent of the TMDS channel can be formed. Although in the above embodiment, the direction opposite to the direction of the TMDS channel is taken as the transmission direction of the ARC, this can also be the same direction as the direction of the TMDS channel. In the opposite direction, an ARC application that supports high-quality audio transmission can be realized, and in the same direction, a transmission application dedicated to audio that does not require video transmission can be realized.

[0094] <2. Second Embodiment>

[0095] While high-quality audio transmission becomes possible in the above-described first embodiment, copyright protection is sometimes required in the transmission. In this second embodiment, a method of authentication and key exchange required for copyright protection is described.

[0096] Figure 8 1 is a view illustrating an overview of a copyright protection technology application system in general high-quality content transmission. The copyright protection technology application system is provided with a transmitter 10 that transmits an audio signal and a receiver 20 that receives the audio signal.

[0097] The transmitter 10 is provided with a transmission unit 11, an encryption unit 12, a communication unit 13, and an authentication / key exchange unit 14. The communication unit 13 performs communication for key exchange and device authentication required for encrypting an audio signal. The authentication / key exchange unit 14 authenticates the device and exchanges keys via the communication unit 13. The encryption unit 12 encrypts the audio signal by the encryption key supplied from the authentication / key exchange unit 14. The transmission unit 11 transmits the audio signal encrypted by the encryption unit 12.

[0098] The receiver 20 is provided with a receiving unit 21, a decryption unit 22, a communication unit 23, and an authentication / key exchange unit 24. The receiving unit 21 receives the encrypted audio signal transmitted from the transmitter 10. The decryption unit 22 decrypts the encrypted audio signal received by the receiving unit 21. The communication unit 23 performs communication for key exchange and device authentication required for decrypting the audio signal. The authentication / key exchange unit 24 authenticates the device and exchanges keys via the communication unit 23.

[0099] That is, the transmitter 10 and the receiver 20 include a bidirectional communication channel for device authentication and key exchange independent of the transmission path for transmitting the encrypted audio signal. For example, device authentication based on the private key of each device (e.g., RSA key pair) is performed as an authentication / key exchange process. During the communication process, the content key is encrypted with a random number shared by the transmitter 10 and the receiver 20, and transmitted from the transmitter 10 to the receiver 20 so that the transmitter 10 and the receiver 20 share the same content key. Then, for example, by using an AES encryptor and decryptor with the content key to encrypt the content information transmitted by the transmitter 10 and decrypt the content information received by the receiver 20, the information is securely transmitted. At the same time, the content key can be updated at a certain interval to further improve the security of the content key.

[0100] Meanwhile, the communication unit 13 or 23 is an example of the communication unit described in the claims.

[0101] In the second embodiment of the present technology, the communication path for copyright protection described above can be implemented in the following manner. As a first example, a DDC 350 compliant with the HDMI standard can be used. When a high-quality audio signal is transmitted according to an embodiment of the present technology, a video signal is not transmitted through a TMDS channel. Therefore, the DDC 350 can be used for copyright protection information communication for this transmission. In the case of communication in the same direction as the transmission direction of the TMDS channel, the DDC compliant with the HDMI standard can be directly applied. In the case of communication in the direction opposite to the transmission direction of the TMDS channel, the communication performed by the DDC 350 compliant with the HDMI standard should be configured in the opposite direction. Therefore, in the second embodiment of the present technology, as described below, the DDC register usually installed on the sink device 200 side is also installed on the source device 100 side, and the sink device 200 is allowed to operate as a master device.

[0102] As a second example, there may be a method of superimposing as an in-phase signal on the utility line 362 and the HPD line 363 for communication. The transmission of data required for authentication is at most about several hundred Kbps in both directions, so that even when this is superimposed as an in-phase signal, the quality of the differential signal can be maintained. According to the second example, no change of the DDC 350 is required.

[0103] An example of changing the DDC 350 to a bidirectional line is described below as a first example of a communication path for copyright protection. Figure 2 As shown, the DDC 350 is formed of three pins: serial clock (SCL), serial data (SDA), and ground (GND). A register group such as the EDID ROM 282 is provided on the sink device 200, and the register group is accessed, and the SDA line is driven based on the timing of the SCL line.

[0104] [Bidirectional DDC]

[0105] Fig. 9 is a diagram illustrating a configuration example of the source device 100 in the second embodiment of the present technology. Fig.10 35 is a diagram illustrating a configuration example of the sink device 200 in the second embodiment of the present technology. Here, a state is described in which the source device 100 and the sink device 200 are connected to each other via the SCL line 351 and the SDA line 352. Meanwhile, a ground line is not described here.

[0106] The source device 100 is provided with a processor 181, a DDC register 183, a selector 184, and drivers 185 to 187. Similarly, the sink device 200 is provided with a processor 281, a DDC register 283, a selector 284, and drivers 285 to 287.

[0107] When data is transmitted from the source device 100 to the sink device 200, the source device 100 acts as a master device, and "1" is output from the processor 181 as the transmission direction signal DIR. According to this situation, the driver 185 operates, and the output of the driver 186 is placed in a high impedance state. Therefore, the clock signal CLK from the processor 181 is output to the SCL line 351. And, the selector 184 selects the data signal DATA from the processor 181. Therefore, the data signal DATA is transmitted to the SDA line 352 via the driver 187.

[0108] In this case, the sink device 200 acts as a slave device, and "0" is output from the processor 181 as the transmission direction signal DIR. According to this situation, the driver 286 operates, and the output of the driver 285 is placed in a high impedance state. Therefore, the value of the SCL line 351 is input to the DDC register 283 as the clock signal CK. And, the selector 284 connects the value of the SDA line 352 as the data signal D to the DDC register 283. Therefore, the DDC register 283 maintains or outputs the data signal D according to the clock signal CK.

[0109] On the other hand, when data is transmitted from the sink device 200 to the source device 100, the sink device 200 acts as a master device, and "1" is output from the processor 281 as the transmission direction signal DIR. Also, in this case, the source device 100 acts as a slave device, and "0" is output from the processor 181 as the transmission direction signal DIR. That is, the source device 100 and the sink device 200 operate opposite to the above-described case. At the same time, when the transmission direction is switched, the change in configuration is required to be known by both the source device 100 and the sink device 200 as described above.

[0110] In this way, the DDC 350 is allowed to perform two-way communication so that information required for copyright protection can be communicated between the source device 100 and the sink device 200.

[0111] [Authentication and key exchange process]

[0112] Fig.11 is a sequence diagram illustrating an example of an authentication and key exchange process in the second embodiment of the present technology.

[0113] First, the source device 100 transmits the public key of the source device 100 assigned the certificate of the certificate authority to the sink device 200 (S911). The sink device 200 receiving the public key of the source device 100 transmits the public key of the sink device 200 assigned the certificate of the certificate authority and the device ID to the source device 100 (S921).

[0114] The source device 100 receiving the public key and device ID of the sink device 200 checks whether the device belongs to an invalid device with reference to the device ID (S913). When it belongs to an invalid device, the process ends. When it does not belong to an invalid device, the source device 100 generates a random number, encrypts the random number with the public key of the sink device 200, and transmits it to the sink device 200 (S914).

[0115] The sink device 200 generates a random number and encrypts the random number with the public key of the source device 100. Next, the sink device 200 sends both the encrypted data received from the source device 100 and the encrypted data encrypted by itself, and transmits the encrypted data encrypted by itself and the signature data to the source device 100 (S925).

[0116] The source device 100 verifies the signature data received from the sink device 200 (S916). Here, when the signature is incorrect, the process stops. When the signature is correct, both the encrypted data received from the sink device 200 and the encrypted data encrypted by itself are sent and transmitted to the sink device 200. Next, a key is generated from the random number transmitted by the source device 100 itself and the data obtained by decrypting the encrypted data received from the sink device 200 (S917).

[0117] The sink device 200 verifies the signature data received from the source device 100 (S928). Here, when the signature is incorrect, the process stops. When the signature is correct, a key is generated from the random number transmitted by the sink device 200 itself and the data obtained by decrypting the encrypted data received from the source device 100 (S929).

[0118] The keys generated in this manner by both the source device 100 and the sink device 200 are used to encrypt and decrypt audio data.

[0119] In this way, according to the second embodiment of the present technology, high-quality audio transmission can be achieved in a copyright-protected state.

[0120] <3. Third embodiment>

[0121] In the above-described first embodiment, the audio signal containing the clock component is transmitted from the sink device 200 to the source device 100 as a differential signal by using the utility line 362 and the HPD line 363. On the other hand, in this third embodiment, the audio signal is transmitted as a differential signal, and the clock signal of the audio signal is transmitted as an in-phase signal. Meanwhile, the basic configuration is similar to that of the first embodiment, so that a detailed description of the basic configuration is omitted.

[0122] In the third embodiment, the word clock of the audio signal can be used as the clock signal. And, in the case of a high-speed word clock, its basic clock can be used. As the frequency of the basic clock, for example, 32KHz, 44.1KHz or 48KHz is adopted. When the basic clock is used, the actual word clock is a multiple of the basic clock. However, a sufficiently low speed signal is required to suppress unnecessary radiation.

[0123] The clock signal as the in-phase signal is transmitted in the same direction as the direction of the audio signal so that the reproduced clock can be easily generated on the receiving side. At the same time, a clock for high-quality reproduction synchronized with the master clock on the receiving side can also be obtained by transmitting the clock signal as the in-phase signal from the receiving side in the opposite direction.

[0124] <4. Application Examples>

[0125] Although the application example regarding the interface circuit conforming to the HDMI standard is described in the above-mentioned embodiment, the present technology can also be applied to another configuration. Herein, the application example regarding the optical disc player, the television receiver, and the digital camera is described as the application example.

[0126] Fig.12 510 is a view illustrating a configuration example of an optical disc player 500 in an embodiment of the present technology. The optical disc player 500 is provided with a processor 511, a flash ROM 512, an SDRAM 513, and a display control unit 514. The optical disc player 500 is also provided with a SATA interface 521, a BD drive 522, an Ethernet (TM) interface 523, and a network terminal 524. The optical disc player 500 is also provided with a high-speed bus interface 525, an HDMI transmission unit 526, an HDMI terminal 527, and a remote control receiving unit 529. The optical disc player 500 is also provided with an MPEG decoder 533, a video output terminal 538, and an audio output terminal 539. The optical disc player 500 is also provided with a graphics generation circuit 542, a panel drive circuit 543, and a display panel 544. The processor 511, the flash ROM 512, the SDRAM 513, the display control unit 514, the SATA interface 521, the Ethernet interface 523, and the MPEG decoder 533 are connected to each other via a bus 510.

[0127] The processor 511 controls the entire optical disk player 500. The flash ROM 512 is a memory that stores programs and the like required for the operation of the processor 511. The SDRAM 513 is a memory that stores data and the like required for the operation of the processor 511.

[0128] The SATA interface 521 is an interface for connecting to a serial ATA. The BD drive 522 is an optical disc drive for driving a Blu-ray (TM) optical disc. The Ethernet interface 523 is an interface for connecting to Ethernet. The network terminal 524 is a terminal for connecting to Ethernet.

[0129] The high-speed bus interface 525 is a utility line 362 and an HPD line 363 that conform to the HDMI standard. The HDMI transmission unit 526 is a transmission circuit of an interface that conforms to the HDMI standard. The HDMI terminal 527 is a terminal that conforms to the HDMI standard.

[0130] The remote control receiving unit 529 receives a signal from a remote controller (not shown) operated by a user.

[0131] The MPEG decoder 533 is a decoder for decoding a signal conforming to the MPEG standard. The video output terminal 538 is a terminal for outputting a video signal. The audio output terminal 539 is a terminal for outputting an audio signal.

[0132] The display control unit 514 performs control required for display on the display panel 544. The graphic generation circuit 542 generates a graphic image to be displayed on the display panel 544. The panel drive circuit 543 is a circuit for driving the display panel 544. The display panel 544 is a panel for displaying a video. Although the optical disc player 500 having the display panel 544 embedded therein is taken here, there may also be a player not having the display panel 544 embedded therein.

[0133] The high-speed bus interface 525 is inserted between the Ethernet interface 523 and the HDMI terminal 527. The high-speed bus interface 525 transmits the data to be transmitted supplied from the processor 511 to the partner device via the HDMI cable from the HDMI terminal 527. The high-speed bus interface 525 also transmits the reception data received from the partner device to the processor 511 via the HDMI terminal 527 from the HDMI cable.

[0134] When recording content, the content data to be recorded is obtained via a digital tuner (not shown) and via the Ethernet interface 523 or the high-speed bus interface 525. The content data is input to the SATA interface 521 and recorded in the BD by the BD drive 522. The content data can also be recorded on a hard disk drive (HDD) (not shown) connected to the SATA interface 521.

[0135] When reproducing content, the content data (MPEG stream) reproduced from the BD by the BD drive 522 is supplied to the MPEG decoder 533 via the SATA interface 521. The MPEG decoder 533 performs a decoding process of the reproduced content data to obtain baseband image and audio data. The image data is output to the video output terminal 538 via the graphic generation circuit 542. And, the audio data is output to the audio output terminal 539.

[0136] Also, when reproducing content, image data obtained by the MPEG decoder 533 is supplied to the panel driving circuit 543 via the graphic generating circuit 542 according to a user operation, and the reproduced image is displayed on the display panel 544. Also, audio data obtained by the MPEG decoder 533 is supplied to a speaker (not shown) according to a user operation, and audio corresponding to the reproduced image is output.

[0137] When reproducing content, if the image and audio data obtained by the MPEG decoder 533 is transmitted via the HDMITMDS channel, the image and audio data are supplied to the HDMI transmission unit 526 for packetization. Then, the image and audio data are output from the HDMI transmission unit 526 to the HDMI terminal 527.

[0138] Also, when reproducing content, if content data reproduced by the BD drive 522 is transmitted to a network, the content data is output to a network terminal 524 via an Ethernet interface 523. Similarly, when reproducing content, if content data reproduced by the BD drive 522 is transmitted to a bidirectional communication path of an HD cable, the content data is output to an HDMI terminal 527 via a high-speed bus interface 525. Here, before outputting the image data, the image data may be encrypted for transmission by using a copyright protection technology such as HDCP, DTCP, and DTCP+.

[0139] Fig.136 is a view illustrating a configuration example of a television receiver 600 in an embodiment of the present technology. The television receiver 600 is provided with a processor 611, a flash ROM 612, an SDRAM 613, and a display control unit 614. The television receiver 600 is also provided with an Ethernet interface 623 and a network terminal 624. The television receiver 600 is also provided with a high-speed bus interface 625, an HDMI receiving unit 626, an HDMI terminal 627, and a remote control receiving unit 629. The television receiver 600 is also provided with an antenna terminal 631, a digital tuner 632, and an MPEG decoder 633. The television receiver 600 is also provided with a video signal processing circuit 641, a graphics generation circuit 642, a panel drive circuit 643, and a display panel 644. The television receiver 600 is also provided with an audio signal processing circuit 651, an audio amplification circuit 653, and a speaker 654. The processor 611 , the flash ROM 612 , the SDRAM 613 , the display control unit 614 , the Ethernet interface 623 , the high-speed bus interface 625 , and the MPEG decoder 633 are connected to one another via the bus 610 .

[0140] The processor 611 controls the entire television receiver 600. The flash ROM 612 is a memory storing programs and the like required for the operation of the processor 611. The SDRAM 613 is a memory storing data and the like required for the operation of the processor 611. The display control unit 614 performs control on the display panel 644 required for display.

[0141] The Ethernet interface 623 is an interface for connecting to Ethernet. The network terminal 624 is a terminal for connecting to Ethernet. The high-speed bus interface 625 is a utility line 362 and an HPD line 363 that conform to the HDMI standard. The HDMI receiving unit 626 is a transmission circuit of an interface that conforms to the HDMI standard. The HDMI terminal 627 is a terminal that conforms to the HDMI standard.

[0142] The remote control receiving unit 629 receives a signal from a remote controller (not shown) operated by a user.

[0143] The antenna terminal 631 is a terminal for outputting a television broadcast signal received by a receiving antenna (not shown). The digital tuner 632 processes the television broadcast signal input to the antenna terminal 631 to extract a partial TS from a predetermined transport stream corresponding to a channel selected by a user.

[0144] The MPEG decoder 633 is a decoder that decodes a signal conforming to the MPEG standard. The MPEG decoder 633 performs a decoding process of a video PES packet formed by a TS packet of video data obtained by the digital tuner 632 to obtain image data. The MPEG decoder 633 also performs a decoding process of an audio PES packet formed by a TS packet of audio data obtained by the digital tuner 632 to obtain audio data.

[0145] The video signal processing circuit 641 and the graphic generation circuit 642 perform signal processing of the image data obtained by the MPEG decoder 633 or the image data received by the HDMI receiving unit 626 as needed. As the signal processing, for example, a scaling process (resolution conversion process), a superposition process of graphic data, a gamma correction of a WCG image, etc. are adopted. The panel driving circuit 643 is a circuit for driving the display panel 644 based on the video (image) data output from the graphic generation circuit 642. The display panel 644 is a panel for displaying a video. The display panel 644 can be formed, for example, by a liquid crystal display (LCD), a plasma display panel (PDP), an organic electroluminescent (EL) panel, etc.

[0146] Meanwhile, although an example in which the display control unit 614 is included in addition to the processor 611 is described in this embodiment, it is also possible that the processor 611 directly controls the display on the display panel 644. Also, the processor 611 and the display control unit 614 may be formed of one chip or a plurality of cores.

[0147] The audio signal processing circuit 651 performs the required processes of the audio signal obtained by the MPEG decoder 633, for example, D / A conversion. The audio amplifier circuit 653 amplifies the audio signal output from the audio signal processing circuit 651 to supply to the speaker 654. Meanwhile, the speaker 654 may be a mono speaker and a stereo speaker. Also, the number of the speakers 654 may be one or two or more. Also, the speaker 654 may be an earphone or a headset. Also, the speaker 654 may support 2.1 channels or 5.1 channels. Also, the speaker 654 may be wirelessly connected to the television receiver 600. Also, the speaker 654 may be another device.

[0148] The television broadcast signal input to the antenna terminal 631 is supplied to the digital tuner 632. The digital tuner 632 processes the television broadcast signal to output a predetermined transport stream corresponding to the channel selected by the user. Then, a partial TS (TS packet of video data and TS packet of audio data) is extracted from the transport stream, and the partial TS is supplied to the MPEG decoder 633.

[0149] The MPEG decoder 633 performs a decoding process of a video PES packet formed of a TS packet of video data to obtain video data. The video data is supplied to the panel drive circuit 643 after undergoing a scaling process (resolution conversion process), a superimposition process of graphic data, etc. performed by the video signal processing circuit 641 and the graphic generation circuit 642 as necessary. Thus, an image corresponding to the channel selected by the user is displayed on the display panel 644.

[0150] And, the MPEG decoder 633 performs a decoding process of the audio PES packet formed by the TS packet of the audio data to obtain the audio data. The audio data is subjected to a required process (e.g., D / A conversion) performed by the audio signal processing circuit 651, and is further amplified by the audio amplification circuit 653 to be supplied to the speaker 654. Therefore, the audio corresponding to the channel selected by the user is output from the speaker 654.

[0151] And, the content data (image data and audio data) supplied from the network terminal 624 to the Ethernet interface 623 or supplied from the HDMI terminal 627 via the high-speed bus interface 625 is supplied to the MPEG decoder 633. Thereafter, an operation similar to the operation when a television broadcast signal is received as described above is performed, an image is displayed on the display panel 644, and audio is output from the speaker 654.

[0152] And, in the HDMI receiving unit 626, image data and audio data transmitted from the optical disc player 500 connected to the HDMI terminal 627 via the HDMI cable are obtained. The image data is supplied to the video signal processing circuit 641. And, the audio data is directly supplied to the audio signal processing circuit 651. Thereafter, an operation similar to the operation when the television broadcast signal is received as described above is performed, an image is displayed on the display panel 644, and audio is output from the speaker 654.

[0153] Fig.14 700 is a view illustrating a configuration example of a digital camera 700 in an embodiment of the present technology. The digital camera 700 is provided with a system control processor 711, a flash ROM 712, an SDRAM 713, and a display control unit 714. The digital camera 700 is also provided with a high-speed bus interface 725, an HDMI transmission unit 726, an HDMI terminal 727, and a user operation unit 728. The digital camera 700 is also provided with a graphics generation circuit 742, a panel drive circuit 743, and a display panel 744. The digital camera 700 is also provided with an imager 751, an imager driver 752, and a camera control unit 753. The digital camera 700 is also provided with an imaging signal processing circuit 754, a microphone 755, an audio signal processing circuit 756, a static image signal processing circuit 757, a dynamic image signal processing circuit 758, a recording / reproducing unit 759, and a memory card 760.

[0154] The system control processor 711 controls the entire digital camera 700. The flash ROM 712 is a memory storing programs and the like required for the operation of the system control processor 711. The SDRAM 713 is a memory storing data and the like required for the operation of the system control processor 711. The display control unit 714 performs control on the display panel 744 required for display.

[0155] The high-speed bus interface 725 is a utility line 362 and an HPD line 363 that conform to the HDMI standard. The HDMI transmission unit 726 is a transmission circuit of an interface that conforms to the HDMI standard. The HDMI terminal 727 is a terminal that conforms to the HDMI standard.

[0156] The user operation unit 728 accepts an operation from the user. The user operation unit 728 may be, for example, a switch, a wheel, a touch panel unit to which the user inputs an instruction by approaching / touching, a mouse, a keyboard, a gesture input unit to detect input of an instruction by a camera, an audio input unit to input an instruction by audio, and a remote controller. The system control processor 711 determines the operation state of the user operation unit 728 to control the operation of the digital camera 700. In addition to the imaging (recording) operation and the reproducing operation, the user may also perform an input operation of various pieces of additional information and the like through the user operation unit 728.

[0157] The graphic generation circuit 742 generates a graphic image to be displayed on the display panel 744. The panel driving circuit 743 is a circuit for driving the display panel 744. The display panel 744 is a panel for displaying a video.

[0158] The imager 751 is a photoelectric conversion element that converts a received optical signal into an electric signal. The imager driver 752 is a driver that drives the imager 751. The camera control unit 753 controls the imager driver 752 and the imaging signal processing circuit 754. The imaging signal processing circuit 754 performs signal processing of the electric signal supplied from the imager 751 as an imaging signal.

[0159] The microphone 755 converts surrounding audio to generate an audio signal.

[0160] The audio signal processing circuit 756 performs signal processing of the audio signal generated by the microphone 755 .

[0161] The still image signal processing circuit 757 performs signal processing of the still image signal supplied from the imaging signal processing circuit 754. The dynamic image signal processing circuit 758 performs signal processing of the dynamic image signal supplied from the imaging signal processing circuit 754 and the audio signal processing circuit 756.

[0162] The recording / reproducing unit 759 accesses the memory card 760, the flash ROM 712, etc. to read / write still image data or moving image data. The memory card 760 is a recording medium that records still image data or moving image data.

[0163] The imaging signal obtained by the imager 751 is supplied to the imaging signal processing circuit 754 for processing, and image data corresponding to the object (captured image data) is obtained from the imaging signal processing circuit 754. When a still image is captured, the still image signal processing circuit 757 applies a compression encoding process or the like to the image data output from the imaging signal processing circuit 754, and still image data is generated. The still image data is recorded in the memory card 760 or the like by the recording / reproducing unit 759.

[0164] Furthermore, when capturing a dynamic image, the dynamic image signal processing circuit 758 applies a compression encoding process or the like conforming to the recording medium format to the image data output from the imaging signal processing circuit 754 and the audio data output from the audio signal processing circuit 756, and dynamic image data added to the audio data is generated. The dynamic image data is recorded in the memory card 760 or the like by the recording / reproducing unit 759.

[0165] When a still image is reproduced, still image data is read from the memory card 760 or the like, and is subjected to a decoding process or the like by the still image signal processing circuit 757, and reproduced image data is obtained. The reproduced image data is supplied to the panel drive circuit 743 via the system control processor 711 and the dynamic image signal processing circuit 758, and the still image is displayed on the display panel 744.

[0166] When reproducing a dynamic image, the dynamic image data is read from the memory card 760 or the like by the recording / reproducing unit 759, and is subjected to a decoding process or the like performed by the dynamic image signal processing circuit 758, and the reproduced image data is obtained. Then, the reproduced image data is supplied to the panel driving circuit 743, and the dynamic image is displayed on the display panel 744.

[0167] When image or audio data about still image data or moving image data recorded in the memory card 760 or the like is transmitted to an external device (sink device), the still image data or moving image data is read from the memory card 760. Then, the read still image data or moving image data is supplied to the still image signal processing circuit 757 or the moving image signal processing circuit 758 to undergo a decoding process or the like, and baseband image and audio data are obtained. Then, the baseband image and audio data are supplied to the HDMI transmission unit 726 to be transmitted to the HDMI cable connected to the HDMI terminal 727.

[0168] And, when the image or audio data about the still image data or the moving image data directly output from the imaging signal processing circuit 754 or the audio signal processing circuit 756 is transmitted to the external device (sink device), this is supplied to the HDMI transmission unit 726. Then, this is transmitted to the HDMI cable connected to the HDMI terminal 727.

[0169] Meanwhile, the above-mentioned embodiments describe examples for implementing the present technology, and there is a correspondence between the items in the embodiments and the subject matter of the present invention specified in the claims. Similarly, there is a correspondence between the subject matter of the present invention specified in the claims and the items with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be embodied by various modifications of the embodiments without departing from the spirit thereof.

[0170] The process described in the above embodiment can be regarded as a method having a series of processes, and can be regarded as a program that allows a computer to execute the series of processes and a recording medium storing the program. For example, a compact disc (CD), a mini disc (MD), a digital versatile disc (DVD), a memory card, a Blu-ray (TM) disc, etc. can be used as a recording medium.

[0171] Meanwhile, the effects described in this specification are merely illustrative and not restrictive; there may also be another effect.

[0172] Meanwhile, the present technology may also have the following configurations.

[0173] (1) An interface circuit comprising:

[0174] a first transmission unit that transmits a first signal including a clock component as a differential signal to an external device via a transmission path;

[0175] a second transmission unit that superimposes a second signal including a clock component as an in-phase signal on the transmission path to transmit to the external device; and

[0176] A state notification unit that communicates with the external device via a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device through a DC bias potential of at least one of the pair of differential transmission paths.

[0177] (2) The interface circuit according to (1) described above, wherein the first signal is an audio signal.

[0178] (3) The interface circuit according to (1) or (2) described above further includes: a communication unit that performs communication with the external device for encrypting and decrypting the first signal via a second transmission path different from the transmission path.

[0179] (4) The interface circuit according to (3) above, wherein

[0180] The transmission path is a utility line and a hot plug detection line forming an HDMI cable, and

[0181] The second transmission path is a display data channel forming the HDMI cable.

[0182] (5) An interface circuit comprising:

[0183] a first transmission unit that transmits a first signal including a clock component as a differential signal to an external device via a transmission path;

[0184] a second transmission unit that superimposes a second signal for decrypting the first signal as an in-phase signal on the transmission path to transmit to the external device; and

[0185] A state notification unit that communicates with the external device via a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device through a DC bias potential of at least one of the pair of differential transmission paths.

[0186] (6) The interface circuit according to (5) described above, wherein the first signal is an audio signal.

[0187] (7) The interface circuit according to (5) or (6) described above, wherein the transmission path is a utility line and a hot plug detection line forming an HDMI cable.

[0188] (8) An interface circuit comprising:

[0189] a first transmission unit that transmits the first signal as a differential signal to an external device via a transmission path;

[0190] a second transmission unit that superimposes a second signal including a clock component of the first signal as an in-phase signal on the transmission path to transmit to the external device; and

[0191] A state notification unit that communicates with the external device via a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device through a DC bias potential of at least one of the pair of differential transmission paths.

[0192] (9) The interface circuit according to (8) described above, wherein the first signal is an audio signal.

[0193] (10) The interface circuit according to (8) or (9) described above, wherein the transmission path is a utility line and a hot plug detection line forming an HDMI cable.

[0194] (11) An interface circuit comprising:

[0195] a first receiving unit that extracts a first signal including a clock component from a differential signal received from an external device via a transmission path;

[0196] a second receiving unit that extracts a second signal including a clock component from an in-phase signal received from the external device via the transmission path; and

[0197] A state receiving unit communicates with the external device via a pair of differential transmission paths included in the transmission path, and is notified of a connection state by the external device through a DC bias potential of at least one of the pair of differential transmission paths.

[0198] (12) The interface circuit according to (11) described above, wherein the first signal is an audio signal.

[0199] (13) The interface circuit according to (11) or (12) described above further includes: a communication unit, which performs communication with the external device for encrypting and decrypting the first signal via a second transmission path different from the transmission path.

[0200] (14) An interface circuit according to any one of (11) to (13) above, wherein

[0201] The transmission path is a utility line and a hot plug detection line forming an HDMI cable, and

[0202] The second transmission path is a display data channel forming the HDMI cable.

[0203] (15) An interface circuit comprising:

[0204] a first receiving unit that extracts a first signal including a clock component from a differential signal received from an external device via a transmission path;

[0205] a second receiving unit that extracts a second signal for decrypting the first signal from the in-phase signal received from the external device via the transmission path; and

[0206] A state receiving unit communicates with the external device via a pair of differential transmission paths included in the transmission path, and is notified of a connection state by the external device through a DC bias potential of at least one of the pair of differential transmission paths.

[0207] (16) The interface circuit according to (15) described above, wherein the first signal is an audio signal.

[0208] (17) The interface circuit according to (15) or (16) described above, wherein the transmission path is a utility line and a hot plug detection line forming an HDMI cable.

[0209] (18) An interface circuit comprising:

[0210] a first receiving unit that extracts a first signal from a differential signal received from an external device via a transmission path;

[0211] a second receiving unit that extracts a second signal including a clock component of the first signal from an in-phase signal received from the external device via the transmission path; and

[0212] A state receiving unit communicates with the external device via a pair of differential transmission paths included in the transmission path, and is notified of a connection state by the external device through a DC bias potential of at least one of the pair of differential transmission paths.

[0213] (19) The interface circuit according to (18) described above, wherein the first signal is an audio signal.

[0214] (20) The interface circuit according to (18) or (19) described above, wherein the transmission path is a utility line and a hot plug detection line forming an HDMI cable.

[0215] (21) An information processing system obtained by connecting a first interface circuit and a second interface circuit to each other via a transmission path, wherein

[0216] The first interface circuit is provided with: a first transmission unit, which transmits a first signal containing a clock component as a differential signal to the second interface circuit via the transmission path; a second transmission unit, which superimposes a second signal containing a clock component as an in-phase signal on the transmission path to transmit it to the second interface circuit; and a state notification unit, which communicates with the second interface circuit via a pair of differential transmission paths included in the transmission path, and notifies the second interface circuit of a connection state of the first interface circuit through a DC bias potential of at least one of the pair of differential transmission paths, and

[0217] The second interface circuit is provided with: a first receiving unit, which extracts the first signal including the clock component from the differential signal received from the first interface circuit via the transmission path; a second receiving unit, which extracts the second signal including the clock component from the in-phase signal received from the first interface circuit via the transmission path; and a status receiving unit, which communicates with the first interface circuit via the pair of differential transmission paths included in the transmission path, and is notified of the connection status by the first interface circuit through the DC bias potential of at least one of the pair of differential transmission paths.

[0218] List of reference numbers

[0219] 10 Transmitter

[0220] 11 Transmission Unit

[0221] 12 Encryption Units

[0222] 13, 23 Communication unit

[0223] 14, 24 Authentication / key exchange unit

[0224] 20 Receiver

[0225] 21 Receiving unit

[0226] 22 Decryption Unit

[0227] 100 Source Device

[0228] 101 Transmitter

[0229] 110 Sink device model detection circuit

[0230] 120 Plug and unplug connection detection circuit

[0231] 140 Source side receiving circuit

[0232] 160 In-phase signal receiving circuit

[0233] 170 Differential signal receiving circuit

[0234] 200 sink device

[0235] 201 Receiver

[0236] 210 Source device model detection circuit

[0237] 220 Plug-in connection transmission circuit

[0238] 250 Sink-side transmission circuit

[0239] 260 In-phase signal transmission circuit

[0240] 270 Differential Signal Transmission Circuit

[0241] 300 Cable

[0242] 310, 320, 330 TMDS channels

[0243] 340 TMDS clock channels

[0244] 350 Display Data Channel (DDC)

[0245] 361 CEC Line

[0246] 362 Utility Lines

[0247] 363 Hot Plug Detect (HPD) Line

[0248] 500 CD player

[0249] 600 TV Receiver

[0250] 700 digital camera.

Claims

1. An information processing device, comprising: One or more interface circuits configured to: modulating the first signal to include a first clock component and an audio signal; unidirectionally transmitting the first signal to an external device by a differential signal via a pair of utility lines and a hot plug detection (HPD) line of a high-definition multimedia interface (HDMI) cable; transmitting a second signal to the external device via the pair of utility lines and the HPD line by an in-phase signal, wherein the second signal includes a second clock component; notifying the external device of the connection state of the information processing apparatus via the HPD line by controlling the voltage; and communicating with the external device via a display data channel DDC of the HDMI cable; and one or more control circuits configured to control processing of data corresponding to the first signal, The first signal is unidirectionally transmitted to the external device via an audio return channel ARC in a direction opposite to a transmission direction of a transition minimized differential signaling TMDS channel of the HDMI cable.

2. The information processing device according to claim 1, wherein: The first signal and the second signal are superimposed to be transmitted via the pair of utility lines and the HPD line.

3. The information processing device according to claim 1, wherein: The one or more interface circuits are further configured to communicate with the external device based on accessing DDC registers via the DDC.

4. The information processing device according to claim 3, wherein: The DDC register is coupled to the external device.

5. The information processing device according to claim 1, wherein: The one or more interface circuits are further configured to receive at least one of a video signal or an audio signal from the external device via the TMDS channel.

6. The information processing device according to claim 1, further comprising: A remote control receiver is configured to receive a user control command from a remote controller, wherein: The user control command corresponds to an operation for transmitting the first signal to the external device, and The one or more control circuits are further configured to control the operation for transmitting the first signal to the external device based on the user control command.

7. The information processing device according to claim 1, wherein: The one or more control circuits are further configured to control an operation for transmitting the first signal to the external device based on activation of the external device.

8. The information processing device according to claim 1, further comprising a display panel configured to display video data, in, The display panel is one of a liquid crystal display (LCD) panel, a plasma display panel (PDP) or an organic electroluminescent panel.

9. The information processing device according to claim 8, wherein: The one or more control circuits are further configured to: decoding content data received from one of a broadcast tuner, a network interface, or an HDMI interface, wherein the content data corresponds to audio data and the video data; outputting the video data to the display panel based on decoding the content data; as well as Based on the decoding of the content data, the audio data corresponding to the first signal is output to the external device. 10 . The information processing device according to claim 9 , further comprising the broadcast tuner and the network interface.

11. An interface device, comprising: One or more interface circuits configured to: modulating the first signal to include a first clock component and an audio signal; unidirectionally transmitting the first signal to an external device by a differential signal via a pair of utility lines and a hot plug detection (HPD) line of a high-definition multimedia interface (HDMI) cable; transmitting a second signal to the external device via the pair of utility lines and the HPD line by an in-phase signal, wherein the second signal includes a second clock component; Notifying the external device of the connection status of the interface device via the HPD line by controlling the voltage; as well as communicating with the external device via a display data channel DDC of the HDMI cable, The first signal is unidirectionally transmitted to the external device via an audio return channel ARC in a direction opposite to a transmission direction of a transition minimized differential signaling TMDS channel of the HDMI cable.

12. The interface device according to claim 11, wherein: The first signal and the second signal are superimposed to be transmitted via the pair of utility lines and the HPD line.

13. The interface device according to claim 11, wherein: The one or more interface circuits are further configured to communicate with the external device based on accessing DDC registers via the DDC.

14. The interface device according to claim 13, wherein: The DDC register is coupled to the external device.

15. An interface system comprising: a first circuit, the first circuit comprising one or more first interface circuits; as well as A second circuit, the second circuit comprising one or more second interface circuits, wherein: The first circuit is connected to the second circuit via a High Definition Multimedia Interface HDMI cable, and The one or more second interface circuits are configured to: modulating the first signal to include a first clock component and an audio signal; unidirectionally transmitting the first signal to the first circuit by differential signaling via a pair of utility lines and a hot plug detection (HPD) line of the HDMI cable; transmitting a second signal to the first circuit via the pair of utility lines and the HPD line by an in-phase signal, wherein the second signal includes a second clock component; notifying the first circuit of a connection state of the second circuit via the HPD line by controlling the voltage; and communicating with the first circuit via a display data channel DDC of the HDMI cable, The first signal is unidirectionally transmitted to the first circuit via an audio return channel ARC in a direction opposite to a transmission direction of a transition minimized differential signaling TMDS channel of the HDMI cable.

16. The interface system of claim 15, wherein: The first signal and the second signal are superimposed to be transmitted via the pair of utility lines and the HPD line.

17. The interface system of claim 15, wherein: The one or more second interface circuits are further configured to communicate with the first circuit based on accessing a DDC register via the DDC.

18. The interface system of claim 17, wherein: The DDC register is coupled to a device implementing the first circuit.

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