Display device

Abstract

A display apparatus includes a display panel. The display panel includes a data line, a sensing line, and a pixel coupled to the data line and the sensing line. A timing controller generates clock-embedded data including image data and a clock training signal. A data driver recovers a clock signal based on the clock training signal of the clock-embedded data, recovers the image data of the clock-embedded data based on the clock signal, supplies a data voltage corresponding to the image data to the data line in a first section, and receives a sensing signal from the pixel through the sensing line in a second section different from the first section. In the second section, the data driver recovers the clock signal when the sensing signal is received.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0021720, filed on February 21, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a display panel driving device, a display device, and a driving method thereof. Background Art

[0004] A display device typically includes pixels, and each pixel in the pixel may include a light-emitting element and a drive transistor that supplies a drive current to the light-emitting element. In such display devices, each pixel in the pixel may degrade. For example, the threshold voltage and mobility of the drive transistor may change over time. In such display devices, the light-emitting element may degrade. Therefore, a technology for sensing characteristic information of a pixel (i.e., a drive transistor and a light-emitting element) can be used to compensate for the degradation of the pixel.

[0005] The display device can transmit various data for generating data signals through an intra-panel interface built between a timing controller ("T-CON") and a source driver ("S-IC"). The display device can use clock-embedded data in which a clock is embedded in the data to reduce the number of lines of the intra-panel interface.

[0006] In such display devices, a clock training signal (or a clock training pattern) for clock recovery may be provided from a timing controller to a data driver to stably recover a clock and data in the data driver. Summary of the Invention

[0007] In a display device, during a display segment of a frame period in which an image is displayed, one horizontal time (i.e., the time data is provided to one pixel row) may be approximately 1.84 microseconds (μs), and therefore, the timing controller may provide a clock training signal to the data driver in units of frames (e.g., at intervals of 1 / 60 second).

[0008] However, during a sensing section of a frame period in which characteristics of pixels are sensed, one sensing horizontal time (i.e., the time during which characteristics of pixels in one pixel row are sensed) may be approximately 635 μs. When a clock training signal is provided in units of frames (e.g., at intervals of approximately three seconds), the clock of the data driver may differ from the clock of the timing controller, and errors may occur in clock and data recovery.

[0009] Furthermore, when the time for transmitting the clock training signal is additionally allocated to one sensing level time, the sensing time may be extended.

[0010] The embodiment provides a display panel driving device, a display device, and a driving method thereof that can stably restore a clock and data while preventing an increase in a sensing time.

[0011] According to an embodiment of the present disclosure, a display device includes: a display panel including data lines, sense lines, and pixels coupled to the data lines and the sense lines; a timing controller generating clock-embedded data including image data and a clock training signal; and a data driver that recovers a clock signal based on the clock training signal of the clock-embedded data, recovers image data of the clock-embedded data based on the clock signal, supplies a data voltage corresponding to the image data to the data lines in a first section, and receives a sense signal from the pixels via the sense lines in a second section different from the first section. In such an embodiment, in the second section, the data driver recovers the clock signal when the sense signal is received.

[0012] In an embodiment, in the second section, the data driver may sequentially receive a plurality of sensing signals from the plurality of pixels and restore the clock signal whenever each of the plurality of sensing signals is received.

[0013] In an embodiment, the data driver may sense each of the plurality of sensing signals of the plurality of pixels in a first cycle and repeatedly restore the clock signal in the first cycle.

[0014] In an embodiment, the second segment may include a first sub-segment, a second sub-segment, and a third sub-segment. In such an embodiment, the data driver may sample a sensing signal from a pixel in the first sub-segment, convert the sampled sensing signal from analog to digital form in the second sub-segment, and transmit the digital sensing signal to the timing controller in the third sub-segment. In such an embodiment, the data driver may recover a clock signal in one of the first to third sub-segments.

[0015] In an embodiment, the data driver may recover the clock signal in the first sub-section.

[0016] In an embodiment, the data driver may not recover the clock signal in the second sub-section.

[0017] In an embodiment, in the second section, the clock embedded data may sequentially include a first control signal for controlling the start of a sensing operation of the data driver and a second signal for controlling the output of a sensing signal of the data driver. In such an embodiment, the clock embedded data may include a clock training signal between the first control signal and the second control signal.

[0018] In one embodiment, the data driver may include: a sampling switch including one end coupled to a sensing line; a capacitor coupled between the other end of the sampling switch and a reference power supply to sample a sensing signal; and an analog-to-digital converter coupled to the other end of the sampling switch. In such an embodiment, the data driver may recover a clock signal when the sampling switch is turned on.

[0019] In an embodiment, the data driver may perform clock training once for each segment in which the sampling switch is turned on.

[0020] In an embodiment, the data driver may provide the reference voltage to the data line in the first to third subsections.

[0021] In an embodiment, the data driver may provide a black data voltage in which pixels do not emit light in the third sub-section.

[0022] In an embodiment, the data driver may recover the clock signal in the third sub-section.

[0023] In an embodiment, the display panel may further include: a scan line, a sensing control line, a first power line, and a second power line. In such an embodiment, the pixel may include: a first transistor, the first transistor including a first electrode coupled to the first power line, a second electrode coupled to the second node, and a gate electrode coupled to the first node; a second transistor, the second transistor including a first electrode coupled to the data line, a second electrode coupled to the first node, and a gate electrode coupled to the scan line; a third transistor including a first electrode coupled to the second node, a second electrode coupled to the sensing line, and a gate electrode coupled to the sensing control line; a storage capacitor coupled between the first node and the second node; and a light-emitting element coupled between the second node and the second power line. In such an embodiment, the data driver may recover the clock signal when the second transistor of the pixel is turned on.

[0024] In an embodiment, in the first section, the data driver may restore the clock signal before or after a portion of clock embedded data corresponding to image data of one frame is received.

[0025] In an embodiment, the timing controller may provide a recovery timing control signal to the data driver, and the data driver may recover the clock signal in response to the recovery timing control signal.

[0026] According to another embodiment of the present disclosure, a display panel driver device for driving a display panel includes data lines, sense lines, and pixels coupled to the data lines and the sense lines. The display panel driver device includes: a timing controller that generates clock-embedded data including image data and a clock training signal; and a data driver that recovers a clock signal based on the clock training signal of the clock-embedded data, recovers image data of the clock-embedded data based on the clock signal, supplies a data voltage corresponding to the image data to the data lines in a first section, and receives a sense signal from the pixels via the sense lines in a second section different from the first section. In such an embodiment, in the second section, the data driver recovers the clock signal when the sense signal is received.

[0027] According to another embodiment of the present disclosure, a method for driving a display device including a display panel, the display panel including data lines, sense lines, and pixels coupled to the data lines and the sense lines, the method comprising: generating clock-embedded data including image data and a clock training signal by a timing controller of the display device; recovering a clock signal by a data driver of the display device based on the clock training signal of the clock-embedded data; recovering image data of the clock-embedded data by the data driver based on the clock signal; supplying a data voltage corresponding to the image data to the data line in a first section by the data driver; and receiving a sense signal from the pixel through the sense line in a second section different from the first section by the data driver. In such an embodiment, receiving the sense signal comprises: recovering the clock signal by the data driver when the sense signal is received.

[0028] In an embodiment, in the second section, the data driver may sequentially receive a plurality of sensing signals from the plurality of pixels and restore the clock signal whenever each of the plurality of sensing signals is received.

[0029] In an embodiment, the second section may include a first sub-section, a second sub-section, and a third sub-section. In such an embodiment, receiving a sensing signal may further include: sampling a sensing signal of one of the pixels in the first sub-section; converting the sampled sensing signal from analog to digital form in the second sub-section; and transmitting the digital sensing signal from the data driver to the timing controller in the third sub-section. In such an embodiment, the data driver may recover a clock signal in one of the first to third sub-sections.

[0030] In an embodiment, the data driver may recover the clock signal in the first sub-section. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the present invention will become more apparent by describing embodiments of the present invention in further detail with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic diagram illustrating a display device according to an embodiment of the present disclosure;

[0033] Figure 2 The diagram is included in Figure 1 A circuit diagram of an embodiment of a pixel in a display device shown in FIG;

[0034] Figure 3 The diagram is included in Figure 1 A circuit diagram of an embodiment of a data driver in a display device shown in FIG;

[0035] Figure 4 The diagram is included in Figure 1 A block diagram of an embodiment of a timing controller and a data driver in a display device shown in FIG;

[0036] Figure 5 The diagram is in the first section Figure 1 A schematic diagram of an embodiment of the operation of the display device shown in FIG;

[0037] Figure 6 The diagram is in the second section Figure 1 A schematic diagram of an embodiment of the operation of the display device shown in FIG;

[0038] Figure 7A and Figure 7B The diagram is in the second section Figure 3 A schematic diagram of an embodiment of the operation of a data driver shown in FIG.

[0039] Figure 8 The diagram is in the second section Figure 1 A schematic diagram of an alternative embodiment of the operation of the display device shown in;

[0040] Figure 9 The diagram is in the second section Figure 1 A schematic diagram of a comparative example of the operation of the display device shown in ;

[0041] Figure 10 is a diagram illustrating the operation according to the embodiment and comparative example of the present invention. Figure 1 A schematic diagram of a sensing signal generated in the display device shown in ; and

[0042] Figure 11 is a schematic diagram illustrating a driving method of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Throughout the text, like reference numerals refer to like elements.

[0044] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0045] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be referred to as a second element, component, region, layer, or section without departing from the teachings herein.

[0046] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, the singular forms "a" and "the" are intended to include plural forms, including "at least one", unless the context clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when used in this specification, the terms "include" or "comprising" specify the presence of the features, regions, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, parts and / or groups thereof.

[0047] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as illustrated in the figures. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is flipped, the element described as being on the "lower" side of the other elements will subsequently be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" can include both "lower" and "upper" orientations depending on the specific orientation of the figures. Similarly, if the device in one of the figures is flipped, the element described as being "below" or "beneath" the other elements will subsequently be oriented "above" the other elements. Thus, the exemplary terms "below" or "below" can include both above and below orientations.

[0048] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations or within ±30%, 20%, 10%, 5% of the stated value.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0050] The embodiments described herein should not be construed as limited to the specific shapes of the regions as illustrated herein, but are intended to include deviations in shape resulting, for example, from manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, illustrated sharp corners may be rounded. Accordingly, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the present claims.

[0051] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0052] Figure 1 Schematic diagram of a display device according to an embodiment of the present disclosure. In an embodiment, the display device may include Figure 1. However, the present disclosure is not limited thereto. In an alternative embodiment, for example, the display device may have a single data driver (or a single source driver IC). Furthermore, the present disclosure is not specifically limited to organic light-emitting display devices and may be applicable to other types of display devices such as liquid crystal display devices.

[0053] Reference Figure 1 An embodiment of the display device 10 may include a display panel 100, a scan driver 210 (or a gate driver or a gate driver IC), a data driver 310 (or a source driver or a source driver IC), and a timing controller 410. The scan driver 210, the data driver 310, and the timing controller 410 may constitute or collectively define a display panel driving device that drives the display panel 100.

[0054] The display panel 100 may include a display area DA in which an image is displayed and a non-display area NDA at the periphery of the display area DA. The display panel 100 may include scan lines SL, sensing control lines SSL, data lines DL, sensing lines RL (or readout lines), and pixels PXL.

[0055] The pixel PXL may be located in an area defined by the scan line SL, the sensing control line SSL, the data line DL, and the sensing line RL. The display panel 100 may include a plurality of pixels. In one embodiment, for example, each of the pixels may be coupled (or connected) to a single data line DL and a single sensing line RL. Figure 2 The detailed configuration of the pixel PXL is described.

[0056] In an embodiment, the timing controller 410 can control the scan driver 210 and the data driver 310. The timing controller 410 can receive a control signal (e.g., a control signal including a clock signal) from the outside and generate a scan control signal (or gate control signal) and a data control signal based on the control signal. The timing controller 410 can provide the scan control signal to the scan driver 210 and provide the data control signal to the data driver 310.

[0057] In such an embodiment, the timing controller 410 can generate frame data (or image data) by rearranging input data (or raw image data) provided from an external source (e.g., a graphics processor), and generate clock-embedded data by inserting a clock training signal (or clock training pattern) into the frame data. The clock training signal can be used to restore the clock signal in the data driver 310. In one embodiment, for example, the clock training signal can include a value corresponding to a square wave, similar to a clock signal. In one embodiment, for example, the timing controller 410 can insert the clock training signal between the frame data and the adjacent frame data.

[0058] The timing controller 410 may provide clock embedded data to the data driver 310. The timing controller 410 may transmit the clock embedded data to the data driver 310 in a data packet form by using a serial interface (or a high-speed serial interface). The timing controller 410 may be arranged or mounted on the control board 400.

[0059] The scan driver 210 and the data driver 310 may drive the display panel 100 .

[0060] The scan driver 210 may receive a scan control signal from the timing controller 410 and generate a scan signal and a sensing control signal (or sensing scan signal) based on the scan control signal. The scan driver 210 may provide the scan signal to the scan line SL and the sensing control signal to the sensing control line SSL.

[0061] The scan driver 210 may be provided or formed on the display panel 100 together with the pixel PXL. However, the present disclosure is not limited thereto. In one embodiment, for example, the scan driver 210 may be arranged or mounted on a separate circuit film and may be coupled to the timing controller 410 mounted on the control board 400 via the circuit film 300 and the printed circuit board 320.

[0062] The data driver 310 may receive a data control signal and clock embedded data from the timing controller 410, recover a clock signal based on a clock training signal of the clock embedded data, and recover frame data from the clock embedded data based on the clock signal. In addition, in a first section (or a first cycle, for example, a display section of a frame cycle in which an image is displayed on the display panel 100), the data driver 310 may generate a data signal corresponding to the frame data and provide the data signal to the data line DL.

[0063] In a second segment different from the first segment (or a second period, for example, a sensing segment of a frame period for sensing characteristic information of the pixel PXL (such as a threshold voltage and / or mobility of a driving transistor included in the pixel PXL)), the data driver 310 may receive a sensing signal from a pixel PXL among a plurality of pixels through a sensing line RL.

[0064] In one embodiment, for example, the second section may be a vertical blank section between the first section and an adjacent first section (e.g., another frame section), and the data driver 310 may receive a sensing signal (e.g., the mobility of the drive transistor or a signal related thereto) from the pixel PXL. In an alternative embodiment, the second section may be a section immediately before the display device 10 is powered off, and the data driver 310 may sequentially receive a sensing signal (e.g., the threshold voltage of the drive transistor of each of the pixels including the pixel PXL) from the pixels in units of pixel rows.

[0065] In an embodiment, in the second section, when a sensing signal is received from the pixel PXL, the data driver 310 may recover the clock signal. In such an embodiment, in the second section, when receiving the sensing signal, the data driver 310 may perform a clock training operation to recover the clock signal.

[0066] In an embodiment, in the second section, the data driver 310 may sequentially receive sensing signals from the pixels and recover the clock signal whenever the data driver 310 receives each of the sensing signals. In an embodiment, for example, in the second section, the data driver 310 may repeatedly sense each of the sensing signals of the pixels at a first cycle (e.g., approximately 635 microseconds (μs)) and recover the clock signal at the first cycle.

[0067] Will refer to it later Figure 6 A detailed operation of recovering the clock signal of the data driver 310 is described.

[0068] The data driver 310 may be arranged or mounted on the circuit film 300 and may be coupled to the timing controller 410 via the printed circuit board 320 and / or a cable.

[0069] In an embodiment, as described above, when a sensing signal is received from a pixel PXL, the display device 10 (or data driver 310) can recover the clock signal. Therefore, because no independent time is allocated to the second segment for recovering the clock signal, the increase of the second segment (i.e., the sensing segment) can be effectively prevented. In such an embodiment, the display device 10 can recover the clock signal in units of pixel rows. Therefore, synchronization between the timing controller 410 and the data driver 310 can be effectively maintained.

[0070] Figure 2 The diagram is included in Figure 1 . A pixel PXL included in an n-th pixel row and a k-th pixel column (n and k are positive integers) is exemplarily illustrated in FIG. Figure 2 middle.

[0071] Reference Figure 2 , the pixel PXL may be coupled to the nth scan line SLn, the kth data line DLk, the nth sensing control line SSLn, and the kth sensing line RLk.

[0072] The pixel PXL may include a light emitting element LED, a first transistor T1 (driving transistor), a second transistor T2 (switching transistor), a third transistor T3 (sensing transistor), and a storage capacitor Cst. Each of the first transistor T1, the second transistor T2, and the third transistor T3 may be a thin film transistor including an oxide semiconductor.

[0073] The anode of the light-emitting element LED can be coupled to the second node N2 (or the second electrode of the first transistor T1), and the cathode of the light-emitting element LED can be coupled to the second power line PL2 to which the second power supply voltage VSS is applied. The light-emitting element LED can emit light at a predetermined brightness corresponding to the amount of current (or driving current) supplied to the light-emitting element LED from the first transistor T1. In an embodiment, the light-emitting element LED can be an organic light-emitting diode. However, the present disclosure is not limited thereto, and alternatively, the light-emitting element LED can include an inorganic light-emitting diode.

[0074] A first electrode of the first transistor T1 may be coupled to a first power line PL1 to which a first power voltage VDD is applied, and a second electrode of the first transistor T1 may be coupled to a second node N2 (or an anode of the light-emitting element LED). A gate electrode of the first transistor T1 may be coupled to a first node N1. The first transistor T1 controls the amount of current flowing through the light-emitting element LED based on the voltage of the first node N1.

[0075] A first electrode of the second transistor T2 may be coupled to the kth data line DLk, and a second electrode of the second transistor T2 may be coupled to the first node N1. A gate electrode of the second transistor T2 may be coupled to the nth scan line SLn. When a scan signal S[n] is supplied to the nth scan line SLn, the second transistor T2 may be turned on to transmit a data voltage DATA (or data signal) from the kth data line DLk to the first node N1.

[0076] The storage capacitor Cst may be coupled between the first node N1 and the anode of the light emitting element LED. The storage capacitor Cst may store the voltage of the first node N1.

[0077] The third transistor T3 may be coupled between the kth sensing line RLk and the second node N2 (or the second electrode of the first transistor T1). The third transistor T3 may couple the second node N2 and the kth sensing line RLk to each other in response to the sensing control signal SEN[n]. A sensing signal may be provided to the kth sensing line RLk. In one embodiment, for example, a sensing voltage (or a node voltage of the second node N2) may be provided to the kth sensing line RLk. However, the present disclosure is not limited thereto, and alternatively, a sensing current corresponding to the node voltage of the second node N2 may be transmitted to the kth sensing line RLk. The sensing voltage may be provided to the data driver 310 (see Figure 1 ).

[0078] However, Figure 2 The embodiment of the pixel PXL shown in FIG. 1 is merely exemplary, and the embodiment of the pixel PXL is not limited thereto.

[0079] Figure 3 The diagram is included in Figure 1 The data driver 310 is briefly shown in FIG. Figure 3 In the embodiment, the characteristic of the pixel PXL is sensed based on a portion of the data driver 310 coupled to the pixel PXL through the k-th sensing line RLk.

[0080] Reference Figure 1 、 Figure 2 and Figure 3 , Figure 3 The pixel PXL shown in FIG is the same as the reference Figure 2 The pixels PXL are substantially the same, and any repeated detailed description thereof will be omitted.

[0081] The data driver 310 may include a digital-to-analog converter (DAC). The DAC may generate a data voltage corresponding to a data value (or grayscale data) included in the frame data (or image data). In one embodiment, for example, the DAC may select one of the gamma voltages based on the data value and output the selected gamma voltage as the data voltage (or data signal).

[0082] In an embodiment, although not shown in the drawings, the data driver 310 may further include an output buffer, and provide the data voltage to the kth data line DLk through the output buffer.

[0083] The data driver 310 may further include a sensing unit SU and an analog-to-digital converter ADC coupled to the kth sensing line RLk.

[0084] The sensing unit SU may include a sensing capacitor CSEN, a first capacitor C1, a second capacitor C2, an initialization switch SW_VINIT (or a first switch), a sampling switch SW_SPL (or a second switch), a sharing switch SW_SHARE (or a third switch), a reset switch SW_RST (or a fourth switch), and an output switch SW_CH (or a fifth switch).

[0085] The initialization switch SW_VINIT may be coupled between a power line to which an initialization voltage VINIT is applied and the kth sensing line RLk. The initialization voltage VINIT may be provided from an independent power source and may have a voltage level lower than the voltage level of the operating point of the light-emitting element LED. When the initialization switch SW_VINIT is turned on, the initialization voltage VINIT may be applied to the kth sensing line RLk. When the third transistor T3 is turned on, the initialization voltage VINIT may be applied to the second node N2 of the pixel PXL. Because the initialization voltage VINIT has a voltage level lower than the voltage level of the operating point of the light-emitting element LED, the light-emitting element LED may not emit light even when the first transistor T1 is turned on.

[0086] The sensing capacitor CSEN may be coupled between the kth sensing line RLk and a reference power source. The reference power source may have a ground voltage, but the present disclosure is not limited thereto. When the initialization switch SW_VINIT is turned off and the third transistor T3 of the pixel PXL is turned on, the sensing capacitor CSEN may be charged by the current provided through the second node N2. In other words, characteristic information of the pixel PXL provided through the second node N2 may be stored in the sensing capacitor CSEN.

[0087] The sampling switch SW_SPL may be coupled between the kth sensing line RLk and the third node N3. The first capacitor C1 may be coupled between the third node N3 and a reference power supply. When the sampling switch SW_SPL is turned on, the first capacitor C1 may sample characteristic information of the pixel PXL (or the first transistor T1) stored in the sensing capacitor CSEN. In other words, the data driver 310 may sample the sensing signal using the switch SW_SPL and the first capacitor C1.

[0088] The sharing switch SW_SHARE can be coupled between the third node N3 and the fourth node N4, the reset switch SW_RST can be coupled between the fourth node N4 and the reference power supply, and the second capacitor C2 can be coupled to the fourth node N4 and the reference power supply. When the sharing switch SW_SHARE is turned on and the first capacitor C1 and the second capacitor C2 share charge, the node voltage of the fourth node N4 (and the node voltage of the third node N3) can change. The sharing switch SW_SHARE, the reset switch SW_RST, and the second capacitor C2 can function as a buffer based on the operation of the sharing switch SW_SHARE and the reset switch SW_RST. The gain of the buffer changes depending on the capacitance ratio of the first capacitor C1 and the second capacitor C2, and the gain of the buffer can be N (N is an integer greater than 1). That is, the sharing switch SW_SHARE, the reset switch SW_RST, and the second capacitor C2 can amplify the node voltage of the third node N3.

[0089] The output switch SW_CH may be coupled between the fourth node N4 and the analog-to-digital converter ADC, and couple the fourth node N4 to an input terminal of the analog-to-digital converter ADC. A node voltage of the fourth node N4 may be applied to the analog-to-digital converter ADC.

[0090] Although not shown in the drawings, the data driver 310 may further include a capacitor coupled between the input terminal of the analog-to-digital converter ADC and a reference power supply to maintain a node voltage of the fourth node N4, and the node voltage of the fourth node N4 is provided to the analog-to-digital converter ADC and an initialization circuit for initializing the input terminal of the analog-to-digital converter ADC (or the capacitor) (for example, a capacitor initialization power supply and a switch for coupling the capacitor initialization power supply to the input terminal of the analog-to-digital converter ADC).

[0091] The analog-to-digital converter ADC may convert a voltage supplied to an input terminal of the analog-to-digital converter ADC into a data value (e.g., a digital code). That is, the data driver 310 may convert a sensing signal sampled by the analog-to-digital converter ADC from an analog form into a digital form. The sensing signal in digital form (e.g., a digital code) may be supplied to the timing controller 410.

[0092] Figure 3, an embodiment in which the sensing unit SU includes capacitors CSEN, C1, and C2 and switches SW_VINIT, SW_SPL, SW_SHARE, SW_RST, and SW_CH is illustrated, but this is merely exemplary and the present disclosure is not limited thereto. In an alternative embodiment, for example, various circuits (e.g., a sensing circuit that converts a sensing current into a sensing voltage by using an amplifier and samples and holds the converted sensing voltage) may be applied as the sensing unit SU as long as the sensing unit SU detects the node voltage of the second node N2 of the pixel PXL (or a current corresponding to the node voltage of the second node N2).

[0093] Figure 4 The diagram is included in Figure 1 , which is a block diagram of an embodiment of a timing controller and a data driver in a display device.

[0094] Reference Figure 4 , an embodiment of the timing controller 410 may include a clock generation circuit 411 , a data processing circuit 412 (or a data alignment circuit), an encoder 413 and a first buffer 414 (or an output buffer).

[0095] The clock generation circuit 411 may generate a first clock signal CLK1 based on an external timing signal provided from the outside (eg, a graphics processor) or a clock training signal (or a clock training pattern) corresponding to the first clock signal CLK1.

[0096] In an embodiment, the clock generation circuit 411 may generate a recovery timing control signal SFC (or a start frame control signal) and provide the recovery timing control signal SFC to the data driver 310 via a recovery timing control line SFCL. The recovery timing control line SFCL may be configured separately from the channel line CHL. The recovery timing control signal SFC may be a signal for controlling the recovery timing of the clock signal recovered in the data driver 310.

[0097] The data processing circuit 412 may generate frame data (or image data) by rearranging input data DATA1 (or raw image data) provided from the outside.

[0098] The encoder 413 may generate the data packet DATA2 (or clock embedded data) in a format determined in the intra-panel interface constructed between the timing controller 410 and the data driver 310. The encoder 413 may embed a clock training signal into the data packet DATA2.

[0099] The first buffer 414 may transmit the data packet DATA2 to the data driver 310 through the channel line CHL.

[0100] The data driver 310 may include a second buffer 311 , a clock recovery circuit 312 , a data recovery circuit 313 , and a data voltage generator 314 .

[0101] The second buffer 311 may receive the data packet DATA2 from the timing controller 410 and transmit the data packet DATA2 to the clock recovery circuit 312 and the data recovery circuit 313. In one embodiment, for example, the second buffer 311 may rearrange in parallel the data packets DATA2 serially transmitted from the timing controller 410 through one channel line CHL (or a pair of signal transmission lines) and output the rearranged data packets DATA2.

[0102] The clock recovery circuit 312 may recover the clock signal based on the clock training signal in the data packet DATA2. In one embodiment, for example, the clock recovery circuit 312 may generate the second clock signal CLK2 based on the clock training signal.

[0103] In an embodiment, the clock recovery circuit 312 can recover the clock signal in response to the recovery timing control signal SFC. In one embodiment, for example, when the recovery timing control signal SFC is at a logic low level, the clock recovery circuit 312 can recover the second clock signal CLK2 from the data packet DATA2. In another embodiment, when the recovery timing control signal SFC is at a logic high level, the clock recovery circuit 312 can recover the second clock signal CLK2 from the data packet DATA2.

[0104] The data recovery circuit 313 can recover the frame data in the data packet DATA2 based on the second clock signal CLK2. In one embodiment, for example, the data recovery circuit 313 can sample each bit of the frame data in the data packet DATA2 based on the second clock signal CLK2.

[0105] The data voltage generator 314 may generate a data voltage (or data signal) based on the recovered frame data. In one embodiment, for example, the data voltage generator 314 may include a shift register, a data latch, and the above referenced Figure 3 The digital-to-analog converter DAC. The shift register can sequentially provide frame data (or parallel data) to the data latch. The data latch can latch the data sequentially received from the shift register and simultaneously provide the data to the digital-to-analog converter DAC. The digital-to-analog converter DAC can convert the digital data into an analog data signal (or data voltage) based on the gamma voltage.

[0106] In the embodiment, as described above, the clock generation circuit 411 of the timing controller 410 provides the restored timing control signal SFC to the clock recovery circuit 312 of the data driver 310, but the present disclosure is not limited thereto. In an alternative embodiment, for example, the clock recovery circuit 312 may provide the timing controller 410 (or the clock generation circuit 411) with a status signal indicating whether the clock recovery circuit 312 has recovered the clock signal.

[0107] Figure 5 The diagram is in the first section Figure 1 A schematic diagram of an embodiment of the operation of a display device is shown in FIG.

[0108] Reference Figure 4 and Figure 5 , the first segment may include a frame segment FRAME and a vertical blank segment VBP.

[0109] The restoration timing control signal SFC generated in the timing controller 410 may have a logic low level in a portion of the vertical blank section VBP and have a logic high level in the frame section FRAME.

[0110] In one embodiment, for example, the recovery timing control signal SFC may have a logic low level between the first time point TP1 and the second time point TP2 in the vertical blank section VBP.

[0111] The data packet DATA2 may include a clock training signal CT (or a clock training pattern) between the first time point TP1 and the second time point TP2. That is, the timing controller 410 may insert the clock training signal CT into the data packet DATA2 corresponding to the period in which the recovery timing control signal SFC has a logic low level.

[0112] The data driver 310 may recover the second clock signal CLK2 based on the clock training signal CT.

[0113] After the second clock signal CLK2 is normally restored, the data packet DATA2 in the frame section FRAME may include valid data AD (ie, frame data).

[0114] The data driver 310 can sample the valid data AD from the data packet DATA2 based on the second clock signal CLK2 and restore the frame data. In addition, the data driver 310 can generate a data signal based on the frame data and can transmit the data signal to the data line DL (see FIG. Figure 1 ) provides a data signal to the pixel PXL. The pixel PXL may emit light at a brightness corresponding to the data signal.

[0115] As reference Figure 5In the first section (i.e., where the image is displayed in reference Figure 1 The data driver 310 may recover the second clock signal CLK2 in units of frames. In one embodiment, for example, the data driver 310 may recover the second clock signal CLK2 in units of 1 / 60s, 1 / 20s, or 1 / 240s.

[0116] Figure 6 The diagram is in the second section Figure 1 A schematic diagram of an embodiment of the operation of a display device is shown in FIG.

[0117] Reference Figure 3 、 Figure 4 、 Figure 5 and Figure 6 , the second segment may include a sensing horizontal segment 1H_S (or horizontal segment). In one embodiment, for example, the sensing horizontal segment 1H_S may be approximately 635 μs. During the sensing horizontal segment 1H_S, the data driver 310 may receive sensing signals from the pixels PXL included in one pixel row. In one embodiment, for example, when the second segment includes a plurality of horizontal segments, the data driver 310 may sequentially receive sensing signals from the pixels included in the plurality of pixel rows.

[0118] At the third time point TP3 (ie, at the start time of the sensing horizontal section 1H_S), the data packet DATA2 may include a start control signal DO. The data driver 310 may, in response to the start control signal DO, set the reference voltage (eg, the reference voltage for detecting the first transistor T1 (see FIG. 1 ) to 0. Figure 3 ) is supplied to the k-th data line DLk (see Figure 3 ).

[0119] When the scan signal S[n] has a logic high level (or a turn-on voltage level), the second transistor T2 may be turned on, and the reference voltage may be supplied to the gate electrode of the first transistor T1.

[0120] Meanwhile, the sensing control signal SEN[n] may have a logic high level, the third transistor T3 may be turned on, and the data driver 310 may be ready to receive a sensing signal from the pixel PXL.

[0121] At a fourth time point TP4, data packet DATA2 may include a first control signal RO_SYNC. The first control signal RO_SYNC may define or control the start of a sensing operation of the data driver 310. In one embodiment, for example, the fourth time point TP4 may be the time elapsed from the time the start control signal DO is generated, relative to the reference sub-segment SP0. In one embodiment, for example, the reference sub-segment SP0 may be approximately 50 μs.

[0122] The data driver 310 may receive a sensing signal from the pixel PXL in response to the first control signal RO_SYNC.

[0123] In an embodiment, the sensing horizontal section 1H_S may include the first, second, and third subsections SP1, SP2, and SP3 after the fourth time point TP4. The data driver 310 may recover a clock signal in at least one of the first, second, and third subsections SP1, SP2, and SP3.

[0124] In the first sub-section SP1, the data driver 310 may sample the sensing signal from the pixel PXL. The first sub-section SP1 may be a section in which the voltage is between the reference Figure 3 The analog front end (AFE) section is accumulated at the front end of the sensing unit SU. In the first sub-section SP1, the sensing signal of the pixel PXL can be stored in the reference Figure 3 The sensing capacitor CSEN is configured to be connected to the sampling switch SW_SPL, and the sampling switch SW_SPL may be turned on to sample the sensing signal in the first capacitor C1. In one embodiment, for example, the first sub-section SP1 may be approximately 236 μs.

[0125] In an embodiment, the sensing control signal SEN[n] may have a logic high level in the first sub-section SP1 to allow the data driver 310 to receive a sensing signal through the kth sensing line RLk.

[0126] In an embodiment, in the first sub-section SP1 , the data driver 310 may recover a clock signal from the data packet DATA2 .

[0127] In one embodiment, for example, in the first sub-segment SP1, the data packet DATA2 may include a clock training signal CT, and the recovery timing control signal SFC may have a logic low level. The data driver 310 may recover the clock signal based on the clock training signal CT in response to the recovery timing control signal SFC. In one embodiment, for example, the data driver 310 may start recovering the clock signal after the first interval INTV1 from the start time of the first sub-segment SP1, and recover the clock signal during the second interval INTV2. In one embodiment, for example, the first interval INVT1 may be approximately 130 μs, and the second interval may be approximately 64 μs. The segment in which the clock signal is recovered in the data driver 310 may be located before the third interval INTV3 from the end time of the sensing horizontal segment 1H_S. In one embodiment, for example, the third interval INTV3 may be approximately 260 μs.

[0128] When the clock signal is recovered in the data driver 310 (or the clock recovery circuit 312), high frequency noise may appear. When the clock signal is recovered while the sensing signal is being received, the high frequency noise may have an effect on the sensing signal. However, as will be described later, Figure 10 As described above, the noise of the sensing signal caused by high-frequency noise can be constantly expressed and predictable. Therefore, the data driver 310 can effectively remove the predicted noise component from the sensing signal (ie, the sensing signal is compensated) to ensure the reliability of the sensing signal.

[0129] In an embodiment, in the first sub-section SP1, the sensing control signal SEN[n] may have a logic high level and the second transistor T2 may maintain a turned-on state. That is, when the second transistor T2 is turned on, the data driver 310 may recover the clock signal.

[0130] In the second sub-section SP2, the data driver 310 may convert the sampled sensing signal from analog form to digital form. The second sub-section SP2 may be a section in which the voltage is between the reference Figure 3 The analog-to-digital conversion section of the analog-to-digital converter ADC that is converted into a data value (eg, a 12-bit digital code) may be approximately 128 μs in one embodiment, for example.

[0131] In one embodiment, the data driver 310 may not recover the clock signal in the second sub-section SP2. High-frequency noise generated during the clock signal recovery process described above may affect the operation of the analog-to-digital converter (ADC) and may also cause irregular noise. That is, when the clock signal is recovered in the second sub-section SP2, noise generated in the analog-to-digital converter (ADC) may not be effectively removed or compensated to ensure the reliability of the sensed signal. Therefore, the data driver 310 does not recover the clock signal in the second sub-section SP2.

[0132] At the fifth time point TP5 (ie, at the end time of the second sub-section SP2 ), the data packet DATA2 may include the second control signal RD_SENSE The second control signal RD_SENSE may control the output of the sensing signal in the data driver 310 .

[0133] In the third sub-section SP3, the data driver 310 may transmit a sensing signal converted in a digital form (e.g., a digital code) to the timing controller 410 in response to the second control signal RD_SENSE. That is, the third sub-section SP3 may be a master-in-slave-out (MISO) section in which the converted sensing signal of the data driver 310 is transmitted to the timing controller 410. In one embodiment, for example, the third sub-section SP3 may be approximately 75 μs.

[0134] The idle section IDLE allocated to be adjacent to the end time of the sensing horizontal section 1H_S may be an edge of the sensing horizontal section 1H_S. In one embodiment, for example, the idle section IDLE may be about 50 μs.

[0135] In an embodiment, the data driver 310 may sequentially receive (or sense) a sensing signal from a pixel (or pixel row) by using a sensing horizontal section 1H_S (e.g., approximately 635 μs) as a section. In such an embodiment, the data driver 310 may repeatedly recover a clock signal by using a sensing horizontal section 1H_S as a section.

[0136] In the examples, as referenced Figure 6 As described above, the data driver 310 can recover the clock signal when sampling the sensing signal from the pixel PXL (or receiving the sensing signal from the pixel PXL) in the second section (or sensing horizontal section 1H_S). Therefore, no independent time is allocated in the sensing horizontal section 1H_S for recovering the clock signal, so that the increase in the sensing horizontal section 1H_S can be prevented.

[0137] High-frequency noise that occurs during the clock signal recovery process may affect the sensing signal. However, the noise of the sensing signal caused by the high-frequency noise is constant and predictable. Therefore, the data driver 310 (or the timing controller 410) can remove the predicted noise from the sensing signal or compensate the sensing signal. Therefore, the reliability of the sensing signal can be ensured.

[0138] In an embodiment, the data packet DATA2 (or clock embedded data) may include a clock training signal CT between the first control signal RO_SYNC and the second control signal RD_SENSE in one sensing horizontal segment 1H_S to allow the data driver 310 to recover the clock signal in the second segment.

[0139] Figure 7A and Figure 7B The diagram is in the second section Figure 3 A schematic diagram of an embodiment of the operation of a data driver is shown in FIG.

[0140] First, refer to Figure 3 、 Figure 6 and Figure 7A , except for the first sub-segment SP1, the operation of the data driver 310 is similar to that of the reference Figure 6 The operations of the data driver 310 are substantially the same or similar, and thus, any repeated detailed description thereof will be omitted.

[0141] In the second section, the data voltage DATA supplied from the data driver 310 to the kth data line DLk may have the reference voltage DATA_REF. In one embodiment, for example, the data driver 310 may supply the reference voltage DATA_REF to the kth data line DLk in the first to third subsections SP1, SP2, and SP3.

[0142] The first sub-section SP1 may sequentially include a delay section DELAY, an initialization section INITIAL, a sampling section SAMPLING, and a sharing section SHARE.

[0143] The delay section DELAY may correspond to a delay time after the data driver 310 receives the first control signal RO_SYNC before the sensing unit SU performs a sensing operation. In one embodiment, for example, the delay section DELAY may be about 4 μs.

[0144] In the initialization section INITIAL, the initialization switch SW_VINIT of the sensing unit SU may be turned on, and the initialization voltage VINIT may be applied to the kth sensing line RLk. The third transistor T3 is in a state where the third transistor T3 is turned on by the sensing control signal SEN[n] having a logic high level (or a turn-on voltage level), and thus the initialization voltage VINIT may be applied to the second node N2. The initialization section INITIAL may be approximately 16 μs.

[0145] In the sampling section SAMPLING, characteristic information of the pixel PXL (or the first transistor T1) may be stored in the sensing capacitor CSEN of the sensing unit SU, and the sampling switch SW_SPL may be turned on to sample the characteristic information of the pixel PXL in the first capacitor C1. In one embodiment, for example, the sampling section SAMPLING may be approximately 200 μs.

[0146] In an embodiment, the clock recovery circuit 312 of the data driver 310 may perform a clock training operation of recovering a clock signal based on the clock training signal CT of the data packet DATA2 (or clock embedded data).

[0147] In one embodiment, for example, the clock recovery circuit 312 may perform a clock training operation at the same time as the sampling section SAMPLING starts. In one embodiment, for example, when the sampling switch SW_SPL of the sensing unit SU is turned on, the clock recovery circuit 312 may recover the clock signal. In one embodiment, for example, the sampling switch SW_SPL of the sensing unit SU is turned on only when the sampling switch SW_SPL of the sensing unit SU is turned on. Figure 6 The sampling section SAMPLING of one sensing horizontal section 1H_S is turned on, and therefore, the clock recovery circuit 312 (or the data driver 310 ) may perform a clock training operation for each section in which the sampling switch SW_SPL is turned on.

[0148] Subsequently, in the sharing section SHARE, the sharing switch SW_SHARE of the sensing unit SU may be turned on, and the sensing unit SU may provide the sampled characteristic information (ie, the sensing signal) to the analog-to-digital converter ADC.

[0149] In an embodiment, in the third sub-section SP3, the pixel PXL (or the light emitting element LED) may emit light based on the gate-source voltage of the first transistor T1 of the pixel PXL. In such an embodiment, when the second section is aligned with the reference Figure 5 When the vertical blank section VBP corresponds to the vertical blank section VBP, the pixel PXL may emit light with an unnecessary brightness in the vertical blank section VBP.

[0150] Thus, in such an embodiment, the display device 10 (see Figure 1 ) can be achieved by changing the second power supply voltage VSS (see Figure 3 ) (eg, by increasing the voltage level of the second power supply voltage VSS) to suppress light emission of the pixel PXL. However, the present disclosure is not limited thereto.

[0151] Reference Figure 3 and Figure 7B In an alternative embodiment, the data driver 310 may provide a black data voltage BLACK to the kth data line DLk in the third sub-section SP3. The black data voltage BLACK may be a data voltage that causes the pixel to not emit light. In one embodiment, for example, the black data voltage BLACK may be a data voltage corresponding to a 0 grayscale or a black grayscale.

[0152] In such an embodiment, the scan signal S[n] may have a logic high level in the third sub-section SP3 . The second transistor T2 may be turned on, and the black data voltage may be supplied to the gate electrode of the first transistor T1 .

[0153] In the third sub-section SP3 (i.e., the section in which the scan signal S[n] has a logic high level), the sensing control signal SEN[n] may have a logic high level. The third transistor T3 may be turned on, and the initialization voltage VINIT may be applied to the second node N2. Therefore, in the third sub-section SP3, the pixel PXL may display black corresponding to the black data voltage or may not emit light.

[0154] In the examples, as referenced Figure 7A and Figure 7B As described above, the data driver 310 (or the clock recovery circuit 312 ) may recover the clock signal in the sampling section SAMPLING (ie, a section in which the sensing unit SU performs a sampling operation of the sensing signal and a section in which the sampling switch SW_SPL of the sensing unit SU is turned on).

[0155] Figure 8 The diagram is in the second section Figure 1 A schematic diagram of an alternative embodiment of the operation of a display device is shown in FIG.

[0156] Reference Figure 3 、 Figure 6 and Figure 8 , except that the data driver 310 recovers the clock signal in the third sub-segment SP3 instead of the first sub-segment SP1, the data driver 310 (or the display device 10 (see Figure 1 )) Operation and reference Figure 6The operations of the data driver 310 are substantially the same or similar, and thus, any repeated detailed descriptions of the same or similar features thereof will be omitted or simplified.

[0157] In an embodiment, Figure 8 As shown in FIG, in the third sub-section SP3, the data driver 310 may recover the clock signal from the data packet DATA2.

[0158] In one embodiment, for example, in the third sub-segment SP3, the data packet DATA2 may include a clock training signal CT, and the recovery timing control signal SFC may have a logic low level. The data driver 310 may recover the clock signal based on the clock training signal CT in response to the recovery timing control signal SFC. In one embodiment, for example, the data driver 310 may start recovering the clock signal from the time the first control signal RO_SYNC is received to after the first interval INTV1', and recover the clock signal during the second interval INTV2'. In one embodiment, for example, the first interval INTV1' may be approximately 340μs, and the second interval INTV2' may be approximately 54μs. The segment in which the clock signal is recovered in the data driver 310 may be located from the end time of the sensing horizontal segment 1H_S to before the third interval INTV3'. In one embodiment, for example, the third interval INTV3' may be approximately 93.5μs.

[0159] In an embodiment in which the timing controller 410 and the data driver 310 are coupled to each other in a point-to-point (P2P) manner rather than a multi-point manner (i.e., a structure in which multiple data drivers are coupled to one line), the data driver 310 can recover the clock signal in the third sub-segment SP3.

[0160] When the timing controller 410 and the data driver 310 are coupled to each other in a multi-point manner, the command for recovering the clock signal can be properly transmitted to the data driver. Figure 6 As described above, the data driver 310 may recover the clock signal in the first sub-section SP1.

[0161] In the examples, as referenced Figure 8 As described above, in the second section, the data driver 310 recovers the clock signal while transmitting the sensing signal (or a data code corresponding to the sensing signal) to the timing controller 410. Therefore, no independent time is allocated in the second section for recovering the clock signal, so that the increase of the second section (i.e., the sensing time) can be prevented.

[0162] Figure 9 The diagram is in the second section Figure 1Schematic diagram of a comparative example of the operation of the display device shown in .

[0163] Reference Figure 6 and Figure 9 In the comparative example, the second section may include the sensing horizontal section 1H_S′, and the sensing horizontal section 1H_S′ may further include a fourth sub-section SP4 subsequent to the third sub-section SP3 .

[0164] The data driver 310 may recover the clock signal in the fourth subsection SP4.

[0165] In the comparative example, Figure 9 As shown in FIG, in the fourth sub-section SP4, the data packet DATA2 may include the clock training signal CT, and the data driver 310 may recover the clock signal based on the clock training signal CT.

[0166] However, since the sensing horizontal section 1H_S′ includes the fourth subsection SP4 , the time in which the sensing signal is received from the pixel PXL may be increased.

[0167] Specifically, when the fourth subsection SP4 is included for each sensing horizontal section 1H_S′, an increment of a total sensing time in which sensing signals are sequentially received from pixels may be further increased.

[0168] In a comparative example, only the sensing horizontal segment 1H_S' of a specific pixel row may include the fourth sub-segment SP4 to reduce the increase in the total sensing time. However, noise may appear in the sensing signal received in the corresponding sensing horizontal segment 1H_S'. In the case of 16 pixel rows, the sensing horizontal segments 1H_S' of the first to fifteenth pixel rows do not include the fourth sub-segment SP4, and only the sensing horizontal segment 1H_S' of the sixteenth (or thirty-second, forty-eight, etc.) pixel row may include the fourth sub-segment SP4. In the actual measurement results of the sensing signal, it was detected that noise had already appeared in the sensing signal of the sixteenth (or thirty-second, forty-eight, etc.) pixel row.

[0169] Figure 10 is a diagram illustrating the operation according to the embodiment and comparative example of the present invention. Figure 1 Schematic diagram of sensing signals generated in the display device shown in .

[0170] Reference Figure 10 , the first graph GRAPH1 (or first curve) represents the Figures 6 to 8 The first sensing signal is obtained by the embodiment of the operation of the display device shown in FIG, and the second graph GRAPH2 (or the second curve) represents the first sensing signal obtained by Figure 9The second sensing signal is obtained in the comparative example of the operation of the display device shown in . The sensing row may represent a pixel row (or pixels included therein) on which the data driver 310 receives the sensing signal, and the sensing value may represent the sensing signal (ie, data code).

[0171] Referring to the second graph GRAPH2, in the case where the data driver 310 recovers the clock signal every sixteen pixel rows, noise in the form of pulses occurs in corresponding pixel rows (e.g., the sixteenth row, the thirty-second row, the forty-eighth row, etc.). When the second sensing signal is expressed in a 12-bit data code, the amplitude of the corresponding noise may be about 5.

[0172] The data driver 310 may perform a compensation operation to remove corresponding noise from the second sensing signal according to the second graph GRAPH2. However, the compensation operation is relatively complex and does not prevent an increase in the sensing horizontal section 1H_S' (and sensing time).

[0173] In an embodiment of the present invention, referring to the first graph GRAPH1, when the data driver 310 recovers the clock signal when receiving the sensing signal, the first sensing signal may include completely uniform noise on the sensing row (i.e., pixel row) compared to the second sensing signal. In one embodiment, for example, when the first sensing signal is exposed to a 12-bit data code, the amplitude of the corresponding noise may be approximately 1.

[0174] The data driver 310 can compensate the first sensing signal by subtracting the entire predicted noise (e.g., a value of 1) from the first sensing signal according to the first graph GRAPH1. That is, through a simpler compensation operation, the data driver 310 can ensure the reliability of the first sensing signal. Further, as shown in FIG. Figures 6 to 8 As described above, no independent time for recovering the clock signal is allocated to the sensing horizontal section 1H_S, so that an increase in the sensing horizontal section 1H_S (and the sensing time) can be prevented.

[0175] Figure 11 is a schematic diagram illustrating a driving method of a display device according to an embodiment of the present disclosure.

[0176] Reference Figure 1 、 Figure 5 and Figure 6 , Figure 11 The driving method shown in Figure 1 is implemented in the display device 10 shown in FIG.

[0177] exist Figure 11In the embodiment of the driving method shown in , at S1110 , clock embedded data (or data packet) including image data and a clock training signal may be generated by the timing controller 410 .

[0178] In an embodiment, Figure 5 As shown in , the timing controller 410 may generate clock embedded data by inserting a clock training signal between frame data in a first segment (or display segment).

[0179] In an alternative embodiment, if Figure 6 As shown in FIG, the timing controller 410 may generate clock embedded data by inserting a clock training signal in the first subsection SP1 in which the data driver 310 senses characteristic information of the pixel PXL in the second section (or sensing section).

[0180] exist Figure 11 In the embodiment of the driving method shown in , at S1120 , the clock signal may be recovered by the data driver 310 based on the clock training signal of the clock embedded data.

[0181] In the examples, as referenced Figure 5 and Figure 6 As described above, when the recovery timing control signal SFC has a logic low level, the data driver 310 (or the clock recovery circuit 312 (see Figure 4 ))The clock signal can be recovered based on the clock training signal of the clock embedded data.

[0182] exist Figure 11 In the embodiment of the driving method shown in FIG, at S1130, the image data (or frame data) can be recovered from the clock embedded data by the data driver 310 based on the clock signal. In one embodiment, for example, Figure 11 In the driving method shown in , image data can be restored by sampling each bit of the image data in the clock-embedded data based on the second clock signal CLK2.

[0183] exist Figure 11 In the embodiment of the driving method shown in , at S1140 , a data voltage corresponding to image data may be supplied to the data line DL by the data driver 310 in the first section (or display section). The pixel PXL may emit light at a brightness corresponding to the data voltage.

[0184] exist Figure 11 In the embodiment of the driving method shown in , at least one sensing signal may be received from at least one of the pixels through the sensing line RL in a second section (or sensing section) different from the first section.

[0185] In one embodiment, for example, the second segment may be a vertical blank segment (or vertical edge segment) between frame segments. Figure 11 In the embodiment of the driving method shown in , the sensing signal (eg, the mobility of the driving transistor or a signal related thereto) may be received from the pixel PXL. In an alternative embodiment, the second section may be a section immediately before the display device 10 is powered off. Figure 11 In the embodiment of the driving method shown in , a sensing signal (eg, a threshold voltage of a driving transistor of each of the pixels including the pixel PXL) may be sequentially received from the pixels.

[0186] In an embodiment, Figure 11 In the driving method shown in , at S1150 , when at least one sensing signal is received by the data driver 310 , a clock signal may be restored by the data driver 310 .

[0187] As reference Figures 6 to 8 As mentioned, Figure 11 In the embodiment of the driving method shown in , the clock signal can be recovered in one of the first to third sub-segments SP1, SP2, and SP3 of the sensing horizontal segment 1H_S included in the second segment. In one embodiment, for example, Figure 11 In the driving method shown in , the clock signal can be recovered in the first sub-segment SP1. Figure 7A As described above, the clock signal may be recovered when the sensing signal is sampled by the data driver 310 (ie, during the sampling section). In an alternative embodiment, the clock signal may be recovered in the third subsection.

[0188] exist Figure 11 In the embodiment of the driving method shown in , when the sensing signals are sequentially received (or sensed) by the data driver 310 in units of pixel rows, the clock signal may be restored each time each of the sensing signals is received. In such an embodiment, the clock signal may be repeatedly restored in units of pixel rows.

[0189] In the examples, as referenced Figure 11 As described above, in the driving method, the clock signal can be recovered while the sensing signal is received (or sampled) from the pixel PX in the second section (or sensing section, or sensing horizontal section 1H_S) through the data driver 310. Therefore, no independent time for recovering the clock signal is allocated to the sensing horizontal section 1H_S (and the sensing section), so that the increase in the sensing horizontal section 1H_S (and the sensing section) can be prevented.

[0190] In embodiments of a display panel driving device, a display device, and a driving method thereof, a clock signal can be recovered from clock-embedded data when pixel characteristics are sensed by a data driver. Thus, clock and data can be stably recovered without increasing sensing time.

[0191] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0192] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, comprising: a display panel comprising data lines, sensing lines, and pixels coupled to the data lines and the sensing lines; a timing controller, wherein the timing controller generates clock embedded data including image data and a clock training signal; as well as a data driver that recovers a clock signal based on the clock training signal of the clock embedded data, recovers the image data of the clock embedded data based on the clock signal, supplies a data voltage corresponding to the image data to the data line in a first section, and receives a sensing signal from the pixel through the sensing line in a second section different from the first section, wherein, in the second section, the data driver recovers the clock signal when the sensing signal is received, and The second section includes a first sub-section, a second sub-section and a third sub-section. The data driver samples the sensing signal of the pixel in the first sub-section, converts the sampled sensing signal from analog form to digital form in the second sub-section, and transmits the digital form of the sensing signal to the timing controller in the third sub-section, and The data driver recovers the clock signal in one sub-section of the first to third sub-sections.

2. The display device according to claim 1, wherein In the second section, the data driver sequentially receives a plurality of sensing signals from a plurality of pixels and restores the clock signal whenever each of the plurality of sensing signals is received.

3. The display device according to claim 2, wherein The data driver senses each of the plurality of sensing signals of the plurality of pixels in a first cycle and repeatedly restores the clock signal in the first cycle. The display device according to claim 1 , wherein: The data driver recovers the clock signal in the first sub-section.

5. The display device according to claim 4, wherein The data driver does not recover the clock signal in the second sub-section. The display device according to claim 4 , wherein: In the second section, the clock embedded data sequentially includes a first control signal for controlling the start of a sensing operation of the data driver and a second control signal for controlling the output of the sensing signal of the data driver, The clock embedded data includes the clock training signal between the first control signal and the second control signal.

7. The display device according to claim 4, wherein The data driver includes: a sampling switch, the sampling switch comprising one end coupled to the sensing line; a capacitor coupled between the other end of the sampling switch and a reference power supply to sample the sensing signal; and an analog-to-digital converter, the analog-to-digital converter being coupled to the other end of the sampling switch, The data driver recovers the clock signal when the sampling switch is turned on.

8. The display device according to claim 7, wherein The data driver performs clock training once for each segment in which the sampling switch is turned on.

9. The display device according to claim 7, wherein The data driver provides a reference voltage to the data line in the first to third subsections.

Images