Display device and method of forming the same

Abstract

In some embodiments, the present disclosure relates to a display device, the display device including a reflector electrode coupled to an interconnect structure. An isolation structure is disposed on the reflector electrode, and a transparent electrode is disposed on the isolation structure. In addition, an optical emitter structure is disposed on the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and includes an outer portion directly overlying the top surface of the isolation structure. A hard mask layer is disposed directly between the top surface of the isolation structure and the outer portion of the via structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices and methods of forming display devices. Background Art

[0002] Many modern electronic devices, such as televisions and cellular devices, use image display devices to convert digital data into optical images. To achieve this, the image display device may include an array of pixel regions. Each pixel region may have an optical emitter structure and may be coupled to a semiconductor device. The semiconductor device may selectively apply an electrical signal (e.g., a voltage) to the optical emitter structure. After the electrical signal is applied, the optical emitter structure may emit an optical signal (e.g., light). The optical emitter structure may be, for example, an organic light emitting diode (OLED) or some other suitable light-emitting device. Summary of the Invention

[0003] An embodiment of the present invention relates to a display device, comprising: a reflector electrode coupled to an internal connection structure; an isolation structure disposed above the reflector electrode; a transparent electrode disposed above the isolation structure; an optical emitter structure disposed above the transparent electrode; a through-hole structure extending from a top surface of the isolation structure to the reflector electrode and including an outer portion directly overlying the top surface of the isolation structure; and a hard mask layer arranged directly between the top surface of the isolation structure and the outer portion of the through-hole structure.

[0004] An embodiment of the present invention relates to a display device, comprising: an isolation structure disposed above a reflector electrode; a transparent electrode disposed above the isolation structure; an optical emitter structure disposed above the transparent electrode; a through-hole structure extending from a top surface of the isolation structure to the reflector electrode and comprising an outer portion directly overlying the top surface of the isolation structure; and a hard mask layer directly arranged between the top surface of the isolation structure and the outer portion of the through-hole structure to completely separate the through-hole structure from the top surface of the isolation structure, wherein the hard mask layer comprises a material different from that of the through-hole structure and the isolation structure.

[0005] An embodiment of the present invention relates to a method for forming a display device, the method comprising: forming an isolation structure over a reflector electrode; forming a hard mask layer over the isolation structure; forming a first opening extending through the hard mask layer and the isolation structure to expose the first surface of the reflector electrode, wherein the inner sidewalls of the hard mask layer and the inner sidewalls of the isolation structure define the sidewalls of the first opening; performing a cleaning process to clean the first surface of the reflector electrode; forming a conductive layer over the hard mask layer, the sidewalls of the first opening and the first surface of the reflector electrode; performing a first removal process to remove a peripheral portion of the conductive layer to form a through-hole structure extending through the isolation structure and directly contacting the first surface of the reflector electrode; and performing a second removal process to remove a peripheral portion of the hard mask layer to expose the isolation structure, wherein after the second removal process, the hard mask layer separates the through-hole structure from the top surface of the isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A Cross-sectional views of some embodiments of a display device are shown having a hard mask layer disposed directly between a via structure and a topmost surface of an isolation structure.

[0008] Figure 1B and Figure 1C Show Figure 1A Cross-sectional views of some alternative embodiments of the via structure and hard mask layer are shown.

[0009] Figure 2 Cross-sectional views of some additional embodiments of display devices including a hard mask layer directly between a via structure and a topmost surface of an isolation structure, and exemplary light paths during operation of the display devices are shown.

[0010] Figures 3 to 13 Cross-sectional views illustrating some embodiments of a method of forming a via structure over an isolation structure in a display device, the method using a hard mask layer between the via structure and the isolation structure to mitigate damage to the isolation structure.

[0011] Figure 14 Shown with Figures 3 to 13 The method shown in FIG. 1 corresponds to a flowchart of some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one element or feature to another element or feature as depicted in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] A display device includes an array of pixel regions, wherein each pixel region includes an isolation structure arranged between a reflector electrode and a transparent electrode. A through-hole structure may extend through the isolation structure and electrically couple the reflector electrode to the transparent electrode. An optical emitter structure may be arranged above the transparent electrode. During operation of the display device, an electrical signal (e.g., a voltage) may be applied from a control circuit system to the reflector electrode and, thereby, to the transparent electrode, causing light to be generated at the interface between the optical emitter structure and the transparent electrode (e.g., due to electron-hole recombination). The light may be reflected by a top surface of the isolation structure and / or may travel through the isolation structure, be reflected by the reflector electrode, and travel back toward the top surface of the isolation structure. Because light of a given wavelength undergoes constructive and / or destructive interference at the top surface of the isolation structure, colored light may be emitted from the top surface of the optical emitter structure depending on the thickness and / or composition of the isolation structure.

[0015] To form the through-hole structure, a first conductive layer may be formed over the isolation structure. A first opening may be formed in the first conductive layer (e.g., metal) and the isolation structure to expose the first surface of the reflector electrode. In some embodiments, a cleaning process (e.g., an argon sputtering process) is performed to remove any residue (e.g., metal oxide) generated on the first surface of the reflector electrode due to the formation of the first opening. However, during the cleaning process, for example, portions of the first conductive layer may degrade, be completely removed, and / or be redeposited in undesirable areas on the isolation structure and / or the reflector electrode. Such effects of the first conductive layer during the cleaning process may be unpredictable and difficult to control. Because the upper surface of the isolation structure receives and reflects light, when the upper surface of the isolation structure is damaged, light may be scattered, which may, for example, cause the emitted light to be a different color and / or reduce the intensity of the emitted light, thereby causing the display device to be unreliable.

[0016] Various embodiments of the present disclosure are directed to a method for using a hard mask layer over an isolation structure during the formation of a through-hole structure to prevent damage to the isolation structure of a display device. In some embodiments, a hard mask layer comprising a dielectric material or a semiconductor material (such as, for example, silicon or silicon nitride) is deposited over the isolation structure. A first opening extending through the hard mask layer and the isolation structure may be formed to expose a first surface of an underlying reflector electrode. In some embodiments, a cleaning process may be performed to remove any residue on the first surface of the reflector electrode formed during the formation of the first opening. In some embodiments, due to the composition of the hard mask layer, the hard mask layer may be stable under the cleaning process and may effectively protect the isolation structure. For example, in some embodiments, during the cleaning process, the hard mask layer may have a substantially uniform etch rate during the cleaning process and / or may have a high resistance to removal during the cleaning process. After the cleaning process, in some embodiments, a conductive layer is formed over the hard mask layer and within the first opening, wherein the conductive layer may comprise a conductive material (e.g., a metal). In some embodiments, a first removal process including a first etchant can be used to selectively remove the conductive layer to form a via structure, and a second removal process including a second etchant different from the first etchant can be used to selectively remove portions of the hard mask layer that are not directly beneath the via structure. The second etchant removes the portions of the hard mask layer at a significantly higher rate (e.g., amount of material per unit time) than the isolation structure. Therefore, when the hard mask layer is removed by the second removal process, damage to the isolation structure by the second etchant is reduced, thereby improving the reliability of the final display device.

[0017] Figure 1AA cross-sectional view 100A of some embodiments of a display device is shown that includes a hard mask layer disposed directly between a via structure and an isolation structure.

[0018] The display device shown in the cross-sectional view 100A includes a first pixel region 101a and a second pixel region 101b. In other embodiments, the display device shown in the cross-sectional view 100A may include one pixel region (e.g., the first pixel region 101a) or more than the first pixel region 101a and the second pixel region 101b. In some embodiments, each of the first pixel region 101a and the second pixel region 101b is configured to emit light of a different color (e.g., red, green, blue) when receiving an electrical signal (e.g., a voltage), and the color of the light depends on the thickness of the isolation structure 106. For example, in some embodiments, the first pixel region 101a may include a first portion 106a of the isolation structure 106 having a first thickness t1; and the second pixel region 101b may include a second portion 106b of the isolation structure 106 having a second thickness t2. In some embodiments, isolation structure 106 may comprise silicon dioxide, silicon nitride, or some other material having optical properties such that incident light may be reflected as colored light due to constructive and / or destructive interference, where the color of the colored light depends, for example, on the thickness of isolation structure 106. For example, in some embodiments, isolation structure 106 comprises silicon dioxide, a first thickness t1 may correspond to green light, and a second thickness t2 may correspond to blue light. It should be understood that the color of the light may depend on the characteristics of the pixel regions (101a, 101b) rather than the thickness of isolation structure 106.

[0019] In some embodiments, the isolation structure 106 is arranged between the reflector electrode 102 and the transparent electrode 112. The first blocking structure 104 can be arranged between portions of the reflector electrode 102 so that each pixel region (101a, 101b) includes an electrically isolated portion of the reflector electrode 102. In some embodiments, the optical emitter structure 110 can be arranged above the transparent electrode 112. Furthermore, in some embodiments, the second blocking structure 114 can be arranged above the isolation structure 106 and between the optical emitter structure 110 and portions of the transparent electrode 112 to isolate the first pixel region 101a from the second pixel region 101b.

[0020] In some embodiments, the reflector electrode 102 can be coupled to the control circuitry 120. For example, in some embodiments, the reflector electrode 102 is disposed on an interconnect structure 130, which includes a network of interconnect wires 134 and interconnecting vias 136 embedded in an interconnect dielectric structure 132. In some embodiments, the interconnect structure 130 is disposed on the substrate 122 and coupled to the semiconductor device 124. In some embodiments, the semiconductor device 124 can be, for example, a metal oxide semiconductor field-effect transistor (MOSFET), which includes source / drain regions 124a located within the substrate 122 and a gate electrode 124b located above the substrate 122. The gate electrode 124b can be separated from the substrate 122 by a gate dielectric layer 124c. The control circuitry 120 is configured to selectively supply an electrical signal (e.g., a voltage) to each of the first pixel region 101a and the second pixel region 101b to emit colored light indicated by digital data.

[0021] In some embodiments, each of the first pixel region 101a and the second pixel region 101b includes a via structure 108, so that an electrical signal (e.g., a voltage) can be supplied from the control circuitry 120 to the transparent electrode 112 and the optical emitter structure 110. The electrical signal (e.g., a voltage) can, for example, cause electron-hole recombination between the transparent electrode 112 and the optical emitter structure 110 to generate light, and the light can be reflected from the top surface 106t of the isolation structure 106 and / or pass through the isolation structure 106, reflected from the reflector electrode 102, and emitted through the top surface of the isolation structure 106. Due to constructive and / or destructive interference, colored light is emitted depending on the thickness, material, and / or other characteristics of the isolation structure 106.

[0022] In some embodiments, the via structure 108 extends from the top surface 106t of the isolation structure 106 and downwardly toward the first surface 102f of the reflector electrode 102, thereby electrically coupling the reflector electrode 102 to the transparent electrode 112 in each pixel region (e.g., 101a, 101b). In some embodiments, the via structure 108 may directly overlie a portion of the top surface 106t of the isolation structure 106; however, in some embodiments, a majority of the top surface 106t of the isolation structure 106 directly contacts the transparent electrode 112 in each pixel region (e.g., 101a, 101b). In some embodiments, the isolation structure 106 may comprise silicon dioxide, and the via structure 108 may comprise a conductive material such as, for example, titanium nitride. It should be understood that other materials for the isolation structure 106 and the via structure 108 are also within the scope of the embodiments of the present disclosure.

[0023] In some embodiments, the hard mask layer 138 is disposed directly between the via structure 108 and the top surface 106t of the isolation structure 106, such that the via structure 108 does not directly contact the top surface 106t of the isolation structure 106. The hard mask layer 138 can mitigate damage to the top surface 106t of the isolation structure 106 during various cleaning and removal processes used to form the via structure 108. In such embodiments, the hard mask layer 138 can comprise a different material than the via structure 108 and the isolation structure 106, so that each of the hard mask layer 138, the via structure 108, and / or the isolation structure 106 can be selectively removed without damaging other features during formation of the display device. In some embodiments, the hard mask layer 138 can comprise silicon or silicon nitride. For example, after forming the through-hole structure 108, portions of the material of the hard mask layer 138 may be selectively removed from portions of the top surface 106t of the isolation structure 106 by an etchant that does not remove the isolation structure 106 during processing, thereby protecting the isolation structure 106 and producing a more reliable display device.

[0024] Figure 1B A cross-sectional view 100B of some embodiments of a through-hole structure in a display device is shown to highlight various features of the through-hole structure and the underlying hard mask layer. In some embodiments, the cross-sectional view 100B corresponds to Figure 1A Box B.

[0025] In some embodiments, the via structure 108 can be described as including a central horizontal segment 108c in contact with the first surface 102f of the reflector electrode 102; sidewall vertical segments 108s in contact with the inner sidewalls 106s of the isolation structure 106; and an upper horizontal segment 108u directly overlying the top surface 106t of the isolation structure 106. The central horizontal segment 108c is connected to the upper horizontal segment 108u via the sidewall vertical segments 108s. In some embodiments, as seen in the cross-sectional view 100B, there are two upper horizontal segments 108u separated from each other by the transparent electrode 112, and there are two sidewall vertical segments 108s separated from each other by the transparent electrode 112. In some embodiments, the upper horizontal segment 108u of the via structure 108 is separated from the top surface 106t of the isolation structure 106 by the hard mask layer 138. In some embodiments, the hard mask layer 138 does not overly the first surface 102f of the reflector electrode 102. In some embodiments, the hard mask layer 138 may have a third thickness t3, and the via structure 108 may have a fourth thickness t4. In some embodiments, the third thickness t3 may be approximately equal to the fourth thickness t4, while in other embodiments, the third thickness t3 may be different from the fourth thickness t4. In some embodiments, the third thickness t3 may be, for example, in a range between approximately 100 angstroms and approximately 700 angstroms. In some embodiments, the fourth thickness t4 may be, for example, in a range between approximately 100 angstroms and approximately 700 angstroms. It should be understood that other values ​​for the third thickness t3 and the fourth thickness t4 are also within the scope of the embodiments of the present disclosure.

[0026] In some embodiments, the hardmask layer 138 has a topmost surface 138t having a first average surface roughness, and the via structure 108 has a topmost surface 108t having a second average surface roughness. In some embodiments, because the hardmask layer 138 may be exposed to a cleaning process (e.g., an argon sputtering process or a bombardment process) before the via structure 108 is formed, the first average surface roughness of the topmost surface 138t of the hardmask layer 138 is greater than the second average surface roughness of the topmost surface 108t of the via structure 108. In some embodiments, to measure the average surface roughness, a roughness measurement tool (e.g., a profilometer or an atomic force microscopy (AFM) tool) calculates a mean line along the surface and measures the deviation between the height of peaks or valleys on the surface and the mean line. After measuring a plurality of deviations at a plurality of peaks and valleys across the entire surface, the average surface roughness is calculated by taking the average of the plurality of deviations, where the deviations are absolute values. In other embodiments, surface roughness is quantified by measuring the total thickness variation (TTV). The total thickness variation of a layer is the difference between the minimum and maximum thicknesses of the layer. The total thickness variation is measured over the entire length of the layer.

[0027] Figure 1C Show Figure 1B A cross-sectional view 100C of some alternative embodiments of the via structure 108 and the hard mask layer 138 is shown. Thus, in some embodiments, the cross-sectional view 100C may correspond to Figure 1A Box B shown.

[0028] In some embodiments, the via structure 108 may have a first width w1 measured between the outermost walls 108os of the via structure 108, wherein the first width w1 may be the maximum width of the via structure 108. In some embodiments, the hardmask layer 138 may have a second width w2 measured between the outermost walls 138os of the hardmask layer 138, wherein the second width w2 may be the maximum width of the hardmask layer 138. In some embodiments, the first width w1 may be less than the second width w2, such that the outermost walls 108os of the via structure 108 directly overlie the hardmask layer 138 while the outermost walls 138os of the hardmask layer 138 are not directly beneath the via structure 108. In some other embodiments (not shown), the first width w1 may be greater than the second width w2, such that the outermost walls 138os of the hardmask layer 138 directly underlie the via structure while the outermost walls 108os of the via structure 108 are not directly beneath the hardmask layer 138. In yet other embodiments, the first width w1 may be approximately equal to the second width w2, such that the outermost wall 138os of the hard mask layer 138 directly overlies the outermost wall 108os of the via structure 108. In some embodiments, the first width w1 may be different from the second width w2 because, during fabrication, the via structure 108 is formed by a first removal process and the hard mask layer 138 is formed by a second removal process that is different from the first removal process. Therefore, the via structure 108 and the hard mask layer 138 are formed independently of each other, which in some embodiments may cause the first width w1 and the second width w2 to be different from each other.

[0029] Figure 2 A cross-sectional view 200 is shown of some alternative embodiments of a display device including a hard mask layer underlying a via structure, along with exemplary light paths produced by the display device during operation.

[0030] In some embodiments, the through-hole structure 108 may completely and continuously fill the space laterally between the inner sidewalls 106s of the isolation structure 106 in each pixel region (e.g., 101a, 101b). In such an embodiment, the transparent electrode 112 does not extend below the top surface 106t of the isolation structure 106.

[0031] In some embodiments, the first pixel region 101a and the second pixel region 101b each include a reflector electrode having substantially equal widths ( Figure 1A 102). However, in other embodiments, such as in Figure 2As shown in cross-sectional view 200 , the first pixel region 101a may have a first reflector electrode portion 102a having a third width w3, and the second pixel region 101b may have a second reflector electrode portion 102b having a fourth width w4. In such embodiments, the third width w3 and the fourth width w4 may be different. For example, in some embodiments, the fourth width w4 may be less than the third width w3. In some embodiments, the minimum width (e.g., w4) corresponds to the pixel region (e.g., 101b) having the portion of the isolation structure 106 with the smallest thickness (e.g., t2). Similarly, in some embodiments, the maximum width (e.g., w3) corresponds to the pixel region (e.g., 101a) having the portion of the isolation structure 106 with the largest thickness (e.g., t1). However, in other embodiments, the relationship between the widths of the reflector electrode 102 and the thickness of the isolation structure 106 is not correlated.

[0032] Cross-sectional view 200 also illustrates an exemplary first light path 202 in second pixel region 101b. In some embodiments, light is generated at a first interface 206 between optical emitter structure 110 and transparent electrode 112 due to control circuitry 120 applying an electrical signal (e.g., a voltage) to reflector electrode 102. For example, in cross-sectional view 200, second pixel region 101b is "ON" (e.g., generating light at first interface 206), while first pixel region 101a is "OFF" (e.g., not generating light at first interface 206). In second pixel region 101b, exemplary first light path 202 illustrates how, in some embodiments, light generated at first interface 206 can be reflected by top surface 106t of second portion 106b of isolation structure 106 and / or travel through second portion 106b of isolation structure 106, be reflected by second reflector electrode portion 102b, and travel back upward toward top surface 106t of second portion 106b of isolation structure 106. Due to constructive and / or destructive interference, the top surface of the optical emitter structure 110 in the second pixel region 101b will only emit / observe from the top surface of the optical emitter structure 110 in the second pixel region 101b colored light having a first wavelength associated with the second thickness t2 of the second portion 106b of the isolation structure 106 or associated with some other feature of the second pixel region 101b. Thus, the control circuitry 120 can use digital data to selectively "turn on" one or more pixel regions (e.g., 101a, 101b) to generate an optical image.

[0033] Furthermore, it should be understood that in some other embodiments, the display device may include, for example, fewer than two pixel regions or more than two pixel regions. In such embodiments, the control circuit system 120 may still use digital data to selectively "turn on" one or more pixel regions in the display device to generate an optical image.

[0034] Figures 3 to 13 Cross-sectional views 300 through 1300 illustrate some embodiments of a method of forming a display device that uses a hard mask layer to mitigate damage to an isolation structure during formation of a via structure extending through the isolation structure. Figures 3 to 13 This is about a method, but it should be understood that Figures 3 to 13 The structure disclosed in is not limited to such a method, but can exist as a structure independently of the method.

[0035] like Figure 3 As shown in cross-sectional view 300 , reflector electrode 102 can be formed above control circuitry 120. In some embodiments, control circuitry 120 can include an interconnect structure 130 disposed above substrate 122. Interconnect structure 130 can include interconnect wires 134 and interconnect vias 136 embedded in interconnect dielectric structure 132. In some embodiments, interconnect wires 134 and interconnect vias 136 can comprise copper, tungsten, or the like. Interconnect structure 130 can couple reflector electrode 102 to semiconductor device 124 integrated on substrate 122. In some embodiments, semiconductor device 124 can be or include a metal oxide semiconductor field effect transistor (MOSFET), wherein the MOSFET includes source / drain regions 124a disposed in substrate 122. Semiconductor device 124 can also include a gate electrode 124b disposed above a gate dielectric layer 124c disposed on substrate 122. It should be understood that other types of semiconductor devices 124 are also within the scope of the present disclosure.

[0036] In some embodiments, the reflector electrode 102 may be separated by a first blocking structure 104, such that the reflector electrode 102 includes, for example, a first reflector electrode portion 102a and a second reflector electrode portion 102b. In some embodiments, the first blocking structure 104 comprises the same material as the interconnect dielectric structure 132. The reflector electrode 102 may comprise a metal that is both conductive and reflective. For example, in some embodiments, the reflector electrode 102 may comprise aluminum or aluminum-copper. In some embodiments, the first blocking structure 104 may be formed using a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), sputtering, etc.), followed by a patterning process (e.g., photolithography and etching). Then, the reflector electrode 102 may be formed on the interconnect dielectric structure 132 using a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.) followed by a patterning process (e.g., photolithography, etching, chemical mechanical planarization (CMP), etc.).

[0037] Furthermore, an isolation structure 106 is formed over reflector electrode 102. In some embodiments, isolation structure 106 includes a first portion 106a and a second portion 106b having a first thickness t1 and a second thickness t2, respectively. In some embodiments, the thicknesses (t1, t2) may be determined based on the material of isolation structure 106 and the predetermined color of light to be emitted from each portion (106a, 106b) of isolation structure 106. In some embodiments, isolation structure 106 comprises a material having optical properties such that incident light is reflected as colored light due to constructive and / or destructive interference, and the color of the colored light depends on the thickness of isolation structure 106. A non-limiting example of such a material includes silicon dioxide. In other embodiments, the color of the colored light may depend on other characteristics of isolation structure 106 (e.g., composition, dimensions, etc.) or characteristics of reflector electrode 102 (e.g., composition, dimensions, etc.), for example. Furthermore, each portion (106a, 106b) of isolation structure 106 may be continuously connected to one another. In some embodiments, the formation of isolation structure 106 may include deposition process steps (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.) and patterning process steps (e.g., photolithography / etching processes). In some embodiments, first barrier structure 104 comprises the same material as isolation structure 106. Furthermore, in some embodiments, first barrier structure 104, interconnect dielectric structure 132, and isolation structure 106 comprise the same material. In other embodiments, first barrier structure 104 and / or interconnect dielectric structure 132 may comprise a dielectric material such as undoped silicate glass (USG), silicon nitride, etc. In some embodiments, first thickness t1 and second thickness t2 of isolation structure 106 may each be within a range of, for example, approximately 200 angstroms to approximately 1500 angstroms.

[0038] In other embodiments, it should be understood that reflector electrode 102 may include more or fewer than two portions, and isolation structure 106 may include more or fewer than two portions. For example, in some embodiments, to form a display device including one pixel region, reflector electrode 102 may include first reflector electrode portion 102a but not second reflector electrode portion 102b. Furthermore, in such embodiments, isolation structure 106 may include first portion 106a but not second portion 106b.

[0039] like Figure 4As shown in the cross-sectional view 400 of , in some embodiments, a conformal hard mask layer 402 is deposited over the isolation structure 106. In some embodiments, the conformal hard mask layer 402 has a fifth thickness t5 in a range of, for example, approximately 100 angstroms and approximately 900 angstroms. The conformal hard mask layer 402 can be deposited by a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). In other embodiments, the conformal hard mask layer 402 can be grown by an epitaxial growth process. In some embodiments, the conformal hard mask layer 402 can include a semiconductor material and / or a dielectric material. For example, in some embodiments, the conformal hard mask layer 402 includes amorphous silicon or silicon nitride. The semiconductor material and / or dielectric material of the conformal hard mask layer 402 is removed from the cleaning process used later (see Figure 7 702) has a substantially constant and therefore predictable and controllable removal rate during the cleaning process (see Figure 7 In addition, the fifth thickness t5 of the conformal hard mask layer 402 is thick enough to be used in a cleaning process (see Figure 7 702) during the cleaning process (see Figure 7 702) causes the top surface 106t of the isolation structure 106 to be exposed.

[0040] like Figure 5 As shown in cross-sectional view 500 of , in some embodiments, a first masking structure 502 may be formed over the conformal hard mask layer 402. The first masking structure 502 may include first openings 504. In some embodiments, each of the first openings 504 may be arranged over each portion (106a, 106b) of the isolation structure 106. In some embodiments, the first masking structure 502 may be formed by photolithography and may include a photosensitive material (e.g., photoresist) formed by a spin-coating process. In such embodiments, the photosensitive material layer is selectively exposed to electromagnetic radiation according to a photomask or reticle. The electromagnetic radiation alters the solubility of exposed regions within the photosensitive material to define soluble regions. Subsequently, the photosensitive material is developed to define the first openings 504 within the photosensitive material by removing the soluble regions. In other embodiments, the first masking structure 502 may include a hard mask layer (e.g., a silicon nitride layer, a silicon carbide layer, etc.) patterned by, for example, a photolithography / etching process or some other suitable patterning process.

[0041] like Figure 6 As shown in the cross-sectional view 600 of FIG. 5 , an etching process may be performed to remove the conformal hard mask layer 402 and the first opening ( FIG. 5 ) of the isolation structure 106 located in the first masking structure 502. Figure 5 504), thereby forming a second opening 604 in the isolation structure 106 and exposing the first surface 102f of the reflector electrode 102. In some embodiments, the second opening 604 has a fifth width w5 ranging from approximately 0.1 micrometers to approximately 0.6 micrometers. The bottom of the second opening 604 may be defined by the first surface 102f of the reflector electrode 102, and the sidewalls of the second opening 604 may be defined by the inner sidewalls 106s of the isolation structure 106. In some embodiments, the etching process is a dry etching process, and residue 608 remains on the first surface 102f of the reflector electrode 102. The residue 608 may include, for example, a metal oxide containing the material of the isolation structure 106, the material of the reflector electrode 102, and / or the material of the conformal hard mask layer 402.

[0042] like Figure 7 As shown in the cross-sectional view 700 of FIG. 7 , the first masking structure ( Figure 6 502), and a cleaning process 702 may be performed on the isolation structure 106 to remove residues on the first surface 102f of the reflector electrode 102 ( Figure 6 608). In the absence of the cleaning process 702, the through-hole structure to be formed (see Figure 10 108) and will be with the through hole structure (see Figure 10 108) may have poor electrical contact between the first surface 102f electrically coupled to the reflector electrode 102 (e.g., the contact resistance may be high). In some embodiments, the cleaning process 702 may be or may include an argon sputtering process. Thus, in some embodiments, the cleaning process 702 includes utilizing a plasma gas (e.g., argon) to bombard the first surface 102f of the reflector electrode 102. As a result, in such embodiments, the plasma gas also bombards the conformal hard mask layer 402, which may increase the surface roughness of the top surface 402t of the conformal hard mask layer 402 and reduce the thickness of the conformal hard mask layer 402. Thus, in some embodiments, prior to the cleaning process 702, the conformal hard mask layer 402 may have a fifth thickness ( Figure 6 t5), and may have a top surface having a third average surface roughness, and after the cleaning process 702, the conformal hard mask layer 402 may have a thickness less than the fifth thickness ( Figure 6 The top surface may have a first average surface roughness greater than the third average surface roughness.

[0043] Since the conformal hard mask layer 402 includes a semiconductor material and / or a dielectric material, the removal rate of the conformal hard mask layer 402 can be more predictable than when the conformal hard mask layer 402 includes a metal. Therefore, even if the cleaning process 702 can reduce the thickness of the conformal hard mask layer 402, the conformal hard mask layer 402 can still completely cover the top surface 106t of the isolation structure 106 throughout the cleaning process 702, thereby protecting the top surface 106t of the isolation structure 106. Since the top surface 106t of the isolation structure 106 is used to reflect light during the operation of the display device (see Figure 2 ), therefore, conformal hard mask layer 402 preventing damage to top surface 106t of isolation structure 106 (eg, increasing surface roughness, changing composition, etc.) is crucial for producing reliable display devices.

[0044] Furthermore, in some embodiments, cleaning process 702 is performed in a plasma bombardment chamber. Material removed during cleaning process 702 may accumulate on the inner sidewalls of the plasma bombardment chamber. Therefore, in some embodiments, the plasma bombardment chamber requires periodic cleaning, which can interrupt production. In some embodiments, because semiconductor and / or dielectric materials are more stable than metal materials during cleaning process 702, the removal rate of semiconductor and / or dielectric materials during cleaning process 702 may be lower than the removal rate of metal during cleaning process 702. Therefore, since conformal hardmask layer 402 comprises semiconductor and / or dielectric materials, less conformal hardmask layer 402 is removed during cleaning process 702 than if conformal hardmask layer 402 comprised metal. Consequently, when conformal hardmask layer 402 comprises semiconductor and / or dielectric materials, the plasma bombardment chamber used for cleaning process 702 does not need to be cleaned as frequently as when conformal hardmask layer 402 comprises metal. In such an embodiment, less frequent cleaning of the plasma bombardment chamber may increase the yield of the final display device.

[0045] like Figure 8 As shown in the cross-sectional view 800 of FIG. 1 , a conductive layer 802 may be deposited over the conformal hard mask layer 402 and along the inner sidewalls 106s of the isolation structure 106 and the first surface 102f of the reflector electrode 102. In some embodiments, the conductive layer 802 has a fourth thickness t4 ranging from, for example, approximately 100 angstroms to approximately 700 angstroms. In other embodiments, the fourth thickness t4 may be ranging from, for example, approximately 100 angstroms to approximately 900 angstroms. In some embodiments, the conductive layer 802 may not fill the second opening ( Figure 7 604), and thus the third opening 804 may still exist between the inner sidewalls 106s of the isolation structure 106. In other words, twice the fourth thickness t4 is smaller than the second opening ( Figure 7 The fifth width of 604) ( Figure 7 In an alternative embodiment, the conductive layer 802 may completely fill the second opening ( Figure 7 604), so that there is no third opening 804 (e.g. Figure 2 108). Therefore, in an alternative embodiment, the fourth thickness t4 may be greater than the second opening ( Figure 7 The fifth width of 604) ( Figure 7 In such an alternative embodiment, the conductive layer 802 may have an upper surface with a small indentation that overlies the first surface 102f of the reflector electrode 102.

[0046] Furthermore, in some embodiments, the conductive layer 802 may include a conductive metal such as, for example, titanium nitride or tantalum nitride. Thus, in some embodiments, the conformal hard mask layer 402 and the conductive layer 802 include different materials. In some embodiments, the conductive layer 802 has a top surface 802t having a first average surface roughness that is less than a second average surface roughness of the conformal hard mask layer 402. The conductive layer 802 is completely separated from the top surface 106t of the isolation structure 106 by the conformal hard mask layer 402.

[0047] In addition, due to the cleaning process ( Figure 7 702) remove the residue ( Figure 8 608), so the conductive layer 802 can directly contact the first surface 102f of the reflector electrode 102. The direct contact between the conductive layer 802 and the reflector electrode 102 enables a reliable electrical connection. The conductive layer 802 can be deposited by a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). In addition, in some embodiments, to prevent the first surface 102f from being damaged during the cleaning process ( Figure 7 702) and before forming the conductive layer 802, the conductive layer 802 can be oxidized with the cleaning process ( Figure 7 In other words, in some embodiments, during the cleaning process ( Figure 7 702) and forming the conductive layer 802 without breaking the vacuum seal. For example, in some embodiments, the cleaning process ( Figure 7 The cleaning process ( 702 ) and the formation of the conductive layer 802 may be performed in the same chamber, such as, for example, in a plasma bombardment chamber. In other embodiments, the cleaning process ( Figure 7 The forming of the conductive layer 802 and the forming of the conductive layer 802 can be performed in different chambers in the same main body so that the vacuum seal is not broken when the substrate 122 is transferred between the chambers.

[0048] like Figure 9As shown in the cross-sectional view 900 of FIG. 8 , above the conductive layer 802 and in the third opening ( Figure 8 The second masking structure 902 may overlie a portion of the top surface 802t of the conductive layer 802. In addition, the second masking structure 902 directly overlies the first surface 102f of the reflector electrode 102 that directly contacts the conductive layer 802. It should be understood that the second masking structure 902 may be formed within the conductive layer 804. Figure 5 The second masking structure 902 is formed by a similar photolithography process as the photolithography process of the first masking structure 502 .

[0049] like Figure 10 As shown in the cross-sectional view 1000 of FIG. 1 , a first removal process 1002 may be performed to remove the conductive layer ( Figure 9 The first removal process 1002 is performed by removing the outer peripheral portion of the isolation structure 106 (not directly under the second masking structure 902) to form the via structure 108. In some embodiments, the via structure 108 extends completely through the isolation structure 106 to directly contact the first surface 102f of the reflector electrode 102. During the first removal process 1002, the conformal hard mask layer 402 may remain on the top surface 106t of the isolation structure 106, so that the first removal process 1002 does not damage the isolation structure 106.

[0050] In some embodiments, the first removal process 1002 includes a wet etching process using a first wet etchant. The first wet etchant includes a first wet etchant that is effective in removing the conductive layer ( Figure 9 802) has a high selectivity but does not remove the conformal hard mask layer 402. In this embodiment, during the first removal process 1002, as the conductive layer ( Figure 9 802) is removed and the conformal hard mask layer 402 is exposed to a first wet etchant that does not remove or removes only a small amount of the conformal hard mask layer 402. Thus, in some embodiments, the first removal process 1002 may include a first wet etchant having a conductive layer ( Figure 9 802) with respect to the conformal hard mask layer 402. In addition, in some embodiments, the first wet etchant also has a conductive layer ( Figure 9 The etchant 802 has a high selectivity ratio relative to the isolation structure 106. In some embodiments, the selectivity ratio of the first material to the second material for the etchant is quantified by the ratio of the etch rate of the first material exposed to the etchant to the etch rate of the second material exposed to the etchant. Therefore, the higher the selectivity ratio, the more likely and faster the first material will be removed by the etchant than the second material.

[0051] In some embodiments, for example, when the conductive layer ( Figure 8When the conductive layer ( 802 ) includes titanium nitride, the first wet etchant of the first removal process 1002 may include hydrogen peroxide. In this embodiment, hydrogen peroxide is effective for the conductive layer ( Figure 9 The etching rate of the conductive layer 802) is greater than the etching rate of hydrogen peroxide on the conformal hard mask layer 402. In addition, in some embodiments, when the isolation structure 106 includes silicon dioxide, the selectivity ratio of titanium nitride to silicon dioxide when hydrogen peroxide is used may be greater than 2,000, and thus the conductive layer ( Figure 9 802) relative to the isolation structure 106 may be greater than 2,000. Furthermore, in such an embodiment, the etching rate of hydrogen peroxide on silicon dioxide may be substantially equal to 0 mm per minute in a temperature environment between about 40 degrees Celsius and about 60 degrees Celsius. Therefore, if the isolation structure 106 including silicon dioxide is exposed to the first wet etchant including hydrogen peroxide, the isolation structure 106 may not be removed and / or damaged. It should be understood that other combinations of materials and / or first wet etchants are also within the scope of the embodiments of the present disclosure, wherein the first wet etchant has a lower etching rate on the conductive layer ( 802) than on the conformal hard mask layer 402 and the isolation structure 106. Figure 9 802) has high selectivity.

[0052] like Figure 11 As shown in the cross-sectional view 1100 of FIG. 1 , a second removal process 1102 may be performed to remove the conformal hard mask layer ( Figure 10 The peripheral portion of the second masking structure 902 that is not directly under the second masking structure 902 is removed to form a hard mask layer 138 that is directly arranged between the through hole structure 108 and the top surface 106t of the isolation structure 106. After the second removal process 1102, the top surface 106t of the isolation structure 106 is exposed. In some embodiments, according to the first removal process ( Figure 10Depending on the timing of the second removal process (1002) and / or the timing of the second removal process (1102), the outermost wall 902os of the second masking structure 902 may directly overlie the outermost wall 108os of the via structure 108, and the via structure 108 may directly overlie the outermost wall 138os of the hard mask layer 138. In other embodiments, due to under-etching and / or over-etching, the outermost wall 902os of the second masking structure 902 may not directly overlie the outermost wall 108os of the via structure 108, and the via structure 108 may not directly overlie the outermost wall 138os of the hard mask layer 138. In some embodiments, the second removal process 1102 does not remove and / or damage the isolation structure 106. For example, in some embodiments, before the second removal process 1102, the top surface 106t of the isolation structure 106 may have a third average surface roughness, and after the second removal process 1102, the top surface 106t of the isolation structure 106 may have a fourth average surface roughness that is approximately equal to the third average surface roughness. Therefore, in some embodiments, a portion of the hard mask layer 138 that directly contacts the top surface 106t of the isolation structure 106 has approximately the same average surface roughness as other portions of the top surface 106t of the isolation structure 106 that are not in direct contact with the hard mask layer 138.

[0053] In some embodiments, since the second removal process 1102 may be or may include a wet etching process using a second wet etchant, the removal and / or damage to the isolation structure 106 during the second removal process 1102 may be reduced. Figure 10 The second wet etchant includes a first etchant for removing the conformal hard mask layer ( Figure 10 402) has a high selectivity but does not remove the through hole structure 108 or the isolation structure 106. In this embodiment, during the second removal process 1102, as the conformal hard mask layer ( Figure 10 402) is removed and the isolation structure 106 is exposed to a second etchant that does not remove or removes only a small amount of the isolation structure 106. Similarly, during the second removal process 1102, the outermost sidewall 108os of the through-hole structure 108 is exposed to a second wet etchant. In this embodiment, the second wet etchant is effective for removing the conformal hard mask layer ( Figure 10 The second etchant has high selectivity to the isolation structure 106 and the through-hole structure 108, but does not have high selectivity to the through-hole structure 108, so that the second etchant does not remove or only removes a small amount of the through-hole structure 108. In other words, during the second removal process 1102, the isolation structure 106 and the through-hole structure 108 remain substantially unchanged.

[0054] For example, in some embodiments, when the conformal hard mask layer ( Figure 10When the conformal hard mask layer ( 402 ) includes amorphous silicon, the second wet etchant of the second removal process 1102 may include tetramethylammonium hydroxide (TMAH). In this embodiment, TMAH is effective for the conformal hard mask layer ( Figure 10 The etching rate of the conformal hard mask layer ( 402 ) is greater than the etching rate of the isolation structure 106 by TMAH, and greater than the etching rate of the through hole structure 108 by TMAH. For example, in some embodiments, when the conformal hard mask layer ( Figure 10 When the conformal hard mask layer ( Figure 10 The selectivity ratio of the isolation structure 106 to the isolation structure 106 may be greater than 2,000. Therefore, the isolation structure 106 may remain substantially unchanged when exposed to TMAH.

[0055] For example, in some other embodiments, when the conformal hard mask layer ( Figure 10 When the conformal hard mask layer ( 402 ) includes silicon nitride, the second wet etchant of the second removal process 1102 may include phosphoric acid. In this embodiment, phosphoric acid is effective for the conformal hard mask layer ( Figure 10 The etching rate of the phosphoric acid 402) is greater than the etching rate of the isolation structure 106 by phosphoric acid, and greater than the etching rate of the phosphoric acid on the through-hole structure 108. For example, in some embodiments, when the conformal hard mask layer ( Figure 10 When the conformal hard mask layer ( 402 ) includes silicon nitride and the isolation structure 106 includes silicon dioxide, phosphoric acid is used at a high temperature (eg, greater than 150 degrees Celsius) Figure 10 The selectivity ratio of 402) relative to the isolation structure 106 can be greater than 20. Therefore, when exposed to phosphoric acid, the isolation structure 106 can remain substantially unchanged.

[0056] It should be understood that other combinations of materials and / or second wet etchants are also within the scope of embodiments of the present disclosure, wherein the second wet etchant has a greater effect on the conformal hard mask layer ( 106 ) than on the isolation structure 106 . Figure 10 However, in some embodiments, the conformal hard mask layer ( Figure 10 402) can be used in cleaning process ( Figure 7 702) during the protection isolation structure 106, and the conformal hard mask layer ( Figure 10 402) can be removed from the isolation structure 106 to form the hard mask layer 138 without damaging the isolation structure 106, thereby improving the reliability of the display device.

[0057] like Figure 12 As shown in the cross-sectional view 1200 of FIG. 1 , the second masking structure ( Figure 11In some embodiments, the second masking structure ( 902 ) is removed using a third wet etchant that does not remove and / or damage the through-hole structure 108 , the hard mask layer 138 , and the isolation structure 106 . Figure 11 902). Therefore, in some embodiments, the third wet etchant and the first removal process ( Figure 10 The first etchant of 1002) is different from that of the second removal process ( Figure 11 The second etchant of 1102) is different.

[0058] like Figure 13 As shown in the cross-sectional view 1300 of FIG, a transparent electrode 112, an optical emitter structure 110, and a second blocking structure 114 are formed on the isolation structure 106 and the through-hole structure 108. In some embodiments, since the transparent electrode 112 fills the third opening ( Figure 8 804), so that transparent electrode 112 has a bottommost surface 112b located below top surface 106t of isolation structure 106. Via structure 108 electrically couples transparent electrode 112 to reflector electrode 102. In some embodiments, transparent electrode 112 may comprise a conductive material that is also optically transparent, such as, for example, indium tin oxide (ITO), fluorine tin oxide (FTO), or the like. In some embodiments, transparent electrode 112 may have a thickness ranging, for example, from approximately 500 angstroms to approximately 3000 angstroms. In some embodiments, optical emitter structure 110 may be or include an organic light emitting diode (OLED) or some other suitable light-generating device. In some embodiments, optical emitter structure 110 may have a thickness ranging, for example, from approximately 500 angstroms to approximately 3000 angstroms.

[0059] In some embodiments, to generate light at the first interface 206 between the transparent electrode 112 and the optical emitter structure 110 during operation of the display device, the transparent electrode 112 and the optical emitter structure 110 may comprise different materials. Furthermore, in some embodiments, a second barrier structure 114 may separate portions of the transparent electrode 112 from portions of the optical emitter structure 110 to define the first pixel region 101a and the second pixel region 101b. It should be understood that a display device may include an array of pixel regions and may include more or fewer than the first pixel region 101a and the second pixel region 101b. Some of the second barrier structures 114 may directly overlie the first barrier structure 104 and may comprise a dielectric material to electrically and optically isolate the pixel regions (101a, 101b) from each other. For example, the second barrier structure 114 may comprise a nitride (e.g., silicon nitride, silicon oxynitride), an oxide (e.g., silicon oxide), or the like. For example, in some embodiments, the second barrier structure 114 may include a multilayer film stack of silicon nitride and silicon oxide. Furthermore, in some embodiments, the second barrier structure 114 may include the same material as the isolation structure 106, the first barrier structure 104, and / or the interconnect dielectric structure 132. Each of the transparent electrode 112, the optical emitter structure 110, and the second barrier structure 114 may be formed by various steps, including deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.), removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.), and / or patterning processes (e.g., photolithography / etching).

[0060] Therefore, the display device includes a control circuit system 120 to selectively operate the first pixel region 101a and the second pixel region 101b. Figure 7 702) is cleaned, so the control circuit system 120 reliably sends a signal (eg, voltage) to the transparent electrode 112. In addition, since the hard mask layer 138 protects the isolation structure 106 from the cleaning process ( Figure 7 702) is damaged, so when the control circuit system 120 operates each of the pixel areas (101a, 101b), each of the pixel areas (101a, 101b) can reliably emit colored light according to the thickness (t1, t2) of the isolation structure 106 and / or according to other characteristics of each of the pixel areas (101a, 101b) (for example, composition, size, etc.).

[0061] Figure 14 Shown corresponding to Figures 3 to 13 Flowchart of some embodiments of method 1400.

[0062] Although method 1400 is shown and described as a series of actions or events below, it should be understood that the order in which these actions or events are shown should not be interpreted in a limiting sense. For example, in addition to the order shown and / or described herein, some actions can also be performed in different orders and / or simultaneously with other actions or events. In addition, not all actions shown are necessary for implementing one or more aspects or one or more embodiments described herein. In addition, one or more actions in the actions illustrated herein can be performed in one or more separate actions and / or stages.

[0063] At act 1402, an isolation structure is formed over the reflector electrode. Figure 3 A cross-sectional view 300 of some embodiments corresponding to act 1402 is shown.

[0064] At act 1404 , a hard mask layer is formed over the isolation structure. Figure 4 A cross-sectional view 400 of some embodiments corresponding to act 1404 is shown.

[0065] At act 1406, a first opening is formed in the hard mask layer and the isolation structure to expose a first surface of the reflector electrode. Figure 6 Cross-sectional view 600 of some embodiments corresponding to act 1406 is shown.

[0066] At act 1408, a cleaning process is performed to clean the first surface of the reflector electrode. Figure 7 Cross-sectional view 700 of some embodiments corresponding to act 1408 is shown.

[0067] At act 1410 , a conductive layer is formed over the hard mask layer and within the first opening. Figure 8 Cross-sectional view 800 of some embodiments corresponding to act 1410 is shown.

[0068] At act 1412 , a first removal process is performed to remove a peripheral portion of the conductive layer, thereby forming a via structure within the first opening. Figure 10 Cross-sectional view 1000 of some embodiments corresponding to act 1412 is shown.

[0069] At act 1414 , a second removal process is performed to remove peripheral portions of the hard mask layer that are not directly beneath the via structure. Figure 11 Cross-sectional view 1100 of some embodiments corresponding to act 1414 is shown.

[0070] At act 1416 , a transparent electrode is formed over the isolation structure and the via structure.

[0071] At act 1418, an optical emitter layer is formed over the transparent electrode. Figure 13 Cross-sectional view 1300 of some embodiments corresponding to acts 1416 and 1418 is shown.

[0072] Thus, embodiments of the present disclosure relate to a display device that includes a hard mask layer disposed above a topmost surface of an isolation structure to mitigate damage to the isolation structure during formation of a via structure extending completely through the isolation structure. Consequently, in some embodiments, the display device can reliably emit colored light during operation.

[0073] Therefore, in some embodiments, embodiments of the present disclosure relate to a display device, comprising: a reflector electrode coupled to an interconnect structure; an isolation structure disposed above the reflector electrode; a transparent electrode disposed above the isolation structure; an optical emitter structure disposed above the transparent electrode; a via structure extending from a top surface of the isolation structure to the reflector electrode and including an outer portion directly overlying the top surface of the isolation structure; and a hard mask layer disposed directly between the top surface of the isolation structure and the outer portion of the via structure. In one embodiment of the present invention, the display device described above comprises a conductive material, and wherein the hard mask layer comprises a dielectric material and / or a semiconductor material. In one embodiment of the present invention, the display device described above comprises a topmost surface having a first average surface roughness, and wherein the hard mask layer comprises a topmost surface having a second average surface roughness, the second average surface roughness being greater than the first average surface roughness. In one embodiment of the present invention, the display device described above comprises a hard mask layer comprising silicon nitride, and wherein the via structure comprises a conductive metal. In one embodiment of the present invention, the display device described above, wherein the hard mask layer comprises amorphous silicon, and wherein the through-hole structure comprises a conductive metal. In one embodiment of the present invention, the display device described above, wherein the through-hole structure directly contacts the first surface of the reflector electrode, and wherein the hard mask layer does not directly overlie the first surface of the reflector electrode. In one embodiment of the present invention, the display device described above, wherein the through-hole structure has a first width that is the maximum width of the through-hole structure, wherein the hard mask layer has a second width that is the maximum width of the hard mask layer, and wherein the first width and the second width are different. In one embodiment of the present invention, the display device described above, wherein the through-hole structure comprises a material different from that of the hard mask layer.

[0074] In other embodiments, embodiments of the present disclosure relate to a display device, comprising: an isolation structure disposed above a reflector electrode; a transparent electrode disposed above the isolation structure; an optical emitter structure disposed above the transparent electrode; a via structure extending from a top surface of the isolation structure to the reflector electrode and including an outer portion directly overlying the top surface of the isolation structure; and a hard mask layer disposed directly between the top surface of the isolation structure and the outer portion of the via structure to completely separate the via structure from the top surface of the isolation structure, wherein the hard mask layer comprises a material different from that of the via structure and the isolation structure. In one embodiment of the present invention, the display device described above, wherein the top surface of the isolation structure has a first portion directly contacting the hard mask layer and a second portion directly contacting the transparent electrode, wherein the first portion of the top surface of the isolation structure has a first average surface roughness, wherein the second portion of the top surface of the isolation structure has a second average surface roughness, wherein the first average surface roughness is approximately equal to the second average surface roughness. In one embodiment of the present invention, the display device described above, wherein the isolation structure comprises silicon dioxide, and wherein the hard mask layer comprises amorphous silicon or silicon nitride. In one embodiment of the present invention, the display device described above, wherein the via structure comprises titanium nitride. In one embodiment of the present invention, the display device described above, wherein the via structure directly contacts the reflector electrode.

[0075] In some other embodiments, embodiments of the present disclosure relate to a method for forming a display device, the method comprising: forming an isolation structure over a reflector electrode; forming a hard mask layer over the isolation structure; forming a first opening extending through the hard mask layer and the isolation structure to expose the first surface of the reflector electrode, wherein the inner sidewalls of the hard mask layer and the inner sidewalls of the isolation structure define the sidewalls of the first opening; performing a cleaning process to clean the first surface of the reflector electrode; forming a conductive layer over the hard mask layer, the sidewalls of the first opening and the first surface of the reflector electrode; performing a first removal process to remove an outer portion of the conductive layer to form a through-hole structure extending through the isolation structure and directly contacting the first surface of the reflector electrode; and performing a second removal process to remove an outer portion of the hard mask layer to expose the isolation structure, wherein after the second removal process, the hard mask layer separates the through-hole structure from the top surface of the isolation structure. In one embodiment of the present invention, the method includes the first removal process using a first wet etchant, and the second removal process using a second wet etchant different from the first wet etchant. In one embodiment of the present invention, the method includes the first wet etchant containing hydrogen peroxide, and the second wet etchant containing tetramethylammonium hydroxide or phosphoric acid. In one embodiment of the present invention, the method includes the hard mask layer containing silicon, the conductive layer containing titanium nitride, and the isolation structure containing silicon dioxide. In one embodiment of the present invention, the method includes the conductive layer and the hard mask layer containing different materials. In one embodiment of the present invention, the method includes the first average surface roughness before forming the hard mask layer, and the second average surface roughness after performing the second removal process, the isolation structure containing a second average surface roughness approximately equal to the first average surface roughness. In one embodiment of the present invention, the method further includes: forming a transparent electrode over the isolation structure and the via structure; and forming an optical emitter structure over the transparent electrode, wherein the transparent electrode and the optical emitter structure contain different materials.

[0076] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: a reflector electrode coupled to the interconnect structure; an isolation structure disposed on the reflector electrode; A transparent electrode, disposed on the isolation structure; an optical emitter structure disposed on the transparent electrode; a via structure extending from a top surface of the isolation structure to the reflector electrode and including an outer portion directly overlying the top surface of the isolation structure; as well as a hard mask layer disposed directly between the top surface of the isolation structure and the outer portion of the via structure, Wherein the through-hole structure has a topmost surface with a first average surface roughness, and wherein the hard mask layer has a topmost surface with a second average surface roughness, the second average surface roughness being greater than the first average surface roughness. 2 . The display device according to claim 1 , wherein the via structure comprises a conductive material, and wherein the hard mask layer comprises a dielectric material and / or a semiconductor material. 3 . The display device of claim 1 , wherein the hard mask layer comprises silicon nitride, and wherein the via structure comprises a conductive metal. 4 . The display device of claim 1 , wherein the hard mask layer comprises amorphous silicon, and wherein the via structure comprises a conductive metal. 5 . The display device of claim 1 , wherein the via structure directly contacts a first surface of the reflector electrode, and wherein the hard mask layer does not directly overlie the first surface of the reflector electrode. 6 . The display device according to claim 1 , wherein the via structure has a first width as a maximum width of the via structure, wherein the hard mask layer has a second width as a maximum width of the hard mask layer, and wherein the first width is different from the second width. The display device according to claim 1 , wherein the via structure comprises a material different from that of the hard mask layer.

8. A display device, comprising: an isolation structure disposed on the reflector electrode; A transparent electrode, disposed on the isolation structure; an optical emitter structure disposed on the transparent electrode; a via structure extending from a top surface of the isolation structure to the reflector electrode and including an outer portion directly overlying the top surface of the isolation structure; as well as a hard mask layer disposed directly between the top surface of the isolation structure and the outer portion of the via structure to completely separate the via structure from the top surface of the isolation structure, wherein the hard mask layer comprises a material different from that of the via structure and the isolation structure, Wherein the through-hole structure has a topmost surface with a first average surface roughness, and wherein the hard mask layer has a topmost surface with a second average surface roughness, the second average surface roughness being greater than the first average surface roughness.

9. A display device according to claim 8, wherein the top surface of the isolation structure has a first portion directly contacting the hard mask layer and a second portion directly contacting the transparent electrode, wherein the first portion of the top surface of the isolation structure has a third average surface roughness, wherein the second portion of the top surface of the isolation structure has a fourth average surface roughness, wherein the third average surface roughness is equal to the fourth average surface roughness.

10. The display device of claim 8, wherein the isolation structure comprises silicon dioxide, and wherein the hard mask layer comprises amorphous silicon or silicon nitride. The display device according to claim 10 , wherein the through-hole structure comprises titanium nitride. 12 . The display device according to claim 8 , wherein the through hole structure directly contacts the reflector electrode.

13. A method of forming a display device, the method comprising: forming an isolation structure over the reflector electrode; forming a hard mask layer over the isolation structure; forming a first opening extending through the hard mask layer and the isolation structure to expose a first surface of the reflector electrode, wherein inner sidewalls of the hard mask layer and inner sidewalls of the isolation structure define sidewalls of the first opening; performing a cleaning process to clean the first surface of the reflector electrode; forming a conductive layer over the hard mask layer, the sidewalls of the first opening, and the first surface of the reflector electrode; performing a first removal process to remove a peripheral portion of the conductive layer to form a via structure extending through the isolation structure and directly contacting the first surface of the reflector electrode; as well as A second removal process is performed to remove a peripheral portion of the hard mask layer to expose the isolation structure, wherein after the second removal process, the hard mask layer separates the via structure from a top surface of the isolation structure.

14. The method of claim 13, wherein the first removal process comprises utilizing a first wet etchant, and wherein the second removal process comprises utilizing a second wet etchant different from the first wet etchant.

15. The method of claim 14, wherein the first wet etchant comprises hydrogen peroxide, and wherein the second wet etchant comprises tetramethylammonium hydroxide or phosphoric acid.

16. The method of claim 13, wherein the hard mask layer comprises silicon, and the conductive layer comprises titanium nitride, and the isolation structure comprises silicon dioxide. The method of claim 13 , wherein the conductive layer and the hard mask layer comprise different materials. 18 . The method of claim 13 , wherein before forming the hard mask layer, the isolation structure has a first average surface roughness, wherein after performing the second removal process, the isolation structure has a second average surface roughness equal to the first average surface roughness.

19. The method according to claim 13, further comprising: forming a transparent electrode on the isolation structure and the through-hole structure; as well as An optical emitter structure is formed over the transparent electrode, wherein the transparent electrode and the optical emitter structure comprise different materials.

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