Display panel

By combining thin film transistors of silicon semiconductor and oxide semiconductors in the display panel, optimizing the driver circuit and signal line configurations, the technical challenges of high-resolution and high-quality image display are solved, achieving higher display performance and lower power consumption.

CN113299691BActive Publication Date: 2025-07-22SAMSUNG DISPLAY CO LTD
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Patent Information

Application Number
CN202011536013.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-02-24
Filing Date
2020-12-23
Publication Date
2025-07-22
Estimated Expiration
2040-12-23

AI Technical Summary

Technical Problem

Existing display devices have challenges in high resolution and high quality image display, especially in the design and material selection of thin film transistors, which are difficult to meet the needs of high reliability and low power consumption at the same time.

Method used

Using a combination of thin film transistors including silicon semiconductors and thin film transistors of oxide semiconductors, the configuration of driving circuits and signal lines is optimized through specific structure and layout design to achieve high resolution and high-quality image display.

Benefits of technology

Improves the resolution and image quality of the display panel, while reducing power consumption, and enhancing the reliability and voltage stability of thin film transistors.

✦ Generated by Eureka AI based on patent content.

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Abstract

A display panel includes: a substrate; a first thin film transistor including a first semiconductor layer and a first gate electrode; a data line extending in a first direction; a scan line extending in a second direction; a second thin film transistor electrically connected to the data line and including a second semiconductor layer and a second gate electrode; a third thin film transistor including a third semiconductor layer and a first upper gate electrode disposed on the third semiconductor layer; a node connection line electrically connecting the first thin film transistor and the third thin film transistor; and a shielding line located between the data line and the node connection line in a plan view and including the same material as the first upper gate electrode of the third thin film transistor. The first semiconductor layer includes a silicon semiconductor, and the third semiconductor layer includes an oxide semiconductor.
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Citation Information

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