Display device

Abstract

A display device is provided. The display device includes: a substrate including an effective area and an ineffective area; a first data conductive layer disposed on the substrate and including signal wiring connected to pixels; a first insulating layer disposed on the first data conductive layer; a second data conductive layer disposed on the first insulating layer and including connecting wiring connected to some of the signal wiring and dummy wiring patterns disconnected from the signal wiring; a second insulating layer disposed on the second data conductive layer; and pixel electrodes disposed on the second insulating layer. The dummy wiring patterns are separated from each other at breakpoints, and the second insulating layer includes a second portion disposed at the breakpoint and a third portion disposed on at least a portion of the connecting wiring, wherein the second portion and the third portion have different thicknesses.

Description

Technical Field

[0001] This disclosure relates to a display device. Background Technology

[0002] With the development of multimedia technology, display devices have become increasingly important. Currently, various types of display devices are used, such as organic light-emitting diode (OLED) devices and liquid crystal display (LCD) devices.

[0003] The display device includes an effective area for displaying an image and an ineffective area disposed around the effective area. Wiring for providing signals to pixels disposed in the effective area may be disposed in the ineffective area. For example, signal wiring may fan out from the pad area and extend toward the effective area.

[0004] Recently, displays with thin bezels have become popular. However, inefficient areas of displays with thin bezels may not provide enough space for fan-out wiring to pass through. Summary of the Invention

[0005] It is conceivable that in a thin-bezel structure, some fan-out wirings would traverse the effective region. However, if fan-out wirings traverse the effective region, the order of data signals would change, and additional mapping of drive signals in the driver chip might be required. Furthermore, signal wiring could include different conductive layers for different regions. In this case, due to process variations in the conductive layers, differences in brightness between different regions could occur.

[0006] This disclosure provides a display device in which interconnect wiring passes through an effective area and employs a typical driver chip. The display device can reduce brightness differences between areas that may be caused by process variations in the conductive layer.

[0007] The embodiments and advantages of this disclosure will become apparent to those skilled in the art from the following detailed description.

[0008] According to an exemplary embodiment of this disclosure, the display device includes connecting wires passing through an effective area and a dummy wiring pattern disposed in a portion of the effective area where no connecting wires are disposed. The dummy wiring pattern may separate at a break that may cause a horizontal difference. The display device includes a dummy groove disposed above the connecting wires or the dummy wiring pattern to suppress the perception of a horizontal difference above the break.

[0009] According to an exemplary embodiment of the present disclosure, the dummy groove provided in the effective area can form an uneven pattern similar to the horizontal difference above the break, thereby improving the problem that the difference in reflectivity caused by the horizontal difference is perceived as a specific pattern.

[0010] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0011] According to an exemplary embodiment of the present disclosure, a display device includes: a plurality of pixels; a substrate including an effective region and an ineffective region, the plurality of pixels being disposed in the effective region and the ineffective region being disposed on one side of the effective region; a first data conductive layer disposed on the substrate and including a plurality of signal wirings connected to the plurality of pixels; a first insulating layer disposed on the first data conductive layer; a second data conductive layer disposed on the first insulating layer and including connecting wirings connected to some of the plurality of signal wirings and a plurality of dummy wiring patterns disconnected from the plurality of signal wirings; a second insulating layer disposed on the second data conductive layer; and a pixel electrode disposed on the second insulating layer, wherein the plurality of dummy wiring patterns are separated from each other at a break, wherein the second insulating layer includes a first portion disposed on the plurality of dummy wiring patterns, a second portion disposed on the break, and a third portion disposed on at least a portion of the connecting wirings, and wherein a second thickness of the second portion is different from a third thickness of the third portion.

[0012] The upper surface of the second insulating layer may have an uneven pattern formed at the second portion.

[0013] The third thickness of the third part can be less than the second thickness of the second part.

[0014] The second thickness of the second part can be equal to the first thickness of the first part, and the third part can have a dummy groove recessed from a portion of the upper surface of the second insulating layer.

[0015] The second portion of the second insulating layer may include a recess formed on the upper surface, and the depth of the dummy groove may be equal to the depth of the recess.

[0016] The display device may also include an emitter layer disposed on a pixel electrode and a common electrode disposed on the emitter layer, wherein the dummy groove may be stacked with the emitter layer in the thickness direction.

[0017] The first thickness of the first part can be equal to the third thickness of the third part, and the second part can have a protruding pattern formed on the upper surface.

[0018] Each of the second and third portions of the second insulating layer may include a protruding pattern formed on the upper surface, and the third thickness of the third portion may be greater than the first thickness of the first portion.

[0019] The first part can also be set on a portion of the connecting wiring and can be connected to the third part.

[0020] At least a portion of the connecting wiring may be located in a non-active area and connected to some of the signal wirings that pass through the active area, wherein the plurality of dummy wiring patterns may be located only in the active area.

[0021] The multiple ineffective fan-out wirings can be set in the ineffective region between the first data conductive layer and the substrate.

[0022] Some of the non-ineffective fan-out wirings can be directly connected to the multiple signal wirings, and other non-ineffective fan-out wirings can be connected to the multiple signal wirings through connecting wirings.

[0023] According to another exemplary embodiment of this disclosure, a display device includes: an effective region and an ineffective region, a plurality of pixels disposed in the effective region and arranged in a matrix, the ineffective region being disposed on one side of the effective region along a first direction and including a pad region; a plurality of ineffective fan-out wirings disposed in the ineffective region and connected to the pad region; a plurality of signal wirings extending along the first direction to pass through the effective region and connected to the plurality of pixels; a plurality of connecting wirings at least partially passing through the effective region and connecting some of the plurality of ineffective fan-out wirings to some of the plurality of signal wirings; and a plurality of dummy wiring patterns configured in the effective region to intersect with some of the plurality of connecting wirings, wherein the plurality of connecting wirings and the plurality of dummy wiring patterns are formed by a conductive layer disposed on the same layer, and wherein the display device further includes: a plurality of disconnections, at which the plurality of dummy wiring patterns are separated; and a plurality of dummy grooves formed above the plurality of connecting wirings and spaced apart from each other at the same spacing as the plurality of disconnections.

[0024] The plurality of connection wires may include: a first extension portion and a second extension portion extending along a first direction; and a third extension portion connecting to the first extension portion and the second extension portion and extending along a second direction intersecting the first direction.

[0025] The plurality of dummy wiring patterns may include: a first dummy wiring pattern that extends along a first direction and intersects with a third extension portion of the plurality of connecting wirings; and a second dummy wiring pattern that extends along a second direction and intersects with a first extension portion or a second extension portion of the plurality of connecting wirings.

[0026] The plurality of disconnections may include first disconnections formed between first dummy wiring patterns spaced apart from each other along a first direction, and wherein the plurality of dummy grooves may include first dummy grooves disposed above the plurality of connecting wirings and located on the same line as the first disconnections.

[0027] Each of the plurality of pixels may include an emitting region and a non-emitting region surrounding the emitting region, and at least a portion of the plurality of connecting wires and the plurality of dummy wiring patterns may overlap with the emitting region.

[0028] At least some of the plurality of disconnected portions and the plurality of dummy grooves may be superimposed on the emission region.

[0029] The plurality of dummy wiring patterns may further include a third dummy wiring pattern, which is disposed in the effective area and extends along the second direction to intersect with the first dummy wiring pattern and the plurality of signal wirings, and the third dummy wiring pattern may not intersect with the first extension portion and the second extension portion.

[0030] The plurality of breaks may include second breaks formed between second dummy wiring patterns spaced apart from each other along a second direction, and wherein the plurality of dummy grooves may include second dummy grooves disposed above a third dummy wiring pattern and located on the same line as the second breaks.

[0031] At least some of the second dummy grooves can also be provided on the third extension.

[0032] The effective area can be divided into an inner effective area and an outer effective area. The multiple non-effective fan-out wirings are arranged along a first direction in the inner effective area. The multiple non-effective fan-out wirings may not be arranged in the outer effective area. Furthermore, the multiple connecting wirings may pass through the inner effective area to be arranged in the outer effective area.

[0033] The first extension portion of the plurality of connecting wires can be located in the inner effective area, the second extension portion of the plurality of connecting wires can be located in the outer effective area, and the third extension portion can be located from the inner effective area to the outer effective area.

[0034] The multiple signal wirings can be formed by a conductive layer disposed beneath the multiple connection wirings and the multiple dummy wiring patterns. Attached Figure Description

[0035] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0036] Figure 1This is a plan view of a display device according to an exemplary embodiment of the present disclosure;

[0037] Figure 2 yes Figure 1 A side view of the display device;

[0038] Figure 3 This is a view showing the layout of pixels of a display device according to an exemplary embodiment of the present disclosure;

[0039] Figure 4 This is a circuit diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure;

[0040] Figure 5 This is a cross-sectional view of a pixel of a display device according to an exemplary embodiment of the present disclosure;

[0041] Figure 6 This is a view showing the layout of some wiring in a display device according to an exemplary embodiment of the present disclosure;

[0042] Figure 7 This is a view showing the layout of the wiring of the data lines according to an exemplary embodiment of the present disclosure;

[0043] Figure 8 It is along Figure 7 A sectional view taken by line VIII-VIII';

[0044] Figure 9 It is along Figure 7 A cross-sectional view taken by line IX-IX';

[0045] Figure 10 This is a diagram illustrating the layout of multiple wires arranged in the effective area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0046] Figure 11 This is a diagram showing a portion of the layout of the connection wiring and dummy wiring patterns in the effective fan-out area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0047] Figure 12 This is a diagram showing a portion of the layout of the connection wiring and dummy wiring patterns in the main effective area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0048] Figure 13 It is along Figure 11 A sectional view taken from lines XIIIA-XIIIA' and XIIIB-XIIIB';

[0049] Figure 14 and Figure 15This is a cross-sectional view illustrating the process steps for manufacturing a display device according to an exemplary embodiment of the present disclosure;

[0050] Figure 16 This is a cross-sectional view showing a portion of the structure of the dummy wiring, connecting wiring, and fifth insulating layer of a display device according to another exemplary embodiment;

[0051] Figure 17 and Figure 18 It shows the manufacturing process. Figure 16 A cross-sectional view of the process steps of the method for the display device shown;

[0052] Figure 19 This is a cross-sectional view showing a portion of the structure of the dummy wiring, connecting wiring, and fifth insulating layer of a display device according to yet another exemplary embodiment;

[0053] Figure 20 and Figure 21 It shows the manufacturing process. Figure 19 A cross-sectional view of the process steps of the method for the display device shown;

[0054] Figure 22 This is a diagram showing a portion of the layout of the connection wiring and dummy wiring patterns in the effective fan-out area of ​​a display device according to another exemplary embodiment of the present disclosure;

[0055] Figure 23 It is along Figure 22 A sectional view taken from lines IIIA-IIIA' and IIIB-IIIB';

[0056] Figure 24 This is a diagram showing a portion of the layout of the connection wiring and dummy wiring patterns in the main effective area of ​​a display device according to another exemplary embodiment of the present disclosure;

[0057] Figure 25 This is a view showing a portion of the layout of some pixels and wiring in a display device according to another exemplary embodiment of the present disclosure;

[0058] Figure 26 It is along Figure 25 A sectional view taken by lines VIA-VIA' and VIB-VIB';

[0059] Figure 27 This is a view showing a portion of the layout of some pixels and wiring in a display device according to yet another exemplary embodiment of the present disclosure;

[0060] Figure 28 It is along Figure 27 A cross-sectional view taken from lines VIIIA-VIIIA' and VIIIB-VIIIB';

[0061] Figure 29 This is a perspective view of a display device according to yet another exemplary embodiment of the present disclosure; and

[0062] Figure 30 yes Figure 29 A plan view of the display device. Detailed Implementation

[0063] This disclosure will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, this disclosure may be embodied in different forms and configurations and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0064] It will also be understood that layers are described as being "on" another layer or substrate, which may be directly on the other layer or substrate, or one or more intermediate layers may exist between them. Throughout this disclosure, the same reference numerals denote the same components.

[0065] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the teachings of this disclosure, a first element may be named a second element. Similarly, a second element may be named a first element.

[0066] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0067] Figure 1 This is a plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 1 The figure shows the shape of the display device 1 when viewed from above before it is bent. In the figure, when viewed from above, the first direction DR1 represents the vertical direction and the second direction DR2 represents the horizontal direction. Figure 2 It shows Figure 1 A side view of the display device when it is bent in the thickness direction.

[0068] Reference Figure 1 and Figure 2The display device 1 can display moving images (e.g., video) or still images. The display device 1 can be used as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, laptop PCs, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), as well as for various products and devices such as televisions, picture frames, monitors, billboards, and the Internet of Things.

[0069] The display device 1 may include a display panel 10. The display panel 10 may include a flexible substrate made of a flexible polymer material such as polyimide. The display panel 10 may be bent, folded, rolled up, or bent.

[0070] Display panel 10 may include an effective area AAR for displaying images and a non-effective area NAR for not displaying images. When viewed from above, display panel 10 may be divided into the effective area AAR and the non-effective area NAR. When viewed from above, the non-effective area NAR may at least partially or completely surround the effective area AAR.

[0071] The effective region AAR can include multiple pixels PX (e.g., Figure 3 (PX1, PX2, and PX3 in the example). Pixels PX can be arranged in a matrix. Each pixel PX may include an emission layer and a circuit layer for controlling the amount of light emitted from the emission layer. The circuit layer may include wiring, electrodes, and at least one transistor. The emission layer may include an organic light-emitting material. The emission layer may be sealed by an encapsulation layer. Exemplary constructions of pixels PX will be described in detail later.

[0072] The display panel 10 may include a main region MR and a curved region BR, the curved region BR being connected to one side of the main region MR in a first direction DR1. The display panel 10 may also include a sub-region SR, the sub-region SR being connected to the curved region BR in the first direction DR1 and being superimposed on the main region MR when curved in the thickness direction.

[0073] The main region (MR) can include the active region (AAR). The inactive region (NAR) can be located at the edge of the active region (AAR) of the main region (MR).

[0074] When viewed from above, the main region MR may have a shape similar to that of the display device 1. The main region MR may have a flat surface in a plane. However, it will be understood that this disclosure is not limited thereto. In addition to the edges (or sides) connected to the curved region BR, at least one edge of the main region MR may be curved to form a curved surface, or may be curved at a right angle.

[0075] The effective region AAR can be set at an edge where at least one of the edges of the main region MR is curved or bent, except for the edge (or side) connected to the curved region BR. However, it will be understood that this disclosure is not limited thereto. Ineffective regions NAR, which do not display an image, can be set at curved or bent edges, or effective regions AAR and ineffective regions NAR can be set together at curved or bent edges.

[0076] The inactive area NAR of the main region MR can extend from the outer boundary of the active area AAR to the edge of the display panel 10. The signal wiring for applying signals to the active area AAR or the driving circuit of the display panel 10 can be set in the inactive area NAR of the main region MR.

[0077] The curved region BR can be connected to the shorter side of the main region MR. The width of the curved region BR (the width in the second direction DR2) can be smaller than the width of the main region MR (the width of the shorter side). The portion of the main region MR that connects to the curved region BR can be cut into an L-shape to reduce the border width.

[0078] Within the curved region BR, the display panel 10 can be bent with a certain curvature toward the opposite side of the display surface. When the display panel 10 is bent at the curved region BR, the surface of the display panel 10 can be flipped. (Refer to...) Figure 2 The surface of the display panel 10 facing upward in the main region MR can be bent so that the surface faces downward in the sub-region SR.

[0079] After the display device 1 is bent, the sub-region SR extends from the bent region BR in a direction parallel to the main region MR. The sub-region SR can be superimposed on the main region MR in the thickness direction of the display panel 10. The sub-region SR can be superimposed on the ineffective region NAR at the edge of the main region MR, and it can also be superimposed on the effective region AAR of the main region MR. The width of the sub-region SR can be, but is not limited to, equal to the width of the bent region BR.

[0080] Pad (or "solder pad") area PDR (see Figure 6 The external device can be located in a sub-region SR of the display panel 10. An external device can be mounted (or attached) to the pad region PDR. Examples of external devices include a driver chip 20, a driver board 30 in the form of a flexible or rigid printed circuit board, and wiring connection films, connectors, etc. More than one external device can be mounted in the sub-region SR. For example, such as... Figure 1 and Figure 2As shown, the driver chip 20 can be disposed in a sub-region SR of the display panel 10, and the driver board 30 can be attached to the end of the sub-region SR. In this case, the display panel 10 may include a first pad region connected to the driver chip 20 and a second pad region connected to the driver board 30. According to another exemplary embodiment, the driver chip 20 can be mounted on a film, and the film can be attached to the sub-region SR of the display panel 10.

[0081] The driver chip 20 can be mounted on the surface of the display panel 10. After the display panel 10 is bent in the thickness direction at the bending region BR as described above, the upper surface of the driver chip 20 can face downwards.

[0082] The driver chip 20 can be attached to the display panel 10 via an anisotropic conductive film or by ultrasonic bonding. The width of the driver chip 20 can be smaller than the width of the display panel 10 in the second direction DR2. The driver chip 20 can be disposed at the center of the sub-region SR along the second direction DR2, and the left and right edges of the driver chip 20 can be spaced apart from the left and right edges of the sub-region SR, respectively.

[0083] The driver chip 20 may include an integrated circuit (IC) for driving the display panel 10. In an exemplary embodiment, the integrated circuit may be, but is not limited to, a data driver integrated circuit that generates and provides data signals. The driver chip 20 may be connected to a wiring pad WR_PD (see [link to documentation]) disposed in the pad region PDR of the display panel 10. Figure 6 This is used to provide data signals to the routing pad WR_PD. The routing WR connected to the routing pad WR_PD (see...) Figure 6 It extends toward pixel PX to apply data signals, etc., to each of pixel PX.

[0084] Figure 3 This is a view showing the layout of pixels of a display device according to an exemplary embodiment of the present disclosure.

[0085] Reference Figure 3 Pixel PX may include a first-color pixel PX1, a second-color pixel PX2, and a third-color pixel PX3. According to an exemplary embodiment of this disclosure, the first-color pixel PX1 may be a red pixel R, the second-color pixel PX2 may be a blue pixel B, and the third-color pixel PX3 may be a green pixel G. Pixels PX may be arranged sequentially and repeatedly to form a matrix.

[0086] Each of the pixels PX may include an emission region EMA and a non-emission region NEA surrounding the emission region EMA. The emission region EMAs of pixels PX1, PX2, and PX3 may have different sizes. For example, the emission region EMA of each of the second-color pixels PX2 may be larger than the emission region EMA of each of the first-color pixels PX1, and the emission region EMA of each of the third-color pixels PX3 may be smaller than the emission region EMA of each of the first-color pixels PX1. The shape of the emission region EMA of each of the pixels PX may be, but is not limited to, a generally octagonal shape. In other embodiments, the emission region EMA may have a hexagonal shape, a circular shape, a rhombus shape, other polygonal shapes, or a polygonal shape with rounded corners (rounded corners), etc.

[0087] In some pixel columns PXC (hereinafter, the first pixel column PXC1), first-color pixels PX1 and second-color pixels PX2 are arranged alternately along a first direction DR1 (column direction). In some other pixel columns PXC (hereinafter, the second pixel column PXC2), third-color pixels PX3 are arranged repeatedly. The first pixel column PXC1 and the second pixel column PXC2 may be arranged alternately along a second direction DR2 (row direction). For example, odd-numbered pixel columns PXC may be the first pixel column PXC1, and even-numbered pixel columns PXC may be the second pixel column PXC2.

[0088] The emission regions EMA of a pixel column PXC can be generally aligned with each other along the first direction DR1. The emission regions EMA of a pixel column PXC and the emission regions EMA of adjacent pixel columns PXC can be staggered. For example, a first-color pixel PX1 and a second-color pixel PX2 in a pixel row PXR (e.g., PXR1, PXR2) can be arranged along the second direction DR2 between adjacent third-color pixels PX3 in the same pixel row PXR. Similarly, a third-color pixel PX3 in a pixel row PXR can be arranged along the second direction DR2 between adjacent first-color pixels PX1 and second-color pixels PX2 in the same pixel row PXR.

[0089] In each of the pixel rows PXR, first color pixels PX1 and second color pixels PX2 can be arranged alternately, with a third color pixel PX3 in between. For example, in the first pixel row PXR1, first color pixels PX1, third color pixels PX3, second color pixels PX2, and third color pixels PX3 are arranged repeatedly. In the second pixel row PXR2, second color pixels PX2, third color pixels PX3, first color pixels PX1, and third color pixels PX3 are arranged repeatedly. The first pixel row PXR1 and the second pixel row PXR2 can be arranged alternately along a first direction DR1 (column direction). For example, starting from the top in the figures, odd-numbered pixel rows PXR can be the first pixel row PXR1, and even-numbered pixel rows PXR can be the second pixel row PXR2. In the pixel row PXR, the emission region EMA of the first color pixel PX1 and the emission region EMA of the second color pixel PX2 can be arranged relative to the emission region EMA of the third color pixel PX3, offset to the other side in the first direction DR1. For example, the emission region EMA of pixel PX in pixel row PXR can be arranged in a zigzag pattern along the second direction DR2.

[0090] Pixels PX belonging to the same pixel column PXC can receive data signals from a common data line, and pixels PX belonging to the same pixel row PXR can receive gate signals from a common scan line. Each pixel PX can be driven by pixel circuitry. Pixel circuitry may include multiple transistors and at least one capacitor.

[0091] Figure 4 This is a circuit diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure.

[0092] Reference Figure 4 The pixel circuit may include a first transistor TR1, a second transistor TR2, a capacitor Cst, and an organic light-emitting diode EL. Scan lines SL, data lines DL, and a first power supply voltage line ELVDDL are connected to the pixel circuit.

[0093] The first transistor TR1 can be a driving transistor, and the second transistor TR2 can be a switching transistor. Although both the first transistor TR1 and the second transistor TR2... Figure 4 The transistor is shown as a P-type metal-oxide-semiconductor (PMOS) transistor, but without departing from the scope of this disclosure, the first transistor TR1 and / or the second transistor TR2 may be an N-type metal-oxide-semiconductor (NMOS) transistor in other embodiments.

[0094] The first electrode (source electrode) of the first transistor TR1 is connected to the first power supply voltage line ELVDDL, and the second electrode (drain electrode) of the first transistor TR1 is connected to the pixel electrode (or anode electrode) of the organic light-emitting diode EL. The first electrode (source electrode) of the second transistor TR2 is connected to the data line DL, and the second electrode (drain electrode) of the second transistor TR2 is connected to the gate electrode of the first transistor TR1. A capacitor Cst is connected between the gate electrode and the first electrode of the first transistor TR1. The common electrode (or cathode electrode) of the organic light-emitting diode EL receives a second power supply voltage ELVSS. The second power supply voltage ELVSS may have a lower voltage level than the first power supply voltage applied from the first power supply voltage line ELVDDL.

[0095] The second transistor TR2 can output a data signal applied to the data line DL in response to a scan signal applied to the scan line SL. The capacitor Cst is charged with a voltage corresponding to the data signal received through the second transistor TR2. The first transistor TR1 can control the amount of drive current flowing through the organic light-emitting diode EL in response to the amount of charge stored in the capacitor Cst.

[0096] Figure 4 The equivalent circuit is merely an example, and the pixel circuit may include more than two transistors (e.g., seven transistors) and two or more capacitors.

[0097] Figure 5 This is a cross-sectional view of a pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 5 For ease of explanation, the diagram is shown in the form of a thin-film transistor. Figure 4 One of the two transistors TR1 and TR2 (e.g., the first transistor TR1).

[0098] Reference Figure 5 A detailed description of pixel PX (e.g., Figure 3 The structure of PX1, PX2, and PX3 in the above description is described. The display panel 10 may include a substrate 100, a buffer layer 105, a semiconductor layer 110, a first insulating layer 121, a first gate conductive layer 130, a second insulating layer 122, a second gate conductive layer 140, a third insulating layer 123, a first data conductive layer 150, a fourth insulating layer 124, a second data conductive layer 160, a fifth insulating layer 125, a pixel electrode 170, a dam 126 including an opening for exposing the pixel electrode 170, an organic layer 190 disposed within the opening of the dam 126, and a common electrode 180 disposed on the organic layer 190 and the dam 126. Each of the layers listed above may include a single layer or a stacked layer containing multiple layers. Other layers may also be disposed between adjacent layers listed above.

[0099] A substrate 100 supports a layer disposed thereon. The substrate 100 may be made of an insulating material such as a polymer resin. Examples of polymer resins may include, but are not limited to, polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl compounds, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or any combination thereof. The substrate 100 may be a flexible substrate that can be bent, folded, or rolled.

[0100] A buffer layer 105 is disposed on the substrate 100. The buffer layer 105 prevents the diffusion of impurity ions and the penetration of moisture and / or air, while providing a flat surface. The buffer layer 105 may include silicon nitride, silicon oxide, silicon oxynitride, etc. Depending on the type of substrate 100, process conditions, etc., the buffer layer 105 may be omitted.

[0101] A semiconductor layer 110 is disposed on the buffer layer 105. The semiconductor layer 110 forms the channel of the thin-film transistor (e.g., the first transistor TR1) of the pixel PX. The semiconductor layer 110 may include polycrystalline silicon. However, it will be understood that this disclosure is not limited thereto. The semiconductor layer 110 may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. Examples of oxide semiconductors may include, but are not limited to, binary compounds (AB) containing one or more of indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB) x C y ) and quaternary compounds (AB) x C y D z ).

[0102] The first insulating layer 121 can be used as a gate insulating layer. The first insulating layer 121 may include silicon compounds, metal oxides, etc. For example, the first insulating layer 121 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. They can be used alone or in any combination. The first insulating layer 121 may include a single layer or multiple layers of different materials stacked on top of each other.

[0103] The first insulating layer 121 is disposed on the semiconductor layer 110. The first insulating layer 121 may be disposed substantially on the entire surface of the substrate 100.

[0104] A first gate conductive layer 130 is disposed on a first insulating layer 121. The first gate conductive layer 130 may include a gate electrode 131 of the thin-film transistor of the pixel PX, a scan line SL connected to the gate electrode 131, and a storage capacitor (e.g., ...). Figure 4 The first electrode 132 of the capacitor Cst). The first gate conductive layer 130 may also include a first ineffective fan-out wiring NFW_1 disposed in the ineffective region NAR (see Figure 8 ).

[0105] The first gate conductive layer 130 may include one or more of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first gate conductive layer 130 may include a single layer or multiple layers.

[0106] The second insulating layer 122 may be disposed on the first gate conductive layer 130. The second insulating layer 122 may be used as an interlayer dielectric layer or a gate insulating layer. The second insulating layer 122 may include inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide.

[0107] The second gate conductive layer 140 is disposed on the second insulating layer 122. The second gate conductive layer 140 may include the second electrode of the storage capacitor. The second gate conductive layer 140 may also include a second inactive fan-out wiring NFW_2 disposed in the inactive region NAR (see Figure 8 The second gate conductive layer 140 may include one or more of the following: molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second gate conductive layer 140 may be made of, but is not limited to, the same material as the first gate conductive layer 130. The second gate conductive layer 140 may comprise a single layer or multiple layers.

[0108] A third insulating layer 123 is disposed on the second gate conductive layer 140. The third insulating layer 123 can serve as an interlayer dielectric layer. The third insulating layer 123 may comprise inorganic insulating materials (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide) or organic insulating materials (such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB)). The third insulating layer 123 may comprise a single layer or multiple layers of different materials stacked on top of each other.

[0109] A first data conductive layer 150 is disposed on the third insulating layer 123. The first data conductive layer 150 may include a first source / drain conductive layer. For example, the first data conductive layer 150 may include a first electrode 151 and a second electrode 152 of the thin-film transistor of the pixel PX. The first data conductive layer 150 may also include signal wirings SW1 and SW2 (see...). Figure 8 The first electrode 151 and the second electrode 152 of the thin-film transistor can be electrically connected to the source region and the drain region of the semiconductor layer 110, respectively, through contact holes passing through the third insulating layer 123, the second insulating layer 122, and the first insulating layer 121. The first data conductive layer 150 may also include a first power supply voltage electrode 153 for the pixel PX.

[0110] The first data conductive layer 150 may include one or more of aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first data conductive layer 150 may include a single layer or multiple layers. For example, the first data conductive layer 150 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0111] A fourth insulating layer 124 is disposed on the first data conductive layer 150. The fourth insulating layer 124 covers the first data conductive layer 150. The fourth insulating layer 124 can be used as an interlayer dielectric layer or a via layer. The fourth insulating layer 124 may include organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0112] The second data conductive layer 160 is disposed on the fourth insulating layer 124. The second data conductive layer 160 may include a second source / drain conductive layer. For example, the second data conductive layer 160 may include a connection electrode 161 for the pixel PX. The second data conductive layer 160 may also include a connection wiring CNW (see...). Figure 8 The connecting electrode 161 can be electrically connected to the second electrode 152 of the thin-film transistor of the pixel PX through a contact hole passing through the fourth insulating layer 124.

[0113] The second data conductive layer 160 may include one or more of the following: aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second data conductive layer 160 may comprise a single layer or multiple layers. The second data conductive layer 160 may be made of, but is not limited to, the same material as the first data conductive layer 150.

[0114] A fifth insulating layer 125 is disposed on the second data conductive layer 160. The fifth insulating layer 125 covers the second data conductive layer 160. The fifth insulating layer 125 can be used as a via layer. The fifth insulating layer 125 may include the same material as the fourth insulating layer 124, or may include one or more materials listed above as examples of materials used as the fourth insulating layer 124.

[0115] Pixel electrode 170 is disposed on the fifth insulating layer 125. Pixel electrode 170 may correspond to a light-emitting element (e.g., Figure 4 The pixel electrode 170 is the anode electrode of an organic light-emitting diode (OLED). The pixel electrode 170 can be electrically connected to a connection electrode 161 included in the second data conductive layer 160 through a contact hole passing through the fifth insulating layer 125, and can be connected to the second electrode 152 of the thin-film transistor through the connection electrode 161. The pixel electrode 170 can be at least partially superimposed on the emission region EMA of the pixel PX.

[0116] The pixel electrode 170 may have, but is not limited to, a stacked structure of layers with high work functions (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In2O3)) and reflective material layers (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or any mixture thereof). The layer with high work functions may be disposed above the reflective material layer, such that the layer with high work functions is positioned closer to the organic layer 190. The pixel electrode 170 may have, but is not limited to, a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag, and ITO / Ag / ITO.

[0117] A dam 126 may be disposed on the fifth insulating layer 125 and the pixel electrode 170. The dam 126 may be at least partially superimposed on the non-emitting region NEA of the pixel PX. The dam 126 may include openings that expose at least a portion of the pixel electrode 170 in the emitting region EMA. Here, the dam 126 may also be referred to as a pixel defining layer. The dam 126 may comprise inorganic insulating materials (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide) or organic insulating materials (such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB)). The dam 126 may comprise a single layer or multiple layers of different materials stacked on top of each other.

[0118] The emitter layer of pixel PX is disposed in the opening of dam 126. The emitter layer may comprise an inorganic or organic material. In an exemplary embodiment, the emitter layer may comprise an organic layer 190. The organic layer 190 may comprise an organic emitter layer, a hole injection / transport layer, and an electron injection / transport layer. The organic layer 190 may be superimposed on the emitter region EMA.

[0119] A common electrode 180 is disposed on the organic layer 190 and the embankment 126. The common electrode 180 may correspond to the cathode electrode of the light-emitting element. The common electrode 180 may also be disposed in the non-emitting region NEA and the emitting region EMA of the pixel PX. For example, the common electrode 180 may be disposed on the entire surface of each pixel PX. The common electrode 180 may include a layer with a small work function, such as Li, Ca, LiF, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, and Ba, or any composite or mixture thereof (e.g., a mixture of Ag and Mg). The common electrode 180 may also include a transparent metal oxide layer disposed on a layer with a small work function.

[0120] Although not shown in the accompanying drawings, an encapsulation layer may be disposed on the common electrode 180. The encapsulation layer may include an inorganic layer. According to an exemplary embodiment of the present disclosure, the encapsulation layer may include a first inorganic layer, an organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the organic layer.

[0121] Figure 6 This is a view showing the layout of some wiring in a display device according to an exemplary embodiment of the present disclosure.

[0122] Reference Figure 6The width of the wiring pads WR_PD arranged in the pad region PDR in the second direction DR2 is smaller than the width of the effective region AAR in the second direction DR2. To cover the width of the effective region AAR, the wiring WR can gradually extend outward from the wiring pads WR_PD along the direction towards the effective region AAR. For example, the wiring WR is arranged in the ineffective region NAR near the effective region AAR. However, as the bezel of the display device 1 decreases, the space for arranging and extending the wiring WR decreases. If the display device 1 has an L-shaped section or if other wiring WRs are placed at corners, the space becomes even more insufficient. As a result, the arrangement of wiring WRs extending from the pad region PDR in the second direction DR2 has a smaller width than in the effective region AAR.

[0123] Based on the relative arrangement of the wiring WR extending from the pad region PDR of the non-effective region NAR adjacent to the effective region AAR, the effective region AAR can be divided into an inner effective region AAR_I and an outer effective region AAR_L. The outer effective region AAR_L includes a first outer effective region AAR_L1 and a second outer effective region AAR_L2. In the inner effective region AAR_I, the wiring WR extending from the pad region PDR of the non-effective region NAR adjacent to the effective region AAR is stacked on a first direction DR1 towards the effective region AAR. In the outer effective region AAR_L, the wiring WR extending from the pad region PDR of the non-effective region NAR adjacent to the effective region AAR is not stacked on a first direction DR1 towards the effective region AAR. Although Figure 6 The diagram shows the inner effective region AAR_I positioned at the center of the effective region AAR, the first outer effective region AAR_L1 positioned on one side of the inner effective region AAR_I along the second direction DR2, and the second outer effective region AAR_L2 positioned on the other side of the inner effective region AAR_I along the second direction DR2; however, this disclosure is not limited thereto. The number and position of the inner effective region AAR_I and the outer effective region AAR_L can vary depending on the position and configuration of the rows of wiring pads WR_PD in the pad region PDR.

[0124] In the inner active region AAR_I, the wiring WR extends along the first direction DR1 from the inactive region NAR adjacent to the inner active region AAR_I (i.e., the inner inactive region NAR), thereby applying a signal to the connected pixel PX. On the other hand, in the outer active region AAR_L, the wiring WR is routed from the inner inactive region NAR to the outside (one side or the other side of the second direction DR2) via the routing WR_CN, and extends along the first direction DR1, thereby applying a signal to the connected pixel PX. The routing WR_CN can pass through the inner active region AAR_I to reach the inactive region NAR adjacent to the outer active region AAR_L (i.e., the outer inactive region NAR). Since other wiring WRs are located in the active region AAR through which the routing WR_CN passes, the routing WR_CN can be located in a different conductive layer than the conductive layer in which other wiring WRs are arranged, to prevent short circuits between the wiring WRs.

[0125] Figure 7 This is a view showing the layout of the signal wiring of a data line according to an exemplary embodiment of the present disclosure. Figure 8 It is along Figure 7 A sectional view taken from line VIII-VIII'. Figure 9 It is along Figure 7 A sectional view taken from line IX-IX'.

[0126] Reference Figures 7 to 9 The data line DL includes a first data line DL1 that provides a first data signal to pixels PX belonging to the first pixel column PXC1, and a second data line DL2 that provides a second data signal to pixels PX belonging to the second pixel column PXC2. The first data line DL1 and the second data line DL2 can be connected from the pad region PDR to pixels PX in the effective region AAR. The first data line DL1 and the second data line DL2 can be arranged alternately along a second direction DR2 in the effective region AAR.

[0127] The first data line DL1 and the second data line DL2 can be divided into inner data lines and outer data lines. The inner data line provides data signals to the pixel PX located in the inner effective area AAR_I, while the outer data line provides data signals to the pixel PX located in the outer effective area AAR_L.

[0128] Internal data lines may include inactive fan-out routing NFW_1 and NFW_2, and signal routing SW1 and SW2. Inactive fan-out routing NFW_1 and NFW_2 may be located in the internal inactive region NAR, and signal routing SW1 and SW2 may be configured to extend from the internal inactive region NAR to the active region AAR.

[0129] The first data line DL1 corresponding to the internal data line may include a second ineffective fan-out routing NFW_2 and a first signal routing SW1. The second data line DL2 corresponding to the internal data line may include a first ineffective fan-out routing NFW_1 and a second signal routing SW2.

[0130] The second ineffective fan-out routing NFW_2 and the first signal routing SW1 of the first data line DL1 can be interconnected at the inner routing contact CNI in the ineffective region NAR adjacent to the inner effective region AAR_I. The first ineffective fan-out routing NFW_1 and the second signal routing SW2 of the second data line DL2 can be interconnected at the inner routing contact CNI in the ineffective region NAR adjacent to the inner effective region AAR_I. At the inner routing contact CNI, the second ineffective fan-out routing NFW_2 and the first signal routing SW1 of the first data line DL1 can be in direct contact with each other. At the inner routing contact CNI, the first ineffective fan-out routing NFW_1 and the second signal routing SW2 of the second data line DL2 can be in direct contact with each other.

[0131] In addition to the ineffective fan-out routing NFW_1 and NFW_2 and the signal routing SW1 and SW2, external data lines may also include WR_CN as trace routing (see...). Figure 6 The connection cabling CNW. Ineffective fan-out cabling NFW_1 and NFW_2 can be set in the inner ineffective area NAR, and signal cabling SW1 and SW2 as well as connection cabling CNW can be set to extend from the inner ineffective area NAR to the effective area AAR.

[0132] The first data line DL1 corresponding to the external data line may include a second ineffective fan-out routing NFW_2, a connection routing CNW, and a first signal routing SW1. The second data line DL2 corresponding to the external data line may include a first ineffective fan-out routing NFW_1, a connection routing CNW, and a second signal routing SW2. The connection routing CNW may correspond to an effective fan-out routing that passes through the effective area AAR.

[0133] The external data line's connection wiring CNW and ineffective fan-out wirings NFW_1 and NFW_2 can be interconnected with each other at the inner wiring contact CNI in the inner ineffective region NAR. At the inner wiring contact CNI, the ineffective fan-out wirings NFW_1 and NFW_2 and the connection wiring CNW can be in direct contact with each other. The connection wiring CNW and signal wirings SW1 and SW2 can be interconnected at the outer wiring contact in the ineffective region NAR adjacent to the outer effective region AAR_L. At the outer wiring contact, the connection wiring CNW and signal wirings SW1 and SW2 can be connected via contact electrode CNE. However, it will be understood that this disclosure is not limited thereto. The connection wiring CNW and signal wirings SW1 and SW2 can be in direct contact with each other in the outer wiring contact without contact electrode CNE. In one embodiment, the connection wiring CNW and / or signal wirings SW1 and SW2 in the outer wiring contact may also include portions conforming to the shape of the contact electrode CNE (e.g., portions bent from the wiring in the second direction DR2).

[0134] Internal data lines include ineffective fan-out cabling NFW_1 and NFW_2, and signal cabling SW1 and SW2, which can be directly connected without crossing the effective area AAR (Area of ​​Interest). These can be referred to as direct-connect data lines or direct-type data lines. External data lines include ineffective fan-out cabling NFW_1 and NFW_2, and signal cabling SW1 and SW2, connected via connecting cabling CNW. These can be referred to as indirect-connect data lines or indirect-type data lines.

[0135] Ineffective fan-out wirings NFW_1 and NFW_2, signal wirings SW1 and SW2, and connection wiring CNW can be formed by conductive layers disposed on different layers. According to an exemplary embodiment of this disclosure, ineffective fan-out wirings NFW_1 and NFW_2 may include a first gate conductive layer 130 and a second gate conductive layer 140, and signal wirings SW1 and SW2 and connection wiring CNW may include a first data conductive layer 150 and a second data conductive layer 160.

[0136] In one embodiment, regardless of whether it is an internal or external data line, the first ineffective fan-out wiring NFW_1 belonging to the second data line DL2 can be formed by the first gate conductive layer 130, and the second ineffective fan-out wiring NFW_2 belonging to the first data line DL1 can be formed by the second gate conductive layer 140. However, it will be understood that this disclosure is not limited thereto. In another embodiment, the first ineffective fan-out wiring NFW_1 can be formed by the second gate conductive layer 140, and the second ineffective fan-out wiring NFW_2 can be formed by the first gate conductive layer 130.

[0137] In one embodiment, whether it is an internal or external data line, the first signal wiring SW1 and the second signal wiring SW2 can be formed by the first data conductive layer 150, and the connection wiring CNW can be formed by the second data conductive layer 160. However, it will be understood that this disclosure is not limited thereto. In another embodiment, both the first signal wiring SW1 and the second signal wiring SW2 can be formed by the second data conductive layer 160, and the connection wiring CNW can be formed by the first data conductive layer 150.

[0138] The contact electrode CNE can be formed from a conductive layer disposed on a different layer than the connection wiring CNW and the signal wirings SW1 and SW2. For example, as Figure 9 As shown, the contact electrode CNE can be formed by the second gate conductive layer 140, but in another example, the contact electrode CNE can be formed by the first gate conductive layer 130.

[0139] Ineffective fan-out wirings NFW_1 and NFW_2 are connected to the wiring pad WR_PD via different conductive layers. For example, ineffective fan-out wirings NFW_1 and NFW_2 can pass through the bend region BR as a first data conductive layer 150 or a second data conductive layer 160, and can extend in the sub-region SR using a first gate conductive layer 130 or a second gate conductive layer 140. The wiring pad WR_PD may include a first gate conductive layer 130 and a second gate conductive layer 140, as well as a first data conductive layer 150 and a second data conductive layer 160 connected to the first gate conductive layer 130 and the second gate conductive layer 140 via contact holes. Contact holes can be formed to connect the conductive layers as the wiring extends from one conductive layer to another.

[0140] Figure 10 This is a diagram illustrating the layout of multiple wirings arranged in the effective area of ​​a display device according to an exemplary embodiment of the present disclosure. Figure 11 This is a diagram showing a portion of the layout of the connection wiring and dummy wiring patterns in the effective fan-out area of ​​a display device according to an exemplary embodiment of the present disclosure. Figure 12 This is a diagram showing a portion of the layout of the connection wiring and dummy wiring patterns in the main effective area of ​​a display device according to an exemplary embodiment of the present disclosure. For ease of explanation, Figures 10 to 12 The relative arrangement of multiple connection wirings CNW and dummy wiring patterns DMP set in the effective area AAR is shown, and multiple signal wirings SW1 and SW2 (not shown) can also be set in the effective area AAR without departing from the scope of this disclosure.

[0141] Reference Figures 10 to 12Multiple wirings can be configured to intersect each other within the effective area AAR of the display device 1. The effective area AAR can be divided into a main effective area AAR_M and an effective fan-out area AAR_F. The connecting wiring CNW is located in the effective fan-out area AAR_F, which is adjacent to the ineffective area NAR containing ineffective fan-out wirings NFW_1 and NFW_2. Multiple signal wirings SW1 and SW2 can extend along the first direction DR1 through the effective fan-out area AAR_F and the main effective area AAR_M.

[0142] The connecting wiring CNW can be disposed at the boundary of pixel PX and may not overlap with the emission area EMA of pixel PX. However, it will be understood that this disclosure is not limited thereto. In some exemplary embodiments, the connecting wiring CNW may be configured to partially overlap with the emission area EMA of pixel PX. When the display device 1 is a top-emitting display device, the connecting wiring CNW that intersects with pixel PX and overlaps with the emission area EMA will not affect the brightness of pixel PX. In addition, signal wirings SW1 and SW2 may overlap with the emission area EMA of pixel PX, or may not overlap with the emission area EMA of pixel PX.

[0143] Within the effective fan-out region AAR_F and the main effective region AAR_M, a dummy wiring pattern DMP with a similar shape to the connecting wiring CNW but electrically isolated can be configured. The connecting wiring CNW can be configured in areas between some pixels PX, but not in areas between others. Configuring connecting wiring CNW in some, but not all, areas between pixels PX causes differences in the reflectivity of the pixels PX. In this case, the difference in reflectivity would be perceived as a specific pattern. To reduce the difference in reflectivity of pixels PX, the dummy wiring pattern DMP can be configured in areas where the connecting wiring CNW is not configured. The dummy wiring pattern DMP can reduce or eliminate the reflectivity differences that would otherwise be perceived as a specific pattern.

[0144] The dummy wiring pattern (DMP) can be formed from the same conductive layer as the connection wiring (CNW). If the connection wiring (CNW) is formed from the second data conductive layer 160, the dummy wiring pattern (DMP) can also be formed from the second data conductive layer 160. The dummy wiring pattern (DMP) can be formed together (simultaneously) with the connection wiring (CNW).

[0145] A dummy routing pattern (DMP) can be formed on the same layer as a connector routing pattern (CNW), but it can be separate from the connector routing pattern (CNW). A dummy routing pattern (DMP) can be a floating routing pattern that does not directly receive electrical signals.

[0146] Figure 11The arrangement of the connection wiring CNW and dummy wiring pattern DMP along pixel columns PXC1 and PXC2 and pixel rows PXR1 and PXR2 in the effective fan-out region AAR_F is shown. Figure 12 The layout of the dummy wiring pattern (DMP) in the main active region AAR_M is shown. In the following text, reference will be made to... Figure 11 and Figure 12 The layout of the Connecting Router (CNW) and Dummy Router Pattern (DMP) is described in more detail.

[0147] Connecting wiring (CNW) and dummy wiring pattern (DMP) can be set in the area between pixel columns PXC and pixel rows PXR of pixel PX. Each of the connecting wiring (CNW) and dummy wiring pattern (DMP) includes a portion extending along a first direction DR1 and a portion extending along a second direction DR2, and they can be arranged in a grid throughout the entire effective area AAR.

[0148] The connecting cabling CNW may include a first extension CNW_1 and a second extension CNW_2 extending along a first direction DR1, and a third extension CNW_3 extending along a second direction DR2.

[0149] Reference Figure 7 and Figure 11 The first extension CNW_1 can extend from the inactive region NAR, where inactive fan-out wirings NFW_1 and NFW_2 are provided, toward the inner active region AAR_I (i.e., along the first direction DR1). The first end of the first extension CNW_1 can be located in the inactive region NAR, and the second end of the first extension CNW_1 can be located in the inner active region AAR_I. The first end of the first extension CNW_1 can be connected to the inactive fan-out wiring NFW at the inner wiring contact CNI.

[0150] The second extension CNW_2 can be connected to the third extension CNW_3 and can extend from the outer active region AAR_L toward the inactive region NAR (i.e., along the first direction DR1). The first end of the second extension CNW_2 can be located in the outer active region AAR_L, and the second end of the second extension CNW_2 can be located in the inactive region NAR adjacent to the outer active region AAR_L. The first end of the second extension CNW_2 can be connected to the second end of the third extension CNW_3. A second bend in the connecting wiring CNW can be provided at the first end of the second extension CNW_2 and / or the second end of the third extension CNW_3. The second end of the second extension CNW_2 can be connected to the signal wiring SW1 and / or SW2 via the contact electrode CNE at the outer wiring contact portion.

[0151] The third extension CNW_3 can be connected to the first extension CNW_1, and can extend along the second direction DR2 from the inner effective region AAR_I toward the outer effective region AAR_L. The first end of the third extension CNW_3 can be located in the inner effective region AAR_I, and the second end of the third extension CNW_3 can be located in the outer effective region AAR_L.

[0152] The first end of the third extension CNW_3 can be connected to the second end of the first extension CNW_1. The first bend in the connecting wiring CNW can be located at the first end of the third extension CNW_3 and / or the second end of the first extension CNW_1. The third extension CNW_3 can be completely located within the effective area AAR.

[0153] The first extension CNW_1 and the second extension CNW_2 of the connecting wiring CNW can be set in the area between pixel columns PXC in the effective area AAR. The third extension CNW_3 of the connecting wiring CNW can be set in the area between pixel rows PXR in the effective area AAR.

[0154] The ends of the first extension portion CNW_1, the second extension portion CNW_2, and the third extension portion CNW_3 may intersect each other. For example, the first and second ends of the third extension portion CNW_3 may intersect the first extension portion CNW_1 and the second extension portion CNW_2, respectively, and extend beyond the first and second extension portions CNW_1 and CNW_2. The length of the third extension portion CNW_3 may be greater than the distance between the first extension portion CNW_1 and the second extension portion CNW_2 in the second direction DR2, and the two ends of the third extension portion CNW_3 may intersect the ends of each of the first and second extension portions CNW_1 and CNW_2. Similarly, the ends of each of the first and second extension portions CNW_1 and CNW_2 disposed in the effective area AAR may intersect the third extension portion CNW_3 and extend beyond the third extension portion CNW_3. However, it will be understood that this disclosure is not limited thereto. For example, the ends of the first extension CNW_1, the second extension CNW_2, and the third extension CNW_3 of the connecting wiring CNW can be connected to each other without crossing each other, and the connecting wiring CNW can be bent at the connection point of the extensions CNW_1, CNW_2, and CNW_3.

[0155] Although not shown in the accompanying drawings, multiple signal traces SW1 and SW2 may extend along the first direction DR1. Multiple signal traces SW1 and SW2 may also be positioned in the region between pixel columns PXC in the effective region AAR, and may intersect with a third extension CNW_3 of the connecting trace CNW that passes through the region between pixel rows PXR. Signal traces SW1 and SW2, and the third extension CNW_3 of the connecting trace CNW, may overlap each other in the thickness direction where they intersect.

[0156] External data lines can be connected to inactive fan-out wiring (NFW) via connection cabling (CNW). Multiple connection cabling (CNW) can be connected to inactive fan-out wiring (NFW) separately, and they can be electrically connected to signal cabling (SW1) and (SW2) in the external active area (AAR_L). Figure 11 In the diagram, the external data lines are shown connected via first connection cabling CNW#1 to fourth connection cabling CNW#4. It will be understood that a greater number of connection cabling CNWs can be configured within the effective fan-out area AAR_F.

[0157] The further an external data line is located within the effective area AAR, the further it can be connected to the ineffective fan-out wiring NFW. In other words, the data line DL adjacent to the inner effective area AAR_I among multiple external data lines can be connected to a relatively close ineffective fan-out wiring NFW. When the signal wirings SW1 and SW2 of the external data lines are far from one side of the second direction DR2, the ineffective fan-out wiring NFW located on the other side of the second direction DR2 can be connected to the signal wirings SW1 and SW2. When viewed from above, the connecting wiring CNW of the external data lines located further out can surround the connecting wiring CNW of the external data lines located further in. Each of the connecting wiring CNWs can have the shortest path in the space between pixel columns PXC or pixel rows PXR, such that the space between pixel columns PXC or pixel rows PXR can be sequentially used as the path of the connecting wiring CNW without wasting space.

[0158] Reference Figure 11 The first extension CNW_1 of the first connecting wiring CNW#1 can be disposed in the space between the fifth pixel column PXC1 and the sixth pixel column PXC2, and the second extension CNW_2 can be disposed in the space between the second pixel column PXC2 and the third pixel column PXC1 from the left side of the figure. The third extension CNW_3 of the first connecting wiring CNW#1 can be disposed in the space between the first pixel row PXR2 and the second pixel row PXR1 from the bottom of the figure.

[0159] The second connecting wire CNW#2 can be configured to surround the first connecting wire CNW#1. The first extension CNW_1 of the second connecting wire CNW#2 can be located in the space between the sixth pixel column PXC2 and the seventh pixel column PXC1, and the second extension CNW_2 can be located in the space between the first pixel column PXC1 and the second pixel column PXC2 from the left side of the figure. The third extension CNW_3 of the second connecting wire CNW#2 can be located in the space between the second pixel row PXR1 and the third pixel row PXR2 from the bottom of the figure.

[0160] Similarly, the third connection wiring CNW#3 may surround the second connection wiring CNW#2, and the fourth connection wiring CNW#4 may surround the third connection wiring CNW#3.

[0161] The extensions of the connecting cabling CNW can intersect each other, and the extensions can extend beyond one another. This arrangement of the connecting cabling CNW can be perceived as a specific pattern within the effective fan-out region AAR_F. As described above, a dummy cabling pattern DMP is provided within the effective fan-out region AAR_F to prevent the connecting cabling CNW from being perceived as a pattern. The dummy cabling pattern DMP can be arranged in a shape similar to the extensions of the connecting cabling CNW, and at least a portion of the dummy cabling pattern DMP can intersect with the extensions of the connecting cabling CNW. The dummy cabling pattern DMP can include patterns extending along a first direction DR1 and a second direction DR2 to further mitigate the problem of perceived differences in reflectivity.

[0162] The dummy routing pattern DMP includes a first dummy routing pattern DMP_1 extending along the first direction DR1 and a second dummy routing pattern DMP_2 extending along the second direction DR2. The first dummy routing pattern DMP_1 and the second dummy routing pattern DMP_2 can be set in the effective fan-out area AAR_F and can cross with the connecting routing CNW.

[0163] Each of the first dummy wiring patterns DMP_1 set in the effective fan-out region AAR_F can intersect with the third extension CNW_3 of the connecting wiring CNW. Each of the first dummy wiring patterns DMP_1 can be connected to the third extension CNW_3 of the connecting wiring CNW at the point where it intersects with the third extension CNW_3. Each of the second dummy wiring patterns DMP_2 can intersect with either the first extension CNW_1 or the second extension CNW_2 of the connecting wiring CNW. The second dummy wiring pattern DMP_2 can be set in the outer effective region AAR_L and the inner effective region AAR_I in the effective fan-out region AAR_F. The second dummy wiring pattern DMP_2 can be connected to either the first extension CNW_1 or the second extension CNW_2 of the connecting wiring CNW at the point where it intersects with the first extension CNW_1 or the second extension CNW_2 of the connecting wiring CNW.

[0164] The first dummy wiring pattern DMP_1 can be separated and spaced apart from each other in the first direction DR1. The first dummy wiring pattern DMP_1 intersecting the third extension CNW_3 of the connecting wiring CNW can be separated from the first dummy wiring pattern DMP_1 intersecting the third extension CNW_3 of another connecting wiring CNW. Some of the first dummy wiring patterns DMP_1 can be arranged along the same extension lines as the first extension CNW_1 and the second extension CNW_2 of another connecting wiring CNW, but can be separated and spaced apart from them. Therefore, even if the first dummy wiring pattern DMP_1 is connected to the third extension CNW_3 of the connecting wiring CNW, the connecting wiring CNWs can be separated from each other.

[0165] Similarly, the second dummy wiring patterns DMP_2 can be separated and spaced apart from each other in the second direction DR2. The second dummy wiring pattern DMP_2 intersecting with the first extension CNW_1 or the second extension CNW_2 of the connecting wiring CNW can be separated from the second dummy wiring pattern DMP_2 intersecting with the first extension CNW_1 or the second extension CNW_2 of another connecting wiring CNW. Some of the second dummy wiring patterns DMP_2 can be set along the same extension line as the third extension CNW_3 of another connecting wiring CNW, but can be separated and spaced apart from it. Therefore, even if the second dummy wiring pattern DMP_2 is connected to the first extension CNW_1 or the second extension CNW_2 of the connecting wiring CNW, the connecting wiring CNWs can be separated from each other.

[0166] Reference Figure 12The dummy wiring pattern DMP may also include a third dummy wiring pattern DMP_3 disposed in the main active area AAR_M where no connecting wiring CNW is disposed. The third dummy wiring pattern DMP_3 may extend along the second direction DR2, and the first dummy wiring pattern DMP_1 disposed in the main active area AAR_M may intersect with the third dummy wiring pattern DMP_3. Compared to the second dummy wiring pattern DMP_2, the third dummy wiring pattern DMP_3 may be configured to extend from the outer active area AAR_L to the inner active area AAR_I without interruption.

[0167] The first dummy routing pattern DMP_1 and the second dummy routing pattern DMP_2 can be arranged in a pattern similar to the connector routing CNW in the effective fan-out area AAR_F, thereby improving the problem that the connector routing CNW is perceptible in the effective fan-out area AAR_F. The third dummy routing pattern DMP_3 can also be arranged in a pattern similar to the connector routing CNW in the main effective area AAR_M, thereby preventing the connector routing CNW from being perceived as a pattern in the entire effective area AAR.

[0168] The dummy wiring pattern DMP and the connecting wiring CNW can be formed as wiring extending along the first direction DR1 and the second direction DR2 throughout the entire effective area AAR, and can be partially disconnected. Some of the wiring extending along the first direction DR1 can be disconnected at the first disconnection CB_1 to form one of the first extension portion CNW_1 and the second extension portion CNW_2 of each of the connecting wiring CNWs, as well as one of the first dummy wiring pattern DMP_1. Some of the wiring extending along the second direction DR2 can be set in the main effective area AAR_M to form the third dummy wiring pattern DMP_3, while some other wiring can be disconnected at the second disconnection CB_2 in the effective fan-out area AAR_F to form one of the third extension portion CNW_3 of each of the connecting wiring CNWs and one of the second dummy wiring pattern DMP_2.

[0169] Multiple first disconnections CB_1 can be spaced apart from each other in each pixel row PXR along the second direction DR2. Multiple second disconnections CB_2 can be spaced apart from each other in each pixel column PXC along the first direction DR1. The first disconnections CB_1 and second disconnections CB_2 can be spaced apart from each other in a regular pattern and can be arranged throughout the effective area AAR. The first disconnections CB_1 and second disconnections CB_2 may not be provided in some pixel columns PXC or pixel rows PXR. For example, each of the connecting wirings CNW can include a first extension CNW_1, a second extension CNW_2, and a third extension CNW_3 that are continuously connected to each other. In addition, a third dummy wiring pattern DMP_3 can be continuously arranged along the second direction DR2. Because wirings that are separated at disconnections CB_1 and CB_2 can exist, while other wirings are arranged throughout the effective area AAR, the difference in reflectivity caused by disconnections CB_1 and CB_2 will be perceived as a pattern. Specifically, the connecting wiring CNW and the dummy wiring pattern DMP are formed by the second data conductive layer 160, and a portion of the upper surface of the fifth insulating layer 125 disposed on the second data conductive layer 160 is recessed or sunken due to the first disconnection CB_1 and the second disconnection CB_2. As a result, the pixel electrode 170 disposed on the fifth insulating layer 125 also forms a horizontal difference that causes a difference in the reflectivity of the incident light.

[0170] According to an exemplary embodiment of the present disclosure, the display device 1 may include a plurality of dummy recesses HT_1, which are superimposed on the connecting wiring CNW and spaced apart from each other at the same spacing as the first disconnection CB_1 and the second disconnection CB_2. The dummy recesses HT_1 may have a similar arrangement to the first disconnection CB_1 and the second disconnection CB_2 in the effective fan-out region AAR_F.

[0171] The first break portion CB_1 can be arranged along at least one direction between adjacent first dummy wiring patterns DMP_1 spaced apart from each other at a constant interval. The first break portion CB_1 can be arranged along a first direction DR1 and can be located in the space between adjacent pixel columns PXC, or it can be arranged along a second direction DR2 in a pixel row PXR. The first extension portion CNW_1 or the second extension portion CNW_2 of the connecting wiring CNW can be arranged on the same line along the direction along which the first break portion CB_1 is arranged. Therefore, the portion with the first break portion CB_1 can be distinguished from the portion with the first extension portion CNW_1 or the second extension portion CNW_2, and can be perceived as a pattern. To prevent this, a plurality of dummy grooves HT_1 can be provided overlapping the first extension portion CNW_1 or the second extension portion CNW_2 of the connecting wiring CNW.

[0172] Multiple dummy grooves HT_1 can be spaced apart from each other at a distance substantially equal to the distance between the disconnections CB_1 and CB_2, and also spaced apart from the disconnections CB_1 and CB_2. For example, the dummy grooves HT_1 can be provided on the first extension CNW_1 or the second extension CNW_2 of the connecting wiring CNW, and some of the dummy grooves HT_1 can be positioned on the same line as the first disconnection CB_1. The spacing between the first disconnections CB_1 can be substantially equal to the spacing between the dummy grooves HT_1 and the first disconnection CB_1.

[0173] The dummy recess HT_1 can be located on the same line as the first break CB_1 in the effective fan-out region AAR_F. The first break CB_1 and the dummy recess HT_1 can be arranged along the first direction DR1 in the space between adjacent pixel columns PXC. Alternatively, the first break CB_1 and the first dummy recess HT_1 can be arranged along the second direction DR2 within the same pixel row PXR. The dummy recess HT_1 included in the display device 1 can prevent the pattern from being perceived, which would otherwise be perceived due to the difference in reflectivity caused by the first break CB_1 and the second break CB_2.

[0174] Figure 13 It is along Figure 11 A sectional view taken from lines XIIIA-XIIIA' and XIIIB-XIIIB'. Figure 13 The cross-section shown passes through the first break CB_1 and the dummy groove HT_1 in the effective fan-out region AAR_F. For ease of illustration, in Figure 13 The components disposed on the pixel electrode 170 are omitted.

[0175] Reference Figure 13 The second data conductive layer 160 may include a dummy wiring pattern (DMP) and a connecting wiring (CNW). The dummy wiring pattern (DMP) may include a first dummy wiring pattern (DMP_1) separated at a first break (CB_1) in the effective fan-out region AAR_F. The fifth insulating layer 125 may be configured to cover the second data conductive layer 160. The upper surface of the fifth insulating layer 125 may be recessed at the portion corresponding to the first break (CB_1) due to the horizontal difference of the underlying layers.

[0176] For example, the fifth insulating layer 125 may include a first portion VP1 covering the first dummy wiring pattern DMP_1 and a portion of the connecting wiring CNW, and a second portion VP2 covering the first break portion CB_1. The first portion VP1 may have a thickness DH_1 and may have a flat upper surface.

[0177] On the other hand, the upper surface of the second portion VP2 of the fifth insulating layer 125 covering the first break CB_1 can be recessed due to the horizontal difference of the second data conductive layer 160 disposed below it. The second portion VP2 of the fifth insulating layer 125 can have a thickness DH_2 that is substantially the same as the first portion VP1, and its upper surface can be recessed from the upper surface of the first portion VP1 by the thickness of the second data conductive layer 160. By applying a uniform insulating material to the entire upper surface of the second data conductive layer 160 and curing it to form the fifth insulating layer 125, a portion of the upper surface of the fifth insulating layer 125 can be recessed due to the horizontal difference below it. At the first break CB_1 of the second data conductive layer 160, a portion of the upper surface of the fifth insulating layer 125 can be recessed at the second portion VP2, and a portion of the upper surface of the pixel electrode 170 disposed thereon can also be recessed. Since the pixel electrode 170 has such a shape, the reflectivity of the incident light varies depending on the position, so the portion where the first break CB_1 is located will be distinguished and perceived as a pattern.

[0178] According to an exemplary embodiment of this disclosure, the fifth insulating layer 125 may include dummy grooves HT_1, which are spaced apart from each other at a spacing substantially the same as that of the first disconnection portion CB_1 and are superimposed on the connection wiring CNW of the second data conductive layer 160. Each of the dummy grooves HT_1 may be formed in a third portion VP3 of the fifth insulating layer 125, the third portion VP3 having a thickness DH_3 different from the other portions of the fifth insulating layer 125. The thickness DH_3 of the third portion VP3 may be different from the thickness DH_1 of the first portion VP1 and the thickness DH_2 of the second portion VP2, and the dummy groove HT_1 may be formed on the upper surface of the third portion VP3.

[0179] The thickness DH_3 of the third portion VP3 of the fifth insulating layer 125, in which the dummy groove HT_1 is formed, can be less than the thickness DH_1 of the first portion VP1 and the thickness DH_2 of the second portion VP2. The first portion VP1 and the second portion VP2 can have uniform thicknesses that conform to the level formed below them, but the third portion VP3 can have a relatively small thickness.

[0180] In addition to the recess formed by the first break portion CB_1 located below it, the portion of the upper surface of the pixel electrode 170 located on the fifth insulating layer 125 corresponding to the dummy groove HT_1 can be recessed. The dummy grooves HT_1 can be spaced apart from each other at the same spacing as the first break portion CB_1, and can also be arranged in a regular pattern.

[0181] like Figure 11As shown, the dummy recess HT_1 can be disposed on a wiring arranged along the first direction DR1 in the space between pixel columns PXC with an area substantially the same as the first break portion CB_1. For example, the dummy recess HT_1 and the first break portion CB_1 disposed in the first pixel row PXR1 from the bottom can be spaced apart at a regular distance and can be disposed between adjacent pixel columns PXC. Similarly, the dummy recess HT_1 and the first break portion CB_1 disposed in each pixel row PXR can be disposed at a regular distance in the effective fan-out region AAR_F. A portion of the fifth insulating layer 125 disposed on the second data conductive layer 160 may include a horizontal difference in the upper surface formed by the dummy recess HT_1 and the first break portion CB_1, such that there is no difference between the portion of the pixel electrode 170 where the first break portion CB_1 is disposed and the portion where the dummy recess HT_1 is formed. In this way, regardless of the location, the effective fan-out region AAR_F with the first break CB_1 can have uniform reflectivity, preventing the first break CB_1 from being seen as a pattern due to differences in reflectivity.

[0182] The dummy groove HT_1 can be formed by using a halftone mask to form the upper surface of the fifth insulating layer 125 with insulating material and curing the insulating material during the process of forming the fifth insulating layer 125. By using a halftone mask to form a horizontal difference (i.e., a recess in the upper surface of the fifth insulating layer 125 that corresponds to the horizontal difference caused by the first break CB_1), a dummy groove HT_1 similar to the recess formed in the fifth insulating layer 125 due to the first break CB_1 can be formed in the fifth insulating layer 125.

[0183] Figure 14 and Figure 15 This is a cross-sectional view illustrating the process steps for manufacturing a display device according to an exemplary embodiment of the present disclosure.

[0184] Reference Figure 14 and Figure 15 The process for forming the fifth insulating layer 125 is described. First, an insulating material layer 125' is formed on the second data conductive layer 160. The insulating material layer 125' can be cured during subsequent processes to form the fifth insulating layer 125. The insulating material layer 125' may include an organic insulating material and therefore may have a relatively flat upper surface before curing. In subsequent processes, when the organic insulating material is cured by an exposure and curing process, the upper surface of the insulating material layer 125' may be recessed in some places due to the horizontal difference below it. Specifically, the portion of the insulating material layer 125' disposed on the first break CB_1 of the second data conductive layer 160 may have a recessed upper surface during the curing process due to the horizontal difference below it.

[0185] On the other hand, since no horizontal difference is formed below it, the insulating material layer 125' disposed on the connecting wiring CNW can have a flat upper surface. According to an exemplary embodiment of the present disclosure, a dummy recess HT_1 can be formed in the fifth insulating layer 125 by performing an exposure process on a portion of the insulating material layer 125'. In an exemplary embodiment, a portion of the insulating material layer 125' on the connecting wiring CNW can be illuminated with light using a halftone mask HTM, and a recess HT' can be formed in a portion of the upper surface of the insulating material layer 125'.

[0186] When the insulating material layer 125' is exposed using a halftone mask HTM, light can be directed only to a portion of the insulating material layer 125', excluding the recessed portion HT'. As a result, the portion of the upper surface of the insulating material layer 125' exposed to light through the halftone mask HTM can be recessed.

[0187] Subsequently, referring to Figure 15 The fifth insulating layer 125 can be formed by curing the insulating material layer 125'. When the insulating material layer 125' is cured, its height can be reduced, so that the upper surface can be bent according to the underlying layer to have a horizontal difference in some areas. The height of the upper surface of the insulating material layer 125' in the underlying layer where no horizontal difference is formed can be uniformly reduced. In doing so, the recess HT' can become a dummy groove HT_1 in the upper surface of the fifth insulating layer 125. After the insulating material layer 125' is cured, the fifth insulating layer 125 is formed including a recess (i.e., the second portion VP2) formed in the portion overlapping with the first break portion CB_1 and a recess formed by the dummy groove HT_1 (i.e., the third portion VP3). The first portion VP1 of the fifth insulating layer 125 has a flat upper surface, while the second portion VP2 and the third portion VP3 have recessed upper surfaces. Therefore, the upper surface of the fifth insulating layer 125 can have a recessed pattern regularly spaced apart from each other throughout the effective area AAR.

[0188] The display device 1 according to an exemplary embodiment of the present disclosure may include a dummy groove HT_1 formed in a fifth insulating layer 125 to prevent the first disconnection CB_1 from being perceived as a pattern in the effective fan-out region AAR_F.

[0189] In the following description, various exemplary embodiments of a display device according to the present disclosure will be described with reference to other accompanying drawings.

[0190] Figure 16 This is a cross-sectional view showing a portion of the structure of the dummy wiring, connecting wiring, and fifth insulating layer of a display device according to another exemplary embodiment.

[0191] The shape of the display device 1 is not particularly limited here, as long as the fifth insulating layer 125 can be regularly shaped to reduce the difference in reflectivity that may be caused by the first break CB_1. In some exemplary embodiments, the fifth insulating layer 125 may include a raised pattern HTP formed at the second portion VP2 where the first break CB_1 is formed and at a third portion VP3 spaced apart from the second portion VP2. The raised pattern HTP may be spaced apart from each other at a constant pitch in the effective fan-out region AAR_F to prevent the portion where the first break CB_1 is provided from appearing different from other portions and thus being perceived as a pattern.

[0192] Reference Figure 16 The fifth insulating layer 125_1 may include a raised pattern HTP formed on the portion of its upper surface corresponding to the first break portion CB_1. The raised pattern HTP may include a first raised pattern HTP_1 and a second raised pattern HTP_2. The first raised pattern HTP_1 is formed on a second portion VP2 of the fifth insulating layer 125 that overlaps with the first break portion CB_1, and the second raised pattern HTP_2 is formed on a third portion VP3 that is spaced apart from the second portion VP2 and overlaps with the connecting wiring CNW. The thickness DH_1 of the first portion VP1, where no raised pattern HTP is formed, may be different from the thickness DH_2 of the second portion VP2 and the thickness DH_3 of the third portion VP3, where raised patterns HTP are formed. Figure 13 Compared to the exemplary embodiments, in Figure 16 In the display device 1, the thickness DH_1 of the first part VP1 of the fifth insulating layer 125 is less than the thickness DH_2 of the second part VP2 and / or the thickness DH_3 of the third part VP3.

[0193] The first protruding pattern HTP_1 and the second protruding pattern HTP_2 can be spaced apart from each other at a constant pitch, and the fifth insulating layer 125 can have recessed patterns in the effective fan-out region AAR_F, the recessed patterns having a constant pitch. The display device 1 can prevent the pattern from being perceived as a pattern due to differences in reflectivity in the effective fan-out region AAR_F.

[0194] Figure 17 and Figure 18 It shows the manufacturing process. Figure 16 A cross-sectional view of the process steps of the method for the display device shown.

[0195] Reference Figure 17 and Figure 18 The raised pattern HTP of the fifth insulating layer 125_1 can also be formed using a halftone mask HTM_1. Figure 14 and Figure 15Compared to the exemplary embodiment, the portion of the insulating material layer 125' other than the second portion VP2 and the third portion VP3 can be illuminated with light via a halftone mask HTM_1. A first protrusion HTP'_1 and a second protrusion HTP'_2 can be formed on the insulating material layer 125' and cured to form a fifth insulating layer 125_1, such that a first protruding pattern HTP_1 and a second protruding pattern HTP_2 can be formed on the upper surface of the fifth insulating layer 125_1. The second protruding pattern HTP_2 can be arranged similarly to the first protruding pattern HTP_1 superimposed on the first break CB_1 to form a uniform raised pattern on the upper surface of the fifth insulating layer 125_1 in the effective fan-out region AAR_F. The display device 1 can prevent the pattern from being perceived as a pattern due to the difference in reflectivity caused by the first break CB_1.

[0196] It will be understood that if the unevenness formed in the second portion VP2 of the fifth insulating layer 125_1 due to the first disconnection CB_1 and the second disconnection CB_2 can be removed, then the dummy groove HT_1 or protruding pattern HTP_2 formed in the third portion VP3 provided on the connecting wiring CNW can be omitted.

[0197] Figure 19 This is a cross-sectional view showing a portion of the structure of the dummy wiring, connecting wiring, and fifth insulating layer of a display device according to yet another exemplary embodiment. Figure 20 and Figure 21 It shows the manufacturing process. Figure 19 A cross-sectional view of the process steps of the method for the display device shown.

[0198] Reference Figures 19 to 21 The fifth insulating layer 125_2 includes a first protruding pattern HTP_1 corresponding to the upper surface of the second portion VP2, while the upper surfaces of the first portion VP1 and the third portion VP3 can be flat. The thickness of the first portion VP1 of the fifth insulating layer 125_2 can be equal to the thickness of the third portion VP3 of the fifth insulating layer 125_2, and the thickness of the second portion VP2 of the fifth insulating layer 125_2 can be greater than the thicknesses of the first portion VP1 and the third portion VP3. This exemplary embodiment is related to... Figure 16 The difference in the exemplary embodiment is that the second protruding pattern HTP_2 formed on the third portion VP3 is omitted in the fifth insulating layer 125_2.

[0199] During the process of forming the fifth insulating layer 125_2, a first protruding portion HTP'_1 is formed at the portion of the insulating material layer 125'_2 that overlaps with the first break portion CB_1 using a halftone mask HTM_1. By curing the insulating material layer 125'_2, a fifth insulating layer 125_2 with a relatively flat upper surface is formed. The second portion VP2 corresponding to the first break portion CB_1 may partially protrude or protrude. It will be understood that the first protruding pattern HTP_1 of this exemplary embodiment may have a relatively low height, so that the upper surface of the fifth insulating layer 125_2 can be formed relatively flat, thereby reducing the difference in reflectivity of the entire effective fan-out region AAR_F. The display device 1 can reduce the recess of the fifth insulating layer 125_2 that would otherwise be formed due to the first break portion CB_1 of the first dummy wiring pattern DMP_1, and the display device 1 can improve the problem of the pattern being perceived as a pattern in the effective fan-out region AAR_F. Other elements are the same as those described above, therefore, redundant descriptions will be omitted.

[0200] Figure 22 This is a diagram showing a portion of the layout of the connection wiring and dummy wiring patterns in the effective fan-out area of ​​a display device according to another exemplary embodiment of the present disclosure. Figure 23 It is along Figure 22 A sectional view taken from lines IIIA-IIIA' and IIIB-IIIB'.

[0201] Reference Figure 22 and Figure 23 In addition to the first break CB_1 where the first dummy wiring pattern DMP_1 separates, the display device 1 may also include a second break CB_2 where the second dummy wiring pattern DMP_2 separates. A portion of the upper surface of the fifth insulating layer 125 may be recessed due to the first break CB_1 and the second break CB_2, and the pattern may be perceived as a pattern. The display device 1 according to this exemplary embodiment may include a first dummy recess HT_1 and a second dummy recess HT_2 having an arrangement similar to that of the first break CB_1 and the second break CB_2.

[0202] The first dummy groove HT_1 and the first break portion CB_1 are positioned on the same line and spaced apart from each other at the same distance as the first break portion CB_1. The second dummy groove HT_2 is positioned on the same line as the first dummy groove HT_1 and the second break portion CB_2, and spaced apart from each other at the same distance as the second break portion CB_2. The first dummy groove HT_1 has been described above, so the second dummy groove HT_2 will be described in detail below.

[0203] As described above, the second dummy wiring pattern DMP_2 can extend along the second direction DR2 to intersect with the first extension portion CNW_1 or the second extension portion CNW_2 of the connecting wiring CNW. Additionally, the second dummy wiring pattern DMP_2 can be provided on the extension line of the third extension portion CNW_3 of the connecting wiring CNW. The second break portion CB_2 between the second dummy wiring patterns DMP_2 spaced apart at a constant interval can be arranged along at least one direction. The second break portion CB_2 can be arranged along the second direction DR2 and can be provided in the space between adjacent pixel rows PXR, or it can be arranged in the pixel column PXC along the first direction DR1. The third extension portion CNW_3 of the connecting wiring CNW can be provided on the same line along the direction along which the second break portion CB_2 is arranged. Therefore, the portion provided with the second break portion CB_2 can be distinguished from the portion provided with the third extension portion CNW_3 of the connecting wiring CNW and can be perceived as a pattern. To prevent this, a plurality of second dummy grooves HT_2 superimposed on the third extension portion CNW_3 of the connecting wiring CNW can be provided.

[0204] The second dummy groove HT_2 can be located on the same line as the second break portion CB_2 in the effective fan-out region AAR_F. The second break portion CB_2 and the second dummy groove HT_2 can be arranged along the second direction DR2 in the space between adjacent pixel rows PXR. Alternatively, the second break portion CB_2 and the second dummy groove HT_2 can be arranged along the first direction DR1 within the same pixel column PXC.

[0205] The second dummy groove HT_2 can be formed in the fifth insulating layer 125, which is superimposed on the connecting wiring CNW, in a manner similar to the first dummy groove HT_1. The first dummy groove HT_1 and the second dummy groove HT_2 can be formed by recessing a portion of the upper surface of the fifth insulating layer 125, such that, in addition to the portions superimposed on the disconnections CB_1 and CB_2, the fifth insulating layer 125 includes multiple dummy grooves HT_1 and HT_2, thereby forming a uniform recessed pattern. Therefore, the problem of perceptible patterns in the effective fan-out region AAR_F due to differences in reflectivity can be suppressed.

[0206] Figure 24 This is a diagram showing a portion of the layout of the connection wiring and dummy wiring patterns in the main effective area of ​​a display device according to another exemplary embodiment of the present disclosure.

[0207] Reference Figure 24Multiple second dummy recesses HT_2 can be disposed on the third dummy wiring pattern DMP_3 within the main effective region AAR_M. The connecting wiring CNW can be disposed only within the effective fan-out region AAR_F, and not within the main effective region AAR_M. In this case, the effective fan-out region AAR_F and the main effective region AAR_M can be distinguished based on the position of the connecting wiring CNW. The first dummy wiring pattern DMP_1, the second dummy wiring pattern DMP_2, and / or the third dummy wiring pattern DMP_3 disposed in each of the effective fan-out region AAR_F and the main effective region AAR_M will result in a difference in reflectivity due to the first disconnection CB_1 and the second disconnection CB_2. To prevent this, multiple dummy recesses HT_2 can also be arranged within the main effective region AAR_M, in addition to the effective fan-out region AAR_F.

[0208] Multiple second dummy grooves HT_2 can be superimposed on each of the third dummy wiring pattern DMP_3 in the main active area AAR_M. The second dummy grooves HT_2 can be arranged along the second direction DR2 in the space between adjacent pixel rows PXR. Additionally, the second dummy grooves HT_2 can be arranged along the first direction DR1 in pixel columns PXC.

[0209] Thus, the multiple dummy grooves, including the first dummy groove HT_1 and the second dummy groove HT_2, which are set in the entire effective fan-out area AAR_F where the connecting wiring CNW is set and the main effective area AAR_M where the connecting wiring CNW is not set, can further prevent the problem of perceptible patterns in the entire effective area AAR.

[0210] Figure 25 This is a view showing a portion of the layout of some pixels and wiring in a display device according to another exemplary embodiment of the present disclosure. Figure 26 It is along Figure 25 A sectional view taken from lines VIA-VIA' and VIB-VIB'.

[0211] Reference Figure 25 and Figure 26 Each pixel PX in the display device 2 includes an emitting region EMA and a non-emitting region NEA. Connecting wiring CNW and dummy wiring pattern DMP can be formed by the second data conductive layer 160 and configured to overlap with the emitting region EMA. The portions of the connecting wiring CNW and dummy wiring pattern DMP extending along the first direction DR1 can overlap with the emitting regions EMA of the first color pixel PX1, the second color pixel PX2, and the third color pixel PX3 (see...). Figure 11 Stacked. This exemplary embodiment and Figure 11The difference in the exemplary embodiment lies in the different arrangements of the connecting wiring CNW and the dummy wiring pattern DMP. Figure 25 Only some of the pixel columns PXC and pixel rows PXR are shown.

[0212] The connecting wiring CNW and the dummy wiring pattern DMP can be formed by the second data conductive layer 160, and are configured to partially overlap with the pixel electrode 170 and the organic layer 190 disposed thereon in the thickness direction. In the case that the display device 2 is a top-emitting display device, the brightness will not be affected even if the connecting wiring CNW intersects with the pixel PX and overlaps with the emitting region EMA.

[0213] The first dummy groove HT_1 and the second dummy groove HT_2 disposed on the connecting wiring CNW, and the first break portion CB_1 and the second break portion CB_2 of the dummy wiring pattern DMP, may not overlap with the emitter region EMA. The pixel electrode 170 disposed on the fifth insulating layer 125 may include portions having an uneven (e.g., curved, recessed, protruding) upper surface due to the first dummy groove HT_1 and the second dummy groove HT_2, and the break portions CB_1 and CB_2. However, because the first dummy groove HT_1 and the second dummy groove HT_2, and the break portions CB_1 and CB_2, do not overlap with the organic layer 190, the pixel electrode 170 may have a flat upper surface in other portions, including the portion on which the organic layer 190 is disposed. However, it will be understood that this disclosure is not limited thereto. In some embodiments, the dummy grooves HT_1 and HT_2, and the break portions CB_1 and CB_2, may be positioned within the emitter region EMA.

[0214] Figure 27 This is a view showing a portion of the layout of some pixels and wiring in a display device according to yet another exemplary embodiment of the present disclosure. Figure 28 It is along Figure 27 A sectional view taken from lines VIIIA-VIIIA' and VIIIB-VIIIB'.

[0215] Reference Figure 27 and Figure 28In the display device 3, the emitting region EMA can be superimposed in the thickness direction with the first dummy groove HT_1 and the second dummy groove HT_2 disposed above the connecting wiring CNW, and the first break portion CB_1 and the second break portion CB_2 of the dummy wiring pattern DMP. The pixel electrode 170 disposed on the fifth insulating layer 125 can have an uneven (e.g., curved, recessed, or protruding) upper surface conforming to the recessed pattern of the fifth insulating layer 125. Since the dummy grooves HT_1 and HT_2 and the break portions CB_1 and CB_2 are superimposed on the organic layer 190, the pixel electrode 170 on which the organic layer 190 is disposed can also have an uneven upper surface. Since the organic layer 190 includes organic material, the upper surface can be formed to be flat despite the uneven pattern of the underlying layer. In addition, when the display device 3 is a top-emitting type display device, the brightness will not be affected even if the first dummy groove HT_1 and the second dummy groove HT_2 and / or the first break portion CB_1 and the second break portion CB_2 are superimposed on the emitting region EMA. The other components are the same as those described above, therefore, redundant descriptions will be omitted.

[0216] Figure 29 This is a perspective view of a display device according to yet another exemplary embodiment of the present disclosure. Figure 30 yes Figure 29 A plan view of the display device.

[0217] Reference Figure 29 and Figure 30 The display device 4 according to this exemplary embodiment includes a plurality of display areas, the plurality of display areas including a front effective area AAR0, side effective areas AAR1, AAR2, AAR3 and AAR4 and corner areas C1, C2, C3 and C4.

[0218] The front effective region AAR0 and the side effective regions AAR1, AAR2, AAR3, and AAR4 can be the effective regions AAR for displaying the image. The side effective regions AAR1, AAR2, AAR3, and AAR4 can be bent at an angle of 30° to 120° relative to the front effective region AAR0.

[0219] Corner regions C1, C2, C3, and C4 can be located between the side effective regions AAR1, AAR2, AAR3, and AAR4. Corner regions C1, C2, C3, and C4 can each comprise a first corner region to a fourth corner region C1, C2, C3, and C4 located between two of the first to fourth side effective regions AAR1, AAR2, AAR3, and AAR4. The first to fourth corner regions C1, C2, C3, and C4 can be configured to be adjacent to the four corners of the front effective region AAR0, respectively. Except for their location, the first to fourth corner regions C1, C2, C3, and C4 can have similar functions or configurations. Corner regions C1, C2, C3, and C4 can correspond to non-effective regions NAR where no image is displayed and can provide space through which wiring can pass.

[0220] According to an exemplary embodiment, and with reference Figure 6 Similar to the described embodiments, the width of the pad region PDR can be smaller than the width of the active region AAR. Therefore, the display device 4 can use a wiring WR extending from the pad region PDR via a direct data line to transmit signals to the first active region AAR1, the front active region AAR0, and the third active region AAR3. Since there is insufficient space for the inactive region NAR in the second active region AAR2 or the fourth active region AA4, signals can be transmitted to them via an indirect data line. For example, the display device 4 can transmit signals to the second active region AAR2 or the fourth active region AA4 via an indirect data line utilizing the wiring WR_CN that passes through the active region AAR as described above. A detailed description of this has already been given above; therefore, redundant descriptions will be omitted.

[0221] It will be understood that those skilled in the art will appreciate that many variations and modifications can be made to the exemplary embodiments without substantially departing from the principles of this disclosure. Therefore, the exemplary embodiments of this disclosure disclosed herein are used and understood in a general and descriptive sense, and not for limiting purposes.

Claims

1. A display device, the display device comprising: Multiple pixels; A substrate includes an effective region and an ineffective region, wherein the plurality of pixels are disposed in the effective region and the ineffective region is disposed on one side of the effective region; A first data conductive layer is disposed on the substrate and includes multiple signal wirings connected to the plurality of pixels; A first insulating layer is disposed on the first data conductive layer; A second data conductive layer is disposed on the first insulating layer and includes connecting wires connected to some of the multiple signal wires and multiple dummy wiring patterns disconnected from the multiple signal wires. A second insulating layer is disposed on the second data conductive layer; as well as Pixel electrodes are disposed on the second insulating layer. The plurality of dummy wiring patterns are separated from each other at the break points. The second insulating layer includes a first portion disposed on the plurality of dummy wiring patterns, a second portion disposed on the break portion, and a third portion disposed on at least a portion of the connecting wiring. The second thickness of the second part is different from the third thickness of the third part.

2. The display device according to claim 1, wherein, The upper surface of the second insulating layer has an uneven pattern formed at the second portion.

3. The display device according to claim 2, wherein, The third thickness of the third part is less than the second thickness of the second part.

4. The display device according to claim 3, in, The second thickness of the second part is equal to the first thickness of the first part, and The third portion has a dummy groove recessed from the upper surface of the second insulating layer.

5. The display device according to claim 4, in, The second portion of the second insulating layer includes a recess formed on the upper surface, and The depth of the dummy groove is equal to the depth of the recess.

6. The display device according to claim 4, further comprising: An emission layer is disposed on the pixel electrode; as well as A common electrode is disposed on the emitter layer. The dummy groove is stacked with the emission layer in the thickness direction.

7. The display device according to claim 3, in, The first thickness of the first portion is equal to the third thickness of the third portion, and The second part has a protruding pattern formed on the upper surface.

8. The display device according to claim 3, in, Each of the second portion and the third portion of the second insulating layer includes a raised pattern formed on the upper surface, and The third thickness of the third part is greater than the first thickness of the first part.

9. The display device according to claim 1, wherein, The first part is also disposed on a portion of the connecting cable and connected to the third part.

10. The display device according to claim 1, in, At least a portion of the connection wiring is disposed in the non-active area and connected to some of the signal wirings that pass through the active area. The plurality of dummy wiring patterns are set only in the effective area.

11. The display device according to claim 10, wherein, Multiple ineffective fan-out wirings are disposed in the ineffective region between the first data conductive layer and the substrate.

12. The display device according to claim 11, wherein, Some of the multiple ineffective fan-out wirings are directly connected to the multiple signal wirings, and other ineffective fan-out wirings are connected to the multiple signal wirings through the connecting wirings.

13. A display device, the display device comprising: The system comprises an effective region and an ineffective region. Multiple pixels are disposed within the effective region and arranged in a matrix. The ineffective region is disposed along a first direction on one side of the effective region and includes a pad region. Multiple ineffective fan-out wires are disposed in the ineffective area and connected to the pad area; Multiple signal wirings extend along the first direction to pass through the effective area and connect to the multiple pixels; Multiple connection wires, at least partially passing through the effective area, and connecting some of the multiple ineffective fan-out wires to some of the multiple signal wires; as well as Multiple dummy wiring patterns are configured to intersect with some of the multiple connecting wirings in the effective area. The multiple connecting wires and the multiple dummy wiring patterns are formed by a conductive layer disposed on the same layer, and The display device further includes: a plurality of disconnections, wherein the plurality of dummy wiring patterns are separated at the plurality of disconnections; and a plurality of dummy grooves formed on the plurality of connecting wirings and spaced apart from each other at the same spacing as the plurality of disconnections.

14. The display device according to claim 13, wherein, The plurality of connecting wires include: a first extension portion and a second extension portion extending along the first direction; and a third extension portion connecting the first extension portion and the second extension portion and extending along a second direction intersecting the first direction.

15. The display device according to claim 14, wherein, The plurality of dummy wiring patterns include: a first dummy wiring pattern extending along the first direction and intersecting with the third extension portion of the plurality of connecting wirings; and a second dummy wiring pattern extending along the second direction and intersecting with the first extension portion or the second extension portion of the plurality of connecting wirings.

16. The display device according to claim 15, in, The plurality of breaks include a first break formed between the first dummy wiring patterns spaced apart from each other along the first direction, and The plurality of dummy grooves includes a first dummy groove disposed above the plurality of connecting wires and located on the same line as the first disconnection portion.

17. The display device according to claim 13, wherein, Each of the plurality of pixels includes an emitting region and a non-emitting region surrounding the emitting region, wherein at least a portion of the plurality of connecting wires and the plurality of dummy wiring patterns overlaps with the emitting region.

18. The display device according to claim 17, wherein, At least some of the plurality of disconnected portions and the plurality of dummy grooves overlap with the emission region.

19. The display device according to claim 15, in, The plurality of dummy wiring patterns also includes a third dummy wiring pattern, which is disposed in the effective area and extends along the second direction to intersect with the first dummy wiring pattern and the plurality of signal wirings. The third dummy wiring pattern does not intersect with the first extension portion and the second extension portion.

20. The display device according to claim 19, in, The plurality of breaks include second breaks formed between the second dummy wiring patterns spaced apart from each other along the second direction, and The plurality of dummy grooves include a second dummy groove disposed above the third dummy wiring pattern and located on the same line as the second disconnection portion.

21. The display device according to claim 20, wherein, At least some of the second dummy grooves are also provided on the third extension.

22. The display device according to claim 14, in, The effective area is divided into an inner effective area and an outer effective area. The multiple ineffective fan-out wirings are arranged along the first direction in the inner effective area, and the multiple ineffective fan-out wirings are not arranged in the outer effective area. The multiple connecting wires pass through the inner effective area to be positioned in the outer effective area.

23. The display device according to claim 22, in, The first extension portion of the plurality of connecting wires is disposed in the inner effective area, and the second extension portion of the plurality of connecting wires is disposed in the outer effective area. The third extension portion is configured to extend from the inner effective region to the outer effective region.

24. The display device according to claim 13, wherein, The multiple signal wirings are formed by a conductive layer disposed beneath the multiple connection wirings and the multiple dummy wiring patterns.

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