Magnetic storage devices

Abstract

The magnetic memory device includes a spin-orbit torque (SOT) sensing structure that can be strained and seedless and formed with perpendicular magnetic anisotropy. A magnetic tunnel junction (MTJ) stack is disposed on the SOT sensing structure. The spacer layer can decouple the layers between the SOT sensing structure and the MTJ stack or decouple the layers within the MTJ stack. One end of the SOT sensing structure can be coupled to a first transistor, and the other end of the SOT sensing structure is coupled to a second transistor.

Description

Technical Field

[0001] Embodiments of the present application relate to a magnetic memory device. Background Art

[0002] Magnetic random access memory (MRAM) provides performance comparable to volatile static random access memory (SRAM) with power consumption comparable to volatile dynamic random access memory (DRAM) and with comparable density. MRAM provides faster access times and experiences minimal degradation over time compared to non-volatile memory (NVM) flash memory, which can only be rewritten a limited number of times. One type of MRAM is spin transfer torque magnetic random access memory (STT-MRAM). STT-MRAM utilizes a magnetic tunnel junction (MTJ) that is written at least in part by a current driven through the MTJ. Another type of MRAM is spin-orbit torque (SOT) MRAM (SOT-MRAM), which typically requires lower switching current than STT-MRAM. Summary of the invention

[0003] An embodiment of the present application provides a magnetic memory device, comprising: a first spin-orbit torque (SOT) sensing structure, the first SOT sensing structure comprising a Hall metal with perpendicular magnetic anisotropy; a first magnetic tunnel junction (MTJ) stack, disposed above the first SOT sensing structure; a first wire coupled to a first side of the first SOT sensing structure; and a second wire coupled to a second side of the first SOT sensing structure.

[0004] An embodiment of the present application provides a magnetic memory device, comprising: a first spin-orbit torque (SOT) sensing structure, the first SOT sensing structure comprising a Hall metal; a magnetic tunnel junction (MTJ) stack, disposed above the first SOT sensing structure, the MTJ stack comprising a spacer layer inserted between a free layer of the MTJ stack and the first SOT sensing structure; a first wire coupled to a first side of the first SOT sensing structure; and a second wire coupled to a second side of the first SOT sensing structure.

[0005] An embodiment of the present application provides a magnetic memory device, comprising: a first spin-orbit torque (SOT) sensing structure, the first SOT sensing structure comprising a multilayer Hall metal with perpendicular magnetic anisotropy; a first magnetic tunnel junction (MTJ) stack, disposed above the first SOT sensing structure; a first source / drain of a first transistor, coupled to a first side of the first SOT sensing structure; and a second source / drain of a second transistor, coupled to a second side of the first SOT sensing structure.

[0006] The embodiments of the present application provide a strained ferromagnetic Hall metal SOT layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity.

[0008] Figure 1 is a schematic diagram of a SOT-MRAM cell according to some embodiments.

[0009] Figure 2 is a schematic diagram of a SOT-MRAM cell according to some embodiments.

[0010] Figure 3A and 3B is a schematic diagram of a SOT sensing structure according to various embodiments.

[0011] Figure 4 is a cross-sectional view of a SOT-MRAM device according to some embodiments.

[0012] Figures 5 to 14 is an intermediate step for forming a SOT-MRAM device according to some embodiments.

[0013] Fig.15 is a cross-sectional view of a SOT-MRAM device according to some embodiments.

[0014] Fig.16 is a perspective view of a SOT-MRAM device according to some embodiments.

[0015] Fig.17 is a circuit diagram of a SOT-MRAM device according to some embodiments.

[0016] Fig.18 The operation of a SOT-MRAM cell according to some embodiments is shown. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different components of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first component on or above a second component may include an embodiment in which the first and second components are directly contacted to form, and may also include an embodiment in which an additional component is formed between the first component and the second component, so that the first and second components may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] In addition, for ease of description, spatial relative terms such as "under...", "below...", "lower", "above...", "upper", etc. may be used herein to easily describe the relationship between one element or component as shown in the figure and another (or other) elements or components. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. In addition, the term "made of..." can mean "including" or "consisting of...". In addition, in subsequent manufacturing processes, there may be one or more additional operations in / between the described operations, and the order of operations may change. In the present disclosure, the phrase "one of A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), unless otherwise specified, it does not mean one element from A, one element from B and one element from C. The materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment may be adopted in other embodiments, and detailed descriptions thereof may be omitted.

[0019] Embodiments use various techniques to enhance the efficiency and operation of SOT-MRAM devices to control the spin and effective resistance of the MRAM film stack. Some embodiments use a Hall metal SOT sensing structure strained to have a strong perpendicular magnetic anisotropy (PMA). The SOT sensing structure can be built directly on the dielectric layer without a seed layer to maintain a high spin Hall angle (SHA). A magnetically coupled tuning spacer can be placed between the SOT sensing structure and the magnetic tunnel junction (MTJ) film stack of the SOT-MRAM so that the magnetic field generated from inside the SOT sensing structure can help the free layer switching of the MTJ film stack. Embodiments can be combined and used on other MTJ film stack arrangements to provide SOT switching at reduced current requirements.

[0020] Spin torque transfer magnetic random access memory (STT-MRAM) is one of the next generation storage technologies for CMOS integrated circuits (ICs). However, fast access applications such as low-level caches require fast access times, but write speeds are generally slower than read speeds. Cache applications for central processing units (CPUs) and / or microcontrollers (MCUs) also require low power consumption. However, STT-MRAM requires a large amount of current to change the magnetization state during write operations. An STT-MRAM cell typically includes a magnetic tunnel junction (MTJ) film stack having a free magnetic layer, a reference or pinned magnetic layer, and a tunnel barrier layer. The magnetization of the magnetic layer can be in-plane or perpendicular to the substrate plane. The free layer is a magnetic layer with two energetically equivalent magnetic states, where the magnetization in the free layer is parallel or antiparallel to the magnetization of the reference layer. By applying a current perpendicular to the MTJ film stack, the magnetic orientation (or torque) of the free magnetic layer can be changed, resulting in a change in the resistance through the MTJ film stack, thereby effectively writing data to the STT-MRAM cell.

[0021] In contrast, magnetic switching via spin-orbit torque (SOT) has the potential to provide orders of magnitude improvements in write current and speed, making SOT promising for high-speed, low-power cache memory applications.

[0022] In SOT-MRAM, the magnetic moment of the free magnetic layer of the MTJ film stack is switched using the spin-orbit interaction effect generated by the flow of current adjacent to the free magnetic layer of the MTJ film stack. The current can flow in the SOT sensing structure. Manipulating the direction of the free magnetic layer causes a change in the resistance of the MTJ film stack, which can be used to record data values ​​in the cell. The magnetic moment of the free magnetic layer can be switched only by the spin-orbit torque or by an auxiliary magnetic field. There are three general types of SOT-MRAM, which depend on the orientation relationship between the magnetization of the free magnetic layer and the write current flowing through the SOT sensing structure. The x-type SOT-MRAM has a free magnetic layer moment parallel to the current passing through the SOT sensing structure and an auxiliary magnetic field orthogonal to the current plane in the SOT sensing structure. The y-type SOT-MRAM has a free magnetic layer moment that is perpendicular to (but in the same plane as) the current direction passing through the SOT sensing structure. The Z-type SOT-MRAM has a free magnetic layer moment orthogonal to the current plane passing through the SOT sensing structure and requires an auxiliary magnetic field parallel to the current.

[0023] Although the present disclosure generally relates to an x-type SOT-MRAM, certain aspects discussed herein can be transferred to other types of SOT-MRAM devices, as will be discussed below. In an x-type SOT-MRAM device, an auxiliary magnetic field for switching the free magnetic layer may be generated outside the cell, thereby complicating the cell structure. Embodiments of the present disclosure improve performance in several ways. In some embodiments of the present disclosure, a strained ferromagnetic SOT sensing structure is provided. The strained ferromagnetic SOT sensing structure not only provides a SOT current, but also provides a built-in perpendicular magnetic field, which is generated by its parallel magnetic anisotropy (PMA) and facilitates the switching of the free magnetic layer torque. In some of these embodiments, a strained ferromagnetic SOT sensing structure can be formed without a seed layer. In some embodiments of the present disclosure, a spacer layer can be provided between the MTJ film stack and the SOT sensing structure to adjust the magnetic coupling therebetween. Specially adjusting the thickness of the spacer layer is used to optimize the magnetic coupling strength between the perpendicular SOT sensing structure and the in-plane free magnetic layer to improve the write efficiency without affecting the read operation. The optimal coupling provides the ability to generate the orthogonal auxiliary magnetic field required to switch the magnetic moment of the free magnetic layer without the need for an external magnetic field, thereby simplifying the design and operation of the memory cell. These embodiments may also be combined in various combinations.

[0024] Figure 1 A SOT-MRAM cell 90 according to some embodiments of the present disclosure is shown (see Figure 2 ) is a schematic diagram of a SOT-MRAM functional element of a MTJ film stack 100. These elements may include a bottom electrode 5 and / or a buffer layer 7, a SOT sensing structure 10, and an MTJ film stack 100. It should be understood that these layers may include multiple sub-layers including different materials, which will be discussed in detail below. The SOT sensing structure 10 serves as a spin-orbit interaction active layer to provide a sensing influence on the MTJ film stack 100. The SOT sensing structure 10 is a vertical Hall metal (p-HM) structure and may be alternatively referred to as a p-HM structure 10.

[0025] The MTJ film stack 100 may also include various configurations. In some embodiments, such as Figure 1 As shown, a free layer 30 is disposed above the SOT sensing structure 10, a barrier layer 40 is disposed above the free layer 30, and a reference layer 50 is disposed above the barrier layer 40. In some embodiments, a magnetic coupling tuning spacer layer 20 (e.g., spacer layer 20A and / or spacer layer 20B) may be inserted between the SOT sensing structure 10 and the free layer 30. Other embodiments may use other arrangements for the MTJ film stack. For example, in some embodiments, Figure 1The structure of the MTJ film stack 100 may be inverted, including all layers of the MTJ film stack 100. As shown, the MTJ film stack 100 includes the pinning layer 60 and is "top pinned". In embodiments where the structure of the MTJ film stack 100 is inverted, the resulting film stack will be considered "bottom pinned". This will be discussed in further detail below.

[0026] refer to Figure 1 , using the spin-orbit torque effect to switch the magnetic moment of the free layer 30. In some embodiments, only the spin-orbit torque effect is used to switch the magnetic moment of the free layer 30. In other embodiments, a combination of effects is used to switch the magnetic moment of the free layer 30. For example, the magnetic moment of the free layer 30 is switched using the spin transfer torque as the main effect, which can be assisted by the spin-orbit torque effect. In other embodiments, the main switching mechanism is the spin-orbit torque effect. In such embodiments, another effect including but not limited to the spin transfer torque can assist in switching.

[0027] The SOT sensing structure 10 may be formed over the optional bottom electrode 5 and / or the optional buffer layer 7. The bottom electrode 5 may include one or more layers of Cu, W, Ta, TiN, TaN, Ru, Au, and aluminum. In some embodiments, the buffer layer may serve as a structural spacer layer of the above SOT sensing structure 10, i.e., separating the structure of the bottom electrode 5 from the structure of the SOT sensing structure 10. In some embodiments, the buffer layer may also serve as a seed layer for the SOT sensing structure 10. In some embodiments, the buffer layer 7 may include a thin deposited insulating material layer having tunneling capability, such as MgO deposited to a thickness between 2 angstroms and 9 angstroms.

[0028] As described above, the SOT sensing structure 10 is a spin-orbit active interface having a strong spin-orbit interaction and can be used to switch the magnetic moment of the free layer 30. The SOT sensing structure 10 is used to generate a spin-orbit magnetic field H z More specifically, the current Jc is driven in the plane through the SOT sensing structure 10. Since the SOT sensing structure 10 is a perpendicular Hall metal (p-HM), the spin-orbit magnetic field H z The spin-orbit magnetic field H is generated perpendicular to the direction of the current Jc. z = equal to the spin-orbit torque T during magnetization, where T in the free magnetic layer 30 = –γ[M×H z]. Therefore, the torque and magnetic field are interchangeably referred to as spin-orbit magnetic field and spin-orbit torque. This reflects the fact that the spin-orbit interaction is the origin of the spin-orbit torque and the spin-orbit magnetic field. For the current Jc driven in the plane in the SOT sensing structure 10 and the spin-orbit interaction, the spin-orbit torque occurs. In contrast, the spin transfer torque is due to the perpendicular plane current flowing through the free layer 30, the barrier layer 40 and the reference layer 50, which injects spin-polarized charge carriers into the free layer 30. T can cause the magnetic moment of the free layer 30 to deflect rapidly from the equilibrium state parallel to the easy axis. The spin-orbit torque T can tilt the magnetization of the free layer 30 much faster than a conventional STT torque with a similar maximum amplitude. In some embodiments, the switching can be accomplished using the spin-orbit torque. In other embodiments, the switching can be accomplished using another mechanism such as the spin transfer torque. Therefore, the generated spin-orbit magnetic field / spin-orbit torque can be used to switch the magnetic moment of the free layer 30.

[0029] The SOT sensing structure 10 includes multiple layers, as shown by the dotted lines. As described above, Figure 1 The SOT sensing structure 10 is a p-HM, or in other words has a perpendicular magnetic anisotropy (PMA) to the plane. Figure 3A and Figure 3B The construction and materials of the SOT sensing structure 10 are discussed in more detail.

[0030] Some embodiments utilize a strained SOT sensing structure 10 that provides high PMA and high spin Hall angle (SHA) without requiring a thick (e.g., between 1 nm and 10 nm) heavy metal seed layer (e.g., tantalum). A heavy metal seed layer can be used to achieve high PMA, which typically dilutes the SHA. In other words, a thicker heavy metal seed layer provides a current shunt path without the impact of SHA. Therefore, if a high PMA can be maintained, eliminating the use of a heavy metal seed layer or reducing the thickness of the heavy metal seed layer is beneficial to increasing the SHA. High PMA and high SHA are beneficial to switching efficiency, thereby reducing the write current when switching the free layer.

[0031] As described above, the SOT sensing structure 10 uses Hall metal so that the interaction of the SOT sensing structure 10 includes the spin Hall effect. For the spin Hall effect, the current Jc is driven in the plane of the SOT sensing structure 10 (i.e., the current in the plane, substantially in Figure 1 In other words, perpendicular to the stacking direction of the films including the SOT sensing structure 10 and the free layer 30 (ie, perpendicular to the normal line of the surface, Figure 1The charge carriers with spins in a specific direction perpendicular to the current direction and perpendicular to the surface normal (z direction) are accumulated on the surface of the SOT sensing structure 10. This diffusion causes a torque T on the magnetization of the free layer 30. As described above, since the torque on the magnetization is equal to the effective magnetic field on the magnetization, the spin accumulation equivalently causes a magnetic field H on the free layer 30. z The spin-orbit magnetic field of the spin Hall effect is the cross product of the spin-orbit polarization and the magnetic moment of the free layer 30. Therefore, the magnitude of the torque is proportional to the in-plane current density Jc and the spin polarization of the carriers. When the polarization caused by the spin Hall effect is parallel to the easy axis of the free layer 30, the spin Hall effect can be used to switch Figure 1 The magnetic stack is shown. A current pulse is driven in-plane through the SOT sensing structure 10. The resulting spin-orbit torque T counteracts the damping torque, which causes the magnetization of the free layer 30 to switch in a manner similar to conventional STT switching.

[0032] The free layer 30 is a data storage layer with a switchable magnetic moment. Within the MTJ film stack 100 of the SOT-MRAM cell 90, the free layer 30 serves as a state holding layer, and its magnetic state determines the state of the SOT-MRAM cell 90. The layer 30 is controllable (e.g., by controlling the current flowing in the SOT sensing structure 10), and by controlling the magnetic moment of the free layer 30 in this manner, the resistance of the SOT-MRAM cell 90 can be set to a high resistance state or a low resistance state. Whether the SOT-MRAM cell 90 is in a high resistance state or a low resistance state depends on the relative orientation of the magnetization of the free layer 30 and the reference layer 50 (see below for more details about the reference layer 50).

[0033] The free layer 30 may be formed of one or more ferromagnetic materials, such as cobalt iron boron (CoFeB), cobalt / palladium (CoPd), cobalt iron (CoFe), cobalt iron boron tungsten (CoFeBW), nickel iron (NiFe), Ru, Co, alloys thereof, the like, or combinations thereof. The free layer 30 may include multiple layers of different materials, such as a Ru layer between two layers of CoFeB, a Co layer between two layers of CoFeB, or a Ru layer and a Co layer between two layers of CoFeB, and other configurations of layers or materials may be used. In some embodiments, the material of the free layer 30 includes a crystalline material deposited to have a specific crystal orientation [e.g., (100) orientation). The total thickness of the free layer 30 may be between about 1 nm and about 4 nm. Embodiments utilize a free layer 30 having in-plane magnetic anisotropy (IMA). The appropriate thickness of the free layer 30 may be determined by the composition of the free layer 30 or the magnetism of the free layer 30.

[0034] In some embodiments, the barrier layer 40 is formed of one or more materials, such as magnesium oxide and aluminum oxide, or a combination thereof. In some embodiments, the material of the barrier layer 40 includes a crystalline material deposited to have a specific crystal orientation [e.g., (100) orientation). The material of the barrier layer 40 can be deposited to have the same crystal orientation as the free layer 30. In some embodiments, the barrier layer 40 can have a thickness between about 0.3nm and about 3nm. In some cases, controlling the thickness of the barrier layer 40 can help control the resistance (RMTJ) of the MTJ film stack 100. For example, a thicker barrier layer 40 can increase the resistance of the MTJ film stack 100. By controlling the resistance RMTJ of the MTJ film stack 100 to match the parasitic resistance of the circuit connected to the SOT-MRAM cell 90, the performance of the SOT-MRAM cell 90 can be improved. In some cases, matching the resistance in this way can increase the range of operating conditions under which the SOT-MRAM cell 90 can be read. The barrier layer 40 can be thin enough so that electrons can tunnel through the barrier layer 40.

[0035] The reference layer 50 is a second magnetic layer whose magnetic moment is unchanged. The reference layer 50 can be made of any material that is the same as the free layer 30 described above, and can have the same material composition as the free layer 30. In some embodiments, the reference layer 50 includes one or more layers of magnetic material. In some embodiments, the reference layer 50 includes a layer of a combination of cobalt (Co), iron (Fe), and boron (B), such as Co, Fe, and B; iron and boron; cobalt and iron; Co; and so on. In some embodiments, the material of the reference layer 50 includes a crystalline material deposited to have a specific crystal orientation [e.g., a (100) orientation). The material of the reference layer 50 can be deposited to have the same crystal orientation as the barrier layer 40. In some embodiments, the thickness of the reference layer 50 is in the range of about 0.2 nm to about 8 nm.

[0036] The pinned layer 60 is a hard bias layer for pinning the spin polarization direction of the reference layer 50 in a fixed direction. The spin polarization direction of the fixed reference layer 50 can switch the SOT-MRAM cell between a low resistance state and a high resistance state by changing the spin polarization direction of the free layer 30 relative to the reference layer 50. If the pinned layer 60 is formed above the reference layer 50, then Figure 1 The example MTJ film stack 100 shown can be considered a "top pinned" MTJ stack. However, in some embodiments, the order of the layers of the MTJ film stack 100 can be reversed. In such embodiments, because the reference layer 50 will be formed above the pinned layer 60, such an MTJ film stack can be considered a "bottom pinned" MTJ stack.

[0037] In some embodiments, the pinned layer 60 may include multiple layers of different materials and may be referred to as a synthetic antiferromagnetic (SAF) layer. For example, the pinned layer 60 may include a stack of one or more ferromagnetic layers and one or more non-ferromagnetic layers. For example, the pinned layer 60 may be formed by a non-ferromagnetic layer sandwiched between two ferromagnetic layers, or may be a stack of alternating non-ferromagnetic layers and ferromagnetic layers. The ferromagnetic layer may be formed by materials such as Co, Fe, Ni, CoFe, NiFe, CoFeB, CoFeBW, alloys thereof, or a combination thereof. The non-ferromagnetic layer may be formed by materials such as Cu, Ru, Ir, Pt, W, Ta, Mg, or a combination thereof. In some embodiments, one or more ferromagnetic layers of the pinned layer 60 may have a thickness between about 2 nm and about 5 nm. In some embodiments, a thicker pinned layer 60 may have stronger antiferromagnetic properties, or may be more sturdy against external magnetic fields or thermal fluctuations. In some embodiments, the thickness of the non-ferromagnetic layer of the pinned layer 60 may be between about 2 angstroms and about 10 angstroms. For example, the pinned layer 60 may include a Ru layer having a thickness between about 4 angstroms and about 8.5 angstroms, but other layers or thicknesses are possible. In some embodiments, one or more layers of the pinned layer 60 include a crystalline material deposited to have a specific crystal orientation, such as a (111) orientation. The pinned layer 60 may be formed to have an in-plane magnetic anisotropy (IMA), i.e., in the same plane as the horizontal direction of the pinned layer 60. In some embodiments, the total thickness of the pinned layer 60 is in the range of about 3 nm to 25 nm.

[0038] In some embodiments, the pinned layer 60 may include an antiferromagnetic material (AFM) layer, such as PtMn or IrMn, to provide a strong exchange bias to fix the pinned layer. This forms a "spin valve structure" and provides better stability of the pinned layer. Without the AFM layer, the stability of the pinned layer 60 is poor and can be called a "pseudo spin valve".

[0039] The cap layer 70 may be a single layer or multilayer structure, which is used to protect the layer below the cap layer 70 during subsequent processes and to provide a top electrode for the via or metal wire connection for coverage. The layer may be formed of a non-ferromagnetic material, such as Cu, Ru, Ir, Pt, W, Ta, Mg, Ti, TaN, TiN, etc. or a combination thereof. In some embodiments, the cap layer 70 may include two non-ferromagnetic material layers sandwiching another non-ferromagnetic material layer, such as another one of Cu, Ru, Ir, Pt, W, Ta, Mg, Ti, TaN, TiN or the like. For example, in some embodiments, the cap layer may include Ta or Ti sandwiched between two layers of Ru. The thickness of the cap layer 70 may be between about 3nm and about 25nm, but other thicknesses may be considered. In an embodiment using multiple layers as the cap layer 70, each layer may be between about 1nm and about 12nm.

[0040] A top electrode 75 may be disposed on the cap layer 70. The top electrode 75 may be used to provide electrical connection to a conductive pattern coupled to the top of the MTJ film stack 100. Any suitable material, such as titanium, titanium nitride, tantalum, tantalum nitride, etc. or a combination thereof.

[0041] In some embodiments, a spacer layer 20 (e.g., spacer layer 20A and / or spacer layer 20B) is disposed between the free layer 30 and the SOT sensing structure 10. The spacer layer 20 relaxes the exchange coupling between the SOT sensing structure 10 and the free layer 30. Since the SOT sensing structure 10 has PMA (perpendicular magnetic anisotropy) and the free layer 30 has IMA (in-plane magnetic anisotropy), the spacer layer 20 is used to adjust the exchange coupling between the SOT sensing structure 10 and the free layer 30 so that they can maintain their specific magnetic anisotropy without harmful coupling effects between the two. Optimal coupling allows the field Hz to be generated internally to assist the switching of the free layer 30 during a write operation. The ferromagnetic SOT sensing structure 10 with PMA enhances the spin Hall angle (SHA), thereby reducing the write current.

[0042] The spacer layer 20 may be formed of a metal material or a dielectric material such as a metal oxide. In the case where the spacer layer 20 is formed of a metal material, the spacer layer 20 may be formed of a metal material such as a non-ferromagnetic metal material such as W, Ru, Pt, Mo, Ti, Mg, etc., or a combination thereof. In the case where the spacer layer 20 is formed of a dielectric material, the spacer layer 20 may be formed of a dielectric material such as magnesium oxide (MgOx), cobalt oxide (CoOx), aluminum oxide (AlOx), etc., or a combination thereof. In some embodiments, the spacer layer 20 may be formed of multiple layers, each of which may be a different material, including a metal material and / or a dielectric material. In some embodiments, the spacer layer 20A may be formed and patterned together with the SOT sensing structure 10, and may have a footprint similar to that of the SOT sensing structure 10. In some embodiments, when the MTJ film stack 100 is patterned, the spacer layer 20B may be patterned so that the spacer layer 20B may have a footprint similar to that of the MTJ film stack 100. In some embodiments, the spacer layer 20A and the spacer layer 20B may exist at the same time.

[0043] The total thickness of the spacer layer 20 (including the spacer layer 20A and the spacer layer 20B) depends on the materials of the free layer 30 and the SOT sensing structure 10. The spacer layer 20 needs to have a certain minimum thickness. By reducing the minimum thickness required for the exchange coupling of the free layer 30 and the SOT sensing structure 10, the maximum thickness of the spacer layer 20 is determined by the SOT effect. If the free layer 30 and the SOT sensing structure 10 are too far apart, the SOT effect will be weakened, thereby reducing the SOT efficiency (spin Hall angle) and affecting the magnetoresistance. Similarly, in the case where the spacer layer 20 is a dielectric material, the thickness of the spacer layer 20 affects the resistance of the MTJ film stack 100. Depends on the materials selected for the spacer layer 20, the free layer 30 and the SOT sensing structure 10. The total thickness of the spacer layer 20 can be between about 2 angstroms and about 13 angstroms. In some embodiments, such as when the spacer layer 20 is made of magnesium oxide, the total thickness of the spacer layer 20 can be between about 6.5 angstroms and about 8.5 angstroms. In other embodiments, such as when the spacer layer 20 is made of magnesium, the total thickness of the spacer layer 20 may be between about 10 angstroms and about 13 angstroms. In other embodiments, such as when the spacer layer 20 is made of titanium, the total thickness of the spacer layer 20 may be between about 6.5 angstroms and about 10 angstroms. In other embodiments, such as when the spacer layer 20 is made of tungsten, the total thickness of the spacer layer 20 may be between about 5 angstroms and about 10 angstroms.

[0044] Figure 2 FIG. 9 is a simplified schematic diagram of a SOT-MRAM cell 90 according to an embodiment of the present disclosure. Figure 1 The materials, configurations, dimensions, processes, and / or operations described herein are described using similar references, and detailed descriptions thereof may be omitted.

[0045] In some embodiments, one end of the SOT sensing structure 10 is coupled to a switching device [e.g., a field effect transistor (FET)], referred to herein as FET110. In some embodiments, the SOT sensing structure 10 is coupled to the drain (or source) of FET 110 (or FET1) through one or more conductive patterns (e.g., vias, wirings, wires, and / or pads), and the gate of the FET is coupled to the word line WL1 120 through one or more conductive patterns. The source (or drain) of FET1 is coupled to the source line SL1 125 through one or more conductive patterns. The other end of the SOT sensing structure 10 is coupled to another switching device [e.g., a field effect transistor (FET)], also referred to herein as FET 110 (or FET2). In some embodiments, the SOT sensing structure 10 is coupled to the drain (or source) of FET2 through one or more conductive patterns, and the gate of FET2 is coupled to the world line WL2 120 through one or more conductive patterns. The source (or drain) of FET2 is coupled to the source line SL2 125 through one or more conductive patterns.

[0046] In some embodiments, the MTJ film stack 100 is disposed above the SOT sensing structure 10 along a vertical direction (film stacking direction) (Z direction). In some embodiments, a spacer layer 20 is disposed between the MTJ film stack 100 and the SOT sensing structure 10. The bit line 160 is electrically coupled to the top of the MTJ film stack 100 through one or more conductive patterns.

[0047] In some embodiments, the MTJ film stack 100 may be inverted and the SOT sensing structure 10 may be disposed above the MTJ film stack 100. In such embodiments, the cap layer 70 may be omitted and the top electrode 75 (see Figure 1 ) can become the bottom electrode 5, and the bottom electrode 5 can become the top electrode 75. The free layer 30 of the MTJ film stack 100 can be disposed on top of the inverted MTJ film stack 100. Embodiments using the spacer layer 20 can have the spacer layer arranged between the SOT sensing structure 10 and the MTJ film stack 100. Also in such embodiments, the wiring arrangement can remain the same, and the drain (or source) of FET1FET 110 is coupled to one end of FET 1 FET 110. The drain (or source) of the SOT sensing structure 10 and FET2 FET 110 is coupled to the other end of the SOT sensing structure through a conductive pattern. Similarly, the bit line 160 can be coupled to the current bottom of the MTJ film stack 100 through one or more conductive patterns. Changes in these aspects will be discussed below in conjunction with the various figures.

[0048] Use as Figure 2 With the arrangement of elements shown, the SOT-MRAM cell 90 can implement an x-type storage element without using an external auxiliary field to switch the free layer 30. In addition, by using the SOT-MRAM cell 90 instead of the STT-MRAM cell, the power requirements are smaller, so that the transistor size of the FET 110 (FET1 and FET2) can also be reduced. In some embodiments, the area of ​​the SOT-MRAM device can be about 50% to 75% of the area of ​​a similar SRAM device, and is about the same as the area of ​​the STT-MRAM device, while requiring less power, thereby providing faster switching, and longer life (increased number of switching cycles).

[0049] If the word line WL1 120 is positively biased and the word line WL2 120 is positively biased, the gates of the FETs 110 (FET1 and FET2) will be turned on. Then, the current Jc can flow through the SOT sensing structure 10 in one direction, thereby inducing the free layer 30 to change the magnetization direction. If the current direction is reversed, the current Jc can flow through the SOT sensing structure 10 in the opposite direction, thereby causing the free layer 30 to change the magnetization intensity in the opposite direction. However, if any of the transistors FETs 110 (FET1 or FET2) is not turned on, the current will not flow through the SOT sensing structure 10, and a read operation can be performed through the MTJ film stack 100 at the bit line 160. The read and write operations will be combined below. Fig.18 Discuss in detail.

[0050] Figure 3A and Figure 3B A SOT sensing structure 10 according to various embodiments is shown. The SOT sensing structure 10 is a spin-orbit active layer that induces a strong spin-orbit interaction with the free layer 30. Figure 3A and Figure 3B In the embodiment, the SOT sensing structure 10 is a strained ferromagnetic structure with perpendicular magnetic anisotropy (PMA). As described above, the strained SOT sensing structure 10 is advantageous for improving the SOT switching efficiency by achieving both high perpendicular-to-plane magnetic anisotropy (PMA) and high spin Hall angle (SHA) without using a thick heavy metal seed layer.

[0051] exist Figure 3A , the SOT sensing structure 10 includes alternating metal layer pairs 14. These metal layer pairs 14 are stacked to form the SOT sensing structure 10. The first metal layer 14A may be made of a non-ferromagnetic metal, such as platinum or palladium, and the second metal layer 14B may be made of a ferromagnetic metal such as cobalt. The first metal layer 14A may have a thickness between 1 nm and 2 nm, and the second metal layer 14B may have a thickness between 0.01 nm and 0.7 nm. Other thicknesses may be considered and may be used. The metal layer pairs 14 are formed in a repeated cycle to form a SOT sensing structure 10 having multiple sets of metal layer pairs 14. The SOT sensing structure 10 may include two or more of these metal layer pairs 14, such as between 2 and 8 metal layer pairs 14, such as 3 to 6 metal layer pairs 14.

[0052] By increasing the ratio of the thickness of the first metal layer 14A to the thickness of the second metal layer 14B and increasing the number of cycles of the metal layer pair 14, the effective perpendicular plane magnetic anisotropy (PMA) of the SOT sensing structure 10 can be increased. Due to the high lattice mismatch between the metal of the first metal layer 14A and the metal of the second metal layer 14B, the high elastic strain between the first metal layer 14A and the second metal layer 14B increases the PMA. For example, the lattice mismatch between the first metal layer 14A and the second metal layer 14B can be between about 6% and about 10%. The additional cycles of the metal layer pair 14 increase the strain in the SOT sensing structure 10 and provide a high PMA, similar to the high PMA provided by the heavy metal seed layer (which can be omitted). Similarly, a high ratio of the thickness of the first metal layer 14A to the thickness of the second metal layer 14B increases the strain and PMA. The ratio can be between about 2 and 20 in some embodiments and between about 3 and 10 in other embodiments.

[0053] The magnetic level associated with PMA can be characterized by the magnetization intensity (coercive force, Hc) or the degree of magnetization (saturation magnetization, Ms) of the SOT sensing structure 10. In some embodiments, the coercive force can be between 200Oe and 1000Oe, for example, between about 300Oe and 600Oe. The magnetic level associated with PMA can also be characterized by the ratio Mr / Ms of the residual magnetization Mr under zero applied magnetic field and the saturation magnetization Ms under a saturation magnetic field (e.g., 10000Oe). In some embodiments, the Mr / Ms ratio can be greater than about 0.30, for example, between about 0.30 and 0.90 or between about 0.60 and 0.80, indicating a strong PMA.

[0054] The SOT sensing structure 10 may be formed by depositing the metal material of the first metal layer 14A using a blanket deposition technique including any suitable deposition technique (e.g., CVD, PVD, ALD, etc.) or a combination thereof. Next, the metal material of the second metal layer 14B may be deposited using a blanket deposition technique including any of the same deposition techniques used to deposit the first metal layer 14A.

[0055] After the cycle of depositing the metal layer pair 14, the total thickness of the SOT sensing structure 10 can be between about 2 nm and about 25 nm, such as between about 3 nm and 18 nm, such as about 5 nm, although other values ​​are contemplated. In some embodiments, after the cycle of depositing the metal layer pair 14, a spacer layer 20 (e.g., Figure 1 The SOT sensing structure 10 may be patterned into a final shape in a subsequent step, or may be patterned into its final shape at this point (before forming any MTJ film stack 100).

[0056] After the cycle of depositing the metal layer pair 14, an anneal may be performed. The post-deposition anneal provides upward diffusion in the metal layer pair 14 and further increases the PMA of the SOT sensing structure 10. The post-anneal may be performed at a temperature between about 300°C and about 400°C for a time of 0.5 hours to 3 hours. In some embodiments, due to the crystal anisotropy of the metal layer pair 14, an in-situ perpendicular magnetic field (out of plane) may be applied during the post-anneal to further increase the PMA. The magnetic field may be between about 1 Tesla and 5 Tesla. During the anneal. In some embodiments, the use of an in-situ perpendicular field during the anneal may transform the SOT sensing structure 10 from a superparamagnetic (neither in-plane nor vertical) to having a primarily perpendicular magnetic anisotropy. In some embodiments, the SOT sensing structure 10 may have partial in-plane and partial perpendicular anisotropy after formation, and the use of an in-situ perpendicular field during the anneal may increase the perpendicular magnetic properties by about 10% to 50%, so that the SOT sensing structure 10 has a primarily perpendicular magnetic anisotropy after annealing. The post-deposition annealing may be performed immediately after the metal layer pair 14 is deposited for the SOT sensing structure 10 , or may be performed in a subsequent process, for example, after the MTJ film stack 100 layers are formed.

[0057] Figure 3B Similar to Figure 3A , wherein like reference numerals refer to like elements. Figure 3B The SOT sensing structure 10 in FIG. 1 includes a base metal layer 12. The base metal layer 12 provides similar functionality to the SOT sensing structure 10 because the high thickness of each layer of the metal layer pair 14 discussed above is utilized. Figure 3A Utilizing the base metal layer 12 allows for greater flexibility in depositing the metal layer pair 14 while maintaining a high PMA for the SOT sensing structure 10. In some embodiments, the base metal layer 12 can be the same material as the metal of the first metal layer 14A. Essentially, the metal of the first metal layer 14A can be made thicker for the first cycle than for subsequent cycles. In other embodiments, the base metal layer 12 can be a different material than the metal of the first metal layer 14A. For example, the metal of the first metal layer 14A can be platinum and the metal of the base metal layer 12 can be palladium, or vice versa.

[0058] The thickness of the first metal layer 14A and the thickness of the second metal layer 14B may each be between about 0.01 nm and 2 nm, and the thickness of the base metal layer 12 may be between 2 nm and 5 nm. Due to the presence of the base metal layer 12, the thickness of the first metal layer 14A and the thickness of the second metal layer 14B can be equal and still achieve high PMA and SHA. Figure 3AIn contrast to the arrangement shown, the thickness ratio of the first metal layer 14A to the second metal layer 14B is not as critical to maintaining a high PMA. For example, in some embodiments, even when the thickness of the first metal layer 14A is the same as the thickness of the second metal layer 14B, the PMA of the SOT sensing structure 10 deposited using the base metal layer 12 can be about 30% to about 60% higher than the PMA without the base metal layer 12.

[0059] Figure 3B The base metal layer 12, the first metal layer 14A and the second metal layer 14B can be used as described above. Figure 3A The in-situ vertical field during annealing can be deposited and annealed using similar processes and materials as those discussed above. Figure 3B The PMA of the SOT sensing structure increases from about 10% to about 40%.

[0060] Figure 4 , Fig.14 and Fig.15 are schematic cross-sectional views of portions of a SOT-MRAM device according to various embodiments. Certain aspects of the illustrated layers of the SOT-MRAM device may be flattened into these cross-sectional views, and it should be understood that certain features depicted may actually exist in other cross-sections. Fig.16 yes Figure 4 , Fig.14 and Fig.15 A three-dimensional diagram of the SOT-MRAM device shown. Fig.17 is with Figure 4 , Fig.14 and Fig.15 Circuit diagrams consistent with those embodiments shown.

[0061] In the following embodiments, the Figure 1 , Figure 2 , Figure 3A and Figure 3B The materials, configurations, dimensions, processes and / or operations described herein may be omitted, and detailed descriptions thereof may be omitted. Figure 4 , Fig.14 and Fig.15In some embodiments, the SOT-MRAM device includes a layered structure having a multi-wiring layer structure. In some embodiments, the multi-layer wiring layer structure includes "Mx" (x = 0, 1, 2, 3, ...) metal wiring layers, which are located at various levels arranged above the substrate; and "Vy" (y = 0, 1, 2, 3, ...) vias (contacts) connect the My metal wiring layer to the My+1 metal wiring layer. The metal wiring layer includes a metal wire embedded in a dielectric material layer. The via includes a conductive plug embedded in an interlayer dielectric (ILD) material that separates adjacent metal wiring layers. For the purpose of illustration and labeling, elements ending with "A" correspond to the level of x = 0, y = 0, elements ending with "B" correspond to the level of x = 1, y = 1, and elements ending with "C" correspond to the level of x = 3, y = 3, and so on. In some embodiments, the even-numbered metal wiring layers extend in one direction (e.g., X), and the odd-numbered metal wiring layers extend in another direction (e.g., Y) that intersects one direction. In some embodiments, the spacing of the metal wiring can generally increase with the increase of the level. For example, the metal wiring pitch in levels M3 and M4 may be the same, and the pitch for metal wiring in M5 or higher levels may be the same and may be greater than the pitch for metal wiring in M3 and M4.

[0062] In some embodiments, the metal wiring and the via are made of one or more of aluminum, cobalt, copper, copper alloys, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof, etc., or combinations thereof. The via may also include a barrier layer or an adhesion material layer surrounding the sides of the via and formed of one or more layers of titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, ruthenium, rhodium, platinum, other precious metals, other refractory metals, nitrides thereof, combinations thereof, etc.

[0063] In some embodiments, the ILD layer is formed of any suitable dielectric material, including, for example, nitrides (such as silicon nitride), oxides (such as silicon oxide, SiOC and SiOCN), SiCN, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., or combinations thereof.

[0064] The contact plug 118 connects the source region 112S or the drain region 112D of the FET 110 to the M0 metal wiring layer (e.g., the conductive line 130A) through the dielectric layer 104. The source line SL1 125 is in the M0 metal wiring layer 110 and is coupled to the source region 112S of the FET 110FET1. The source line SL2 125 is in the M0 metal wiring layer and is coupled to the source region 112S of the FET 110FET2. The drain region 112D of the FET 110FET1 is coupled to one end of the SOT sensing structure 10. The drain region 112D of the FET 110FET2 is coupled to the other end of the SOT sensing structure 10. The bit line BL 160 is coupled to the top of the MTJ film stack 100 in the upper MJ metal stack 100. The word line WL1 is coupled to the gate electrode of the FET 110FET1, and the word line WL2 is coupled to the gate electrode of the FET 110FET2.

[0065] It should also be understood that Figure 4 The schematic diagram in is merely an illustration of one embodiment and may be changed without departing from the spirit of the present disclosure. For example, it should be understood that multiple intermediate layers may be included as needed to accommodate any desired wiring layout. In particular, when a particular element is described as being in a particular metal wiring layer, the present disclosure contemplates that any desired number of metal wiring layers may be inserted between the described metal wiring layers. For example, where one element is described as being in an M2 metal wiring layer and another element is described as being in an M3 metal wiring layer, there may be any number of metal wiring layers between the M2 metal wiring layer and the M3 metal wiring. In addition, as described above, the MTJ film stack 100 may be formed such that the SOT sensing structure 10 is disposed above the MTJ film stack 100.

[0066] In some embodiments, FET 110 is a planar FET, a fin FET, or a gate-all-around FET. Electrode 80 is coupled to drain region 112D of FET 110, and source region 112S of FET 110 is coupled to source line SL125. In some embodiments, source region 112S is shared by two adjacent FETs 110 (see Fig.15 In some embodiments, a pair of FETs 110 (FET1 and FET2) is connected by a dummy gate structure 121 to another pair of FETs 110 (e.g., Figure 4 The word line WL 120 is coupled to the gate of the FET 110 and switches whether current can flow from the source line SL 125 through the MTJ film stack 100 to the bit line BL 160.

[0067] Reference Figure 4, two SOT-MRAM cells 90 of the SOT-MRAM device 300 are shown, including MC1 and MC2. Figure 4 As shown, the source regions 112S of adjacent SOT-MRAM cells 90 may be separated by a dummy gate structure 121, similar to the separation of the drain regions 112D of the FETs 110 (FET1 and FET2) by the dummy gate structure 121. In some embodiments, two adjacent SOT-MRAM cells 90 may share a common source region 112S (e.g., see Fig.15 ).

[0068] The SOT sensing structure 10 may be disposed in the M1 metal wiring layer and may be coupled to the drain region 112D (or source region 112S) of each FET 110 of MC1. The MTJ film stack 100 may be disposed on the SOT sensing structure 10 in the V1 layer, for example, in the bottom V1A of the V1 layer. The via 126B may connect the top of the MTJ film stack 100 to the bit line BL signal 160 in the M2 metal wiring layer. The source line SL1 and the source line SL2 may be disposed in the M0 metal wiring layer and may be coupled to the source region 112S (or drain region) of each FET 110 (FET1 and FET2, respectively). The word line WL1 and the word line WL2 are respectively connected to the gate electrode of each FET 110 (FET1 and FET2, respectively). These connections may enter the metal wiring layer through vias and wiring patterns in another cross section. As shown in FIG. Figure 4 As shown, the source lines (eg, SL1 and SL2 ) are respectively directed in the Y direction and have a small cross section along the X direction.

[0069] In some embodiments, the MTJ film stack 100 , the SOT sense wiring structure 10 , the source lines 125 ( SL1 and SL2 ), and the bit lines BL 160 may each be shifted down a metal wiring layer or shifted up one or more metal wiring layers.

[0070] Figures 5 to 14 Shows Figure 4 The SOT-MRAM device 300 is an intermediate step in the formation of the SOT-MRAM device 300. Materials that can be used to form various structures and elements of the SOT-MRAM device 300 have been described above and will not be repeated herein.

[0071] Figure 5 1 shows a cross-sectional view of a substrate 102 and a plurality of FETs 110 formed on the substrate 102 according to some embodiments. The FETs 110 are part of a subsequently formed SOT-MRAM cell 90 of the SOT-MRAM device 300. Figure 5Some exemplary FETs 110 are shown in FIG. 1 . The substrate 102 may be a semiconductor substrate, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0072] In some embodiments, FET 110 is a fin field effect transistor (FinFET) including a fin (or channel region) 116, a gate structure 114, and a source region 112S and a drain region 112D. Figure 5 As shown, the fin 116 is formed on the substrate 102 and may include the same material as the substrate 102 or a different material. In some embodiments, a dummy fin (not shown) may be formed between some of the fins 116 to improve process uniformity. The gate structure 114 is formed on a plurality of fins 116 and extends in a direction perpendicular to the fins 116. In some embodiments, a spacer (not shown) may be provided on the sidewall of the gate structure 114. The gate structure 121 may be formed between some of the gate structures 114 to improve process uniformity. In some embodiments, the dummy gate structure 121 may be considered a "dummy transistor" or a "dummy FinFET". Some gate structures 114 are used as word lines in the SOT-MRAM device 300 (described in more detail below) and are labeled "WL" accordingly, such as "WL2". The source region 112S and the drain region 112D are formed in the fin 116 on either side of the gate structure 114. The source region 112S and the drain region 112D may be, for example, an implanted region of the fin 116 or an epitaxial material grown therein. exist Figure 5 In the illustrated embodiment, one side of each fin 116 is adjacent to the source region 112S, and the other side of each fin 116 is adjacent to the drain region 112D.

[0073] The FET 110 shown in the figure is representative, and some components of the FET 110 may have been omitted from the figure for clarity. In other embodiments, the arrangement, configuration, size or shape of components such as the fin 116, the dummy fin, the gate structure 114, the dummy gate structure 21, the source region 112S, the drain region 112D or other components may be different from that shown. In other embodiments, the FET 110 may be another type of transistor, such as a planar transistor.

[0074] exist Figure 6In some embodiments, dielectric layer 104 is formed over substrate 102 and patterned to expose source region 112S and drain region 112D. Dielectric layer 104 may cover FET 110 and may be considered an interlayer dielectric (ILD) in some embodiments. Dielectric layer 104 may be formed of any suitable dielectric material, including, for example, any of the materials listed above for ILD. Dielectric layer 104 may be formed using any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. or a combination thereof. In some embodiments, dielectric layer 104 may be a low-k dielectric material, for example, a dielectric material having a dielectric constant (k value) less than about 3.0.

[0075] The dielectric layer 104 may be patterned to form an opening 106 that exposes the source region 112S and the drain region 112D so that a contact plug 118 (see FIG. 3 ) may be subsequently formed. The dielectric layer 104 may be patterned using appropriate photolithography and etching processes. For example, a photoresist structure (not shown) may be formed on the dielectric layer 104 and patterned. The opening 106 may be formed by etching the dielectric layer 104 using the patterned photoresist structure as an etching mask. The dielectric layer 104 may be etched using an appropriate etching process, such as a wet etching process or a dry etching process.

[0076] Go to Figure 7 According to some embodiments, contact plugs 118 are formed to form electrical connections with source region 112S and drain region 112D. In some embodiments, contact plugs 118 are formed by depositing a barrier layer (not shown separately) extending into opening 106, depositing a conductive material over the barrier layer, and performing a planarization process or a grinding process such as a chemical mechanical polishing (CMP) process to remove excess portions covering the conductive barrier layer and the conductive material. The barrier layer or the conductive material of contact plug 118 may be formed using a suitable process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, etc. If a barrier layer is used, the barrier layer may be formed of any suitable material, such as TiN, Ti, TaN, Ta, etc., or a combination thereof.

[0077] Go to Figure 8 , forming a conductive line 130A to electrically connect the contact plug 118 and provide electrical wiring within the SOT-MRAM device. The conductive line 130A may be formed in a dielectric layer 128A formed above the dielectric layer 104. The dielectric layer 128A may be similar to the above for the dielectric layer 104 (see Figure 6 ) and can be deposited using similar methods. In some embodiments, dielectric layer 128A can be considered an inter-metal dielectric layer (IMD).

[0078] The conductive line 130A may be formed using a suitable technique such as damascene, dual damascene, electroplating, deposition, or the like, or a combination thereof. In some embodiments, the conductive line 130A is formed by first depositing a dielectric layer 128A and patterning the dielectric layer 128A to form an opening (e.g., using a suitable photolithography and etching process), and then filling the opening in the dielectric layer 128A with a conductive material. For example, the conductive line 130A may be formed by depositing an optional blanket barrier layer (not separately shown) on the patterned dielectric layer 128A, depositing a conductive material on top of the blanket barrier layer, and performing a planarization process such as a CMP process. A grinding process is performed to remove excess portions covering the conductive barrier layer and the conductive material. The barrier layer or the conductive material may be similar to that described above for the contact plug 118 (see Figure 7 ) and can be deposited using similar techniques. In some embodiments, for example, if a dual damascene process is used to form the contact plug 118 and the conductive line 130A, the conductive materials of the contact plug 118 and the conductive line 130A can be deposited in the same step.

[0079] In some embodiments, conductive line 130A is formed by first depositing an optional blanket barrier layer on dielectric layer 104 and contact plug 118, depositing a conductive material over the blanket barrier layer, and then patterning the barrier layer and the conductive material (e.g., using appropriate photolithography and etching processes) to form conductive line 130A. Dielectric layer 128A may be deposited on conductive line 130A, and a planarization process may be performed to expose conductive line 130A.

[0080] exist Fig. 9 In some embodiments, vias 126A are formed in dielectric layer 124A to form electrical connections with conductive line 130A. In some embodiments, dielectric layer 124A is first formed over conductive line 130A and dielectric layer 128A. Dielectric layer 124A may be a material similar to that described above for dielectric layer 104, and vias 126A may be formed using processes and materials similar to those described above for contact plug 118. The above steps are repeated to form the desired number of metal wiring layers.

[0081] In some embodiments, the via 126A formed under the SOT sensing structure 10 may be formed of copper, tungsten, or titanium nitride using a single damascene process and may serve as the bottom electrode 5 of the SOT sensing structure 10 (see Figure 1 As discussed above with respect to the contact plug 118, an optional barrier layer may also be used to prevent the material of the contact plug 118 from diffusing into the surrounding dielectric layer 124A.

[0082] like Fig. 9As shown, after forming the via 126A, the film stack of the SOT sensing structure 10 can be deposited. As described above, in some embodiments, the via 126A can be used as the bottom electrode 5. In some embodiments, a buffer layer 7 can be formed over the via 126A using any suitable process alone or in conjunction with the SOT sensing structure 10. In embodiments utilizing a buffer layer, the buffer layer can include magnesium oxide, etc., deposited to a thickness between about 0.2 and 0.9 nm. The bottom electrode 5 can be formed using the techniques discussed above with respect to the formation of the conductive line 130A.

[0083] After forming the buffer layer 7 (if used), the SOT sensing structure 10 film stack can be deposited. Figure 3A and Figure 3B The SOT sensing structure 10 is formed using processes and materials such as those discussed above. Figure 3A and 3B With the processes and materials discussed above, a spacer layer 20 is deposited on the SOT sensing structure 10 .

[0084] In some embodiments, after depositing the spacer layer 20 , the MTJ film stack 100 is sequentially deposited as described below, and vacuum is not broken during the entire deposition process of depositing the optional buffer layer 7 , the SOT sensing structure 10 , and the MTJ film stack 100 .

[0085] In some embodiments, after depositing the film stack of the SOT sensing structure 10, annealing may be performed to increase the perpendicular magnetic anisotropy, such as described above with respect to Figure 3A and Figure 3B In some embodiments, annealing may also be performed in an in-situ perpendicular field to further increase the perpendicular magnetic anisotropy. In some embodiments, the SOT sensing structure 10 may alternatively or additionally be annealed after the MTJ film stack 100 is deposited.

[0086] exist Fig.10 In the embodiment, the MTJ film stack 100 can be deposited in successive layers, such as Figure 1 The layers for the MTJ film stack 100 are formed above the SOT sensing structure 10, including the free layer 30, the barrier layer 40, the reference layer 50, the pinned layer 60, and the cap layer 70. Then, in some embodiments, a top electrode 75 is deposited (see Figure 1 ), while in other embodiments, a hard mask 101 may be deposited (see Fig. 11B) is used as a top electrode. In some embodiments, the spacer layer 20 can be formed as the first layer below the free layer 30. Each layer of the MTJ film stack 100 can be formed by a suitable film formation method that can provide precise thickness control capabilities. Such methods can include, for example, physical vapor deposition (PVD) sputtering. Other methods may include: molecular beam epitaxy (MBE); pulsed laser deposition (PLD); atomic layer deposition (ALD); electron beam (e-beam) epitaxy; or any combination thereof. If the thickness of the deposition can be precisely controlled, chemical vapor deposition (CVD) or its derivatives can be used.

[0087] After depositing the MTJ film stack 100 layer, annealing may be performed. If a first anneal is performed after depositing the SOT sensing structure 10, in some embodiments, a second anneal after depositing the MTJ film stack 100 may be performed in the presence of a horizontal magnetic field to set the in-plane anisotropic crystal of the AFM layer. In particular, the post-annealing may be performed at a temperature between about 300°C and about 400°C for a time between 0.5 hours and 3 hours. During the annealing, the magnetic field may be between about 1 Tesla and 5 Tesla. If the first anneal after depositing the SOT sensing structure 10 is not performed, the first anneal after depositing the MTJ film stack 100 may be performed in the presence of a vertical magnetic field to enhance the PMA of the SOT sensing structure 10. Then, a second anneal may also be performed in the presence of a horizontal magnetic field to set the AFM layer.

[0088] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig.11F and Fig.11G Various views are shown in the process of patterning the MTJ film stack 100 to form the MTJ pillar and patterning the SOT sensing structure 10 film stack to form the SOT sensing structure 10. Fig.11A In the embodiment, the hard mask layer 101 is deposited on the layers of the MTJ film stack 100. The hard mask layer 101 can be deposited using any suitable process and can be made of any suitable material (e.g., silicon nitride) or a conductive metal layer (e.g., tantalum, tungsten, titanium nitride, etc.) or a combination thereof (e.g., a first layer of a conductive metal and a second layer of a dielectric such as silicon nitride). In embodiments where the hard mask layer 101 includes a metal, the hard mask layer 101 can also serve as a top electrode 75 ( Figure 1 ). The hard mask layer 101 is patterned and etched by using one or more photolithography techniques, such as Fig. 11B shown.

[0089] exist Fig. 11CIn the embodiment, the hard mask layer 101 is used as a mask to pattern the various films of the MTJ film stack 100. In some embodiments, the MTJ film stack 100 can be used to pattern the spacer layer 20, as shown. Fig. 11C (as well as Fig.12 ), and in other embodiments, such as Fig.11E (as well as Fig.12 The spacer layer 20 is patterned by using the SOT sensing structure 10 film stack shown in the right side of FIG. Other embodiments may pattern the spacer layer 20 into a first spacer layer 20A and a second spacer layer 20B, such as Figure 1 In some embodiments, Fig. 11C As shown, the cross-sectional view of the MTJ film stack 100 has a conical (mesa) shape. In some embodiments, the hard mask layer 101 or a dielectric portion of the hard mask layer 101 may be consumed in the patterning of the MTJ film stack 100. The remaining metal portion of the hard mask layer 101 may be used as a top electrode 75 (hereinafter labeled as top electrode 75).

[0090] exist Fig.11D In the embodiment of the present invention, a dielectric protection layer 103 is blanket deposited using any suitable deposition technique (e.g., PVD, CVD, ALD, etc., or a combination thereof). The dielectric protection layer 103 is deposited on the films of the SOT sensing structure 10 and the patterned MTJ film stack 100, and may be formed of any suitable material such as silicon nitride, silicon carbide, etc., or any combination thereof.

[0091] exist Fig.11E In the embodiment, the film stack of the SOT sensing structure 10 is patterned using suitable photolithography and etching techniques to form the SOT sensing structure 10. In case the optional buffer layer 7 is used, it is also patterned together with the SOT sensing structure 10 film stack to have the same shape in a top view. Fig.11E An embodiment is also shown in which the spacer layer 20 is not patterned as part of the MTJ film stack 100, but is formed as part of the film stack of the SOT sensing structure 10. As described above, the spacer layer 20 may include a portion of the spacer layer 20B patterned as part of the MTJ film stack 100 and a portion of the spacer layer 20A patterned as part of the SOT sensing structure 10, for example. Figure 1 shown.

[0092] Fig.11F and Fig.11G 1 and 2 show top views of the MTJ film stack 100 and the SOT sensing structure 10. In these views, the dielectric protection layer 103 and the top electrode 75 are omitted, and the vias 126A are shown in dashed lines because they are underneath. The shape of the SOT sensing structure 10 can be rectangular (eg Fig.11F) or oval, and in some embodiments, for example Fig.11G As shown, there may be a portion in the middle that is narrower than the outer portion (eg, an hourglass or bow tie), with the narrow portion aligned with the MTJ film stack 100 .

[0093] exist Fig.12 In the embodiment, after patterning the MTJ film stack 100 and the SOT sensing structure 10, one or more dielectric material layers, such as ILD 124B, including any of the above-mentioned ILD candidate materials, are deposited to completely cover the MTJ film stack 100. A planarization operation such as CMP may be performed to level the upper surface of the ILD 124B. In some embodiments, the CMP will have a floating stopper in the ILD 124B, such as Fig.12 As shown. In other embodiments, the CMP may stop on the protective dielectric layer 103. As described above, the left MTJ film stack 100, the spacer layer 20, and the SOT sensing structure 10 are patterned so that the spacer layer 20 is patterned together with the MTJ film stack 100 and has the same shape as the MTJ film stack 100. The right MTJ film stack 100, the spacer layer 20 patterned SOT sensing structure 10, and the SOT sensing structure 10 so that the spacer layer 20 is patterned with the SOT sensing structure 10 and has the same shape as the SOT sensing structure 10. This embodiment diagram is omitted in subsequent figures. According to some embodiments, a combination of the two may also be utilized.

[0094] exist Fig.13 In the embodiment, after forming the MTJ film stack 100 and depositing the ILD 124B and performing CMP, a via 126B can be formed through the ILD 124B and the protective dielectric layer 103 to contact the top electrode 75 on the MTJ film stack 100, and the via 126B can be formed using a process and material similar to that used to form the via 126A. For example, the via 126B can be formed using a damascene process, in which a mask is used to pattern an opening in the ILD 124B and the dielectric protective layer 103 is etched, and an optional diffusion barrier layer is deposited in the opening, followed by a conductive plug material, followed by CMP.

[0095] exist Fig.14 124B, a conductive line 130C is formed to electrically connect the via 126B and provide electrical routing to the bit line 160 in the SOT-MRAM device 300. The conductive line 130C may be formed in a dielectric layer 128C located above the ILD 124B. The dielectric layer 128C may be a material similar to that described above for the dielectric layer 104 and may be deposited using techniques similar to the dielectric layer 104. In some embodiments, the dielectric layer 128C may be considered an intermetallic dielectric (IMD).

[0096] Fig.15 An embodiment of a SOT-MRAM device 400 is shown in which the source region 112S of an adjacent FET 110 is shared between two SOT-MRAM cells 90 (e.g., MC1 and MC2). Sharing the source line SL (e.g., SL2 / 3 as shown) and the source region 112S allows for greater device density. The SOT-MRAM device 400 can be formed using processes and materials similar to those used to form the SOT-MRAM device 300.

[0097] Fig.16 According to some embodiments Fig.14 A three-dimensional view of a SOT-MRAM cell 90 (eg, MCl) of a SOT-MRAM device 300. Figures 1 to 14 Materials, configurations, dimensions, processes, and / or operations are described, and detailed descriptions thereof may be omitted.

[0098] In some embodiments, the word line 120 (coupled to the gate of the FET 110) extends in the Y direction, and the source lines 125SL1 and SL2 extend in the X direction. The SOT sensing structure 10 is located above the source or drain region of two adjacent FETs 110 and is coupled to the respective source or drain regions of the two adjacent FETs 110 at either end through vias and metal wiring layers. In some embodiments, the SOT sensing structure 10 may have a direction primarily in the X direction.

[0099] like Fig.16 As shown, in some embodiments, the MTJ film stack 100 is disposed on the SOT sensing structure 10, and a spacer layer 20 is inserted between the MTJ film stack 100 and the SOT sensing structure 10. The MTJ film stack 100 may have a circular column or an elliptical column, which may be tapered as shown in other figures. The bit line 160 is electrically coupled to the top of the MTJ film stack 100 through a through hole and / or a top electrode of the MTJ film stack, and may extend in the X direction.

[0100] Fig.17 is a portion of a circuit diagram of a SOT-MRAM device consistent with the SOT-MRAM device 300 according to some embodiments. Figures 1 to 14 Materials, configurations, dimensions, processes, and / or operations are described, and detailed descriptions thereof may be omitted.

[0101] In some embodiments, the bit line BL and the source lines (e.g., SL1 and SL2) extend in the row direction, while the word lines (e.g., WL1 and WL2) extend in the column direction. In some embodiments, the SOT-MRAM cell is arranged at a position defined by the bit line BL, two word lines WL1 and WL2, and two source lines SL1 and SL2. The number of memory cells coupled to the same word line and / or the same bit line is not limited to three or four, and may be greater than 3, such as 4, 8, 16, 32, 64, 128, 256, 512, 512, or more than 1024. The word lines WL1 and WL2 are connected to a word driver circuit (row decoder), and the source lines SL1 and SL2 are connected to a current source circuit, which is also used as a write driver circuit together with the word driver circuit. One end of the SOT sensing structure 10 (SOT) is coupled to the source or drain of the FET 110 (see Fig.14 ), the other end of the SOT sensing structure SOT is coupled to the other source or drain of the FET 110. One end of the MTJ film stack M is coupled to the SOT sensing structure SOT, and the other end of the MTJ film stack M is coupled to the corresponding bit line BL. The gate of the FET 110 is coupled to the word lines WL1 and WL2, and the drain or source of the corresponding FET 110 is coupled to the source lines SL1 and Sl2.

[0102] exist Fig.17 In some embodiments, vertically adjacent SOT-MRAM cells along the column direction are coupled to the same read word lines WL1 and WL2, respectively. Horizontally adjacent SOT-MRAM cells along the row direction are coupled to the same bit line BL and the same source lines SL1 and SL2, respectively. In some embodiments, adjacent FETs 110 in adjacent SOT-MRAM cells along the row direction may share the same source line SL, such as Fig.15 shown.

[0103] Fig.18 The operation of the SOT-MRAM cell according to an embodiment of the present disclosure is shown. In a write operation, a write current flows through the SOT sensing structure SOT. When a first type of data (e.g., "0") is written to the MTJ film stack 100, the word line WL1 and the word line WL2 are set to the gate electrode of the turn-on FET 110. The first source line SL1 is set to apply a first potential (e.g., a write voltage Vw), and the second source line SL2 is to a second potential (e.g., ground or 0V), the first potential being greater than the second potential. The bit line BL can be floating. The electrons flowing in the parallel Hall metal of the SOT sensing structure 10 have a positive spin Hall angle and induce a SOT on the free layer 30, thereby changing the spin characteristics of the electrons of the free layer 30.

[0104] When writing the second type of data (e.g., "1") to the MTJ film stack 100, the word line WL1 and the word line WL2 are set to the gate electrode of the turn-on FET 110. SL1 is set to a second potential (e.g., ground or 0V), and the second source line SL2 is set to a first potential (e.g., a write voltage Vw) that is greater than the second potential. The bit line BL may be floating. Electrons flowing in opposite directions in the parallel Hall metals of the SOT sensing structure 10 have a negative spin Hall angle and induce SOT on the free layer 30, causing the spin characteristics of the electrons of the free layer 30 to change.

[0105] When reading data from the MTJ film stack 100, the read operation can be performed in several different ways. Either of the word lines WL1 or WL2 is turned on the corresponding FET 110, while the other is turned off. SL1 or SL2 connected to the cutoff gate can float, while SL1 or SL2 connected to the cutoff gate is coupled to a second potential (e.g., ground or 0V). The potential Vread at the bit line BL can be used to calculate the resistance of the SOT and MTJ to determine whether the MTJ is set to a "1" state or a "0" state. In some embodiments, the amplitude of Vread is about 1 / 2 to about 1 / 50 of Vw. In other embodiments, the read current flows from the bit line BL to the source line SL1 or SL2 from the MTJ film stack 100 to the SOT sense wiring layer 15 in the opposite direction, in other words, from the read bit line RBL to the source line SL. In this case, Vread is higher than the source line voltage (e.g., Vread is positive).

[0106] Embodiments advantageously provide several configurations to enhance effectiveness, reduce complexity, and reduce power consumption of SOT-MRAM devices. In some embodiments, a strained PMA Hall metal SOT sensing structure is used to provide SOT sensing on a free layer. The strained PMA Hall metal SOT sensing structure allows a SOT-MRAM device to be formed without using a thick metal seed layer to provide perpendicular magnetic anisotropy, thereby reducing power consumption and increasing the spin Hall angle. Some embodiments also use a spacer layer between the SOT sensing structure and the free layer of the MTJ film stack. The spacer layer provides flexibility to optimize the magnetic coupling between the PMA SOT sensing structure and the IMA free layer. This allows the SOT sensing structure to operate under an internally generated magnetic field rather than an externally generated magnetic field. Embodiments may combine a (seedless) strained SOT sensing structure and a spacer layer to provide further advantages in efficiency while reducing power consumption, thereby allowing the use of smaller switching transistors.

[0107] One embodiment is a magnetic memory device including a first spin-orbit torque (SOT) sensing structure, which may include a Hall metal having perpendicular magnetic anisotropy. The magnetic memory device also includes a first magnetic tunnel junction (MTJ) stack disposed above the first SOT sensing structure. The device also includes a first wire coupled to a first side of the first SOT sensing structure. The device also includes a second wire coupled to a second side of the first SOT sensing structure. In one embodiment, the first SOT sensing structure may include alternating metal layers of a first non-ferromagnetic metal and a second ferromagnetic metal. In one embodiment, the thickness of the bottom layer of the first metal is greater than the thickness of the second layer of the first metal, and the first layer of the second metal is inserted between the bottom layer and the second layer. In one embodiment, the first metal has a first lattice constant and the second metal has a second lattice constant, wherein the first lattice constant and the second lattice constant are different. In one embodiment, the first metal has a first thickness, wherein the second metal has a second thickness, and wherein the SOT sensing structure has no metal seed layer, and the third thickness of the metal seed layer is greater than 10 times the first thickness or 10 times the second thickness. Thickness. In one embodiment, the magnetic memory device may include: a spacer layer inserted between the first SOT sensing structure and the first MTJ stack. In one embodiment, the spacer layer may include a metal or a metal oxide. In one embodiment, the spacer layer may include aluminum oxide, magnesium oxide, cobalt oxide, tungsten, ruthenium, platinum, molybdenum, titanium or magnesium.

[0108] Another embodiment is a magnetic memory device including a first spin-orbit torque (SOT) sensing structure, the first SOT sensing structure including a Hall metal. The magnetic memory device also includes a top-fixed magnetic tunnel junction (MTJ) stack disposed above the first SOT sensing structure, the MTJ stack including a spacer layer inserted between a free layer of the MTJ stack and the first SOT sensing structure. The magnetic memory device also includes a first wire coupled to a first side of the first SOT sensing structure. The magnetic memory device also includes a second wire coupled to a second side of the first SOT sensing structure. In one embodiment, the MTJ stack includes: a free layer, a barrier layer above the free layer, a reference layer above the barrier layer, a second spacer layer above the reference layer, and a pinned layer above the second spacer layer. In one embodiment, the first SOT sensing structure includes alternating metal layers of a first ferromagnetic material and a second non-ferromagnetic material. In one embodiment, the lattice mismatch of the first ferromagnetic material and the second non-ferromagnetic material is between 6% and 10%. In one embodiment, the spacer layer has the same shape as the shape of the SOT sensing structure in a top view.

[0109] Another embodiment is a magnetic memory device including a first spin-orbit torque (SOT) sensing structure, which may include a multilayer Hall metal having perpendicular magnetic anisotropy. The magnetic memory device also includes a first magnetic tunnel junction (MTJ) stack disposed above the first SOT sensing structure. The device also includes a first source / drain of a first transistor coupled to a first side of the first SOT sensing structure. The device also includes a second source / drain of a second transistor coupled to a second side of the first SOT sensing structure. In one embodiment, the first SOT sensing structure may include alternating metal layers of a first metal and a second metal, wherein a first thickness of the first metal is between 1 nm and 2 nm, and a second thickness of the second metal is between 0.01 nm and 0.7 nm. In one embodiment, the first SOT sensing structure may include: the first metal layer may include a first metal, wherein the thickness of the first metal layer is between 2 nm and 5 nm, and alternating metal layers of a second metal and a third metal. , wherein the thickness of each alternating metal layer is between 0.01 nm and 2 nm. In one embodiment, the first metal and the second metal are the same material. In one embodiment, the first metal layer has a first thickness between 2 nm and 5 nm, wherein the second thickness of each alternating metal layer of the second metal and the third metal is between 0.01 nm and 2 nm. In one embodiment, the magnetic memory device may include a spacer layer interposed between the first MTJ stack and the first SOT sensing structure. In one embodiment, the first SOT sensing structure may include alternating metal layers of the first metal and the second metal, wherein the lattice mismatch between the first metal and the second metal is between 6% and 10%.

[0110] An embodiment of the present application provides a magnetic memory device, comprising: a first spin-orbit torque (SOT) sensing structure, the first SOT sensing structure comprising a Hall metal having perpendicular magnetic anisotropy; a first magnetic tunnel junction (MTJ) stack disposed above the first SOT sensing structure; a first wire coupled to a first side of the first SOT sensing structure; and a second wire coupled to a second side of the first SOT sensing structure. In some embodiments, the first SOT sensing structure comprises alternating metal layers of a first non-ferromagnetic metal and a second ferromagnetic metal. In some embodiments, the thickness of the bottom layer of the first metal is greater than the thickness of the second layer of the first metal, and the first layer of the second metal is inserted between the bottom layer and the second layer. In some embodiments, the first metal has a first lattice constant and the second metal has a second lattice constant, wherein the first lattice constant and the second lattice constant are different. In some embodiments, the first metal has a first thickness, wherein the second metal has a second thickness, and wherein the SOT sensing structure does not have a metal seed layer having a third thickness greater than 10 times the first thickness or 10 times the second thickness. In some embodiments, it also includes: a spacer layer inserted between the first SOT sensing structure and the first MTJ stack. In some embodiments, the spacer layer comprises a metal or a metal oxide. In some embodiments, the spacer layer includes aluminum oxide, magnesium oxide, cobalt oxide, tungsten, ruthenium, platinum, molybdenum, titanium, or magnesium.

[0111] An embodiment of the present application provides a magnetic memory device, comprising: a first spin-orbit torque (SOT) sensing structure, the first SOT sensing structure comprising a Hall metal; a magnetic tunnel junction (MTJ) stack, disposed above the first SOT sensing structure, the MTJ stack comprising a spacer layer inserted between a free layer of the MTJ stack and the first SOT sensing structure; a first wire coupled to a first side of the first SOT sensing structure; and a second wire coupled to a second side of the first SOT sensing structure. In some embodiments, the MTJ stack comprises: a free layer, a barrier layer located above the free layer, a reference layer located above the barrier layer, a second spacer layer located above the reference layer, and a pinned layer located above the second spacer layer. In some embodiments, the first SOT sensing structure comprises alternating metal layers of a first ferromagnetic material and a second non-ferromagnetic material. In some embodiments, the lattice mismatch between the first ferromagnetic material and the second non-ferromagnetic material is between 6% and 10%. In some embodiments, the spacer layer has the same shape as the shape of the SOT sensing structure in a top view.

[0112] An embodiment of the present application provides a magnetic memory device, comprising: a first spin-orbit torque (SOT) sensing structure, the first SOT sensing structure comprising a multilayer Hall metal having perpendicular magnetic anisotropy; a first magnetic tunnel junction (MTJ) stack, disposed above the first SOT sensing structure; a first source / drain of a first transistor, coupled to a first side of the first SOT sensing structure; and a second source / drain of a second transistor, coupled to a second side of the first SOT sensing structure. In some embodiments, the first SOT sensing structure comprises alternating metal layers of a first metal and a second metal, wherein the first thickness of the first metal is between 1 nm and 2 nm, and the second thickness of the second metal is between 0.01 nm and 0.7 nm. In some embodiments, the first SOT sensing structure comprises: a first metal layer, comprising a first metal, wherein the thickness of the first metal layer is between 2 nm and 5 nm, and alternating metal layers of a second metal and a third metal, wherein the thickness of each of the alternating metal layers is between 0.01 nm and 2 nm. In some embodiments, the first metal and the second metal are the same material. In some embodiments, the first metal layer has a first thickness between 2 nm and 5 nm, wherein the second thickness of each of the alternating metal layers of the second metal and the third metal is between 0.01 nm and 2 nm. In some embodiments, a spacer layer is further included, interposed between the first MTJ stack and the first SOT sensing structure. In some embodiments, the first SOT sensing structure includes alternating metal layers of the first metal and the second metal, wherein the lattice mismatch between the first metal and the second metal is between 6% and 10%.

[0113] The foregoing summarizes the components of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A magnetic storage device, comprising: a first spin-orbit torque sensing structure, the first spin-orbit torque sensing structure comprising a Hall metal having perpendicular magnetic anisotropy, the first spin-orbit torque sensing structure comprising alternating metal layers of a first metal and a second metal, the first metal comprising a non-ferromagnetic metal, the second metal comprising cobalt, the first spin-orbit torque sensing structure not comprising a seed layer; a first magnetic tunnel junction stack disposed above the first spin-orbit torque sensing structure; a first wire coupled to a first side of the first spin-orbit torque sensing structure; as well as The second wire is coupled to the second side of the first spin-orbit torque sensing structure.

2. The magnetic memory device according to claim 1, wherein: By passing a current through the first magnetic tunnel junction stack without applying an external magnetic field, the free layer of the first magnetic tunnel junction stack is configured to change the spin polarization direction relative to the reference layer of the first magnetic tunnel junction stack, so that the magnetic memory device switches between high resistance and low resistance states.

3. The magnetic memory device according to claim 2, wherein: The thickness of the bottom layer of the first metal is greater than the thickness of the second layer of the first metal, and the first layer of the second metal is interposed between the bottom layer and the second layer.

4. The magnetic memory device according to claim 2, wherein: The first metal has a first lattice constant and the second metal has a second lattice constant, wherein the first lattice constant and the second lattice constant are different.

5. The magnetic memory device according to claim 2, wherein: The first metal has a first thickness, wherein the second metal has a second thickness, and the first thickness is greater than the second thickness.

6. The magnetic memory device according to claim 1, further comprising: A spacer layer is interposed between the first spin-orbit torque sensing structure and the first magnetic tunnel junction stack.

7. The magnetic memory device according to claim 6, wherein: The spacer layer includes metal or metal oxide.

8. The magnetic memory device according to claim 7, wherein: The spacer layer includes aluminum oxide, magnesium oxide, cobalt oxide, tungsten, ruthenium, platinum, molybdenum, titanium or magnesium.

9. A magnetic storage device comprising: a first spin-orbit torque sensing structure, the first spin-orbit torque sensing structure comprising a Hall metal, the first spin-orbit torque sensing structure comprising alternating metal layers of a first ferromagnetic material including cobalt and a second non-ferromagnetic material; a magnetic tunnel junction stack disposed above the first spin-orbit torque sensing structure, the magnetic tunnel junction stack comprising a spacer layer interposed between a free layer of the magnetic tunnel junction stack and the first spin-orbit torque sensing structure; a first wire coupled to a first side of a first spin-orbit torque sensing structure; as well as The second wire is coupled to the second side of the first spin-orbit torque sensing structure.

10. The magnetic memory device according to claim 9, wherein: The magnetic tunnel junction stack includes a free layer, a barrier layer over the free layer, a reference layer over the barrier layer, a second spacer layer over the reference layer, and a pinned layer over the second spacer layer.

11. The magnetic memory device according to claim 10, wherein: By passing a current through the first spin-orbit torque sensing structure without applying an external electric field, the free layer of the magnetic tunnel junction stack is configured to change the spin polarization direction relative to the reference layer of the magnetic tunnel junction stack, so that the magnetic memory device switches between high resistance and low resistance states.

12. The magnetic memory device according to claim 9, wherein: The lattice mismatch between the first ferromagnetic material and the second non-ferromagnetic material is between 6% and 10%.

13. The magnetic memory device according to claim 9, wherein: The spacer layer has the same shape as that of the first spin-orbit torque sensing structure in a top view.

14. A magnetic storage device comprising: a first spin-orbit torque sensing structure, the first spin-orbit torque sensing structure comprising a multilayer Hall metal having perpendicular magnetic anisotropy; a first magnetic tunnel junction stack disposed above the first spin-orbit torque sensing structure; a spacer layer disposed between the first spin-orbit torque sensing structure and the first magnetic tunnel junction stack, the spacer layer having a thickness configured to adjust exchange coupling of the first spin-orbit torque sensing structure with a free layer of the first magnetic tunnel junction stack; a first source / drain of a first transistor coupled to a first side of the first spin-orbit torque sensing structure; as well as A second source / drain of the second transistor is coupled to a second side of the first spin-orbit torque sensing structure.

15. The magnetic memory device according to claim 14, wherein: The first spin-orbit torque sensing structure includes alternating metal layers of a first metal and a second metal, wherein a first thickness of the first metal is between 1 nm and 2 nm, and a second thickness of the second metal is between 0.01 nm and 0.7 nm.

16. The magnetic memory device according to claim 14, wherein: The first spin-orbit torque sensing structure comprises: a first metal layer, comprising a first metal, wherein the thickness of the first metal layer is between 2 nm and 5 nm, and Alternating metal layers of the second metal and the third metal, wherein each of said alternating metal layers has a thickness between 0.01 nm and 2 nm.

17. The magnetic memory device according to claim 16, wherein: The first metal and the second metal are the same material.

18. The magnetic memory device according to claim 14, wherein: The first magnetic tunnel junction stack has a circular column or an elliptical column.

19. The magnetic memory device according to claim 14, wherein: The spacer layer includes aluminum oxide, magnesium oxide, cobalt oxide, tungsten, ruthenium, platinum, molybdenum, titanium or magnesium.

20. The magnetic memory device according to claim 14, wherein The first spin-orbit torque sensing structure includes alternating metal layers of a first metal and a second metal, wherein a lattice mismatch between the first metal and the second metal is between 6% and 10%.

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