Spin-orbit torque memory device

Abstract

A spin-orbit torque magnetoresistive random access memory (SOT MRAM) device is provided. Each SOT MRAM device uses a topological conductor (i.e., a topological metal or a topological semimetal) as both an interconnect layer and an SOT layer, which are integrated at the same metal layer. The SOT MRAM device also includes a magnetic tunnel junction (MTJ) structure contacting the SOT layer, and a contact structure contacting the MTJ structure.

Description

BACKGROUND

[0001] The present application relates to memory devices, and more specifically to spin orbit torque (SOT) magnetoresistive random access memory (MRAM) devices.

[0002] MRAM is a non-volatile random access memory technology in which data is stored by magnetic storage elements. These elements are typically formed of two ferromagnetic plates, each of which can hold a magnetization, separated by a thin dielectric layer (i.e., tunnel barrier layer). One of the two plates (i.e., magnetic reference or pinned layer) is a magnet whose direction of magnetic moment is set to a particular direction; the magnetization of the other plate (i.e., magnetic free layer) can change in at least two different directions, thereby representing different digital states for memory applications, such as 0 and 1. In MRAM, such elements can be referred to as magnetic tunnel junction (MTJ) structures. In a typical MTJ structure, the magnetization of the magnetic reference layer is fixed in one direction (e.g., pointing upwards), while the direction of the magnetic free layer can be "switched" by some external force, such as a magnetic field or a spin torque generated by a charge current. A smaller current (of either polarity) can be used to read the resistance of the device, which depends on the relative orientation of the magnetization of the magnetic free layer and the magnetic reference layer. When the magnetizations are anti-parallel, the resistance is typically higher, while when they are parallel, the resistance is typically lower (although this can be reversed, depending on the materials).

[0003] One type of MRAM that can use MTJ structures is spin transfer torque (STT) MRAM. STT MRAM has the advantage of lower power consumption and better scalability than conventional MRAM, which uses a magnetic field to flip the active elements. In STT MRAM, the spin transfer torque is used to flip (switch) the orientation of the magnetic free layer. For STT MRAM devices, a current through the MTJ structure is used to switch or "write" the bit state of the MTJ memory element. A current down through the MTJ structure causes the magnetic free layer to be parallel to the magnetic reference layer, while a current up through the MTJ structure causes the magnetic free layer to be anti-parallel to the magnetic reference layer.

[0004] Another type of MRAM that can use MTJ structures is a SOT MRAM device. SOT memory devices do not require passing high currents through the MTJ structure during a write operation, which is accomplished by passing current through a SOT layer. SOT memory devices are being actively considered as a beyond STT MRAM option for reducing write current and eliminating read disturbance. Existing SOT MRAM devices include a SOT layer (for writing) of a different material than the interconnect metal and a MTJ structure (for reading) integrated thereon. The SOT layer is connected to one of the metal interconnect layers (e.g., the first metal layer, Ml) through a SOT via layer. As a result, in addition to patterning the metal interconnects and the SOT layer, the SOT via layer must also be patterned. Furthermore, the SOT layer and the SOT via become a limiting factor for inserting the SOT MRAM device between lower metal interconnect layers in advanced nodes for density and to reduce parasitic resistance. SUMMARY

[0005] A SOT MRAM device for use in a structure is provided. Each of the SOT MRAM devices of the present application uses a topological conductor (i.e., a topological metal or a topological semimetal) as both an interconnect layer and a SOT layer to integrate the SOT layer and the interconnect layer in the same metal layer. The SOT MRAM device also includes a MTJ structure contacting the SOT layer and a MTJ contact structure contacting the MTJ structure. Using a topological conductor as both an interconnect layer and a SOT layer can absorb the SOT layer into the interconnect layer and eliminate the associated SOT via layer, simplifying patterning and allowing insertion of the SOT MRAM device at a lower metal level.

[0006] In one aspect of the present application, a memory structure is provided. In one embodiment of the present application, the memory structure includes a SOT layer and an interconnect layer at the same metal level of a back end of line (BEOL) structure, where the SOT layer and the interconnect layer are both composed of a topological conductor. In the present application, the SOT layer and the interconnect layer are composed of the same topological conductor. The memory structure also includes a MTJ structure, the MTJ structure including a magnetic free layer forming an interface with the SOT layer, and a MTJ contact structure contacting the MTJ structure.

[0007] In some embodiments of the present application, the topological conductor is a material selected from a metal or a semimetal, where the metal or semimetal has a conducting surface state protected by a nontrivial band structure topology, where the surface conductivity is greater than the bulk conductivity of the metal or semimetal. Typically, the surface conductivity of the topological conductor is at least two times greater than the bulk conductivity.

[0008] In some embodiments of the application, the topological conductor is a Weyl semimetal, a multi-fold fermion semimetal, a magnetic Weyl semimetal, a Kramers-Weyl fermion semimetal, or a triple-point topological metal.

[0009] In some embodiments of the application, the MTJ structure includes, from bottom to top, a magnetic free layer, a tunnel barrier layer, a magnetic reference layer, and an electrode layer. In such embodiments, the MTJ structure is located above the SOT layer, but below the contact structure.

[0010] In some embodiments of the application, the MTJ structure includes, from bottom to top, an electrode layer, a magnetic reference layer, a tunnel barrier layer, and a magnetic free layer. In such embodiments, the MTJ structure is located above the contact structure, but below the SOT layer.

[0011] In some embodiments of the application, the MTJ contact structure is composed of a conductive metal, a conductive metal alloy, or another topological conductor. When the MTJ contact structure is composed of a topological conductor, the topological conductor can be the same or different in composition from the topological conductor that provides the SOT layer and the interconnect layer.

[0012] In some embodiments of the application, the SOT layer and the interconnect layer are separated by an interconnect dielectric layer.

[0013] In some embodiments of the application, the memory structure further includes an SOT contact structure electrically connected to the SOT layer by a via structure.

[0014] In some embodiments of the application, the memory structure further includes an SOT contact structure electrically connected to the SOT layer by a via portion of the SOT contact structure.

[0015] In some embodiments of the application, the SOT contact structure described in the above embodiments includes a conductive metal, a conductive metal alloy, or another topological conductor, wherein the other topological conductor is the same or different in composition from the topological conductor that provides the SOT layer and the interconnect layer.

[0016] In some embodiments of the application, the memory structure further includes at least one via structure contacting a bottommost surface of the SOT layer.

[0017] In some embodiments of the application, the at least one via structure is composed of a conductive metal, a conductive metal alloy, or another topological conductor, wherein the other topological conductor is the same or different in composition from the topological conductor that provides the SOT layer and the interconnect layer.

[0018] In some embodiments of the application, the SOT layer further comprises at least one via portion, the at least one via portion being on a side of the SOT layer opposite a side of the SOT layer that contacts the MTJ structure, wherein both the SOT layer and the at least one via portion are composed of a topological conductor.

[0019] In some embodiments of the application, the memory structure further comprises a via structure below the interconnect layer.

[0020] In some embodiments of the application, both the SOT layer and the interconnect layer are electrically connected to source / drain regions of a transistor.

[0021] In another aspect of the application, a structure is provided. In one embodiment, the structure comprises a memory device region comprising a memory structure located therein. The memory structure comprises a SOT layer and an interconnect layer at a same metal level of a BEOL structure, wherein both the SOT layer and the interconnect layer are composed of a topological conductor. The memory structure further comprises an MTJ structure comprising a magnetic free layer forming an interface with the SOT layer, and an MTJ contact structure contacting the MTJ structure. In addition to the memory device region, the structure comprises a non-memory device region located adjacent to the memory device region. The non-memory device region comprises another interconnect layer, wherein the other interconnect layer is at the same metal level as both the SOT layer and the interconnect layer, and the other interconnect layer is composed of a topological conductor.

[0022] In some embodiments of the structure of the application, both the SOT layer and the interconnect layer are electrically connected to source / drain regions of a transistor located in the memory device region, and the other interconnect layer is electrically connected to source / drain regions of a transistor located in the non-memory device region. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a cross-sectional view of a structure comprising a SOT MRAM device according to a first embodiment of the application.

[0024] Figure 2 is a cross-sectional view of a SOT MRAM device according to a second embodiment of the application.

[0025] Figure 3 is a cross-sectional view of a SOT MRAM device according to a third embodiment of the application.

[0026] Figure 4 is a cross-sectional view of a SOT MRAM device according to a fourth embodiment of the application.

[0027] Figure 5 is a cross-sectional view of a SOT MRAM device according to a fifth embodiment of the application.

[0028] Figures 6A-6K is a cross-sectional view of a method that can be used to form a SOT MRAM device according to embodiments of the present application. DETAILED DESCRIPTION

[0029] The present application will now be described in greater detail by reference to the following discussion and the drawings that accompany the present application. It is noted that the drawings of the present application are for purposes of illustration only, and thus are not drawn with respect to scale. It is further noted that like and corresponding elements are identified by like reference numerals.

[0030] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of various embodiments of the present application. Those of ordinary skill in the art, however, will understand that various embodiments of the present application can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.

[0031] It is understood that when an element as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It is further understood that when an element is referred to as being "under" or "beneath" another element, it can be directly under the other element, or intervening elements can also be present. In contrast, when an element is referred to as being "directly under" or "directly beneath" another element, there are no intervening elements present.

[0032] As noted above, SOT MRAM devices are provided in the present application. Each of the SOT MRAM devices of the present application uses a topological conductor (i.e., a topological metal or a topological semimetal) as both an interconnect layer and a SOT layer to integrate the SOT layer and the interconnect layer in the same metal layer. By "same metal layer" it is meant that the SOT layer and the interconnect layer are laterally adjacent to each other, and each is in one of M1, M2, M3,... Mn of a BEOL structure. The SOT layer and the interconnect layer typically have at least one topmost surface that is coplanar with each other. The SOT MRAM device also includes an MTJ structure that contacts the SOT layer and an MTJ contact structure that contacts the MTJ structure. Using a topological conductor as both an interconnect layer and a SOT layer can absorb the SOT layer into the interconnect layer and eliminate the associated SOT via layer, simplifying patterning and allowing the SOT MRAM device to be inserted at a lower metal level. These and other aspects of the present application will now be described in greater detail.

[0033] Reference is first made to Figure 1 , having a structure according to embodiments of the present application. Figure 1The structure shown includes a SOT MRAM device according to a first embodiment of this application, located in memory device region A1. In some embodiments, such as Figure 1 As shown, non-memory device region A2 is located adjacent to memory device region A1. Figure 1 The image shows a box outlined with a dashed line around its perimeter. This boxed area represents the memory device region A1 contained within the SOT MRAM device. Figure 1 One type of SOT MRAM device that can be used is shown below. Figures 2-5 It shows a replacement Figure 1 Other SOT MRAM devices shown in the diagram.

[0034] It is worth noting that the structure shown includes a semiconductor substrate 10; please note that... Figure 1 Only the upper portion of the semiconductor substrate 10 is shown. The semiconductor substrate 10 may be made of at least one semiconductor material having semiconductor properties. Illustrative examples of semiconductor materials that can be used in this application include, but are not limited to, silicon (Si), silicon-germanium (SiGe) alloys, silicon-germanium carbide (SiGeC) alloys, germanium (Ge), III / V compound semiconductors, II / VI compound semiconductors, or multilayer stacks comprising at least two semiconductor materials. In some embodiments, the semiconductor substrate 10 may be a bulk semiconductor substrate (i.e., a substrate entirely composed of one or more semiconductor materials). In other embodiments, the semiconductor substrate 10 may be a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer, such as silicon dioxide and / or boron nitride, located between a first semiconductor material and a second semiconductor material. In one example, the SOI substrate includes Si as the first semiconductor material, silicon dioxide as an insulator, and Si as the second semiconductor material.

[0035] Figure 1 The illustrated structure may also include a shallow trench isolation structure 12 (or a similar insulating structure) located in the semiconductor substrate 10, which can be used to separate the memory device region A1 from the non-memory device region A2. The shallow trench isolation structure 12 is made of any trench dielectric material, such as silicon oxide. In some embodiments, trench dielectric pads made of, for example, silicon nitride (SiN) may be present along the sidewalls and bottomwalls of the trench dielectric material. The shallow trench isolation structure 12 may have an uppermost surface coplanar with the uppermost surface of the unetched portion of the semiconductor substrate 10. The shallow trench isolation structure 12 can be formed by first forming (by photolithography and etching) trenches in the upper portion of the semiconductor substrate 10, depositing optional trench dielectric liner material and trench dielectric material in the trenches, and subsequently performing a planarization process or an etch-back process.

[0036] Figure 1The illustrated structure also includes a plurality of transistors. In the drawing, four transistors T1, T2, T3, and T4 are shown by way of example. In the illustrated embodiment, T1, T2, and T3 are located in the memory device region Al, while T4 is located in the non-memory device region A2. In the illustrated embodiment, T1 and T3 are both access devices, with T1 serving as a write line transistor for the memory device, and T3 serving as a read line transistor for the memory device. T2 is a dummy transistor, i.e., an inactive transistor. T4 can be a logic transistor. Each transistor, e.g., T1, T2, T3, and T4, is a field effect transistor (FET) that includes a gate dielectric material that contacts a semiconductor channel (the channel is located between a source region and a drain region of the transistor), the gate dielectric material including, for example, a high-k (k equals 4.0 or greater) material, and a gate conductor material (including a work function metal) that contacts the gate dielectric material. The FETs can be planar transistors and / or non-planar transistors. Exemplary non-planar transistors include, but are not limited to, a stacked FET, a nanosheet FET, or a FinFET. The transistors also include Figure 1 source / drain regions (not shown) in the illustrated embodiment, the source / drain regions would be located in the semiconductor substrate 10 and at the footprint of each transistor. The transistors can be formed using techniques known to those skilled in the art. Note that the transistors are present in the front end of line (FEOL) level of the illustrated structure. Figure 1

[0037] Figure 1 The illustrated structure also includes a middle of line (MOL) dielectric layer 16 that is composed of one or more MOL dielectric materials, such as silicon oxide, silicon nitride, undoped silicate glass (US), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric, chemical vapor deposition (CVD) low-k dielectric, or any combination thereof. As used throughout this application, the term “low-k dielectric” means a dielectric material that has a dielectric constant k that is less than 4.0; note that all dielectric constants k referred to herein are relative to vacuum, unless otherwise specified. The MOL dielectric layer 16 can be formed by a deposition process, including but not limited to CVD, plasma-enhanced chemical vapor deposition (PECVD), or spin-on. The MOL dielectric layer 16 is formed between and on top of each transistor, i.e., T1, T2, T3, and T4.

[0038] Figure 1 ​The structure also includes a plurality of source / drain contact structures 18. Each source / drain contact structure 18 extends through the MOL dielectric layer 16 and contacts a surface of one of the source / drain regions (not shown) of the underlying transistor. The source / drain contact structures 18 typically have a top surface that is coplanar with the top surface of the MOL dielectric layer 16. Each source / drain contact structure 18 is composed of a contact conductor material. The contact conductor material can include, for example, a silicide liner such as TiSi, NiSi, PtSi, NiPtSi, an adhesion metal liner such as TiN, and a conductive metal such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. The source / drain contact structures 18 can also include one or more contact liners (not shown). In one or more embodiments, the contact liner (not shown) can include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof such as Ti / TiN and Ti / WC. In one or more embodiments in which a contact liner is present, the contact liner (not shown) can include a silicide liner such as TiSi, NiSi, PtSi, NiPtSi, and the like, as well as a diffusion barrier material as defined above. The source / drain contact structures 18 can be formed using a metallization process that includes forming contact openings in the MOL dielectric layer 16 and thereafter filling (including deposition and planarization) each contact opening with at least the contact conductor material.

[0039] In the present application, the MOL dielectric layer 16 and the source / drain contact structures 18 are present in the MOL layer of the structure, which is on top of the FEOL layer of the structure.

[0040] Figure 1The structure shown can also include a dielectric cap layer 19 located on the MOL dielectric layer 16, which can be omitted in some embodiments of the present application. When present, the dielectric cap layer 19 is composed of a dielectric material having a different composition than the MOL dielectric layer 16. Illustrative examples of dielectric materials that can be used as the dielectric cap layer 19 include, but are not limited to, dielectric materials containing silicon, carbon, and hydrogen atoms. In some embodiments, the dielectric material providing the dielectric cap layer 19 can include atoms of at least one of nitrogen and oxygen in addition to carbon and hydrogen atoms. In other embodiments, the dielectric material providing the dielectric cap layer 19 can include boron atoms in addition to silicon, nitrogen, carbon, and hydrogen atoms. In one example, the dielectric material providing the dielectric cap layer 19 can be composed of an NBLOK dielectric material containing silicon, carbon, hydrogen, nitrogen, and oxygen atoms. In an alternative example, the dielectric material providing the dielectric cap layer 19 can be composed of an SiBCN dielectric material containing silicon, boron, carbon, hydrogen, and nitrogen atoms. The dielectric cap layer 19 can be formed using a deposition process such as CVD, PECVD, atomic layer deposition (ALD), or spin-on.

[0041] Figure 1 The structure shown also includes a plurality of via structures 30, a plurality of interconnect layers 32Y and 32Z, and at least one SOT layer 32X. Each of the interconnect layers 32Y and 32Z and the at least one SOT layer 32X is present in a first interconnect dielectric layer ILD1. The interconnect layers 32Y and 32X are present in the memory device region Al, while the interconnect layer 32Z is present in the non-memory device region A2. As shown, the plurality of interconnect layers 32Y and 32Z and the at least one SOT layer 32X are all located at the same metal level of the semiconductor structure. The SOT layer 32X is spaced apart from the interconnect layers 32Y present in the memory device region Al by the ILD1. As shown, one end of each of the via structures 30 is designed to contact one of the underlying source / drain contact structures 18. As shown, the opposite end of some of the via structures 30 is designed to contact the interconnect layers 32Y and 32Z, and the opposite end of at least one of the via structures 30 is designed to contact the SOT layer 32X. The plurality of via structures 30, the plurality of interconnect layers 32Y and 32Z, the at least one SOT layer 32X, and the first interconnect dielectric layer ILD1 are formed using various deposition and metallization processes (described in more detail below in connection with the process flow shown in FIG. 3). Figures 6A-6K The process flow shown in FIG. 3 describes this aspect of the present application in more detail.

[0042] The first interconnect dielectric layer ILD1 can be composed of any interconnect dielectric material including, for example, silicon oxide (SiOx), silicon nitride (SiNx), SiCOH, SiNCH, SiCN, SiCNO, SiNCOH, silsesquioxane, C-doped oxides including Si, C, O, and H atoms (i.e., organosilicates), thermoset polyarylene ethers, or multilayers thereof. The term “polyarylene” is used in this application to mean aryl moieties or inertly substituted aryl moieties linked together by bonds, fused rings, or inert linking groups such as oxygen, sulfur, sulfone, sulfoxide, carbonyl, and the like. The first interconnect dielectric layer ILD1 can have a dielectric constant of about 4.0 or less (all dielectric constants mentioned herein are measured relative to vacuum unless otherwise specified). In one embodiment, the first interconnect dielectric layer ILD1 has a dielectric constant of 2.8 or less. These dielectrics generally have lower parasitic cross-talk compared to dielectric materials having a dielectric constant greater than 4.0.

[0043] In some embodiments of the application, each of the plurality of via structures 30 (via structures can also be labeled as Vx-1, as shown in Figure 4 and 5 In some embodiments of the application, each of the plurality of via structures 30 (via structures can also be labeled as Vx-1, as shown in

[0044] In some embodiments, a diffusion barrier liner (not shown) can be present at least along sidewalls (in some embodiments, along a bottom wall) of each of the plurality of via structures 30, when present, the diffusion barrier liner can be composed of any known diffusion barrier material such as Ta, TaN, Ti, TiN, W, or WN. In some embodiments, the diffusion barrier liner can include a material stack of two or more diffusion barrier materials. In one example, the diffusion barrier liner can be composed of a Ta / TaN stack or a Ti / TiN stack.

[0045] The plurality of interconnect layers 32Y and 32Z and the at least one SOT layer 32X present in the first interconnect dielectric layer ILD1 are all composed of topologically identical topological conductors. In embodiments of the present application, the topological conductors that provide each of the interconnect layers 32Y and 32Z and the at least one SOT layer 32X are either compositionally identical to or compositionally different from the topological conductors that can be used in certain embodiments of the present application to provide the via structure 30, the term "topological conductor" is used herein to define a conductive material (i.e., a topological metal or a topological semimetal) whose nontrivial bulk band structure topology guarantees the existence of a conductive surface state with suppressed carrier scattering, such that the surface conductivity is much larger (two-fold or more) than the bulk (i.e., the portion of the material below the surface of the material) conductivity of the material. Topological conductors generally have high charge-to-spin current conversion efficiency, and thus, they are good spin current sources and can be used as SOT materials.

[0046] In the present application, the topological conductors (i.e., topological metals or topological semimetals) that can be used are classified according to the dimensionality of their band crossings and their band degeneracy at the band crossings. Topological conductors with 0D band crossings include Weyl semimetals and multi-Weyl semimetals. The former have a 2-fold band degeneracy, while the latter can have a 3-, 4-, 6-, or 8-fold band degeneracy at the nodes. Nonmagnetic, noncentrosymmetric Weyl semimetals include TaAs, TaP, NbAs, NbP, (Mo, W)Te2, LaAlGe, and TaIrTe4. Magnetic Weyl semimetals include Co3Sn2S2, Mn 3+x Sn 1-x , EuCd2As2, RAlGe (where R is a rare-earth metal), and PrAlGe. Multi-fold Weyl semimetals include CoSi, RhSi, CoGe, RhGe, and AlPt. Double-Weyl semimetals can also be used in some embodiments of the present application.

[0047] Weyl nodes and Fermi arcs also exist in nonmagnetic chiral crystals with relevant spin-orbit coupling. Candidates for these so-called Kramers-Weyl Fermion topological semimetals include Ag3BO3 (SG-156), T1Te2O6 (SG-150), Ag2Se (SG-19), and the like, where SG = space group.

[0048] Topological conductors with 1D band crossings are referred to as topological nodal-line semimetals. These semimetals include Co2MnGa and XY4 crystals (X = Ir, Ta, Re; Y = F, Cl, Br, I) whose lattices are formed by octahedra, similar to IrF4.

[0049] Besides the aforementioned topological materials, another type of usable topological conductor is the three-point topological metal. These are characterized by a topologically protected Weyl node across three frequency bands, two of which degenerate along a high-symmetry direction in the Brillouin zone. They differ from topological half-metals in that the band gap between the conduction and valence bands closes along this high-symmetry line. Examples of three-point topological metals include WC, MoC, MoP, MoN, and ZrTe.

[0050] Unlike topological insulators, topological conductors exhibit significantly higher carrier densities at the Fermi level, along with high carrier mobility, resulting in high current-carrying capacity. With topological half-metals reaching sizes below approximately 10 nm, carrier transport via the Fermi-arc states becomes significant, potentially surpassing bulk transport. Depending on the type of impurity scattering and the type of topological half-metal, significant surface-state transport can persist up to approximately 100 nm.

[0051] If the film thickness exceeds the material-dependent threshold, such as approximately 2.5 nm in CoSi, electron transport through the Fermi arc state is robust against defects and impurities, ensuring high electron mobility at the Fermi arc surface, even at very small thicknesses. Furthermore, bulk electron scattering is generally suppressed because multiple bands across the Weyl node are orthogonal to each other, ensuring high electron mobility near the Weyl node. These considerations imply that topological conductors with (1) high Chern numbers, (2) many pairs of Weyl nodes, and (3) very few or no topologically insignificant large-volume bands near the Fermi level are preferred application materials.

[0052] As an example, the Weyl half-metal NbAs exhibits a lower resistivity (1–5 μΩ-cm) at the submicron scale than its bulk resistivity (approximately 35 μΩ-cm), resulting in a potential reduction of more than 50% in the resistance-capacitance product (RC) at the 5 nm node size. Extremely low resistivity is also observed in the topological metal MoP (~9 nΩ-cm at 2 K, 8.2 μΩ-cm at 300 K). For comparison, the bulk resistivity of Cu is approximately 2 μΩ-cm, increasing to approximately 15 μΩ-cm at the 15–18 nm scale.

[0053] As described above, the topological conductors that can be used in this application include, but are not limited to, Weyl half-metals such as NbAs, TaAs, NbP, TaP, and (Mo, W)Te2; multi-fermion systems such as RhSi and CoSi; and magnetic Weyl half-metals such as Co3Sn2S2 and Mn2. 3+x Sn 1-x PrAlGe, etc.; Kramers-WeylFermionns Ag2Se, etc., and three-point topological metals MoP, WC, etc.

[0054] Figure 1 The structure shown in FIG. 1 also includes MTJ structures 38P located in memory device region Al. The MTJ structures 38P form an interface with the SOT layer 32X. The MTJ structures 38P are stacks comprising patterned magnetic material including a magnetic free layer, a tunnel barrier layer, a magnetic reference layer, and an electrode layer. Other magnetic and non-magnetic layers can be present in the patterned magnetic material-containing stack that provides the MTJ structures 38P. In some embodiments, the patterned magnetic material-containing stack that provides the MTJ structures 38P includes, from bottom to top, a magnetic free layer, a tunnel barrier layer, a magnetic reference layer, and an electrode layer. In other embodiments, the patterned magnetic material-containing stack that provides the MTJ structures 38P includes, from bottom to top, an electrode layer, a magnetic reference layer, a tunnel barrier layer, and a magnetic free layer; this embodiment would require a complete inversion of the memory structure such that the SOT layer 32X is located above the MTJ structures 38P. In this application, the magnetic free layer of the MTJ structures 38P forms an interface with the SOT layer 32X.

[0055] The magnetic free layer is composed of at least one magnetic material having a magnetization that can change orientation relative to the magnetization orientation of the magnetic reference material. Exemplary magnetic materials for the magnetic free layer include, but are not limited to, alloys and / or multilayers of cobalt, iron, cobalt-iron alloys, nickel-iron alloys, and cobalt-iron-boron alloys. The magnetic free layer can have a thickness from 0.3 nm to 3 nm; although other thicknesses are possible and can be used as the thickness of the magnetic free layer.

[0056] The tunnel barrier layer includes a tunnel barrier material. The tunnel barrier material is formed in a thickness that provides an appropriate tunneling resistance. Tunnel barrier materials that can be used in this application include, but are not limited to, magnesium oxide, aluminum oxide, and titanium oxide, or materials of higher electrical tunneling conductance, such as semiconductors or low band gap insulators. The thickness of the tunnel barrier layer will depend on the material selected. In one example, the thickness of the tunnel barrier layer can be 0.5 nm to 1.5 nm; although other thicknesses are possible as long as the thickness of the tunnel barrier layer provides an appropriate tunneling resistance.

[0057] The magnetic reference layer is composed of a magnetic material having a fixed magnetization. The magnetic material providing the magnetic reference layer is composed of a metal or metal alloy including one or more metals that exhibit high spin polarization. In alternative embodiments, exemplary metals for forming the magnetic reference layer include iron, nickel, cobalt, chromium, boron, and manganese. Exemplary metal alloys can include those of the above-mentioned metals. In another embodiment, the magnetic reference layer can be a multilayer arrangement having (1) a high spin polarization region formed of a metal and / or metal alloy using the above-mentioned metals, and (2) a region constructed of one or more materials that exhibit strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials that can be used that have strong PMA include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and can be arranged as alternating layers. The strong PMA region can also include alloys that exhibit strong PMA, exemplary alloys include cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloys can be arranged as alternating layers. In one embodiment, combinations of these materials and regions can also be employed. In another embodiment, combinations of these materials and regions can form a synthetic antiferromagnetic layer to pin the magnetization of the magnetic reference layer. The magnetic reference layer can have a thickness of 0.3 nm to 30 nm; although other thicknesses are possible and can be used as the thickness of the magnetic reference layer.

[0058] The electrode layer is composed of a conductive material, such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The electrode layer can have a thickness of 5 nm to 100 nm; other thicknesses are possible and can be used as the thickness of the electrode layer in this application.

[0059] The MTJ structure 38P can be formed by deposition and patterning. Deposition includes one or more deposition processes including, but not limited to, CVD, PECVD, PVD, atomic layer deposition (ALD) including plasma enhanced ALD, or sputtering. Patterning can include reactive ion etching or ion beam etching (IBE).

[0060] Figure 1 The structure shown in FIG. 4A can further include an encapsulation liner 40L located on the ILD 1 and laterally surrounding the MTJ structure 38P. The encapsulation liner 40L includes one of the dielectric materials described above for the dielectric cap layer 19, and can be formed by depositing a dielectric material and then removing the dielectric material that provides the encapsulation liner 40L formed on top of the MTJ structure 38P. The removal of this dielectric material formed on top of the MTJ structure 38P can be performed during the formation of the contact structures 44B and 44D.

[0061] Figure 1 The structure shown in FIG. 4A further includes contact structures 44B and 44D. In some embodiments, as shown in FIG. 4A, the contact structures 44B and 44D are formed by depositing a conductive material and then removing the conductive material that provides the contact structures 44B and 44D formed on top of the MTJ structure 38P. The removal of this conductive material formed on top of the MTJ structure 38P can be performed during the formation of the encapsulation liner 40L.Figure 3 , 4 and 6K, contact structures 44A and 44C can also be formed. Contact structure 44B provides an upper metal layer contact to MTJ structure 38P; thus, contact structure 44B can be referred to herein as an MTJ contact structure. Contact structure 44B forms an interface with MTJ structure 38P. Contact structure 44D provides an upper metal layer contact to interconnect layer 32Z present in the non-memory device region. Contact structure 44D can be referred to as a non-memory interconnect contact structure.

[0062] When contact structure 44A is present, contact structure 44A provides an upper metal layer contact to SOT layer 32X formed in memory device region A1. Thus, contact structure 44A can be referred to herein as an SOT contact structure. In some embodiments, contact structure 44A (i.e., the SOT contact structure) includes a via portion V x+1 filled with the same material as contact structure 44A. In such embodiments, the via portion V x+1 of contact structure 44A forms an interface with SOT layer 32X (see, e.g., Figs. Figure 5 and 6K ). In other embodiments, a via structure 31 composed of a different conductive material than contact structure 44A forms the interface with SOT layer 32X (see, e.g., Fig. Figure 3 ).

[0063] When contact structure 44C is present, contact structure 44C provides an upper metal layer contact to interconnect layer 32Y formed in non-memory device region A2 (see, e.g., Fig. Figure 6K ). Thus, contact structure 44C can be referred to herein as an interconnect contact structure. In Figure 6K embodiments, contact structure 44C includes a via portion V x+1 . Via portion V x+1 may be composed of the same or a different material than contact structure 44C.

[0064] In this application, contact structures 44A, 44B, 44C, and 44D are composed of a conductive metal, a conductive metal alloy, or a topological conductor as described above. The topological conductor providing contact structures 44A, 44B, 44C, and 44D can be the same or different in composition from the topological conductor providing interconnect layers 32Y, 32Z, and SOT layer 32X. In embodiments, each via portion V x+1The materials can be made of the same or different compositions from those selected from the conductive metals, conductive metal alloys, or topological conductors described above. In embodiments including the second via structure 31, the second via structure 31 can be made of a material with a different composition from the overlying and connected conductive structure. For example, contact structure 44A can be made of a topological conductor, while the second via structure 31 can be made of Cu. Each contact structure 44A, 44B, 44C, and 44D is formed using a metallization process.

[0065] Figure 1 The structure also includes a second interconnect dielectric layer ILD2. The second ILD layer ILD2 includes at least one dielectric material used for the first interconnect dielectric layer ILD1. The second interconnect dielectric layer ILD2 is embedded in at least a portion of each of the conductive contact structures 44A, 44B, 44C, and 44D. The second interconnect dielectric layer ILD2 is formed by a deposition process, such as CVD, PECVD, ALD, or spin coating. In this application, the second interconnect dielectric layer ILD2 is typically formed prior to the formation of the contact structures 44A, 44B, 44C, and 44D.

[0066] In short, Figure 1 The structure shown includes a memory device region A1. It includes a memory structure located therein, comprising an SOT layer 32X and an interconnect layer 32Y situated on the same metal layer as the BEOL structure. Both the SOT layer 32X and the interconnect layer 32Y are composed of topological conductors. An MTJ structure 38P is located on the SOT layer 32X, and an MTJ contact structure 44B is located on the MTJ structure 38P. In addition to the memory device region A1, the structure also includes a non-memory device region A2 located adjacent to the memory device region A1. The non-memory device region A2 includes another interconnect layer 32Z, situated on the same metal layer as the SOT layer 32X and the interconnect layer 32Y, and this other interconnect layer 32Z is ​​composed of topological conductors.

[0067] Now for reference Figures 2-5 It illustrates other SOT MRAM devices according to this application, which can be used as Figure 1 The alternative to the SOT MRAM device shown is noteworthy. Figure 2 The SOT MRAM device shown includes an SOT layer 32X, a via structure 30 located below the SOT layer 32X, an MTJ structure 38P located on top of the SOT layer 32X, a contact structure 44B located on the MTJ structure 38P, a contact structure 44A located on one side of the MTJ structure 38P, and a via structure 31 connecting the contact structure 44A to the SOT layer 32X. Figure 3The SOT MRAM device shown includes an SOT layer 32X, an MTJ structure 38P on top of the SOT layer 32X, a contact structure 44B on the MTJ structure 38P, a contact structure 44A on each side of the MTJ structure 38P, and a via structure 31 electrically connecting each contact structure 44A to the SOT layer 32X. Figure 4 The SOT MRAM device shown includes a via portion V x-1 The SOT layer 32X. Here, the SOT layer 32X and the via portion V x-1 It has a single structure and is composed of the same topological conductors. Figure 4 The SOT MRAM device shown also includes an MTJ structure 38P on top of the SOT layer 32X and a contact structure 44B on the MTJ structure 38P. Figure 5 The SOT MRAM device shown is similar to Figure 3 The SOT MRAM device shown, except for the via structure 31 which is covered by the via portion V x+1 Instead. Here, electrical contact structure 44A and via portion V x+1 It has an integral structure and is made of the same material, namely, a conductive metal, a conductive metal alloy, or a topological conductor as described above.

[0068] Now for reference Figures 6A-6K This paper illustrates a method that can be used to form an SOT MRAM device according to an embodiment of this application. Figures 6A-6K The method shown in the document is only applicable to... Figure 1 Within the memory device region A1 depicted. It is worth noting that... Figure 6A It is shown to include at least one first conductive structure 22 embedded in the first interconnect dielectric layer 20 (two of which are in Figure 6A The interconnect level is shown as an example.

[0069] The first dielectric layer 20 may be composed of one of the interconnect dielectric materials mentioned above for ILD1. The first dielectric layer 20 may be formed by a deposition process, such as CVD, PECVD, ALD, sputtering, or spin coating. The first dielectric layer 20 may have a thickness from 50 nm to 250 nm. Other thicknesses less than 50 nm and greater than 250 nm may also be used as the thickness of the first interconnect dielectric layer 20 in this application.

[0070] The first conductive structure 22 may be made of a conductive metal, a conductive metal alloy, or a topological conductor. In some embodiments, a diffusion barrier pad (not shown) may be present at least along the sidewalls of the via structure 22 (or, in some embodiments, along the bottom wall), and the diffusion barrier pad includes one of the aforementioned diffusion barrier materials.

[0071] Figure 6A The structural example shown can first deposit a first dielectric layer 20, the first deposition step can include, for example, CVD, PECVD, ALD, sputtering, or spin-on. Next, at least one contact opening is formed in the first dielectric layer 20 by photolithography and etching. Photolithography includes forming a photoresist material on a surface of a material layer or structure that needs to be patterned, exposing the deposited photoresist material to a pattern of radiation, and then developing the exposed photoresist material. The etching used in providing the at least one contact opening into the first dielectric layer 20 can include a dry etching process (i.e., reactive ion etching, plasma etching, or ion beam etching) or a chemical wet etching. Next, if a diffusion barrier material layer is present, a diffusion barrier material layer can be formed in the at least one via opening and on top of the first dielectric layer 20, the formation of the diffusion barrier material layer including a deposition process, such as CVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD). The diffusion barrier material layer does not fill all of the at least one contact opening. Next, one of the above-described conductive materials (e.g., Cu) is then deposited on the diffusion barrier material layer. The deposition of the conductive material can include CVD, PECVD, PVD, ALD, sputtering, or electroplating. A planarization process, such as chemical mechanical polishing (CMP), is then performed to remove the diffusion barrier material layer (if present) and the conductive material or topological semimetal formed on top of the first dielectric layer 20 outside of the at least one opening, after the planarization process, the conductive material and the diffusion barrier material layer (if present) remain in the opening. The conductive material remaining in the opening provides at least one first conductive structure 22, and if present, the diffusion barrier material layer remaining in the opening provides a diffusion barrier liner (not shown) in Figure 6A In embodiments of the present application, the at least one first conductive structure 22 has a top surface that is coplanar with at least a top surface of the first interconnect dielectric layer 20; if the diffusion barrier liner is present, the topmost surface of the at least one first conductive structure 22 can also be coplanar with a topmost surface of the diffusion barrier layer as well as with a topmost surface of the first dielectric layer 20.

[0072] Reference is now made to Figure 6B , which shows the interconnect level shown in Figure 6A after formation of a dielectric cap material layer 24 and a second dielectric layer 26 on the interconnect level. As shown, the dielectric cap material layer 24 is on the first dielectric layer 20 and the at least one conductive structure 22, while the second dielectric layer 26 is on the dielectric cap layer 24, in some embodiments (not shown) the formation of the dielectric cap layer 24 can be omitted.

[0073] When present, the dielectric cap layer 24 comprises one of the dielectric materials described above for the dielectric cap layer 19, and the dielectric material providing the dielectric cap layer 24 can have a thickness of 10 nm to 200 nm. Other thicknesses are also possible, and as the thickness of the dielectric material providing the dielectric cap layer 24, the dielectric cap layer 24 can be formed using a deposition process such as CVD, PECVD, ALD, sputtering, or spin coating.

[0074] The second dielectric layer 26, shown on the interconnect level if the dielectric cap layer 24 is not present, comprises one of the dielectric materials mentioned above for the ILD 1, and the dielectric material providing the second dielectric layer 26 can be the same or different in composition from the dielectric material providing the first interconnect dielectric layer 20, and the dielectric material providing the second dielectric layer 26 is different in composition from the dielectric cap layer 24, and the second dielectric layer 26 can be formed using a deposition process such as CVD, PECVD, ALD, sputtering, or spin coating. Figure 6A The second dielectric layer 26, shown on the interconnect level if the dielectric cap layer 24 is not present, comprises one of the dielectric materials mentioned above for the ILD 1, and the dielectric material providing the second dielectric layer 26 can be the same or different in composition from the dielectric material providing the first interconnect dielectric layer 20, and the dielectric material providing the second dielectric layer 26 is different in composition from the dielectric cap layer 24, and the second dielectric layer 26 can be formed using a deposition process such as CVD, PECVD, ALD, sputtering, or spin coating.

[0075] Reference is now made to Figure 6C , which shows the exemplary structure after formation of at least one via opening 28 (two of which are shown by way of example) in the dielectric material stack of the second dielectric layer 26 and the dielectric cap layer 24. Figure 6C Reference is now made to Figure 6B , which shows the exemplary structure after formation of a via structure 30 in each via opening 28. As shown, each via opening 28 physically exposes a surface of the underlying first conductive structure 22, and such at least one via opening 28 can be formed by lithography and etching. A cleaning step can be used to clean the physically exposed surface of the underlying metal-containing structure.

[0076] Reference is now made to Figure 6D , which shows the exemplary structure after formation of a via structure 30 in each via opening 28. As shown, each via opening 28 physically exposes a surface of the underlying first conductive structure 22, and such at least one via opening 28 can be formed by lithography and etching. A cleaning step can be used to clean the physically exposed surface of the underlying metal-containing structure. Figure 6C In some embodiments, in addition to the via structure 30, a diffusion barrier liner (not shown) can be present in each via opening 28, and when present, the diffusion barrier liner is present along the sidewalls and the bottom wall of the via structure 30, the via structure 30 comprises one of the conductive metals or metal alloys described above for the at least one first conductive structure 22, and the optional diffusion barrier liner comprises one of the diffusion barrier materials described above. In some embodiments, the via structure 30 is composed of a topological conductor as defined above. The via structure 30 can be formed using a metallization process (deposition followed by planarization) as described above in forming the first conductive structure 22. Each via structure 30 has a topmost surface that is generally coplanar with at least the topmost surface of the second interconnect dielectric layer 26.

[0077] Reference is now made to Figure 6E , which shows the exemplary structure after formation of a topological conductor layer 32. As shown, the topological conductor layer 32 is formed on the second dielectric layer 26 and the dielectric cap layer 24, and the topological conductor layer 32 comprises one of the conductive metals or metal alloys described above for the at least one first conductive structure 22. The topological conductor layer 32 can be formed using a deposition process such as CVD, PECVD, ALD, sputtering, or spin coating. Figure 6DThe exemplary structure shown is illustrated. As shown, a topological conductor layer 32 is formed on the physically exposed uppermost surface of the second interconnect dielectric layer 26 and on the physically exposed uppermost surface of each via structure 30. The topological semi-metallic conductor 32 comprises one of the topological materials mentioned above. The topological conductor layer 32 can be formed using deposition processes such as CVD, PECVD, ALD, sputtering, or molecular beam epitaxy (MBE). In one example, the topological conductor layer 32 is composed of CoSi sputtered from a Co-Si target at a temperature between 250°C and 550°C, and the topological conductor layer 32 can have a thickness from 3 nm to 50 nm. Other thicknesses less than 3 nm and greater than 50 nm can also be used as the thickness of the topological conductor layer 32 in this application.

[0078] Now for reference Figure 6F This illustrates the process after patterning the topological conductor layer 32 to have openings 34. Figure 6E In the exemplary structure shown, opening 34 physically exposes the surface of the underlying second dielectric layer 26. Opening 34 can be formed by photolithography and etching. In this invention, one of the remaining (unetched) portions of the topological conductor layer 32 not located above the via structure 30 will serve as the SOT layer 32X, while the other remaining portion of the topological conductor layer 32 located above the via structure 30 will serve as the interconnect layer 32Y. In the exemplary structure, the SOT layer 32X and the adjacent interconnect layer 32Y, both composed of the same topological conductor, are located on the same metal layer.

[0079] Now for reference Figure 6G It shows the result after forming a dielectric material plug 36 in the opening 34. Figure 6F In the exemplary structure shown, a dielectric plug 36 separates the sidewalls of the SOT layer 32X from the sidewalls of the interconnect layer 32Y, and the dielectric plug 36 is formed to be in direct physical contact with the surface of the underlying and previously physically exposed second dielectric layer 26. The dielectric plug 36 comprises a dielectric material that is compositionally the same as or different from the dielectric material providing the second dielectric layer 26. Typically, the dielectric material providing the dielectric plug 36 is compositionally the same as the dielectric material providing the second dielectric layer 26. The dielectric plug 36 can be formed by depositing (e.g., CVD, PECVD, ALD, or spin coating) the dielectric material, followed by a planarization process. Sputter cleaning can be performed after the planarization process. The dielectric plug 36 typically has an uppermost surface that is coplanar with the uppermost surfaces of both the SOT layer 32X and the interconnect layer 32Y.

[0080] Now for reference Figure 6H This illustrates the formation of a stack 38 of magnetic materials after the formation of a capping layer comprising a magnetic free layer material capping layer, a tunnel barrier material capping layer, a magnetic reference layer material capping layer, and an electrode material capping layer. Figure 6GThe uniform layer of electrode material will then be patterned and used as an etch mask for the remaining uniform layers of the stack 38 containing magnetic material, noting that other magnetic and non-magnetic materials commonly present in MTJ structures can be formed in the stack 38 containing magnetic material as described in Figure 6H

[0081] The above has been described with respect to Figure 1 Each of the magnetic free layer material, tunnel barrier material, magnetic reference layer material, and electrode material used herein to form the stack 38 containing magnetic material, as described above and as illustrated in the exemplary structure of Figure 6H

[0082] Referring now to Figure 6I , it is explained that after patterning the stack 38 containing magnetic material to provide the MTJ structure 38P Figure 6H The exemplary structure illustrated in FIG. 3B. The MTJ structure 38P is directly on the uppermost surface of the SOT layer 32X. The MTJ structure includes the remaining (i.e., unpatterned) portions of the stack 38 containing magnetic material described above. That is, the MTJ structure contains the remaining portions of the overlayer of magnetic free layer material, the overlayer of tunnel barrier material, the overlayer of magnetic reference layer material, and the remaining locations of electrode material.

[0083] ​​The patterning of the magnetic material-containing stack 38 includes a photolithography process in which a patterned resist (not shown) is formed on the topmost surface of the top electrode material of the magnetic material-containing stack 38, which can be formed by depositing a photoresist material, exposing the photoresist material to a desired pattern of illumination, and developing the exposed photoresist material. The patterned resist protects a portion of the blanket layer of electrode material while leaving other portions of the blanket layer of top electrode material physically exposed. The physically exposed portions of the blanket layer of top electrode material are removed in an initial transfer etch. After the initial transfer etch, the patterned resist is removed using a conventional resist removal process, such as ashing. The patterning is continued with another etch, in which the remaining portions of electrode material serve as an etch mask for the remaining patterning process. This other etch stops on the surface of the SOT layer 32X. This other etch removes the remaining portions of the magnetic material-containing stack 38 that are not covered by the remaining portions of the top electrode material. The transfer etch and the subsequently performed etch can include ion beam etching, reactive ion beam etching, or any combination thereof. The transfer etch can be the same as or different from the other etch used in this patterning step. For example, the transfer etch can include reactive ion etching, while the other etch can include ion beam etching.

[0084] In some embodiments of the present application, Figure 6I The exemplary structure shown in FIG. 3A can be subjected to an oxygen treatment process or any other gas treatment process or etching process in order to remove any unwanted metal particles that can have been redeposited on the sidewalls of the MTJ structure 38P during this patterning.

[0085] Referring now to Figure 6J illustrates the exemplary structure after forming a cap layer 40 and a third interconnect dielectric layer 42 Figure 6I The exemplary structure shown in FIG. 3A, the cap layer 40 surrounds the MTJ structure 38P and is present on the SOT layer 32X, the dielectric material plug 36, and the interconnect layer 32Y. The cap layer 40 includes one of the materials previously mentioned herein for the cap liner 40L. The cap layer 40 can have a thickness from 3 nm to 200 nm. Other thicknesses are also possible and can be used as the thickness of the cap layer 40.

[0086] The third dielectric layer 42 formed on the cap layer 40 can include one of the dielectric materials mentioned above for the ILD 1, the dielectric material providing the third dielectric layer 42 can be the same or different in composition from the dielectric material providing the first dielectric layer 20 and / or the second dielectric layer 26, the third dielectric layer 42 can be formed using one of the deposition processes mentioned above for forming the first dielectric layer 20.

[0087] Referring now to Figure 6K illustrates the exemplary structure after forming contact structures 44A, 44B, and 44CFigure 6J The exemplary structures shown in FIGS. 1-3. In this application, contact structure 44A is in contact with a surface of SOT layer 32X, contact structure 44B is in contact with a surface of MTJ structure 38P (typically in contact with the remaining top electrode material portion of MTJ structure 38P), and contact structure 44B is in contact with a surface of interconnect layer 32Y. Each of contact structures 44A, 44B, and 44C can include a diffusion barrier liner as described above. Each of contact structures 44A, 44B, and 44C includes a conductive metal, a conductive metal alloy, or a topological semimetal as described above. Each of contact structures 44A, 44B, and 44C is formed using a metallization process as described above in forming first conductive structure 22. As shown in FIG. 3, contact structures 44A and 44C include via portions labeled V Figure 6K X+1

[0088] While the application has been particularly shown and described with reference to particular embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the scope of the application. Accordingly, the disclosed application is to be considered merely as illustrative and not restrictive, and the scope of the application is to be determined by the appended claims.​​

Claims

1. A memory structure comprising: a spin orbit torque (SOT) layer and an interconnect layer, the SOT layer and the interconnect layer being located at a same metal level of a back end of line (BEOL) structure, wherein both the spin orbit torque (SOT) layer and the interconnect layer are composed of a topological conductor; a magnetic tunnel junction (MTJ) structure having a magnetic free layer forming an interface with the SOT layer; and an MTJ contact structure contacting the MTJ structure.

2. The memory structure of claim 1, wherein the topological conductor comprises a material selected from a metal or a semimetal, wherein the metal or semimetal has a band-structure-protected conducting surface state, wherein a surface conductivity of the conducting surface state is greater than a bulk conductivity of the metal or semimetal.

3. The memory structure of claim 2, wherein the topological conductor comprises a Weyl semimetal, a multifold fermion semimetal, a magnetic Weyl semimetal, a Kramers-Weyl fermion semimetal, or a three-dimensional topological metal.

4. The memory structure of any preceding claim, wherein the MTJ structure comprises, from bottom to top, the magnetic free layer, a tunnel barrier layer, a magnetic reference layer, and an electrode layer.

5. The memory structure of any preceding claim, wherein the MTJ structure comprises, from bottom to top, an electrode layer, a magnetic reference layer, a tunnel barrier layer, and the magnetic free layer.

6. The memory structure of any preceding claim, wherein the MTJ contact structure is composed of a conductive metal, a conductive metal alloy, or another topological conductor.

7. The memory structure of any preceding claim, wherein the SOT layer and the interconnect layer are separated by an interconnect dielectric layer.

8. The memory structure of any preceding claim, further comprising an SOT contact structure electrically connected to the SOT layer by a via structure.

9. The memory structure of claim 8, wherein the SOT contact structure comprises a conductive metal, a conductive metal alloy, or another topological conductor, wherein the other topological conductor is the same or different in composition from the topological conductor providing the SOT layer and the interconnect layer.

10. The memory structure of any preceding claim, further comprising an SOT contact structure electrically connected to the SOT layer by a via portion of the SOT contact structure.

11. The memory structure of claim 10, wherein the SOT contact structure comprises a conductive metal, a conductive metal alloy, or another topological conductor, wherein the other topological conductor is the same or different in composition from the topological conductor providing the SOT layer and the interconnect layer.

12. The memory structure of any preceding claim, further comprising at least one via structure contacting a bottommost surface of the SOT layer. ​ 13. The memory structure of claim 12, wherein the at least one via structure is composed of a conductive metal, a conductive material alloy, or another topological conductor that is the same in composition as the topological conductor providing the SOT layer and the interconnect layer or is different in composition.

14. The memory structure of any one of the preceding claims, wherein the SOT layer further comprises at least one via portion located on a side of the SOT layer opposite a side of the SOT layer in contact with the MTJ structure, wherein both the SOT layer and the at least one via portion are composed of the topological conductor.

15. The memory structure of any one of the preceding claims, further comprising a via structure located below the interconnect layer.

16. The memory structure of any one of the preceding claims, wherein the SOT layer is electrically connected to a source / drain region of a transistor.

17. A structure comprising: a memory device region comprising a memory structure located therein, the memory structure comprising a spin orbit torque (SOT) layer and an interconnect layer located at a same metal level of a back end of line (BEOL) structure, wherein both the spin orbit torque (SOT) layer and the interconnect layer are composed of a topological conductor, a magnetic tunnel junction (MTJ) structure having a magnetic free layer forming an interface with the SOT layer, and an MTJ contact structure contacting the MTJ structure; and a non-memory device region adjacent to the memory device region, the non-memory device region comprising another interconnect layer, wherein the another interconnect layer is located at the same metal level as both the SOT layer and the interconnect layer, and the another interconnect layer is composed of the topological conductor.

18. The structure of claim 17, wherein the topological conductor comprises a material selected from a metal or a semimetal, wherein the metal or semimetal has a band-structure-protected conductive surface state with a surface conductivity greater than a bulk conductivity of the metal or semimetal.

19. The structure of claim 18, wherein the topological conductor comprises a Weyl semimetal, a multifold fermion semimetal, a magnetic Weyl semimetal, a Kramers-Weyl fermion semimetal, or a three-dimensional topological metal.

20. The structure of any one of the preceding claims, wherein the SOT layer is electrically connected to a source / drain region of a transistor located in the memory device region, and the another interconnect layer is electrically connected to a source / drain region of a transistor located in the non-memory device region.

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