BiSb topological insulator with seed layer or interlayer to prevent Sb diffusion and promote BiSb (012) orientation

Abstract

A spin orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a seed layer over the substrate, and a bismuth antimony (BiSb) layer having a (0120) orientation on the seed layer. The seed layer includes a silicide layer and a surface control layer. The silicide layer includes a material of NiSi, NiFeSi, NiFeTaSi, NiCuSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, or a combination thereof. The surface control layer includes a material of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, or a combination thereof, where M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Application No. 16 / 861,118, filed April 28, 2020, which is incorporated herein by reference in its entirety. Background Technology Technical Field

[0004] The embodiments disclosed herein generally relate to a bismuth-antimony (BiSb) topological insulator having a seed layer and / or interlayer to prevent Sb diffusion and promote BiSb(012) orientation.

[0005] Description of related fields

[0006] BiSb with (012) orientation is a narrow-gap topological insulator with giant spin Hall effect and high conductivity. BiSb is a material proposed for various spin-orbit torque (SOT) magnetic tunnel junction (MTJ) applications, such as spin Hall layers for energy-assisted magnetic recording write heads and magnetoresistive random access memory (MRAM) devices.

[0007] However, BiSb materials have not yet been used in commercial SOT applications due to several obstacles. For example, BiSb materials are generally soft, have a low melting point, large grain size, are easily damaged by ion milling, and exhibit significant Sb migration problems during hot annealing due to their film roughness, and it is difficult to maintain the (012) orientation to obtain the maximum spin Hall effect.

[0008] Therefore, there is a need for an improved SOT MTJ device and method that includes a BiSb layer with (012) orientation. Summary of the Invention

[0009] The embodiments disclosed herein generally relate to a bismuth-antimony (BiSb) topological insulator having a seed layer and / or interlayer to prevent Sb diffusion and promote BiSb(012) orientation.

[0010] In one embodiment, the spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a seed layer above the substrate, and a bismuth-antimony (BiSb) layer with a (012) orientation on the seed layer. The seed layer includes a silicide layer and a surface control layer. The silicide layer comprises a material of NiSi, NiFeSi, NiFeTaSi, NiCuSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, or combinations thereof. The surface control layer comprises a material of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, or combinations thereof, wherein M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si.

[0011] In another embodiment, the SOT MTJ device includes a substrate and a BiSb layer having a (012) orientation on the substrate. An interlayer is located above the BiSb layer. The interlayer includes a silicide layer. The silicide layer comprises a material of NiSi, FeSi, CoSi, NiCuSi, NiCoSi, NiFeTaSi, CoCuSi, or a combination thereof.

[0012] In another embodiment, the SOT MTJ device includes a substrate, a seed layer above the substrate, and a BiSb layer with a (012) orientation on an amorphous film. The seed layer comprises an amorphous film, the nearest neighbor peak spacing of which is the same as that on the surface of the amorphous film. to The (111) interplanar spacing of the fcc lattice with the a-axis within the range is matched, or to The (002) interplanar spacing of the hcp lattice with the a-axis within the range is matched. Attached Figure Description

[0013] Therefore, a detailed understanding of the foregoing features of this disclosure, a more specific description of this disclosure, and the foregoing brief overview can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should therefore not be considered as limiting its scope, as this disclosure allows for other equally effective embodiments.

[0014] Figures 1A to 1E This is a schematic cross-sectional view of some embodiments of an SOT MTJ device, which has a BiSb layer with (012) orientation formed on a substrate.

[0015] Figure 2This is a schematic plan view showing some embodiments of a BiSb layer with a seed layer or interlayer having a (012) orientation.

[0016] Figure 3 This is a schematic diagram of some implementations of a magnetic media driver including an EAMR write head.

[0017] Figure 4 This is a partial cross-sectional side view of a read / write head facing a magnetic medium according to certain implementation schemes.

[0018] Figure 5 This is a schematic diagram of the MFS for some implementations of a part of the EAMR write head.

[0019] Figures 6 to 8 The X-ray diffraction (XRD) 2θ scan of a sample including a BiSb layer with (012) orientation is shown.

[0020] Figure 9 and Figure 10 The surface roughness measurements of the BiSb layer above the seed layer of different materials are shown.

[0021] Figure 11 and Figure 12 X-ray diffraction (XRD) 2θ scan of a sample including a BiSb layer with (012) orientation is shown.

[0022] Figure 13 and Figure 14 The diagram shows the relationship between the amorphous peak lattice spacing and composition of various metal alloys.

[0023] Figure 15 This is a schematic diagram of some implementations of a storage cell array configured at an intersection.

[0024] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the accompanying drawings. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0025] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, consider any combination of the following features and elements (whether or not related to different embodiments) to achieve and practice this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a particular advantage is achieved by a given embodiment is not a limitation of this disclosure. Therefore, the following aspects, features, embodiments, and advantages are illustrative only and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims.

[0026] Certain embodiments of this disclosure generally relate to a seed layer for promoting the growth of a bismuth-antimony (BiSb) layer with a (012) orientation. The (012)-oriented BiSb layer exhibits a large spin Hall angle effect and high conductivity. The (012)-oriented BiSb layer can be used to form spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices. For example, the (012)-oriented BiSb layer can be used as a spin Hall layer in a spin-orbit torque device with an energy-assisted magnetic recording (EAMR) write head. As another example, the (012)-oriented BiSb layer can serve as a spin Hall electrode layer in a magnetoresistive random access memory (MRAM) device. In some aspects, the seed layer provides a smooth interface for the growth of the (012)-textured BiSb layer. The seed layer maintains or enhances the (012) texture of the BiSb layer. In some aspects, the seed layer acts as a barrier to prevent Sb migration from the BiSb layer during processing, such as during thermal annealing. In some respects, the seed layer maintains the conductivity of the BiSb layer, giving it a resistance of approximately 1000 μΩ-cm or less. In other respects, the seed layer comprises a silicide layer, wherein the silicide layer has a higher or equivalent resistance than the BiSb layer, so that current is not shunted from the BiSb through the seed layer.

[0027] Certain embodiments of this disclosure generally relate to an interlayer that maintains a BiSb layer with a (012) orientation. The (012)-oriented BiSb layer exhibits a large spin Hall angle effect and high conductivity. The (012)-oriented BiSb layer can be used to form spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices. For example, the (012)-oriented BiSb layer can be used as a spin Hall layer in a spin-orbit torque device with an energy-assisted magnetic recording (EAMR) write head. As another example, the (012)-oriented BiSb layer can serve as a spin Hall electrode layer in a magnetoresistive random access memory (MRAM) device. In some aspects, the interlayer provides a smooth interface over the (012)-textured BiSb layer. The interlayer maintains or enhances the (012) texture of the BiSb layer. In some aspects, the interlayer acts as a barrier to prevent Sb migration from the BiSb layer during processing, such as during thermal annealing. In some respects, the interlayer maintains the conductivity of the BiSb layer, giving it a resistance of approximately 1000 μΩ-cm or less. In other respects, the interlayer includes a silicide layer, wherein the silicide layer has a higher or equivalent resistance than the BiSb layer, so that current is not shunted from the BiSb through the interlayer.

[0028] Figure 1A This is a schematic cross-sectional view of some embodiments of an SOT MTJ device 10, which has a BiSb layer 50 with a (012) orientation formed over a substrate 20. The substrate 20 may be a silicon substrate, an alumina substrate, or other suitable substrate. The substrate 20 may include one or more layers deposited thereon and / or formed thereon. For example, the substrate 20 may include an oxide layer thermally grown or deposited thereon.

[0029] In some embodiments, the base layer 22 is deposited over the substrate 20. In some embodiments, the base layer 22 includes a silicon layer. In some embodiments, the silicon layer is undoped. In some embodiments, the silicon layer is doped (such as n-doped or p-doped) to adjust the conductivity of the base layer 22. In some embodiments, the thickness of the silicon layer is approximately [missing information]. to approximately In some embodiments, the substrate 22 comprises a metal layer consisting of NiM, CoM, NiFeM, CoCuM, NiCuM, NiFeTaM, or combinations thereof, wherein M is selected from the group consisting of Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si. In some embodiments, the substrate 22 comprises a silicon layer and a metal layer. The metal layer can increase the conductivity of the silicon layer. For example, the substrate 22 may comprise a metal layer between the silicon layer and the substrate 20. The metal layer in contact with the silicon layer or the silicon substrate 20 will form an amorphous, smooth silicide layer that is non-magnetic at a temperature of about 300°C or lower. In some embodiments, the SOT MTJ device 10 does not include the substrate 22.

[0030] A seed layer 30 is deposited over a substrate 20, such as on a base layer 22 or on the substrate 20. The seed layer 30 includes a silicide layer 32. In some embodiments, the silicide layer 32 comprises NiSi, NiFeSi, NiFeTaSi, NiCuSi, NiCoSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, or combinations thereof. In some embodiments, the thickness of the silicide layer 32 is approximately [missing information]. to approximately In some embodiments, the silicide layer 32 comprises one or more laminated stacks consisting of a silicon layer 34 and a metal layer 36. Figure 1A The diagram illustrates a laminated stack consisting of a silicon layer 34A and a metal layer 36A. Alternating silicon layers 34 and metal layers 36 mix with each other at room temperature to form a thin nanocrystalline silicide layer. Room temperature as used herein refers to a temperature from about 15°C to about 25°C. In some embodiments, the silicide layer 32 includes a metal layer 36 that mixes with the silicon substrate 20 at room temperature to form a thin nanocrystalline layer. The nanocrystalline silicide layer is stable at temperatures of about 300°C or below (maintaining nanocrystalline, smooth, and high resistivity). In some embodiments, the metal layer 36 includes Ni, NiFe, NiFeTa, NiCu, Co, CoFe, CoFeTa, CoCu, or combinations thereof. In some embodiments, the silicide layer comprises one to four laminated stacks consisting of silicon layers 34 and metal layers 36.

[0031] In some embodiments, the seed layer 30 comprises an amorphous film whose nearest-neighbor peak spacing is similar to that in... to The (111) interplanar spacing of the fcc lattice with the a-axis within the range is matched, or to matches the (002) interplanar spacing of the hcp lattice with an a-axis within a range. In some aspects, the amorphous film can be represented by a large number of local hexagonal lattices, where the nearest-neighbor peaks come from a large number of local fcc (111) surfaces and are attributed to the (111) fcc interplanar spacing. Thus, any nearest-neighbor peak interplanar spacing matches the (111) interplanar spacing of the fcc lattice with an a-axis within the range from to or matches the (002) interplanar spacing of the hcp lattice with an a-axis within the range from to An amorphous or near-amorphous material can be used to promote a strong BiSb (012) texture. Figure 11 shows the XRD scan of the metal layer 36 composed of NiFeTa x and NiFeW x . The vertical lines represent the fcc (111) interplanar spacings of NiFeTa x and NiFeW x , which support a strong BiSb (012) texture. Figure 12 shows the scanning of the amorphous NiFeTa seed composition with a BiSb (012) texture, where the Ta composition matches the expected value of the measured lattice parameter of the approximate rectangular surface (short 'a' side) of the amorphous-based alloy, which supports a strong BiSb (012) texture. In addition, Figure 13 shows the relationship diagram of the lattice spacing of the amorphous peak converted to the fcc a-axis and the alloy elements (NiFe) (1-x) M x composed of. The rectangular box represents the lattice parameter range of the amorphous alloy to produce a strong (012) BiSb texture, as well as the composition range of the NiFeM amorphous alloy, where M = Ta, W, Si. For the alloy element (NiFe)(1 - x)M x (x = Ta), W within the lattice parameter range of the rectangular box to match BiSb and produce a strong (012) BiSb texture is 22 < x < 43, such as 32 < x < 37, and for NiFeW x is 19 < x < 40, such as 28 < x < 40. As shown, the lattice parameter of NiFeSi is not within the range that directly promotes a strong BiSb (012) texture. However, when used with a surface control layer with a (111) fcc or (002) hcp texture, and the control layer is within this range, such as Cu, CuAgNi, then the silicide promotes a strong BiSb (012) texture and has better control over the growth and interface roughness of BiSb.

[0032] ​In some embodiments, the seed layer 30 further includes a surface control layer 40 between the silicide layer 32 and the BiSb layer 50. In some embodiments, the surface control layer 40 includes NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAg, CuAgM, CuM, or combinations thereof, wherein M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si. In some embodiments, the thickness of the surface control layer is approximately [missing information]. to approximately In some embodiments, the surface control layer 40 includes a first layer above the silicide layer 32 and a second layer above the first layer. The first layer comprises NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuAg, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, CoCu, or combinations thereof, wherein M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si. The second layer comprises CoNi, NiSi, CoSi, NiCoSi, CuAgNi, CuM, CuNiM, Ni, CoCu, Cu, Co, NiCu, or combinations thereof, wherein M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si.

[0033] Seed layer 30 facilitates the growth of BiSb layer 50 with (012) orientation. In some embodiments, a thin silicide layer 32 is formed by direct contact between silicon layer 34 and metal layer 36 at room temperature via migration of metal and silicon. The silicide layer is nanocrystalline or amorphous with reduced surface roughness. The silicide layer has a moderately high resistivity, greater than about 200 μΩ-cm. The silicide is nonmagnetic and stable at temperatures of about 300°C or lower (remaining nanocrystalline, smooth, high resistivity, and nonmagnetic). The silicide layer 32 with its nanocrystalline structure exhibits hexagonal local symmetry, which enhances the growth of BiSb with (012) orientation.

[0034] Crystalline nickel or cobalt disilicide layers with nanocrystalline structures exhibit hexagonal local symmetry, whose a hcp The dimensions are approximately and a of the silicide layer hcp The size of the surface control layer is approximately 40. hcp It is 1.5 times the size, but it will strongly cover the lattice of the control layer 40 and can also be used as a seed layer to promote strong BiSb(012) growth.

[0035] The surface control layer 40 has an fcc(111) or hcp(002) surface. In certain embodiments, the surface control layer 40 comprises one or more hcp materials having a (002) orientation, with an a hcp dimension ranging from about to about This surprisingly provides for the growth of a BiSb layer having a (012) orientation. For example, the a hcp dimension of NiFe is about

[0036] In certain embodiments, the surface control layer 40 comprises one or more fcc materials having a (111) orientation, with an a-axis dimension ranging from about to about This surprisingly provides for the growth of a BiSb layer having a (012) orientation. For example, the a-axis dimension of NiFe having an fcc(111) orientation is about

[0037] Figure 14 The same figure is shown, except that the fcc is replaced by a hcp lattice (square root coefficient). For amorphous silicides with lattice parameters outside this range, such as NiFeSi, they do not directly promote the BiSb(012) texture, but when used in combination with a surface control layer having an ffc or hcp texture within this range, a strong BiSb(012) texture can be produced. An example of an amorphous silicide used in combination with a surface control layer having a (111) fcc or (002) hcp texture within the range to promote BiSb(012) growth is NiFe-silicide formed within the range of about to and a Cu or CuAgNi surface control layer formed with a thickness of about to about .

[0038] Surprisingly, the seed layer 30 provides for the growth of a BiSb layer 50 having a (012) orientation. The BiSb layer 50 comprises Bi 1-x Sb x , where x is 0 < x < 1. In certain embodiments, the BiSb layer 50 comprises Bi 1-x Sb x , where x is 0.05 < x < 0.2 or comprises an antimony atomic percentage content of about 7% to about 22%. In certain embodiments, the BiSb layer 50 is formed with a thickness of about to about such as about to about

[0039] Table 1 shows an example comparing the performance of a BiSb layer with (012) orientation with β-tantalum and a BiSb layer with (001) orientation.

[0040]

[0041] Compared to β-tantalum (β-Ta) or (001) oriented BiSb layers, (012) oriented BiSb layers have similar electrical conductivity and a larger spin Hall angle. Therefore, BiSb (012) requires relatively less power to generate the spin Hall effect compared to β-Ta or BiSb (001).

[0042] In some embodiments, the silicon substrate 22 (if present), seed layer 30, and BiSb layer 50 are deposited by physical vapor deposition (PVD), such as sputtering, molecular beam epitaxy, ion beam deposition, other suitable PVD processes, or combinations thereof. The SOT MTJ device 10 includes any suitable layer on the BiSb layer 50 to form any suitable device.

[0043] Figure 1B This is a schematic cross-sectional view of some embodiments of the SOT MTJ device 10, which has Figure 1A A BiSb layer 50 with (012) orientation is formed, and an interlayer 70 is deposited on top of the BiSb layer 50.

[0044] The interlayer 70 includes a silicide layer 72. In some embodiments, the silicide layer 72 includes NiSi, FeSi, CoSi, NiCuSi, NiCoSi, NiFeTaSi, CoFeSi, CoCuSi, or combinations thereof. In some embodiments, the thickness of the silicide layer 72 is approximately [missing information]. to approximately In some embodiments, the silicide layer 72 comprises one or more laminated stacks consisting of a silicon layer 74 and a metal layer 76. Figure 1C The diagram illustrates a laminated stack consisting of a silicon layer 74A and a metal layer 76A. In some embodiments, the metal layer 76 comprises Ni, Fe, Co, NiCu, NiFeTa, CoFe, CoCu, or combinations thereof. In some embodiments, the silicide layer comprises one to four laminated stacks consisting of silicon layers 74A and metal layers 76.

[0045] In some embodiments, the interlayer 70 comprises an amorphous film whose nearest-neighbor peak spacing is similar to that in... to The (111) interplanar spacing of the fcc lattice with the a-axis within the range is matched, or to matches the (002) interplanar spacing of the hcp lattice with an a-axis within a range. If, in some respects, the amorphous film can be represented by a large number of local hexagonal lattices, where the nearest neighbor peaks originate from a large number of local fcc (111) surfaces and are attributed to the (111) fcc interplanar spacing. Thus, any nearest neighbor peak interplanar spacing matches the (111) interplanar spacing of the fcc lattice with an a-axis within the range from to or matches the (002) interplanar spacing of the hcp lattice with an a-axis within the range from to An amorphous or nearly amorphous material can be used to promote a strong BiSb (012) texture. Figure 11 shows the XRD scan of the metal layer 36 composed of NiFeTa x and NiFeW x The vertical lines represent the fcc (111) interplanar spacings of NiFeTa x and NiFeW x which support a strong BiSb (012) texture. Figure 12 shows the compositional scan of the amorphous NiFeTa seed for the BiSb (012) texture, where the Ta composition matches the expected value of the measured lattice parameter of the approximate rectangular surface (short 'a' side) of the amorphous-based alloy, which supports a strong BiSb (012) texture texture. In addition, Figure 13 shows the relationship diagram of the lattice spacing of the amorphous peaks converted to the fcc a-axis with the alloying elements (NiFe) of M = Ta, W, Si (1-x) M x The rectangular box represents the range of lattice parameters of the amorphous alloy to produce a strong (012) BiSb texture, as well as the compositional range of the NiFeM amorphous alloy, where M = Ta, W, Si. For the alloying element (NiFe)(1 - x)M x (M = Ta), within the range of lattice parameters within the rectangular box to match BiSb and produce a strong (012) BiSb texture, the W for NiFeTa x is 22 < x < 43, such as 32 < x < 37, and for NiFeW x is 19 < x < 40, such as 28 < x < 40. As shown, the lattice parameters of NiFeSi are not within the range that directly promotes a strong BiSb (012) texture. However, when used with a surface control layer such as Cu, CuAgNi, then the silicide promotes a strong BiSb (012) texture.

[0046] In some embodiments, the interlayer 70 further includes a surface control layer 71 between the BiSb layer 50 and the silicide layer 72. The surface control layer 71 comprises Cu, Ni, NiFe, Co, or combinations thereof. In some embodiments, the thickness of the surface control layer 71 is approximately [missing information]. to In some implementations, Figures 1A to 1B Each surface control layer 40, 71 can be used to improve smoothness and reduce Sb migration in the BiSb layer 50.

[0047] Figure 14 The same figure is shown, except that hcp (square root coefficient) is used instead of fcc. For amorphous silicides with lattice parameters outside this range, such as NiFeSi, BiSb(012) texture is not directly promoted, but when used with a surface control layer with (111)ffc or (002)hcp texture within this range, the silicide can promote a strong BiSb(012) texture. An example of an amorphous silicide used with a surface control layer within this range to promote BiSb(012) growth with a (111)fcc or (002)hcp texture is a thickness of approximately to The NiFe-silicide formed within the range and the thickness of the formed is approximately to approximately Cu or CuAgNi surface control layer.

[0048] Figure 1C This is a schematic cross-sectional view of some embodiments of the SOT MTJ device 10, which has Figure 1B A BiSb layer 50 with a (012) orientation is formed to create an SOT-based energy-assisted magnetic recording (EAMR) element. A spin torque layer (STL) 60 is formed above the interlayer 70. The STL 60 contains ferromagnetic materials, such as one or more CoFe, CoIr, NiFe, and CoFeM layers, where M = B, Ta, Re, or Ir. A spin current is generated in the BiSb layer by the charge current of the BiSb layer 50, which acts as a spin Hall layer. Spin-orbit coupling between the BiSb layer and the spin torque layer (STL) 60 causes magnetization switching or precession of the STL 60 through spin-orbit coupling from the spin current of the BiSb layer 50. The magnetization switching or precession of the STL 60 can generate an auxiliary DC electric field for the write field. The SOT-based EAMR element has several times the power efficiency compared to a spin torque-based microwave-assisted magnetic recording (MAMR) element.

[0049] In some embodiments, additional layers, such as spacer layer 62 and pinning layer 64, are formed on STL 60. Pinning layer 64 may partially pin STL 60. Pinning layer 64 may comprise a single or multiple layers of PtMn, NiMn, IrMn, IrMnCr, CrMnPt, FeMn, other antiferromagnetic materials, or combinations thereof. Spacer layer 62 comprises a single or multiple layers of magnesium oxide, aluminum oxide, other nonmagnetic materials, or combinations thereof.

[0050] Figure 1D This is a schematic cross-sectional view of some embodiments of the SOT MTJ device 10, which has Figure 1C A BiSb layer 50 with a (012) orientation is formed to create a SOT-based magnetoresistive random access memory (MRAM) device. A free vertical magnetic anisotropy (PMA) ferromagnetic layer 80 is formed over the interlayer 70. For example, the free PMA ferromagnetic layer 80 may include a stack of one or more Co / Pt, Co / Pd, Co / Ni, CoFeB, FePt, other PMA-inducing layers, or combinations thereof. An insulating layer 84, such as an MgO layer, is formed over the free PMA layer 80. A reference PMA ferromagnetic layer 88 is formed over the insulating layer 84. The reference PMA ferromagnetic layer 88 may include a stack of one or more Co / Pt, Co / Pd, Co / Ni, CoFeB, FePt, other PMA-inducing layers, or combinations thereof. The reference PMA ferromagnetic layer 88 may include one or more synthetic antiferromagnetic (SAF) needle structures. A capping layer 92 may be formed over the PMA layer 88. The capping layer 92 comprises NiFe, SiN, Si, NiFeTa, NiTa, Pt, Co, Cu, Ni, NiCu, CoCu, Ru, Ta, Cr, Au, Rh, CoFe, CoFeB, other non-magnetic materials, other magnetic materials, or combinations thereof. The capping layer 92 can be tuned to have a higher resistance than the PMA layer 88 so that current is not shunted from the PMA layer 88 through the capping layer 92, protecting the SOT MTJ device 10 during deposition, annealing, patterning, cleaning, and other processes.

[0051] Figure 1E This is a schematic cross-sectional view of some embodiments of the SOT MTJ device 10, which has Figure 1CA BiSb layer 50 with a (012) orientation is formed to create a SOT-based magnetoresistive random access memory (MRAM) device. A reference PMA ferromagnetic layer 88 is formed over the substrate 20. The reference PMA ferromagnetic layer 88 may include a stack of one or more Co / Pt, Co / Pd, Co / Ni, CoFeB, FePt, other PMA-inducing layers, or combinations thereof. The reference PMA ferromagnetic layer 88 may include one or more SAF needle structures. An insulating layer 84, such as an MgO layer, is formed over the reference PMA ferromagnetic layer 88. A free PMA ferromagnetic layer 80 is formed over the insulating layer 84. For example, the free PMA ferromagnetic layer 80 may include a stack of one or more Co / Pt, Co / Pd, Co / Ni, CoFeB, FePt, other PMA-inducing layers, or combinations thereof.

[0052] A seed layer 30 is formed above the free PMA ferromagnetic layer 80. A first BiSb layer 50 is formed above the seed layer 30. An interlayer 70 is formed above the BiSb layer 50.

[0053] A capping layer 92 may be formed above the interlayer 70. The capping layer 92 comprises NiFe, SiN, Si, NiFeTa, NiTa, Pt, Co, Cu, Ni, NiCu, CoCu, Ru, Ta, Cr, Au, Rh, CoFe, CoFeB, other non-magnetic materials, other magnetic materials, or combinations thereof. The capping layer 92 may be tuned to have a higher resistance than the PMA layer 88 so that current is not shunted from the PMA layer 88 through the capping layer 92, protecting the SOT MTJ device 10 during deposition, annealing, patterning, cleaning, and other processes.

[0054] Figures 1A to 1E The silicide layer 32 of the seed layer 30 or the silicide layer 72 of the interlayer 70 can be formed by co-sputtering Si with a metal (such as Ni, Fe, Co, etc.), or by laminating Si with a metal to produce silicides. The silicide layers 32 and 72 can be further thermally annealed. The resistivity of the silicide layers 32 and 72 is higher than that of the BiSb layer 50, so current will not be shunted from the BiSb layer through the silicide layers. In some embodiments, the resistivity of the silicide layer is greater than about 200 μΩ-cm.

[0055] Figures 1A to 1E The seed layer 30 and / or the silicide layer 32 Figures 1C to 1D The silicide layer 72 of the interlayer 70 acts as a barrier to reduce Sb migration from the BiSb layer 50. Sb migration from the BiSb layer 50 may adversely reduce the spin Hall angle, change the orientation of the BiSb layer 50 with (012) alignment, and / or reduce the conductivity of the BiSb layer 50.

[0056] In some respects, silicide layers 32 and / or 72 reduce current shunting in the BiSb layer 50 by providing a higher resistivity layer near the conductive BiSb layer 50 compared to seed layers or sandwich layers composed of metals, metal alloys, or other non-silicide materials. The increased resistance of seed layer 30 and / or sandwich layer 70 can reduce electrical shunting of current from the BiSb layer 50 through seed layer 30 and / or sandwich layer 70. Electro-shutdown currents degrade the performance of SOT MTJ devices, such as SOT-based EAMR devices or SOT-based MRAM devices.

[0057] Table 2 shows examples of the resistivity of silicide layers compared to metal layers. For example, the resistivity of NiFe / Si laminates ranges from about 240 μΩ-cm to about 350 μΩ-cm, depending on the number of layers stacked. Silicate layers, such as NiFe / Si, NiFeTa / Si, Co / Si, Ni / Si, Cu / Si, NiCu / Si, CoCu / Si, CoFe / Si, and other silicides, have higher resistivity than metal layers alone.

[0058]

[0059] In some aspects, the silicide layer 32 provides a smooth interface for the growth of the surface control layer 40 to grow a BiSb layer 50 with a (012) orientation. In some aspects, the silicide layer 72 provides a smooth interface for the growth of the material above it. These smooth interfaces reduce Sb migration from the BiSb layer 50 due to roughness between the interfaces. In some embodiments, the silicide layer 32 or the silicide layer 72 is formed or maintained as a low-roughness BiSb layer 50 with a (012) texture, consisting of a laminate with a silicon layer and a metal layer thickness ratio in the range of about 2:1. For example, Si / NiFe To Si / NiFe The stacking of the laminates produces or maintains a BiSb layer 50 with a low roughness (012) texture.

[0060] In some implementations, Figures 1B to 1E The surface control layer 71 of the interlayer 70 helps reduce Sb migration from the BiSb layer 50 and improves the smoothness of the interface. In some embodiments, the surface control layer 71 can improve the texture and magnetic anisotropy of the magnetic layer formed thereon, such as Figures 1D to 1E The PMA layer is formed above it. In some embodiments, the surface control layer 71 can be used as a spacer to adjust the resistivity so that current is not shunted from the BiSb layer 50. Figure 1D The PMA layer forms above it. In some implementations, Figures 1B to 1EThe interlayer 70 does not include the surface control layer.

[0061] Figure 2 This means that in Figures 1A to 1E A BiSb layer 50 with (012) orientation is formed on the seed layer 30, or... Figures 1B to 1E A schematic plan view of some embodiments of the interlayer 70 formed above the BiSb layer 50. The seed layer 30 includes a surface control layer 40 having a (111)fcc orientation or a (002)hcp orientation. The interlayer 70 includes a surface control layer 71 having a (111)fcc orientation or a (002)hcp orientation. Different symbols for each layer represent atoms at different depths.

[0062] In some embodiments, since the a-axis lattice parameter of the surface control layer 40 is approximately 2:3 to the a-axis ratio of the silicide layer 32 of the seed layer 30, a BiSb layer 50 with a (012) orientation sits above the surface control layer 40 with a seed layer 30 having a (111) fcc orientation or a (002) hcp orientation. (The last part, "made of Ni," appears to be a fragment and doesn't need a direct translation.) x Fe 1-x The surface control layer 40, composed of (111) lattice, has an x-axis of approximately 0.5, and its a-axis lattice parameter is approximately 2:3 in ratio to the a-axis of the silicide layer 32. The NiFe (111) surface can be aligned with the silicide layer 32. The a-axis lattice parameter of the NiFe thin film... hcp The parameter is approximately The silicide layer 32 of the seed layer 30 can be crystalline, nanocrystalline, or amorphous, depending on the underlying layer during the growth of the silicide layer 32. Crystalline silicide layers 32 exhibit hexagonal symmetry, while nanocrystalline silicide layers 32 exhibit localized hexagonal symmetry. Amorphous silicides, such as NiFeSi, whose lattice parameters are outside this range, do not directly promote BiSb(012) texture, but when used with a surface control layer containing (111)fcc or (002)hcp textures within this range, the silicide can promote strong BiSb(012) textures. For example, crystalline nickel disilicide (NiSi2) has an a... hcp The parameter is approximately a of cobalt silicide (CoSi2) hcp The parameter is approximately a-NiFe hcp The size ratio with α-silicide hcp is approximately 2:3. Figure 2 The superimposed structure can be seen.

[0063] Figure 2 The parameter drawn in the middle is a = approximately And b = approximately The rectangular profile of the NiFe(111) surface shows that the NiFe(111) surface is related to the parameter a = approximately And b = approximately The approximately rectangular BiSb(012) surface has about 3% misalignment in one direction. Therefore, the (111) textured NiFe film can be used as part of the seed layer 30 for growing the (012) textured BiSb layer 50. For ease of explanation, Figure 2 The NiFe atoms located at the center of each hexagon are omitted. However, these NiFe atoms, together with the NiFe atoms at the vertices of the hexagons, exist at the center of each hexagon to form the (111) surface of NiFe.

[0064] In some embodiments, since the a-axis lattice parameter ratio of the surface control layer 71 to the a-axis ratio of the crystalline disilicide layer 72 of the interlayer 70 is approximately 2:3, a BiSb layer 50 with a (012) orientation is formed above the surface control layer 71 of the interlayer 70 with a (111) fcc orientation or a (002) hcp orientation. (The last part, "made of Ni," appears to be a fragment and doesn't need a direct translation.) x Fe 1-x The surface control layer 71, composed of (111) lattice elements with an x-axis of approximately 0.5, has an a-axis lattice parameter ratio of approximately 2:3 to that of the silicide layer 72. The NiFe (111) surface can be aligned with the silicide layer 72. The a-axis lattice parameter of the NiFe thin film... hcp The parameter is approximately The silicide layer 72 of the interlayer 70 can be crystalline, nanocrystalline, or amorphous. The nanocrystalline silicide layer 72 exhibits localized hexagonal symmetry. Amorphous silicides, such as NiFeSi, whose lattice parameters are outside this range, do not directly promote BiSb(012) texture, but when used with a surface control layer containing (111)fcc or (002)hcp textures within this range, the silicide promotes a strong BiSb(012) texture. For example, crystalline nickel disilicide (NiSi2) has an a... hcp The parameter is approximately a of cobalt silicide (CoSi2) hcp The parameter is approximately a-NiFe hcp The size ratio with that of α-silicide hcp is approximately 2:3.

[0065] Figure 2 The dimension drawn in the image is a = approximately And b = approximately The rectangular outline of the NiFe(111) surface shows that the NiFe(111) surface is perpendicular to a dimension of approximately a. And b = approximately The approximately rectangular BiSb (012) surface has a misalignment of about 3% in one direction. Therefore, the (111) textured NiFe film can be used as part of the interlayer 70 to maintain or enhance the (012) textured BiSb layer 50.

[0066] The surface control layer 40 of the seed layer 30 or the surface control layer 71 of the interlayer 70 is smooth and has reduced interface roughness to enhance the BiSb layer 50 with (012) texture.

[0067] In some implementations, such as Figure 2 As shown, an (111) oriented fcc material, a (002) oriented hcp material, or a combination thereof, can be approximately aligned with a (012) oriented BiSb layer 50. The (111) orientation of the fcc material or the (002) orientation of the hcp material promotes the growth of (012) oriented BiSb, rather than (001) oriented BiSb. In SOT MTJ devices, the (012) oriented BiSb layer 50 exhibits a higher spin Hall angle and higher performance than the (001) oriented BiSb layer. SOT MTJ devices can be configured in a vertical stack configuration or an in-plane stack configuration. SOT MTJ devices can be used in applications such as EAMR write heads, MRAM, artificial intelligence chips, and others.

[0068] Figure 3 This is a schematic diagram of certain embodiments of a magnetic media drive including an EAMR write head with an SOT MTJ device. Such a magnetic media drive may be a single drive or include multiple drives. For ease of illustration, a single disk drive 100 is shown according to some embodiments. As shown, at least one rotatable disk 112 is carried on a spindle 114 and rotated by a drive motor 118. Magnetic recording on each disk 112 is in the form of any suitable pattern of data tracks, such as a toroidal pattern of concentric data tracks (not shown) on the disk 112.

[0069] At least one slider 113 is positioned near the disk 112, each slider 113 supporting one or more head assemblies 121 including SOT MTJ devices. As the disk 112 rotates, the slider 113 moves radially in and out above the disk surface 122, allowing the head assemblies 121 to access different tracks of the disk 112 for writing desired data. Each slider 113 is attached to an actuator arm 119 via a suspension 115. The suspension 115 provides a slight spring force that biases the slider 113 toward the disk surface 122. Each actuator arm 119 is attached to an actuator device 127. Figure 3 The actuator device 127 shown may be a voice coil motor (VCM). The VCM includes a coil capable of moving within a fixed magnetic field, the direction and speed of which the coil moves are controlled by a motor current signal supplied by the control unit 129.

[0070] During operation of the disk drive 100, the rotation of the disk 112 creates an air bearing between the slider 113 and the disk surface 122, which applies an upward force or lift to the slider 113. Thus, during normal operation, the air bearing counteracts the slight spring force of the suspension 115 and supports the slider 113 away from and slightly above the disk surface 122 with a small, substantially constant gap.

[0071] Various components of the disk drive 100 are controlled during operation by control signals (such as access control signals and internal clock signals) generated by the control unit 129. Typically, the control unit 129 includes logic control circuitry, storage devices, and a microprocessor. The control unit 129 generates control signals that control various system operations, such as drive motor control signals on line 123 and head position and seek control signals on line 128. The control signals on line 128 provide the desired current distribution to move and position the slider 113 onto the desired data track on the disk 112. Write and read signals are transmitted via the recording channel 125 to and from the write and read heads on component 121.

[0072] The above description of typical magnetic media drivers and Figure 3 The accompanying illustrations are for illustrative purposes only. It should be apparent that a magnetic media drive may contain a large number of media or disks and actuators, and each actuator may support multiple sliders.

[0073] Figure 4 This is a partial cross-sectional side view of some embodiments of a read / write head 200 with an SOT MTJ device. The read / write head 200 faces the magnetic medium 112. The read / write head 200 may correspond to Figure 3 The read / write head assembly 121 described herein. The read / write head 200 includes a media surface (MFS) 212 facing the disk 112, such as a gas bearing surface, an EAMR write head 210, and a magnetic read head 211. (As...) Figure 4 As shown, the magnetic medium 112 moves through the EAMR write head 210 in the direction indicated by arrow 232, and the read / write head 200 moves in the direction indicated by arrow 234.

[0074] In some embodiments, the magnetic read head 211 is a magnetoresistive (MR) read head, which includes an MR sensing element 204 located between MR shields S1 and S2. In other embodiments, the magnetic read head 211 is a magnetic tunnel junction (MTJ) read head, which includes an MTJ sensing element 204 located between MR shields S1 and S2. The magnetic field of adjacent magnetized regions in the disk 112 can be detected as a recording bit by the MR (or MTJ) sensing element 204.

[0075] The EAMR write head 210 includes a master electrode 220, a front shield 206, a rear shield 240, a spin-orbit torque (SOT) device 230, and a coil 218 that excites the master electrode 220. The coil 218 may have a "pancake" structure, rather than... Figure 4 The illustrated "spiral" structure, a "pancake" structure, is wound around the back contact between the main electrode 220 and the tail shield 240. An SOT MTJ device 230 is formed in the gap 254 between the main electrode 220 and the tail shield 240. The main electrode 220 includes a tail cone 242 and a front cone 244. The tail cone 242 extends from a recessed location in the MFS 212. The front cone 244 extends from a recessed location in the MFS 212. The tail cone 242 and the front cone 244 may have the same taper and the taper is measured relative to the longitudinal axis 260 of the main electrode 220. In some embodiments, the main electrode 220 does not include the tail cone 242 and the front cone 244. Instead, the main electrode 220 includes a tail side (not shown) and a front side (not shown), and the tail side and the front side are substantially parallel. The main electrode 220 can be a magnetic material, such as an FeCo alloy. The front shield 206 and the rear shield 240 can be magnetic materials, such as a NiFe alloy. In some embodiments, the rear shield 240 may include a rear shield thermal seed layer 241. The rear shield thermal seed layer 241 may comprise a high-torque material, such as CoFeN or FeXN, wherein M comprises at least one of Rh, Al, Ta, Zr, and Ti. In some embodiments, the rear shield 240 does not include a rear shield thermal seed layer.

[0076] Figure 5 yes Figure 4 MFS schematic diagram of a portion of the EAMR write head 210 of the SOT MTJ device 230, including Figure 1C The SOT MTJ device 10 or other suitable EAMR write head is used. The EAMR write head 210 includes a master electrode 220 and a tail shield 240 in the track direction. The SOT MTJ device 230 is disposed in the gap between the master electrode and the tail shield 240. The EAMR write head 210 includes a dual STL layer 60 (as shown) or a single STL layer.

[0077] During operation, a spin current is generated in the BiSb layer 50, which serves as a spin Hall layer, through the charge current. Spin-orbit coupling between the BiSb layer and the STLs 60, via the spin-orbit coupling from the spin current in the BiSb layer 50, causes magnetization switching or precession of the STLs 60. This magnetization switching or precession of the STLs 60 generates an auxiliary field in the write field. Compared to MAMR write heads based on spin-transfer torque, the SOT-based energy-assisted write head exhibits several times the power efficiency.

[0078] Figure 15 This is a schematic diagram of some embodiments of a memory cell array 1500 configured at an intersection. The cell array 1500 consists of multiple memory cells 1520 forming an SOT-based MRAM device. Figure 15 As shown, each storage cell 1520 of the storage cell array 1500 includes Figure 1E The bottom pin of the SOT MTJ device 10. In other embodiments (not shown), the memory cells 1520 of the memory cell array 1500 may be Figure 1D The SOT MTJ device 10 is a pin-type SOT MTJ device. Each memory cell in the memory cell 1520 can be in a state representing a 1 or 0 bit value. The memory cell array 1500 includes a plurality of bottom electrodes 1524 and a plurality of spin-orbit material electrodes 1526. The spin-orbit material electrodes 1526 include a BiSb layer with a (012) orientation. Each memory cell 1520 can be part of a two-terminal device or a three-terminal device. For example, in a two-terminal device, the bottom electrode 1524 can be used as a bit line and the spin-orbit material electrode 1526 can be used as a word line. For example, in a three-terminal device, the bottom electrode 1524 can be used as both a bit line and a read word line, and the spin-orbit material electrode 1526 can be used as a write word line. The cross-point array embodiment shown is merely an exemplary MRAM embodiment, and the SOT MTJ device embodiment disclosed herein can be implemented in other types of MRAM devices. Other architectures of the memory cell array 1500 may include various types and combinations of terminals, gates, transistors, and lines.

[0079] Certain embodiments of this disclosure generally relate to a seed layer and / or interlayer for promoting or maintaining the growth of a bismuth-antimony (BiSb) layer with a (012) orientation. In some aspects, the seed layer and / or interlayer provides a smooth interface for the BiSb layer with a (012) texture. In some aspects, the seed layer and / or interlayer acts as a barrier to prevent Sb migration from the BiSb layer during processing, such as during thermal annealing. The seed layer and / or interlayer promotes and / or maintains the growth of the BiSb layer with a (012) orientation. The BiSb layer with a (012) orientation exhibits a large spin Hall angle effect and high conductivity, such as a resistance of about 1000 μΩ-cm or less. The BiSb layer with a (012) orientation can be used to form spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices. For example, the BiSb layer with a (012) orientation can be used as a spin Hall layer in a spin-orbit torque device with an energy-assisted magnetic recording (EAMR) write head. For example, a BiSb layer with (012) orientation can be used as a spin Hall electrode layer in a magnetoresistive random access memory (MRAM) device.

[0080] In one embodiment, the spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a seed layer above the substrate, and a bismuth-antimony (BiSb) layer with a (0120) orientation on the seed layer. The seed layer includes a silicide layer and a surface control layer. The silicide layer comprises a material of NiSi, NiFeSi, NiFeTaSi, NiCuSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, or combinations thereof. The surface control layer comprises a material of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, or combinations thereof, wherein M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si.

[0081] In another embodiment, the SOT MTJ device includes a substrate and a BiSb layer having a (012) orientation above the substrate. An interlayer is located above the BiSb layer. The interlayer includes a silicide layer. The silicide layer comprises a material of NiSi, FeSi, CoSi, NiCuSi, NiFeTaSi, CoCuSi, or a combination thereof.

[0082] In another embodiment, the SOT MTJ device includes a substrate, a seed layer above the substrate, and a BiSb layer with a (012) orientation on an amorphous film. The seed layer comprises an amorphous film, the nearest neighbor peak spacing of which is the same as that on the surface of the amorphous film. to The (111) interplanar spacing of the fcc lattice with the a-axis within the range is matched, or to The (002) interplanar spacing of the hcp lattice with the a-axis within the range is matched.

[0083] Example

[0084] The following are examples illustrating various implementation schemes for the BiSb layer, such as... Figures 1A to 1E BiSb layer 50, Figure 3 Magnetic drive 100 Figure 3 Write head 210, Figure 4 and Figure 5 The SOT MTJ device 230, other BiSb layers, other magnetic actuators, other SOT MTJ devices, and variations thereof. Unless expressly stated in the claims, these embodiments are not intended to limit the scope of the claims.

[0085] Example A

[0086] In Example A, a thickness of approximately [missing information] was formed by physical vapor deposition (PVD). Samples of non-conductive amorphous silicon substrates. A single-component hierarchical silicide layer, approximately Si thickness, was formed on the substrate of a laminated silicon / NiFe laminate using PVD. NiFe Si NiFe Si and NiFe Through PVD A Cu surface control layer is formed on the layer, with a thickness of approximately [missing information - likely a number] via PVD deposition. Silicide layer. The surface control layer is composed of... It is made of Cu. A BiSb layer with a thickness of approximately [missing information] is formed on the Cu layer by PVD. The sample was subjected to X-ray diffraction (XRD) 2θ scanning, such as... Figure 6 As shown, the BiSb layer exhibits a (012) orientation, while the number of (003) orientations is small or nonexistent.

[0087] Example B

[0088] In Example B, sample 710 was formed using PVD technology, and the thickness of its laminate stack was approximately Si. and NiFe After room temperature fusion, the laminates stacked to form a high-resistivity, single-component, hierarchical silicide layer. A Cu surface control layer with a thickness of approximately [missing information] was then formed on the silicide layer via PVD. A BiSb layer with a thickness of approximately [missing information] was formed on the surface control layer using PVD. A layer with a thickness of approximately Si was formed on the BiSb layer by PVD. NiFe Si and NiFe The interlayers are stacked in a laminated manner. After fusion at room temperature, the interlayer laminates are stacked to form a high-resistivity, single-component, hierarchical silicide layer.

[0089] Sample 720 was formed by PVD of a seed layer of laminated stacks, with a thickness of approximately Si. and NiFe Seed layers were stacked and fused at room temperature to form a high-resistivity, single-component, hierarchical silicide layer. A Cu surface control layer, approximately [thickness missing], was then formed on the silicide layer using PVD. A BiSb layer with a thickness of approximately [missing information] was formed on the surface control layer using PVD. A layer with a thickness of approximately Si was formed on the BiSb layer by PVD. and NiFe The interlayers are stacked in a laminated manner. After fusion at room temperature, the interlayer laminates are stacked to form a high-resistivity, single-component, hierarchical silicide layer.

[0090] Sample 730 is a laminate stack formed by PVD technology, with a thickness of approximately NiFe. Si and NiFe After room temperature fusion, the laminates stacked to form a high-resistivity, single-component, hierarchical silicide layer. A Cu surface control layer with a thickness of approximately [missing information] was then formed on the silicide layer via PVD. A BiSb layer with a thickness of approximately [missing information] was formed on the surface control layer using PVD. A layer with a thickness of approximately Si was formed on the BiSb layer by PVD. and NiFe The interlayers are stacked in a laminated manner. After fusion at room temperature, the interlayer laminates are stacked to form a high-resistivity, single-component, hierarchical silicide layer.

[0091] Sample 740 is a laminate stack formed by PVD technology, with a thickness of approximately NiFe. Si and NiFe After room temperature fusion, the laminates stacked to form a high-resistivity, single-component, hierarchical silicide layer. A Cu surface control layer with a thickness of approximately [missing information] was then formed on the silicide layer via PVD. A BiSb layer with a thickness of approximately [missing information] was formed on the surface control layer using PVD. A layer with a thickness of approximately Si was formed on the BiSb layer by PVD. and NiFe The interlayers are stacked in a laminated manner. After fusion at room temperature, the interlayer laminates are stacked to form a high-resistivity, single-component, hierarchical silicide layer.

[0092] Sample 750 was formed by PVD deposition of a non-conductive amorphous Si substrate, with a thickness of approximately [missing information]. A laminated stack with a thickness of approximately Si is formed on the substrate by PVD. NiFe Si NiFe Si and NiFe After fusion at room temperature, the laminates stacked to form a high-resistivity, single-component, hierarchical silicide layer. A layer with a thickness of approximately [missing information] was then formed on the silicide layer via PVD. NiFe and A Cu surface control layer is formed. The surface control layer is still metallic. A BiSb layer with a thickness of approximately [missing information] is formed on the surface control layer via PVD. A layer with a thickness of approximately Si was formed on the BiSb layer by PVD. and NiFe The interlayer is a laminated stack. After room temperature fusion, the laminated stack forms a high-resistivity, single-component, hierarchical silicide layer. A NiFe capping layer with a thickness of approximately [missing information] is formed on the interlayer by PVD. The capping layer is still metallic.

[0093] Sample 760 is a laminate stack formed by PVD technology, with a thickness of approximately Si. and NiFe After room temperature fusion, the laminates stacked to form a high-resistivity, single-component, hierarchical silicide layer. A Cu surface control layer with a thickness of approximately [missing information] was then formed on the silicide layer via PVD. A BiSb layer with a thickness of approximately [missing information] was formed on the surface control layer using PVD. A layer with a thickness of approximately Si was formed on the BiSb layer by PVD. NiFe Si and NiFe The interlayers are stacked in a laminated manner. After fusion at room temperature, the interlayer laminates are stacked to form a high-resistivity, single-component, hierarchical silicide layer.

[0094] like Figure 7As shown, X-ray diffraction (XRD) 2θ scans were performed on samples 710, 720, 730, 740, 750, and 760. The samples show a (012) orientation of the BiSb layer, while the seed layer and surface control layer of the silicide layer and the interlayer provide a low amount or no (003) orientation.

[0095] Example C

[0096] In Example C, sample 810 was formed on a silicon wafer by PVD with a thickness of approximately A NiFe layer was formed. After fusing at room temperature, the NiFe layer formed a high-resistivity silicide layer with the silicon wafer. A CoCu surface control layer with a thickness of approximately [missing information] was then formed on the silicide layer by PVD. A BiSb layer with a thickness of approximately [missing information] was formed on the surface control layer using PVD. A Co surface control layer with a thickness of approximately [missing information] was formed on the BiSb layer by PVD. A metal layer with a thickness of approximately NiFeTa is formed on the surface control layer. and Pt The surface control layer of Co helps to provide the texture of Pt(111) through the growth of vertical magnetic layers on the amorphous NiFeTa layer.

[0097] Sample 820 was formed on a silicon wafer by PVD with a thickness of approximately It is formed by a NiFe layer. After fusing at room temperature, the NiFe layer forms a high-resistivity silicide layer with the silicon wafer. A Cu surface control layer with a thickness of approximately [missing information] is then formed on the silicide layer by PVD. A BiSb layer with a thickness of approximately [missing information] was formed on the surface control layer using PVD. A Co surface control layer with a thickness of approximately [missing information] was formed on the BiSb layer by PVD. A metal layer with a thickness of approximately NiFeTa is formed on the surface control layer. and Pt The surface control layer of Co helps to provide the texture of Pt(111) through the growth of vertical magnetic layers on the amorphous NiFeTa layer.

[0098] Sample 830 was formed on a silicon wafer by PVD with a thickness of approximately It is formed by a NiCu layer. The bottom of the NiCu layer, after room temperature fusion, forms a high-resistivity silicide layer with the silicon wafer. A layer with a thickness of approximately [missing information] is formed on top of the NiCu layer, which serves as a surface control layer, using PVD. A BiSb layer. A Co surface control layer with a thickness of approximately [missing information] is formed on the BiSb layer by PVD. A metal layer with a thickness of approximately NiFeTa is formed on the surface control layer. and Pt The surface control layer of Co helps to provide the texture of Pt(111) through the growth of vertical magnetic layers on the amorphous NiFeTa layer.

[0099] Sample 840 was formed on a silicon wafer by PVD with a thickness of approximately It is formed by a NiFeTa layer. The bottom of the NiFeTa layer, after room temperature fusion, forms a high-resistivity silicide layer with the silicon wafer. A layer with a thickness of approximately [missing information] is formed on top of the NiFeTa layer, which serves as a surface control layer, using PVD. A BiSb layer. A Co surface control layer with a thickness of approximately [missing information] is formed on the BiSb layer by PVD. A metal layer with a thickness of approximately NiFeTa is formed on the surface control layer. and Pt The surface control layer of Co helps to provide the texture of Pt(111) through the growth of vertical magnetic layers on the amorphous NiFeTa layer.

[0100] Sample 850 was formed on a silicon wafer by PVD with a thickness of approximately It is formed by a CoCu layer. The bottom of the CoCu layer, after room temperature fusion, forms a high-resistivity silicide layer with the silicon wafer. A layer with a thickness of approximately [missing information] is formed on top of the CoCu layer, which serves as a surface control layer, using PVD. A BiSb layer. A Co surface control layer with a thickness of approximately [missing information] is formed on the BiSb layer by PVD. A metal layer with a thickness of approximately NiFeTa is formed on the surface control layer. and Pt The surface control layer of Co helps to provide the texture of Pt(111) through the growth of vertical magnetic layers on the amorphous NiFeTa layer.

[0101] Sample 860 was formed on a silicon wafer by PVD with a thickness of approximately It is formed by a NiFe layer. After fusing at room temperature, the NiFe layer forms a high-resistivity silicide layer with the silicon wafer. A Co surface control layer with a thickness of approximately [missing information] is formed on the silicide layer by PVD. A BiSb layer with a thickness of approximately [missing information] was formed on the surface control layer using PVD. A Co surface control layer with a thickness of approximately [missing information] was formed on the BiSb layer by PVD. A metal layer with a thickness of approximately NiFeTa is formed on the surface control layer. and Pt The surface control layer of Co helps to provide the texture of Pt(111) through the growth of vertical magnetic layers on the amorphous NiFeTa layer.

[0102] Sample 870 was formed on a silicon wafer by PVD with a thickness of approximately It is formed by a NiFeTa layer. The bottom of this NiFeTa layer, after room temperature fusion, forms a high-resistivity silicide layer with the silicon wafer. A NiCu surface control layer, with a thickness of approximately [missing information], is formed on top of the NiFeTa layer by PVD. A BiSb layer with a thickness of approximately [missing information] was formed on the surface control layer using PVD. A Co surface control layer with a thickness of approximately [missing information] was formed on the BiSb layer by PVD. A metal layer with a thickness of approximately NiFeTa is formed on the surface control layer. and Pt The surface control layer of Co helps to provide the texture of Pt(111) through the growth of vertical magnetic layers on the amorphous NiFeTa layer.

[0103] like Figure 7 As shown, X-ray diffraction (XRD) 2θ scans were performed on samples 810, 820, 830, 840, 850, 860, and 870. The samples exhibit a (012) orientation of the BiSb layer, with a low or absent (003) orientation provided by the seed layer and surface control layer of the silicide layer, as well as the interlayer. A non-conductive, single-component, graded silicide layer, mixed with all or part of the metal layer formed on the silicon wafer, was formed on the top surface of the silicon wafer at room temperature. The silicide layer was stable, amorphous, smooth, and high-resistivity, used for growing its BiSb layer. In samples 830 and 850, Cu from the Cu alloy metal layer formed on the silicon wafer tended to be pushed out of the silicide layer, thus forming a Cu layer as a surface control layer for growing the BiSb layer thereon.

[0104] Some Cu remains in the silicide. The surface control layer on the BiSb layer reduces the surface roughness of BiSb and promotes the texture of the magnetic layer formed thereon.

[0105] Example D

[0106] In Example D, a seed layer is deposited over the substrate by PVD deposition, and then a PVD deposition with a thickness of approximately [missing information] is performed on the seed layer. A BiSb layer was formed, thus creating the sample. A capping layer was deposited on the BiSb layer. The surface roughness of the BiSb interface was measured using XRR. Some samples were further annealed at around 210°C, and the surface roughness of the BiSb interface was remeasured. The measured surface roughness was plotted on... Figure 9 middle.

[0107] Sample 901 includes a thickness of approximately [missing information - likely a number] deposited on a silicon wafer. The Ta seed layer. (By...) silicon NiFe, Si and A layered silicide capping layer composed of Fe was deposited on the BiSb layer, resulting in an effective total thickness of approximately [missing information]. Sample 902 includes a thickness of approximately [missing information - likely a number] deposited on a silicon wafer. The Cr seed layer. (From) silicon NiFe, Si and A layered silicide capping layer composed of Fe was deposited on the BiSb layer, resulting in an effective total thickness of approximately [missing information]. Sample 903 includes deposits deposited to approximately Thickness of Si and deposited to approximately A seed layer of Cu of a certain thickness. (From...) silicon NiFe, Si and A layered silicide capping layer composed of Fe was deposited on the BiSb layer, resulting in an effective total thickness of approximately [missing information]. Sample 904 includes a thickness of approximately [missing information - likely a number] deposited on a silicon wafer. NiFe seed layer. Deposited on the BiSb layer using... cobalt, NiFeTa and A capping layer composed of Pt. Sample 905 includes a layer deposited on a silicon wafer with a thickness of approximately Cu seed layer. A layer of material is deposited on top of the BiSb layer. cobalt, NiFeTa and A capping layer composed of Pt. Sample 906 includes a layer deposited on a silicon wafer with a thickness of approximately [missing information]. NiFe and redeposited to a thickness of approximately A Cu seed layer. A layer of Cu is deposited on top of the BiSb layer. cobalt, NiFeTa and A capping layer composed of Pt. Sample 907 includes a layer deposited on a silicon wafer with a thickness of approximately A CoCu seed layer. A layer of material is deposited on top of the BiSb layer. cobalt, NiFeTa and A capping layer composed of Pt. Sample 908 includes a layer deposited on a silicon wafer with a thickness of approximately NiFeTa seed layer. Deposited on the BiSb layer by... cobalt, NiFeTa and A capping layer composed of Pt. Sample 909 includes a layer deposited on a silicon wafer with a thickness of approximately NiFeTa and redeposited to a thickness of approximately A seed layer of NiCu. Deposited on the BiSb layer using... cobalt, NiFeTa and A capping layer composed of Pt. Sample 910 includes a layer deposited on a silicon wafer with a thickness of approximately Co seed layer. Deposited on BiSb layer by... cobalt, NiFeTa and A capping layer composed of Pt. Sample 911 includes a layer deposited on a silicon wafer with a thickness of approximately NiCu seed layer. A layer of material is deposited on top of the BiSb layer. cobalt, NiFeTa and The capping layer consists of Pt. Sample 912 includes Si deposited to approximately Thickness, then NiFe is deposited to approximately Thickness, then Cu is deposited to approximately A seed layer of varying thickness. (From) silicon NiFe, Si and A layered silicide capping layer composed of Fe was deposited on the BiSb layer, resulting in an effective total thickness of approximately [missing information]. Sample 913 includes NiFe deposited to approximately The thickness is then Si is deposited to approximately [a certain thickness]. The thickness was then increased, and NiFe was deposited to approximately [a certain thickness]. The thickness is then increased, and Cu is deposited to approximately [a certain thickness]. The thickness of the seed layer. (By...) silicon NiFe, Si and A layered silicide capping layer composed of Fe was deposited on the BiSb layer, resulting in an effective total thickness of approximately [missing information].

[0108] Each sample consists of a silicide layer formed by mixing metal with the underlying silicon wafer and / or a metal-mixed layer formed with deposited silicon. Samples 901 and 902 with metal seed layers exhibit BiSb layers with high surface roughness. Samples 903-913 with seed layers consisting of silicide layers show BiSb layers with low surface roughness.

[0109] Example E

[0110] In Example E, the sample was deposited using PVD to form a thickness of approximately Si and A NiFe laminate was stacked. After room temperature fusion, the laminate was stacked on top of or throughout the silicon wafer to form a high-resistivity silicide layer. A Cu surface control layer with a thickness of approximately [missing information] was formed on the silicide layer by PVD. A BiSb layer with a thickness of approximately [missing information] was formed on the surface control layer using PVD.

[0111] Sample 1001 includes a layer of approximately [thickness missing] formed on a BiSb layer by PVD. A Ta layer of approximately [thickness missing]. Sample 1002 includes a BiSb layer formed by PVD with a thickness of [thickness missing]. The Ta layer. Sample 1003 includes a BiSb layer with a thickness of approximately formed by PVD. The Cr layer.

[0112] Sample 1004 includes a layer of approximately [thickness missing] formed on a BiSb layer by PVD. The Si interlayer.

[0113] Sample 1005 comprises a sandwich of laminated stacks formed on a BiSb layer by PVD, with a thickness of approximately Cu. and a-Si Some Cu forms silicides, while most of Cu remains metallic Cu.

[0114] Sample 1006 comprises a sandwich of laminated stacks formed on a BiSb layer by PVD, with a thickness of approximately NiFe. and Si After fusion at room temperature, the sandwich laminates are stacked to form a high-resistivity, single-component, hierarchical silicide layer.

[0115] Sample 1007 comprises a sandwich of laminated stacks formed on a BiSb layer by PVD, with a thickness of approximately Si. and NiFe After fusion at room temperature, the sandwich laminates are stacked to form a high-resistivity, single-component, hierarchical silicide layer.

[0116] Sample 1008 comprises a sandwich of laminated stacks formed on a BiSb layer by PVD, with a thickness of approximately NiFe. and Si After fusion at room temperature, the sandwich laminates are stacked to form a high-resistivity, single-component, hierarchical silicide layer.

[0117] The surface roughness of the deposited sample was measured. The sample was further annealed at a temperature of approximately 210°C, and the surface roughness was measured again. Figure 10 The surface roughness of the deposited and annealed samples is plotted. Samples 1001, 1002, and 1003 show higher surface roughness after annealing, indicating that the metal layer on the BiSb layer did not improve the smoothness of the BiSb layer by allowing Sb migration during annealing. Samples 1004, 1005, 1006, 1007, and 1008 show lower surface roughness after annealing, indicating that the interlayer on the BiSb layer improved the smoothness of the BiSb layer by restricting Sb migration during annealing.

[0118] Example F

[0119] In Example F, sample 1101 was formed by PVD of a CoCu seed layer on a silicon wafer, with a thickness of approximately The bottom portion of the seed layer, after room temperature fusion with the top portion of the silicon wafer, forms a high-resistivity, single-component, hierarchical silicide layer. A BiSb layer with a thickness of approximately [missing information] is then formed on the top portion of the seed layer via PVD. A Co interlayer with a thickness of approximately [missing information] was formed on the BiSb layer by PVD. A Pt seed layer is deposited above the interlayer, such as for growing PMA layers.

[0120] Sample 1102 is a seed layer formed by PVD, which is approximately NiFe and The thickness is [not specified]. The NiFe in the seed layer, after room temperature fusion with the top portion of the silicon wafer, forms a high-resistivity, single-component, hierarchical silicide layer. A BiSb layer with a thickness of approximately [not specified] is formed on the Cu of the seed layer via PVD. A NiCu interlayer with a thickness of approximately [missing information] was formed on the BiSb layer by PVD. NiCu interlayers can also be laminates consisting of thin Ni and Cu layers. A Pt seed layer is deposited on top of the interlayer, for example, for growing PMA layers.

[0121] Sample 1104 was prepared by PVD on NiCu A control layer with a thickness of approximately A NiFe seed layer was formed. After the NiFe in the seed layer fused with the top portion of the silicon wafer at room temperature, a high-resistivity, single-component, hierarchical silicide layer was formed. A BiSb layer with a thickness of approximately [missing information - likely a unit of measurement] was then formed on the NiCu control layer via PVD. A Co interlayer with a thickness of approximately [missing information] was formed on the BiSb layer by PVD. A Pt seed layer is deposited above the interlayer, such as for growing PMA layers.

[0122] Sample 1105 was prepared by PVD. An amorphous seed NiFeTa33 layer, approximately NiFeTa33 in thickness, is formed beneath the NiCu control layer. NiCu interlayers can also be laminates composed of thin Ni and Cu layers. A NiFeTa33 seed layer, after room temperature fusion with the top portion of a silicon wafer, forms a high-resistivity, single-composition, hierarchical silicide layer. A BiSb layer with a thickness of approximately [missing information] is formed on the NiCu control layer via PVD. A Co interlayer with a thickness of approximately [missing information] was formed on the BiSb layer by PVD. A Pt seed layer is deposited above the interlayer, such as for growing PMA layers.

[0123] Sample 1106 is a NiCu seed layer formed by PVD, with a thickness of approximately NiCu interlayers can also be laminates composed of thin Ni and Cu layers. Some Ni seed layers, after room temperature fusion with the top portion of a silicon wafer, form high-resistivity, single-component, hierarchical silicide layers. BiSb layers with a thickness of approximately [missing information] are formed on the NiCu control layer via PVD. A Co interlayer with a thickness of approximately [missing information] was formed on the BiSb layer by PVD. A Pt seed layer is deposited above the interlayer, such as for growing PMA layers.

[0124] like Figure 11 As shown, X-ray diffraction (XRD) 2θ scans were performed on samples 1101, 1102, 1104, 1105, and 1106. These samples show a (012) orientation of the BiSb layer, with a low or no (003) orientation provided by the seed layer and interlayer. Each sample has a silicide layer formed from the seed layer and the top surface of the silicon wafer. Each of these samples includes an interlayer, which helps to improve the roughness of the BiSb (i.e., increase the smoothness during annealing). The interlayer can be selected to enhance the texture of subsequent layers, such as the seed layer of a vertical magnetic layer. For example, sample 1102 shows that the interlayer of the Ni / Cu layer composite enhances the (111) texture to obtain better vertical magnetic anisotropy properties, such as for the growth of Pt (111) for a PMA seed layer. Sample 1105 shows that NiCu is used as a control layer, which can also be used to enhance the growth of the Pt (111) seed layer texture for a PMA layer when used with an amorphous seed layer NiFeTa.

[0125] Example G

[0126] In Example G, an amorphous NiFeTa layer is deposited on the substrate by PVD, and a BiSb layer is deposited on the NiFeTa layer to approximately [the desired thickness]. The thickness is thus formed into a sample. The NiFeTa layer of sample 1201 contains approximately 62 atomic % of Ta and is deposited to The thickness. The NiFeTa layer of sample 1202 contains approximately 33 atomic % of Ta and is deposited to The thickness. The NiFeTa layer of sample 1203 contains approximately 27 atomic % of Ta and is deposited to The thickness. The NiFeTa layer of sample 1204 contains approximately 22 atomic % of Ta and is deposited to The thickness.

[0127] Figure 12 Shows the XRD 2θ scan of the amorphous NiFeTa seed composition with BiSb(012) texture, where the composition of Ta matches the expected value of the measured lattice parameter of the amorphous-based alloy, which matches the approximately rectangular surface (short 'a' side) of BiSb(012).

[0128] Compared with sample 1203, sample 1202 shows more BiSb(012) texture. Compared with sample 1204, sample 1203 shows more BiSb(012) texture. Compared with sample 1201, sample 1204 shows more BiSb(012) texture.

[0129] Figure 12 The inset in shows the surface schematic diagram of the amorphous NiFeTa layer. The amorphous NiFeTa layer shows a surface with local hexagonal symmetry and uniform grain size.

[0130] Example H

[0131] Figure 13 Shows the relationship diagram of the lattice spacing of the amorphous peak converted to the fcc a-axis and the alloy elements (NiFe)(1-x)M with M = Ta, W, Si x The rectangular box represents the lattice parameter range of the amorphous alloy to produce a strong (012) BiSb texture, as well as the composition range of the NiFeM amorphous alloy, where M = Ta, W, Si. For the alloy element (NiFe)(1-x)M x (M = Ta), within the lattice parameter range in the rectangular box to match BiSb and produce a strong (012) BiSb texture, the W for NiFeTa x Is 22 < x < 43, such as 32 < x < 37, and for NiFeW xIt is 19 < x < 40, such as 28 < x < 40. The NiFeSi lattice seems to be lower than the lattice spacing to directly promote a strong BiSb(012) texture. However, when NiFeSi is used together with a surface control layer such as Cu, CuAgNi, NiFeSi promotes a strong BiSb(012) texture. For example, forming a NiFe silicide with a thickness of about to and forming a Cu or CuAgNi seed layer with a thickness of about to thereon can promote a strong BiSb(012) texture.

[0132] Example I

[0133] Figure 14 shows a relationship diagram of the amorphous peak lattice spacing converted to hcp (square root coefficient) and the alloy element (NiFe)(1 - x)M with M = Ta, W, Si x composition. For amorphous silicides whose lattice parameters are not within this range, such as NiFeSi, they do not directly promote the BiSb(012) texture, but when used together with a surface control layer having a (111) ffc or (002) hcp texture within this range, then the silicide promotes a strong BiSb(012) texture. For example, forming a NiFe silicide with a thickness of about to and forming a Cu or CuAgNi seed layer with a thickness of about to thereon can promote a strong BiSb(012) texture.

[0134] Although the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be envisioned without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device, comprising: Substrate; A seed layer above the substrate, the seed layer comprising: A silicide layer comprising a material selected from the group consisting of NiSi, NiFeSi, NiFeTaSi, NiCuSi, NiCoSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, and combinations thereof; and A surface control layer comprising a material selected from the group consisting of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, and combinations thereof, wherein M is selected from the group consisting of Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, and Si; and The seed layer has a bismuth-antimony layer with a (012) orientation; and The surface control layer is located between the silicide layer and the bismuth-antimony layer.

2. The SOT MTJ device according to claim 1, wherein the thickness of the silicide layer is from 1 Å to 30 Å.

3. The SOT MTJ device of claim 1, wherein one or more laminated stacked silicide layers comprise a silicon layer and a metal layer, the metal layer comprising a material selected from the group consisting of Ni, NiFe, NiFeTa, NiCu, Co, CoFe, CoFeTa, CoCu, and combinations thereof.

4. The SOT MTJ device of claim 3, wherein the silicide layer comprises one to four laminated stacks.

5. The SOT MTJ device according to claim 1, wherein the thickness of the surface control layer is 1 Å to 20 Å.

6. The SOT MTJ device of claim 1, wherein the surface control layer comprises a first layer above the silicide layer and a second layer above the first layer. The first layer comprises a material selected from the group consisting of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuAg, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoCu, and combinations thereof, wherein M is selected from the group consisting of Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, and Si. The second layer comprises materials selected from the group consisting of CoNi, NiSi, CoSi, NiCoSi, CuAgNi, CuM, CuNiM, Ni, CoCu, Cu, Co, NiCu and combinations thereof, wherein M is selected from the group consisting of Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti and Si.

7. The SOT MTJ device according to claim 1, further comprising a silicon substrate between the substrate and the seed layer, the silicon substrate having a thickness of 1 Å to 30 Å.

8. A magnetic medium driver, the magnetic medium driver comprising the SOT MTJ device according to claim 1.

9. A magnetoresistive random access memory device, the magnetoresistive random access memory device comprising the SOT MTJ device according to claim 1.

10. A magnetic recording write head, the magnetic recording write head comprising the SOT MTJ device according to claim 1.

11. A spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device, comprising: Substrate; A seed layer disposed above the substrate, the seed layer comprising: A first silicide layer comprising a material selected from the group consisting of NiSi, NiFeSi, NiFeTaSi, NiCuSi, NiCoSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, and combinations thereof; and A first surface control layer comprising a material selected from the group consisting of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, and combinations thereof, wherein M is selected from the group consisting of Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, and Si; A bismuth-antimony layer above the seed layer, the bismuth-antimony layer having a (012) orientation, wherein the first surface control layer is located between the first silicide layer and the bismuth-antimony layer; and The interlayer above the bismuth-antimony layer, the interlayer comprising: The second silicide layer comprises a material selected from the group consisting of NiSi, FeSi, CoSi, NiCuSi, NiCoSi, NiFeTaSi, CoCuSi, and combinations thereof.

12. The SOT MTJ device of claim 11, wherein the thickness of the second silicide layer is from 1 Å to 30 Å.

13. The SOT MTJ device of claim 11, wherein the second silicide layer comprises one or more laminated stacks, the laminates comprising a silicon layer and a metal layer, the metal layer comprising a material selected from the group consisting of Ni, Fe, Co, NiCu, NiFeTa, CoCu, NiFe, NiFeCu, Cu, and combinations thereof.

14. The SOT MTJ device of claim 13, wherein the second silicide layer comprises one to four laminated stacks.

15. The SOT MTJ device of claim 11, wherein the interlayer further comprises a second surface control layer between the bismuth-antimony layer and the second silicide layer, the second surface control layer comprising a material selected from the group consisting of Cu, Ni, NiFe, Co, NiCu, NiFeTa, CoCu, NiFeCu, and combinations thereof.

16. The SOT MTJ device of claim 15, wherein the thickness of the interlayer is 1 Å to 10 Å.

17. The SOT MTJ device of claim 11, further comprising a vertical magnetic anisotropy (PMA) ferromagnetic layer above the interlayer.

18. A magnetic medium driver, the magnetic medium driver comprising the SOT MTJ device according to claim 11.

19. A magnetoresistive random access memory device, the magnetoresistive random access memory device comprising the SOT MTJ device according to claim 11.

20. A magnetic recording write head, the magnetic recording write head comprising the SOT MTJ device according to claim 11.

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