Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method of fabricating the semiconductor device includes forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and patterning the first SOT layer, the etch stop layer, and the MTJ stack to form an MTJ.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing magnetoresistive random access memory (MRAM) devices. Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for fabricating a semiconductor device, which mainly involves first forming a magnetic tunneling junction (MTJ) stacked structure on a substrate, then forming an etch stop layer on the MTJ stacked structure, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stacked structure to form an MTJ.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate, a first spin orbit torque (SOT) layer disposed on the MTJ, a spacer wall disposed next to the MTJ and the first SOT layer, and a second SOT layer disposed on the first SOT layer.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate, a first spin orbit torque (SOT) layer disposed on the MTJ, an etch stop layer disposed between the MTJ and the first SOT layer, and a second SOT layer disposed on the first SOT layer. Attached Figure Description

[0007] Figures 1 to 6 This is a schematic diagram of a method for fabricating an MRAM cell according to an embodiment of the present invention;

[0008] Figures 7 to 12 This is a schematic diagram of a method for fabricating an MRAM cell according to an embodiment of the present invention;

[0009] Figure 13 This is a schematic diagram of the structure of an MRAM cell according to an embodiment of the present invention.

[0010] Explanation of main component symbols

[0011] 12: Base

[0012] 14: MRAM region

[0013] 16: Logical Area

[0014] 18: Interlayer dielectric layer

[0015] 20: Metal interconnect structure

[0016] 22: Metal interconnect structure

[0017] 24: Intermetallic dielectric layer

[0018] 26: Metal interconnects

[0019] 28: Stop Layer

[0020] 30: Intermetallic dielectric layer

[0021] 32: Metal interconnects

[0022] 34: Barrier Layer

[0023] 36: Metal layer

[0024] 38: Lower electrode

[0025] 40: MTJ stacked structure

[0026] 42: Upper electrode

[0027] 44: First SOT layer

[0028] 46: Patterned Mask

[0029] 48:MTJ

[0030] 50: Covering layer

[0031] 52: Intermetallic dielectric layer

[0032] 54: Second SOT layer

[0033] 56: Intermetallic dielectric layer

[0034] 58: Metal interconnects

[0035] 60: Stop Layer

[0036] 62: Intermetallic dielectric layer

[0037] 64: Metal interconnects

[0038] 66: Interstitial wall

[0039] 112: Base

[0040] 114: MRAM region

[0041] 116: Logical Region

[0042] 118: Interlayer dielectric layer

[0043] 120: Metal interconnect structure

[0044] 122: Metal interconnect structure

[0045] 124: Intermetallic dielectric layer

[0046] 126: Metal interconnects

[0047] 128: Stop Layer

[0048] 130: Intermetallic dielectric layer

[0049] 132: Metal interconnect

[0050] 134: Barrier Layer

[0051] 136: Metal layer

[0052] 138: Lower electrode

[0053] 140: MTJ stacked structure

[0054] 142: Upper electrode

[0055] 144: First SOT Layer

[0056] 146: Hard Mask

[0057] 148:MTJ

[0058] 150: Covering layer

[0059] 152: Intermetallic dielectric layer

[0060] 154: Second SOT Layer

[0061] 156: Intermetallic Dielectric Layer

[0062] 158: Metal interconnects

[0063] 160: Stop Layer

[0064] 162: Intermetallic dielectric layer

[0065] 164: Metal interconnects

[0066] 166: Etching Stop Layer

[0067] 168: Interstitial wall Detailed Implementation

[0068] Please refer to Figures 1 to 6 , Figures 1 to 6 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0069] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0070] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0071] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethylorthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0072] Next, a lower electrode 38, an MTJ stack structure 40, an upper electrode 42, a first spin orbit torque (SOT) layer 44, and a patterned mask 46 are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 40 can be formed by first sequentially forming a pinned layer, a barrier layer, and a free layer on the lower electrode 38. In this embodiment, the lower electrode 38 and the upper electrode 42 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixing layer can also be made of antiferromagnetic (AFM) materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer can be made of insulating materials containing oxides, such as aluminum oxide (AlOx) or magnesium oxide (MgO), but is not limited to these. The free layer can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer can be "freely" changed by an external magnetic field. In this embodiment, the first SOT layer 44 is preferably used as a channel for a spin orbit torque (SOT) MRAM, therefore its material can include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (Bi). x Se 1-x (or a combination thereof). The patterned mask 46 may contain conductive or dielectric materials, such as, but not limited to, titanium nitride.

[0073] Subsequently, as Figures 1 to 2As shown, using a patterned mask 46 as a mask, one or more etching processes are performed to remove a portion of the first SOT layer 44, a portion of the upper electrode 42, a portion of the MTJ stack structure 40, a portion of the lower electrode 38, and a portion of the intermetallic dielectric layer 30 to form at least one MTJ 48 in the MRAM region 14, and then the patterned mask 46 is removed. It is worth noting that the etching process performed on the patterned upper electrode 42, MTJ stack structure 40, lower electrode 38, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. It should also be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, part of the metal interconnects 32 can be removed at the same time, so that the metal interconnects 32 form an inclined sidewall near the junction of MTJ 48.

[0074] A masking layer 50 is then formed on the MTJ 48, covering the surface of the intermetallic dielectric layer 30 of the MRAM region 14 and the logic region 16. In this embodiment, the masking layer 50 preferably comprises silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to the fabrication process requirements.

[0075] Then as Figure 3 As shown, without using any patterned mask, such as a patterned photoresist, an etching process is directly performed to remove part of the masking layer 50 to form a spacer wall 66 surrounding or disposed on the sidewalls of the MTJ 48 and the first SOT layer 44. The spacer wall 66 formed preferably presents an approximately I-shape at the cross-sectional angle. Then, a deposition process, such as atomic layer deposition (ALD), is performed to form an intermetallic dielectric layer 52 on the first SOT layer 44, the spacer wall 66, and the intermetallic dielectric layer 30. Then, a planarization process, such as chemical mechanical polishing (CMP) or etch-back process, is performed to remove part of the intermetallic dielectric layer 52, so that the top surface of the remaining intermetallic dielectric layer 52 is approximately flush with the top surface of the spacer wall 66 and the top surface of the first SOT layer 44.

[0076] Subsequently, as Figure 4As shown, a second SOT layer 54 is first formed on the first SOT layer 44 and the intermetallic dielectric layer 52. Then, a pattern transfer fabrication process is performed, for example, using a patterned mask (not shown) to remove a portion of the second SOT layer 54 located on the intermetallic dielectric layer 52. This leaves the remaining second SOT layer 54 on the intermetallic dielectric layers 52 on both sides of the first SOT layer 44, in addition to being located on the first SOT layer 44 and the spacer 66. In this embodiment, the second SOT layer 54 and the first SOT layer 44 preferably contain the same material. The second SOT layer 54 also serves as a channel for a spin orbit torque (SOT) MRAM, therefore its material can include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), and bismuth selenide (Bi). x Se 1-x (or a combination thereof).

[0077] like Figure 5 As shown, another intermetallic dielectric layer 56 is then formed on the second SOT layer 54 and the intermetallic dielectric layers 52 on both sides. The intermetallic dielectric layer 56 is preferably conformally disposed on the second SOT layer 54, and the intermetallic dielectric layers 52 and 56 may contain an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, for example, but not limited to silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH). Next, a planarization process is performed, for example, using a chemical mechanical polishing (CMP) process or an etch-back process to remove part of the intermetallic dielectric layer 56, but leaving the top surface of the remaining intermetallic dielectric layer 56 higher than the top surface of the second SOT layer 54.

[0078] A pattern transfer fabrication process is then performed, for example, by using a patterned mask (not shown) to remove a portion of the intermetallic dielectric layer 56, a portion of the intermetallic dielectric layer 52, a portion of the intermetallic dielectric layer 30, and a portion of the stop layer 28 between MRAM region 14 and logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. The contact holes are then filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, for example, by chemical mechanical polishing to remove a portion of the metal material to form contact plugs or metal interconnects 58 electrically connecting the metal interconnects 26 within the contact holes.

[0079] Then as Figure 6As shown, a stop layer 60 is first formed in the MRAM region 14 and the logic region 16, covering the intermetallic dielectric layer 56 and the metal interconnects 58. An intermetallic dielectric layer 62 is then formed on the stop layer 60. One or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 62 and part of the stop layer 60 in the MRAM region 14 and the logic region 16, forming contact holes (not shown). Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 64 in the MRAM region 14 and the logic region 16, respectively, electrically connecting the underlying MTJ 48 and the metal interconnects 58. Preferably, the metal interconnects 64 in the MRAM region 14 directly contact the underlying second SOT layer 54, while the metal interconnects 64 in the logic region 16 contact the underlying metal interconnects 58.

[0080] In this embodiment, stop layer 60 and stop layer 28 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 64 disposed within the intermetallic dielectric layer 62 can be embedded within the intermetallic dielectric layer 62 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 64 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0081] Please continue to refer to Figures 7 to 12 , Figures 7 to 12 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 7 As shown, a substrate 112 is first provided, for example, a substrate 112 made of semiconductor material, wherein the semiconductor material may be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 114 and a logic region 116 are preferably defined on the substrate 112.

[0082] As in the foregoing embodiments, the substrate 112 may include active components such as metal-oxide-semiconductor (MOS) transistors, passive components, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 118 covering the substrate. More specifically, the substrate 112 may include planar or non-planar (such as fin structure transistors) MOS transistor elements, wherein the MOS transistor may include a gate structure (e.g., a metal gate) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 118 may be disposed on the substrate 112 and cover the MOS transistor, and the interlayer dielectric layer 118 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistor. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0083] Then, metal interconnect structures 120 and 122 are sequentially formed on the interlayer dielectric layer 118 to electrically connect the aforementioned contact plug. The metal interconnect structure 120 includes an intermetal dielectric layer 124 and a metal interconnect 126 embedded in the intermetal dielectric layer 124. The metal interconnect structure 122 includes a stop layer 128, an intermetal dielectric layer 130 and a metal interconnect 132 embedded in the stop layer 128 and the intermetal dielectric layer 30.

[0084] In this embodiment, each metal interconnect 126 in the metal interconnect structure 120 preferably includes a trench conductor, and the metal interconnect 132 in the metal interconnect structure 122 located in the MRAM region 114 includes a via conductor. Furthermore, each metal interconnect 126 and 132 in the metal interconnect structures 120 and 122 can be embedded in the intermetallic dielectric layers 124 and 130 and / or the stop layer 128 using a single damascene fabrication process or a double damascene fabrication process and be electrically connected to each other. For example, each metal interconnect 126, 132 may further include a barrier layer 134 and a metal layer 136. The barrier layer 134 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 136 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or double-damascene fabrication processes are well known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 136 in the metal interconnect 126 preferably contains copper, the metal layer 136 in the metal interconnect 132 preferably contains tungsten, the intermetallic dielectric layers 124 and 130 preferably contain silicon oxide such as tetraethyl orthosilicate (TEOS), and the stop layer 128 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0085] Next, a lower electrode 138, an MTJ stack structure 140, an upper electrode 142, an etch stop layer 166, a first spin orbit torque (SOT) layer 144, and a patterned hard mask 146 are formed on the metal interconnect structure 122. In this embodiment, the MTJ stack structure 140 can be formed by first sequentially forming a pinned layer, a barrier layer, and a free layer on the lower electrode 138. In this embodiment, the lower electrode 138 and the upper electrode 142 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). In addition, the fixed layer can also be made of antiferromagnetic (AFM) materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer can be made of insulating materials containing oxides, such as aluminum oxide (AlOx) or magnesium oxide (MgO), but is not limited to these. The free layer can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer can be "freely" changed by an external magnetic field. In this embodiment, the etch stop layer 166 preferably comprises a metal such as ruthenium (Ru), and the first SOT layer 144 preferably serves as a channel for a spin orbit torque (SOT) MRAM, therefore its material may include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), or bismuth selenide (Bi). x Se 1-x (or a combination thereof). The patterned hard mask 146 may contain conductive or dielectric materials, such as, but not limited to, titanium nitride.

[0086] Then as Figures 7 to 8As shown, a reactive ion etching (RIE) process is performed using a patterned hard mask 146 as a mask to remove a portion of the first SOT layer 144 and expose the surface of the etch stop layer 166. The etch stop layer 166 preferably prevents the gas components used in the reactive ion etching process from damaging the magnetic material in the underlying MTJ stack structure 140. Subsequently, another etching process, such as ion beam etching (IBE), is performed to remove a portion of the etch stop layer 166, a portion of the upper electrode 142, a portion of the MTJ stack structure 140, a portion of the lower electrode 138, and a portion of the intermetallic dielectric layer 130 to form at least one MTJ 148 in the MRAM region 114. Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 130 is preferably slightly lower than the upper surface of the metal interconnect 132, and the upper surface of the intermetallic dielectric layer 130 preferably has an arc or curved shape. In addition, when removing part of the intermetallic dielectric layer 130 using the ion beam etching process in this embodiment, part of the metal interconnect 132 can be removed at the same time, so that the metal interconnect 132 forms an inclined sidewall near the junction of MTJ 148.

[0087] It is worth noting that after the MTJ 148 is formed using the patterned hard mask 146 in this stage, part of the hard mask 146 remains on top of the first SOT layer 144. Then, a masking layer 150 is formed on the hard mask 146 and covers the surface of the inter-metal dielectric layer 130 of the MRAM region 114 and the logic region 116. In this embodiment, the masking layer 150 preferably contains silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide can be selected according to the fabrication process requirements.

[0088] Then as Figure 9 As shown, a photolithography and etching process can be performed. For example, a patterned mask (not shown) such as a patterned photoresist can be used as the mask. An etching process can be used to remove part of the masking layer 150, followed by a deposition process such as atomic layer deposition (ALD) to form an intermetallic dielectric layer 152 on the masking layer 150. It should be noted that when patterning the masking layer 150 using the patterned mask in this stage, the intermetallic dielectric layer 130 below the masking layer 150 can be patterned simultaneously according to the manufacturing process or product requirements, so that the sidewalls of the masking layer 150 are flush with the sidewalls of the intermetallic dielectric layer 130. This variation is also within the scope of this invention.

[0089] Then, a planarization process can be performed first, such as chemical mechanical polishing (CMP) to remove part of the intermetallic dielectric layer 152, so that the top of the remaining intermetallic dielectric layer 152 is roughly flush with the top of the masking layer 150. Then, an etching process is used to remove part of the intermetallic dielectric layer 152 and part of the masking layer 150 at the same time, thereby forming a spacer wall 168 of the remaining masking layer 150 on the sidewalls of MTJ 148, etch stop layer 166 and first SOT layer 144. At the same time, the spacer wall 168 is roughly flush with the top surface of the remaining intermetallic dielectric layer 152, and the top surfaces of both are slightly lower than the top surface of the first SOT layer 144 but higher than the top surface of the etch stop layer 166. Or, from another angle, the first SOT layer 144 protrudes slightly from the intermetallic dielectric layer 152. It should be noted that although this embodiment uses a patterned mask to form a gap wall 168 with an approximate L-shaped cross section, it is not limited thereto. According to other embodiments of the present invention, a gap wall with an I-shaped cross section can be formed by analogy with the foregoing embodiment. If the gap wall has an I-shaped cross section, the top surface of the gap wall is preferably flush with the top surface of the first SOT layer 144. This variation is also within the scope of the present invention.

[0090] Subsequently, as Figure 10 As shown, a second SOT layer 154 is formed and fully covers the hard mask 146, the first SOT layer 144, the spacer wall 168, and the intermetallic dielectric layer 152. Then, a pattern transfer fabrication process is performed, for example, using a patterned mask (not shown) as a mask to remove part of the second SOT layer 154 located on the intermetallic dielectric layer 152, so that the remaining second SOT layer 154, except for being located on the top surface of the hard mask 146, the sidewalls of the first SOT layer 144, and the top surface of the spacer wall 168, is still located on the intermetallic dielectric layer 152 on both sides of the spacer wall 168. The sidewalls of the remaining second SOT layer 154 can be approximately flush with the sidewalls of the spacer wall 168 below.

[0091] In this embodiment, the second SOT layer 154 and the first SOT layer 144 preferably contain the same material. The second SOT layer 154 also serves as a channel for a spin orbit torque (SOT) MRAM, therefore its material may include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), or bismuth selenide (Bi). x Se 1-x(or a combination thereof). It should also be noted that the second SOT layer 154 formed in this stage is preferably conformally disposed on the top surface of the hard mask 146, the sidewalls of the first SOT layer 144, and the surface of the gap wall 168 and the intermetallic dielectric layer 152. Therefore, the top surface of the second SOT layer 154 disposed above the intermetallic dielectric layer 152 is preferably lower than the top surface of the second SOT layer 154 disposed directly above the hard mask 146 or the first SOT layer 144.

[0092] like Figure 11 As shown, another intermetallic dielectric layer 156 is then formed on the second SOT layer 154 and the intermetallic dielectric layers 152 on both sides. The intermetallic dielectric layers 152 and 156 may contain an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH). Next, a planarization process is performed, such as a chemical mechanical polishing (CMP) process or an etch-back process, to remove part of the intermetallic dielectric layer 156 or even part of the second SOT layer 154 located directly above the hard mask 146, so that the top surface of the remaining second SOT layer 154 is approximately flush with the top surface of the intermetallic dielectric layer 156.

[0093] A pattern transfer fabrication process is then performed, for example, by using a patterned mask (not shown) to remove a portion of the intermetallic dielectric layer 156, a portion of the intermetallic dielectric layer 152, a portion of the intermetallic dielectric layer 130, and a portion of the stop layer 128 between the MRAM region 114 and the logic region 116 to form contact holes (not shown) and expose the underlying metal interconnects 126. The contact holes are then filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Next, a planarization fabrication process is performed, for example, by chemical mechanical polishing to remove a portion of the metal material to form contact plugs or metal interconnects 158 electrically connecting the metal interconnects 26 within the contact holes.

[0094] Then as Figure 12As shown, a stop layer 160 is first formed in the MRAM region 114 and the logic region 116, covering the intermetallic dielectric layer 156 and the metal interconnects 158. An intermetallic dielectric layer 162 is then formed on the stop layer 160. One or more photolithography and etching processes are performed to remove portions of the intermetallic dielectric layer 162 and the stop layer 160 in the MRAM region 114 and the logic region 116, forming contact holes (not shown). Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 164 in the MRAM region 114 and the logic region 116, electrically connecting to the underlying MTJ 148 and the metal interconnects 158. Preferably, the metal interconnects 164 in the MRAM region 114 directly contact the underlying second SOT layer 154, while the metal interconnects 164 in the logic region 116 contact the underlying metal interconnects 158.

[0095] In this embodiment, stop layer 160 and stop layer 128 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, metal interconnects 164 disposed within the intermetallic dielectric layer 162 can be embedded within the intermetallic dielectric layer 162 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnect 164 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0096] Please refer to again Figure 13 , Figure 13 A schematic diagram of the structure of an MRAM cell according to an embodiment of the present invention is also disclosed. For example... Figure 13 As shown, the present invention can be used in Figure 11During the planarization process of forming the intermetallic dielectric layer 156, only a portion of the intermetallic dielectric layer 156 is removed, but the second SOT layer 154 directly above the hard mask 146 is not removed. In other words, after forming the intermetallic dielectric layer 156, the top surface of the second SOT layer 154 disposed above the intermetallic dielectric layer 152 is preferably still lower than the top surface of the second SOT layer 154 disposed directly above the hard mask 146 or the first SOT layer 144. This variation is also within the scope of this invention.

[0097] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Include: A magnetic tunneling junction (MTJ) stack structure is formed on the substrate; An etch stop layer is formed on the magnetic tunneling junction stack structure; A first spin orbit torque (SOT) layer is formed on the etch stop layer; as well as The first spin-orbit torque layer, the etch stop layer, and the magnetic tunneling junction stack are patterned to form a magnetic tunneling junction. The substrate includes an MRAM region and a logic region, and the method includes: A first intermetallic dielectric layer is formed on the substrate; A first metal interconnect is formed within the first intermetallic dielectric layer of the MRAM region; A hard mask is formed on the first spin-orbit torque layer; The magnetic tunnel junction is formed on the first metal interconnect. A masking layer is formed on the hard mask and the first intermetallic dielectric layer; A second intermetallic dielectric layer is formed on the cover layer; A second spin-orbit torque layer is formed on the hard mask and the second intermetallic dielectric layer; Pattern the second spin-orbit torque layer; A third intermetallic dielectric layer is formed on the second spin-orbit torque layer; as well as A second metal interconnect is formed in this logic region.

2. The method of claim 1, further comprising: Pattern the overlay layer; The second intermetallic dielectric layer is formed on the cover layer; Remove the masking layer and the second intermetallic dielectric layer to expose the hard mask, wherein the top surface of the masking layer is lower than the top surface of the first spin-orbit torque layer; and The second spin-orbit torque layer is formed on the hard mask, the cover layer, and the second intermetallic dielectric layer.

3. The method of claim 2, further comprising patterning the cover layer and the first intermetallic dielectric layer, wherein the sidewalls of the cover layer are flush with the sidewalls of the first intermetallic dielectric layer.

4. The method of claim 1, further comprising: Remove the masking layer to form a spacer wall surrounding the magnetic tunneling junction, the etch stop layer, and the first spin-orbit torque layer; The second intermetallic dielectric layer is formed on the gap wall; Planarize the second intermetallic dielectric layer; The second spin-orbit torque layer is formed on the hard mask and the second intermetallic dielectric layer; Pattern the second spin-orbit torque layer; The third intermetallic dielectric layer is formed on the second spin-orbit torque layer; as well as The second metal interconnect is formed in the logic region.

5. The method of claim 1, further comprising: A stop layer is formed on the third intermetallic dielectric layer; A fourth intermetallic dielectric layer is formed on the stop layer; A third metal interconnect is formed in the MRAM region and connects to the second spin-orbit torque layer; and A fourth metal interconnect is formed in the logic region and connected to the second metal interconnect.

6. A semiconductor element, characterized in that, Include: A magnetic tunneling junction (MTJ) is located on a substrate. The first spin orbit torque (SOT) layer is disposed on the magnetic tunneling junction; An etch stop layer is disposed between the magnetic tunneling junction and the first spin-orbit torque layer; and The second spin-orbit torque layer is disposed on the first spin-orbit torque layer. The semiconductor element further includes a hard mask disposed between the first spin-orbit torque layer and the second spin-orbit torque layer.

7. The semiconductor device of claim 6, wherein the substrate includes an MRAM region and a logic region, and the semiconductor device comprises: A first intermetallic dielectric layer is disposed on the substrate; The first metal interconnect is disposed within the first metal inter-dielectric layer of the MRAM region; The magnetic tunnel junction is located on the inner interconnect of the first metal; A second intermetallic dielectric layer surrounds the magnetic tunneling junction; and The second metal interconnect is located within the second metal inter-dielectric layer of the logic region.

8. The semiconductor device of claim 7, further comprising: A stop layer is disposed on the second intermetallic dielectric layer; A third intermetallic dielectric layer is disposed on the stop layer; A third metal interconnect is located in the MRAM region and connects to the second spin-orbit torque layer; and The fourth metal interconnect is located in the logic area and connected to the second metal interconnect.

9. The semiconductor device of claim 6, further comprising a spacer wall disposed adjacent to the magnetic tunnel junction and the first spin-orbit torque layer.

10. The semiconductor element of claim 9, wherein the spacer wall comprises an L-shape.

11. The semiconductor device of claim 10, wherein the top surface of the gap wall is lower than the top surface of the first spin-orbit torque layer.

12. The semiconductor element of claim 9, wherein the spacer wall comprises an I-shape.

13. The semiconductor device of claim 12, wherein the top surface of the spacer wall is flush with the top surface of the first spin-orbit torque layer.

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