Texture recognition module and display device

Abstract

The present application provides a texture recognition module and a display device. The texture recognition module includes a substrate, a thin film transistor structure layer located on the substrate, a conductive layer located on the side of the thin film transistor structure layer away from the substrate, and at least one first capacitor plate located on the side of the conductive layer away from the substrate. The texture recognition module includes at least one texture recognition unit, at least one texture recognition unit includes a first capacitor plate, and a first thin film transistor and a second thin film transistor located in the thin film transistor structure layer, the first thin film transistor includes a first pole and a second pole, the first pole is configured to receive an input signal; the second thin film transistor includes a third pole and a fourth pole, the third pole is configured to output the collected texture signal. In at least one of the texture recognition units, the second pole and the fourth pole are electrically connected to the first capacitor plate respectively. The conductive layer includes at least one conductive structure, and the conductive structure is connected to a constant electrical signal.

Description

Technical Field

[0001] The present application relates to the technical field of texture recognition, and in particular to a texture recognition module and a display device. Background Art

[0002] Organic light-emitting display devices have the advantages of low power consumption, fast response speed, wide viewing angle, high resolution, etc. Not only are their application fields diversified, but display devices are also gradually developing towards multifunctionality. For example, a display device has multiple fingerprint recognition units, which are used for fingerprint recognition.

[0003] The fingerprint recognition unit of the existing display device needs to be improved. Summary of the invention

[0004] According to a first aspect of an embodiment of the present application, a texture recognition module is provided. The texture recognition module includes a substrate, a thin film transistor structure layer located on the substrate, a conductive layer located on a side of the thin film transistor structure layer away from the substrate, and at least one first capacitor plate located on a side of the conductive layer away from the substrate;

[0005] The texture recognition module includes at least one texture recognition unit, and at least one of the texture recognition units includes the first capacitor plate, and a first thin film transistor and a second thin film transistor located in the thin film transistor structure layer; the first thin film transistor includes a first electrode and a second electrode, and the first electrode is configured to receive an input signal; the second thin film transistor includes a third electrode and a fourth electrode, and the third electrode is configured to output a collected texture signal; in at least one of the texture recognition units, the second electrode and the fourth electrode are electrically connected to the first capacitor plate respectively;

[0006] The conductive layer includes at least one conductive structure, and the conductive structure is connected to a constant electrical signal.

[0007] In one embodiment, the conductive layer further includes a transition portion, and at least one of the texture recognition units further includes the transition portion; in at least one of the texture recognition units, the second pole and the fourth pole are electrically connected to the first capacitor plate through the transition portion.

[0008] In one embodiment, in at least one of the texture recognition units, the second electrode and the fourth electrode are electrically connected to the first capacitor plate through different adapters.

[0009] In one embodiment, in at least one of the texture recognition units, the second electrode and the fourth electrode are electrically connected to the first capacitor plate through the same adapter.

[0010] In one embodiment, the transfer portion and the conductive structure are formed in one patterning process.

[0011] In one embodiment, the texture recognition module also includes a first input signal line, a second input signal line and an output signal line arranged in the same layer, and the output signal line is located between the first input signal line and the second input signal line; the first input signal line or the second input signal line is electrically connected to the first pole, and the output signal line is electrically connected to the third pole.

[0012] In one embodiment, the texture recognition module further includes a connecting portion, the connecting portion is located on a side of the first input signal line close to the substrate, and at least one of the first input signal lines is electrically connected to at least one of the second input signal lines through the connecting portion.

[0013] In one embodiment, the first thin film transistor includes a first gate electrode, the second thin film transistor includes a second gate electrode, and the connecting portion, the first gate electrode, and the second gate electrode are formed in one patterning process.

[0014] In one embodiment, the texture recognition module also includes a shielding layer, which is located between the connecting part and the output signal line, and the overlapping part of the orthographic projection of the connecting part on the substrate and the orthographic projection of the output signal line on the substrate overlap with the orthographic projection of the shielding layer on the substrate.

[0015] In one embodiment, the orthographic projection of the output signal line on the substrate falls within the orthographic projection of the shielding layer on the substrate, and / or the orthographic projection of the connecting portion on the substrate falls within the orthographic projection of the shielding layer on the substrate.

[0016] In one embodiment, the first capacitor plate is configured to form a capacitor with the texture to be identified.

[0017] In one embodiment, the conductive structure is electrically connected to the first electrode to provide the input signal to the first electrode.

[0018] In one embodiment, the texture recognition module further includes a second capacitor plate disposed opposite to the first capacitor plate, and a photoelectric material layer located between the first capacitor plate and the second capacitor plate.

[0019] In one embodiment, the texture recognition module further includes an output signal line, the output signal line is electrically connected to the third electrode, and an orthographic projection of the output signal line on the substrate overlaps with an orthographic projection of the conductive structure on the substrate.

[0020] In one embodiment, the texture recognition module further includes a light-emitting layer, the light-emitting layer includes a plurality of sub-pixels, and the first capacitor plate, the photoelectric material layer and the second capacitor plate are respectively located on a side of the light-emitting layer close to the substrate.

[0021] In one embodiment, the texture recognition module further includes a light-emitting layer, the light-emitting layer includes a plurality of sub-pixels, the light-emitting layer includes a first electrode, a light-emitting material layer located on a side of the first electrode away from the substrate, and a second electrode located on a side of the light-emitting material layer away from the substrate; the second capacitor plate is located on a side of the first capacitor plate away from the substrate;

[0022] The first capacitor plate is disposed in the same layer as the first electrode; and the second capacitor plate is disposed in the same layer as the second electrode.

[0023] In one embodiment, the second capacitor plate is electrically connected to the second electrode.

[0024] According to a second aspect of an embodiment of the present application, a display device is provided, wherein the display device includes the above-mentioned texture recognition module.

[0025] The main technical effects achieved by the embodiments of the present application are:

[0026] The texture recognition module and display device provided by the embodiments of the present application, the texture recognition unit includes a first capacitor plate, a first thin film transistor and a second thin film transistor, the first electrode of the first thin film transistor receives an input signal, and the third electrode of the second thin film transistor outputs the collected texture signal, that is, the first thin film transistor is used to receive the input signal, and the second thin film transistor is used to output the texture signal. Compared with the solution of using one thin film transistor for both receiving the input signal and outputting the texture signal, it helps to simplify the control of the thin film transistor and saves the time for switching the input signal and the output signal of the thin film transistor, which can increase the recognition rate of the texture recognition module and improve the sensitivity of the texture recognition module; the conductive layer is located on the side of the thin film transistor structure layer away from the substrate, the conductive structure connects a stable electrical signal, and the conductive structure can avoid signal interference between the conductive components in the thin film transistor structure layer and the conductive components located on the side of the conductive layer away from the substrate, which helps to improve the accuracy of the collected texture signal, thereby improving the accuracy of texture recognition. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a partial structural schematic diagram of a texture recognition module provided by an exemplary embodiment of the present application;

[0028] Figure 2 yes Figure 1 The cross-sectional view of the texture recognition module shown is obtained by cutting along AA;

[0029] Figure 3 is a partial structural schematic diagram of a texture recognition module provided by another exemplary embodiment of the present application;

[0030] Figure 4 yes Figure 3 The cross-sectional view of the texture recognition module shown is obtained by cutting along BB;

[0031] Figure 5 is a partial cross-sectional view of a texture recognition module provided by another exemplary embodiment of the present application;

[0032] Figure 6 is a partial cross-sectional view of a texture recognition module provided by another exemplary embodiment of the present application;

[0033] Figure 7 is a circuit diagram of a texture recognition module provided by another exemplary embodiment of the present application;

[0034] Figure 8 yes Figure 7 A circuit diagram showing a connection between a texture recognition unit and a processing chip in a texture recognition module;

[0035] Fig. 9 yes Figure 8 The driving timing diagram of the texture recognition unit shown;

[0036] Fig.10 is a partial cross-sectional view of a texture recognition module provided by another exemplary embodiment of the present application;

[0037] Fig.11 It is a partial cross-sectional view of a texture recognition module provided by another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0038] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0039] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0040] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0041] The embodiment of the present application provides a texture recognition module and a display device. The texture recognition module and the display device in the embodiment of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features in the following embodiments can complement or combine with each other.

[0042] The present application embodiment provides a pattern recognition module. Figures 1 to 6 The texture recognition module 100 includes a substrate 10, a thin film transistor structure layer 20 located on the substrate 10, a conductive layer 30 located on a side of the thin film transistor structure layer 20 away from the substrate, and at least one first capacitor plate 41 located on a side of the conductive layer 30 away from the substrate 10.

[0043] The texture recognition module includes at least one texture recognition unit, and at least one of the texture recognition units includes a first capacitor plate 41, and a first thin film transistor 21 and a second thin film transistor 22 located in the thin film transistor structure layer 20. The first thin film transistor 21 includes a first electrode 211 and a second electrode 212, and the first electrode 211 is configured to receive an input signal. The second thin film transistor 22 includes a third electrode 221 and a fourth electrode 222, and the third electrode 221 is configured to output the collected texture signal. In at least one of the texture recognition units, the second electrode 212 and the fourth electrode 222 are electrically connected to the first capacitor plate 41, respectively.

[0044] Among them, one of the first electrode 211 and the second electrode 212 is a source electrode, and the other is a drain electrode; one of the third electrode 221 and the fourth electrode 222 is a source electrode, and the other is a drain electrode. For the first thin film transistor and the second thin film transistor, when using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged. For example, when the first thin film transistor 21 is an N-type transistor, the first electrode 211 is a drain electrode, and the second electrode 212 is a source electrode; when the second thin film transistor 22 is an N-type transistor, the third electrode 221 is a source electrode, and the fourth electrode 222 is a drain electrode. When the first thin film transistor 21 is a P-type transistor, the first electrode 211 is a source electrode, and the second electrode 212 is a drain electrode; when the second thin film transistor 22 is a P-type transistor, the third electrode 221 is a drain electrode, and the fourth electrode 222 is a source electrode.

[0045] The conductive layer 30 includes at least one conductive structure 31, and the conductive structure 31 is connected to a constant electrical signal. For example, the conductive structure 31 is connected to the VDD signal, VSS signal or other constant signals of the texture recognition module, or the conductive structure 31 is grounded, but the present application is not limited thereto. The conductive structure is connected to a constant electrical signal, which means that the value of the electrical signal connected to the conductive structure 31 is fixed, or the value of the electrical signal connected to the conductive structure varies within a certain range, for example, the difference between the maximum value and the minimum value of the electrical signal connected to the conductive structure is less than 0.05V.

[0046] The texture recognition module provided by the embodiment of the present application comprises a first capacitor plate 41, a first thin film transistor 21 and a second thin film transistor 22. The first electrode 211 of the first thin film transistor 21 receives an input signal, and the third electrode 221 of the second thin film transistor 22 outputs the collected texture signal. That is, the first thin film transistor 21 is used to receive the input signal, and the second thin film transistor 22 is used to output the texture signal. Compared with the solution of using one thin film transistor for both receiving the input signal and outputting the texture signal, it helps to simplify the control of the thin film transistor and saves the time for switching the input signal and the output signal of the thin film transistor, which can increase the recognition rate of the texture recognition module and improve the sensitivity of the texture recognition module. The conductive layer 30 is located on the side of the thin film transistor structure layer 20 away from the substrate, and the conductive structure 31 is connected to a constant electrical signal. The conductive structure 31 can avoid signal interference between the conductive components in the thin film transistor structure layer and the conductive components located on the side of the conductive layer 30 away from the substrate, which helps to improve the accuracy of the collected texture signal, thereby improving the accuracy of texture recognition.

[0047] In one embodiment, the pattern recognition module is used to recognize patterns to be recognized, the patterns to be recognized include fingerprints, palm prints, toe prints, etc., and the parts of the patterns to be recognized include fingers, palms, toes, etc.

[0048] In one embodiment, the substrate 10 may be a rigid substrate, and the material of the rigid substrate is, for example, glass or metal. In another embodiment, the substrate 10 may also be a flexible substrate, and the material of the flexible substrate may include one or more of PI (polyimide), PET (polyethylene terephthalate) and PC (polycarbonate).

[0049] In one embodiment, the first thin film transistor 21 may further include a first active layer 213 and a first gate electrode 214. The first active layer 213 includes a channel region 215, and a first region 216 and a second region 217 located on both sides of the channel region 215. The first gate electrode 214 is located on the side of the first active layer 213 away from the substrate 10 or on the side close to the substrate 10. The embodiment of the present application does not limit the position of the first gate electrode 214. The position of the first gate electrode 214 has no absolute relationship with the position of the conductive layer, substrate, and first capacitor plate of the texture recognition module. The first electrode 211 is electrically connected to the first region 216, and the second electrode 212 is electrically connected to the second region 217. The first gate electrode 214 of the first thin film transistor 21 is connected to the first scan line G1, and the first scan line G1 provides a scan signal to the first gate electrode 214 to control the first thin film transistor 21 to be turned on or off.

[0050] The second thin film transistor 22 may also include a second active layer 223 and a second gate electrode 224. The second active layer 223 includes a channel region 225, and a third region 226 and a fourth region 227 located on both sides of the channel region 225. The second gate electrode 224 is located on the side of the second active layer 223 away from the substrate 10 or on the side close to the substrate 10. The embodiment of the present application does not limit the position of the second gate electrode 224. The position of the second gate electrode 224 has no absolute relationship with the position of the conductive layer, substrate, and first capacitor plate of the pattern recognition module. The third electrode 221 is electrically connected to the third region 226, and the fourth electrode 222 is electrically connected to the fourth region 227. The second gate electrode 224 of the second thin film transistor 22 is connected to the second scan line G2, and the second scan line G2 provides a scan signal to the second gate electrode 224 to control the second thin film transistor 22 to be turned on or off. The second gate electrode 224 and the first gate electrode 214 are located in the same layer and can be formed in a single patterning process. The first active layer 213 and the second active layer 223 may be located on the same layer.

[0051] like Figure 2 and Figure 4As shown, when the first gate electrode 214 is located on the side of the first active layer 213 facing away from the substrate 10, and the second gate electrode 224 is located on the side of the second active layer 223 facing away from the substrate 10, the thin film transistor structure layer 20 may further include a gate electrode insulating layer 51 located between the first active layer 213 and the first gate electrode 214, and an interlayer dielectric layer 52 located on the side of the first gate electrode 214 facing away from the substrate 10. The first pole 211 and the second pole 212 penetrate the gate insulating layer 51 and the interlayer dielectric layer 52 respectively, and are electrically connected to the first active layer 213. The third pole 221 and the fourth pole 222 penetrate the gate insulating layer 51 and the interlayer dielectric layer 52 respectively, and are electrically connected to the second active layer 223. The embodiment of the present application does not limit the shape of the gate insulating layer. In another embodiment, the gate insulating layer is a patterned film layer, and the orthographic projection of the portion of the gate insulating layer corresponding to the first gate electrode 214 on the substrate roughly coincides with the orthographic projection of the first gate electrode 214 on the substrate, and the orthographic projection of the portion of the gate insulating layer corresponding to the second gate electrode 224 on the substrate roughly coincides with the orthographic projection of the second gate electrode 224 on the substrate. At this time, the first pole 211, the second pole 212, the third pole 221 and the fourth pole 222 penetrate the interlayer dielectric layer 52.

[0052] like Figure 5 As shown, when the first gate electrode 214 is located on the side of the first active layer 213 close to the substrate, and the second gate electrode 224 is located on the side of the second active layer 223 close to the substrate, the thin film transistor structure layer 20 may further include a gate insulating layer 81 and an insulating layer 82. The gate insulating layer 81 is located between the first active layer 213 and the first gate electrode 214. The first pole 211 and the second pole 212 are directly in contact with the side and top of the first active layer 213, respectively, and the third pole 221 and the fourth pole 222 are directly in contact with the side and top of the second active layer 223, respectively. In other embodiments, the position where the first pole and the second pole contact the first active layer 213 may also be other positions, as long as the first pole and the second pole can be guaranteed to contact the first active layer. The insulating layer 82 covers the first pole 211, the second pole 212, the third pole 221 and the fourth pole 222.

[0053] In one embodiment, the texture recognition module 100 further includes an input signal line and an output signal line 62. The input signal line includes a first input signal line 61. The first input signal line 61 is electrically connected to the first electrode 211 of the first thin film transistor 21, and the first input signal line 61 provides an input signal to the first electrode 211. The output signal line 62 is electrically connected to the third electrode 221 of the second thin film transistor 22, and the third electrode 221 outputs the collected texture signal to the output signal line 62.

[0054] In one embodiment, see Figure 7 The multiple texture recognition units of the texture recognition module 100 are arranged in a matrix, and the multiple texture recognition units are arranged in multiple rows and columns. Figure 6 In the embodiment, the first direction X may be a row direction, and the second direction Y may be a column direction. The first gate electrodes 214 of the first thin film transistors 21 of the same row of texture recognition units may be connected to the same first scan line G1, the second gate electrodes 224 of the second thin film transistors 22 of the same row of texture recognition units may be connected to the same second scan line G2, and the third electrodes 221 of the second thin film transistors 22 of the same column of texture recognition units may be connected to the same output signal line 62.

[0055] In one embodiment, the texture recognition module further includes a driving chip, the first scanning signal line G1 and the second scanning line G2 are respectively connected to the driving chip, and the driving chip drives the first scanning signal line G1 and the second scanning line G2 to provide scanning signals.

[0056] In one embodiment, the output signal line 62 may be electrically connected to the processing chip 860. The processing chip 860 may include an AFE (Active Front End, rectifier feedback unit) and an ADC (Analog-to-Digital Converter). The output signal line 62 is electrically connected to the input end of the AFE, and the output end of the AFE is electrically connected to the ADC. The AFE integrates the electrical signal output by the output signal line 62 and converts it into a voltage signal, and the ADC converts the analog signal input by the AFE into a digital signal, which is a texture image signal. The controller performs texture recognition based on the texture image signal. The embodiment of the present application does not limit the specific structure of the processing chip and the process of data processing.

[0057] In one embodiment of the texture recognition module of the present application, the texture recognition module is as follows: Figures 1 to 4 As shown, the first capacitor plate 41 is used to form a capacitor with the texture to be identified. The working process of the texture identification module is as follows:

[0058] First, the first scanning line G1 provides a scanning signal to the first gate electrode 214 of the first thin film transistor 21, and the first thin film transistor 21 is turned on. The first thin film transistor 21 inputs the input signal received by the first electrode 211 to the first capacitor plate 41 through the second electrode 212. The input signal is a voltage signal, so that the first capacitor plate 41 forms a capacitor with the texture to be identified. In this process, the second thin film transistor 22 is in a cut-off state.

[0059] Subsequently, the first scanning line G1 stops providing scanning signals to the first gate electrode 214 of the first thin film transistor 21, and the first thin film transistor 21 is turned off; at the same time, the second scanning line G2 provides scanning signals to the second gate electrode 224 of the second thin film transistor 22, so that the second thin film transistor 22 is turned on, and the second thin film transistor 22 outputs the capacitance signal (that is, the texture signal) between the first capacitor plate 41 and the texture to be identified. Then, the processing chip can receive the capacitance signal output by the output signal line and convert it into an image signal.

[0060] In one embodiment, see Figures 1 to 4 , the conductive layer 30 also includes a transition portion 32. At least one of the texture recognition units also includes the transition portion 32. In at least one of the texture recognition units, the second electrode 212 of the first thin film transistor 21 and the fourth electrode 222 of the second thin film transistor 22 are electrically connected to the first capacitor plate 41 through the transition portion 32. Specifically, an insulating layer 56 is provided between the transition portion 32 and the first capacitor plate 41, and the transition portion 32 is electrically connected to the first capacitor plate 41 through a conductive column 88, and the conductive column 88 passes through the insulating layer 56.

[0061] In one embodiment, see Figures 1 to 4 , the texture recognition module also includes a transfer structure 63, and the transfer structure 63 is located between the thin film transistor structure layer 20 and the conductive layer 30. At least one texture recognition unit includes a transfer structure, and in at least one texture recognition unit, the second pole 212 and the fourth pole 222 are electrically connected to the transfer part 32 through the transfer structure 63. Specifically, the transfer structure 63 and the thin film transistor structure layer 20 are provided with an insulating layer 53, and the transfer structure 63 is electrically connected to the second pole 212 and the fourth pole 222 through a conductive column 87, and the conductive column 87 penetrates the insulating layer 53; an insulating layer 54 and an insulating layer 55 are provided between the transfer structure 63 and the transfer part 32, and the transfer structure 63 is electrically connected to the transfer part 32 through a conductive column 86, and the conductive column 86 penetrates the insulating layer 54 and the insulating layer 55. In other embodiments, only one insulating layer may be provided between the transfer structure 63 and the transfer part 32, or more than two insulating layers may be provided. That is, the second electrode 212 and the fourth electrode 222 are electrically connected to the first capacitor plate 41 through the conductive pillar 87 , the transfer structure 63 and the conductive pillar 86 , the transfer portion 32 and the conductive pillar 88 respectively.

[0062] If the adapter part 32 and the adapter structure 63 are not provided, the second pole 212 and the fourth pole 222 are electrically connected to the first capacitor plate 41 through the conductive pillars penetrating the insulating layer (including the various insulating layers located between the thin film transistor structure layer 20 and the first capacitor plate 41). Since the distance between the second pole 212 and the fourth pole 222 and the first capacitor plate 41 is too large, it is difficult to make the conductive pillars penetrate the various insulating layers located between the thin film transistor structure layer 20 and the first capacitor plate 41 when forming the conductive pillars. The contact effect between the formed conductive pillars and the second pole 212 and the fourth pole 222 is poor, which leads to poor reliability of the electrical connection between the second pole 212 and the fourth pole 222 and the first capacitor plate 41, affecting the reliability of the texture recognition module 100. In the embodiment of the present application, the adapter part 32 and the adapter structure 63 are located between the first capacitor plate 41 and the second pole 212 and the fourth pole 222, so that the distance between the adapter part 32 and the first capacitor plate 41 is small, the distance between the adapter part 32 and the adapter structure 63 is small, and the distance between the adapter structure 63 and the thin film transistor structure layer 20 is small, so that the connection reliability between the formed conductive column 88 and the first capacitor plate 41 and the adapter part 32 is better, and the connection reliability between the formed conductive column 86 and the adapter part 32 and the adapter structure 63 is better, and the connection reliability between the formed conductive column 87 and the adapter structure 63 and the second pole 212 and the fourth pole 222 is better, so that the electrical connection reliability between the first capacitor plate 41 and the second pole 212 and the fourth pole 222 is better, thereby ensuring the reliability of the texture recognition module 100.

[0063] In one embodiment, see Figures 1 to 4 , the transition portion 32 and the conductive structure 31 are formed in one patterning process. That is, the thickness and material of the transition portion 32 and the conductive structure 31 are substantially the same. Among them, the thickness of the transition portion 32 and the conductive structure 31 being substantially the same means that the thickness of the two is the same, or the difference in thickness between the two is small, for example, the thickness ratio of the transition portion 32 to the conductive structure 31 is in the range of 0.8 to 1.2. With this arrangement, the transition portion 32 and the conductive structure 31 can be formed simultaneously through one patterning process, which helps to simplify the preparation process.

[0064] Furthermore, there is a gap between the transition portion 32 and the conductive structure 31 , and the two are not in contact. A hollow portion may be provided on the conductive structure 31 , and the transition portion 32 is located in the hollow portion of the conductive structure 31 .

[0065] In one embodiment, the transfer structure 63, the input signal line, the output signal line, the conductive pillar 87, the first electrode 211, the second electrode 212, the third electrode 221 and the fourth electrode 222 can all be formed in one patterning process. In another embodiment, the first electrode 211, the second electrode 212, the third electrode 221, the fourth electrode 222 and the conductive pillar 87 can be formed in one patterning process, and the transfer structure 63, the input signal line and the output signal line can be formed in one patterning process.

[0066] In one embodiment, the conductive pillars 86 and the conductive layer 30 can be formed in one patterning process.

[0067] In one embodiment, the conductive pillar 88 and the first capacitor plate 41 can be formed in one patterning process.

[0068] In some embodiments, Figure 1 and Figure 2 As shown, in at least one texture recognition unit, the second electrode 212 and the fourth electrode 222 are electrically connected to the first capacitor plate 41 through different adapters 32 .

[0069] In another embodiment, if Figure 3 and Figure 4 As shown, in at least one texture recognition unit, the second pole 212 and the fourth pole 222 are electrically connected to the first capacitor plate 41 through the same adapter 32. When preparing the conductive layer 30, in order to ensure the reliability of the electrical connection between the adapter 32 and the conductive pillars 86 and 87, the size of the adapter 32 is usually set to be larger. Compared with the solution in which the second pole 212 and the fourth pole 222 corresponding to the same capacitor plate are electrically connected to the first capacitor plate 41 through different adapters 32, when the second pole 212 and the fourth pole 222 are electrically connected to the first capacitor plate 41 through the same adapter 32, the total area of ​​the adapter 32 corresponding to the first capacitor plate 41 and the sum of the area of ​​the gap between the adapter 32 and the conductive structure 31 can be made smaller, so that the size of the conductive structure 31 can be set to be larger, which helps to improve the shielding effect of the conductive structure 31. Furthermore, the first thin film transistor inputs an electrical signal to the first capacitor plate 41 and the second thin film transistor collects a capacitance signal between the first capacitor plate 41 and the pattern to be identified at different times, so the second electrode 212 and the fourth electrode 222 are connected to the first capacitor plate 41 through the same adapter 32, which does not affect the signal transmission between the first capacitor plate 41 and the second electrode 212 and the fourth electrode 222. In the embodiment of the present application, the distance between the first thin film transistor and the second thin film transistor can also be adjusted so that the distance between the first thin film transistor and the second thin film transistor is smaller, so as to reduce the size of the adapter 32, thereby increasing the size of the conductive structure 31 and improving the shielding effect of the conductive structure 31.

[0070] In one embodiment, see Figure 2 and Figure 4 , the orthographic projections of the conductive pillars 86 and 88 on the substrate 10 fall on the orthographic projections of the connecting portion 32 connected thereto on the substrate 10, and the orthographic projections of the conductive pillars 86 and 87 on the substrate 10 fall on the orthographic projections of the connecting structure 63 connected thereto on the substrate 10. Such an arrangement can improve the reliability of the connection between the conductive pillars 86 and 88 and the connecting portion 32, and improve the reliability of the connection between the conductive pillars 86 and 87 and the connecting structure 63. The conductive pillars 86 and the conductive layer 30 can be formed simultaneously, the conductive pillars 88 and the first capacitor plate 41 can be formed simultaneously, and the conductive pillars 87 and the connecting structure 63 can be formed simultaneously.

[0071] In one embodiment, see Figures 1 to 4 , the input signal line includes a first input signal line 61 and a second input signal line (not shown, located on the side of the output signal line 62 away from the first input signal line 61, and the extension direction of the first input signal line 61 is substantially the same as the extension direction of the second input signal line), and the first input signal line, the second input signal line and the output signal line 62 are arranged in the same layer. The first input signal line 61, the second input signal line and the output signal line 62 can be formed in one patterning process. Such an arrangement helps to simplify the preparation process. The first input signal line 61 and the second input signal line extend along a first direction X, and the output signal line 62 extends along a second direction Y. The first direction X can be a row direction, and the second direction Y can be a column direction.

[0072] Furthermore, the transfer structure 63 and the input signal line and the output signal line can be formed in one patterning process. This arrangement helps to simplify the manufacturing process.

[0073] Furthermore, if Figure 2 and Figure 4 As shown, the first input signal line 61 is electrically connected to the first electrode 211 of the first thin film transistor 21 through a conductive column 87 penetrating the insulating layer 53 .

[0074] Furthermore, if Figure 1 and Figure 3 As shown, the extension direction of the output signal line 62 is substantially perpendicular to the extension direction of the input signal line. The extension direction of the output signal line 62 is substantially perpendicular to the extension direction of the input signal line, which means that the angle between the extension direction of the output signal line 62 and the extension direction of the input signal line is between 80° and 90°. There is a gap between the first input signal line 61 and the second input signal line, and the output signal line 62 is located between the first input signal line 61 and the second input signal line.

[0075] In one embodiment, Figure 1 and Figure 3As shown, the texture recognition module 100 also includes a connecting portion 65, and the connecting portion 65 is located on the side of the first input signal line 61 close to the substrate, and at least one of the first input signal lines 61 is electrically connected to at least one of the second input signal lines through the connecting portion 65. The orthographic projection of the gap between the first input signal line 61 and the second input signal line on the substrate overlaps with the orthographic projection of the connecting portion 65 on the substrate, and the orthographic projection of the first input signal line 61 on the substrate and the orthographic projection of the second input signal line on the substrate both overlap with the orthographic projection of the connecting portion on the substrate. With such a configuration, the connecting portion 65 can electrically connect the first input signal line 61 with the second input signal line without affecting the arrangement of the input signal line and the output signal line.

[0076] In one embodiment, the first gate electrode 214 of the first thin film transistor 21, the second gate electrode 224 of the second thin film transistor 22 and the connecting portion 65 are formed in one patterning process. In this way, the connection portion 65 does not add additional process steps, which helps to simplify the manufacturing process.

[0077] In one embodiment, Figure 2 and Figure 4 As shown, the texture recognition module 100 further includes a shielding layer 67, at least part of which is located between the connecting portion and the output signal line 62, and the overlapping part of the orthographic projection of the connecting portion on the substrate 10 and the orthographic projection of the output signal line 62 on the substrate 10 overlap with the orthographic projection of the shielding layer 67 on the substrate 10. The shielding layer 67 is connected to a constant electrical signal. With such a configuration, the shielding layer 67 can avoid the generation of coupling capacitance between the input signal line 62 and the connecting portion, thereby affecting the signal transmitted by the output signal line, thereby ensuring the accuracy of the output signal of the output signal line and improving the accuracy of the texture recognition module in recognizing the texture.

[0078] Further, the overlapping portion of the orthographic projection of the connecting portion on the substrate 10 and the orthographic projection of the output signal line 62 on the substrate 10 falls within the orthographic projection of the shielding layer on the substrate. The overlapping portion of the orthographic projection of the connecting portion on the substrate 10 and the orthographic projection of the output signal line 62 on the substrate 10 falls within the orthographic projection of the shielding layer 67 on the substrate 10, which means that the overlapping portion of the orthographic projection of the connecting portion on the substrate 10 and the orthographic projection of the output signal line 62 on the substrate 10 are located within the orthographic projection of the shielding layer 67 on the substrate 10, and the area of ​​the overlapping portion is smaller than the area of ​​the orthographic projection of the shielding layer 67 on the substrate 10; or, the area of ​​the overlapping portion of the orthographic projection of the connecting portion on the substrate 10 and the orthographic projection of the output signal line 62 on the substrate 10 is equal to the area of ​​the orthographic projection of the shielding layer 67 on the substrate 10.

[0079] Further, the orthographic projection of the output signal line on the substrate falls within the orthographic projection of the shielding layer on the substrate, and / or the orthographic projection of the connecting portion on the substrate falls within the orthographic projection of the shielding layer on the substrate.

[0080] Further, the orthographic projection of the shielding layer 67 on the substrate 10 coincides with the orthographic projection of the output signal line 62 on the substrate 10, or the orthographic projection of the shielding layer on the substrate 10 coincides with the orthographic projection of the connecting portion on the substrate 10. The orthographic projection of the shielding layer 67 on the substrate 10 coincides with the orthographic projection of the output signal line 62 or the connecting portion on the substrate 10, which means that the two are roughly coincident. Among them, the orthographic projection of the shielding layer 67 on the substrate 10 coincides with the orthographic projection of the output signal line 62 or the connecting portion on the substrate 10, which means that the ratio of the areas of the orthographic projections of the two is between 0.8 and 1.2. With such a configuration, the shielding layer 67 can effectively shield the signal interference generated between the input signal line 62 and the connecting portion.

[0081] In one embodiment, the shielding layer 67 is provided with a via hole, and the third electrode 221 of the second thin film transistor 22 is electrically connected to the output signal line 62 through the via hole. At this time, the orthographic projection of the shielding layer 67 on the substrate 10 coincides with the orthographic projection of the output signal line 62 on the substrate 10, and the orthographic projection of the shielding layer 67 on the substrate 10 includes the orthographic projection of the via hole on the substrate 10. In this embodiment, the output signal line 62 is electrically connected to the third electrode 221 of the second thin film transistor 22 through the conductive column 89 that penetrates the insulating layer 53 and the shielding layer 67.

[0082] In one embodiment, see Figure 2 and Figure 4 , the texture recognition module includes an insulating layer 53, an insulating layer 54, an insulating layer 55, an insulating layer 56 and an insulating layer 57. The insulating layer 53 is located between the shielding layer 67 and the output signal line 62, the insulating layer 54 and the insulating layer 55 are located between the output signal line 62 and the conductive layer 30, and the insulating layer 55 is located between the insulating layer 54 and the conductive layer 30, and the insulating layer 56 is located between the conductive layer 30 and the first capacitor plate 41. The insulating layer 57 is located on the side of the first capacitor plate 41 away from the substrate 10. The insulating layer 53 and the insulating layer 54 can be inorganic layers, and the insulating layer 55 and the insulating layer 56 can be planarization layers, and the material thereof is an organic material. The insulating layer 57 can be an organic layer. The number of insulating layers of the texture recognition module in the embodiment of the present application may be different from this, and the number of insulating layers is not limited.

[0083] In one embodiment, the texture recognition module is Figures 1 to 4In the texture recognition module shown, the first capacitor plate 41 is configured to form a capacitor with the texture to be recognized, and the texture recognition module may also include a light-emitting layer, the light-emitting layer includes a plurality of sub-pixels, and the light-emitting layer may be located on a side of the first capacitor plate close to the substrate. In other embodiments, the positional relationship between the light-emitting layer and the first capacitor plate may be different from this.

[0084] Further, the orthographic projection of the first capacitor plate 41 on the substrate may not overlap with the orthographic projection of the sub-pixel on the substrate 10. Specifically, the orthographic projection of the first capacitor plate 41 on the substrate does not overlap with the orthographic projection of the pixel opening of the pixel defining layer on the substrate. Alternatively, the first capacitor plate 41 is a transparent plate, and the material of the transparent plate is, for example, indium tin oxide or indium zinc oxide. In this way, the first capacitor plate 41 does not affect the emission of light emitted by the sub-pixel.

[0085] Below Figure 1 and Figure 4 The preparation process of the texture recognition module shown in the figure is introduced. The "composition process" mentioned in the embodiment of the present application includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching and stripping the photoresist. Deposition can be carried out by processes such as sputtering, evaporation or chemical vapor deposition, and etching can be carried out by processes such as dry etching or wet etching. "Thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a composition process during the entire production process, the "thin film" can also be called a "layer". When the "thin film" still requires a composition process during the entire production process, it is called a "thin film" before the composition process, and it can be called a "layer" after the composition process. The "layer" after the composition process contains at least one "pattern".

[0086] In one embodiment, Figure 1 and Figure 4 The preparation process of the texture recognition module shown can be as follows:

[0087] First, a substrate 10 is provided.

[0088] Subsequently, an active layer thin film is deposited on the substrate, and the active layer thin film is patterned through a patterning process to form a first active layer 213 and a second active layer 223 in at least one texture recognition unit.

[0089] Subsequently, a gate insulating layer 51 and a first conductive film are deposited in sequence, and the first conductive film is patterned by a patterning process to form a first gate electrode 214 , a second gate electrode 224 , and a connecting portion.

[0090] Subsequently, the interlayer dielectric layer 52 is deposited in sequence, and the gate insulating layer 51 and the interlayer dielectric layer 52 are etched.

[0091] Subsequently, a second conductive film is deposited and patterned by a patterning process to form a shielding layer 67 .

[0092] Subsequently, the insulating layer 53 is deposited, and the insulating layer 53 and the insulating layer 52 are etched to form a first through hole penetrating the insulating layer 53 and the insulating layer 54 , and at least one second through hole also penetrates the shielding layer 67 .

[0093] Subsequently, a third conductive film is deposited and patterned to form input signal lines, output signal lines 62, a transfer structure 63, and first pole 211, second pole 212, third pole 221, fourth pole 222 and a conductive column 87 in the first through hole.

[0094] Subsequently, an insulating layer 54 and an insulating layer 55 are deposited in sequence, and the insulating layer 54 and the insulating layer 55 are etched to form a plurality of second through holes penetrating the insulating layer 54 and the insulating layer 55 .

[0095] Subsequently, a fourth conductive film is deposited and patterned to form a conductive column 86 and a conductive layer 30 located in the second through hole.

[0096] Subsequently, an insulating layer 56 is deposited and etched to form a third through hole penetrating the insulating layer 56 .

[0097] Subsequently, a fifth conductive film is deposited and patterned to form a conductive column 88 and a first capacitor plate 41 located in the third through hole.

[0098] Subsequently, an insulating layer 57 is deposited.

[0099] In another embodiment of the texture recognition module of the present application, Figures 5 to 8 As shown, the conductive structure 31 of the conductive layer 30 is electrically connected to the first electrode 211, and provides the input signal to the first electrode 211 of the first thin film transistor 21. In this way, the conductive structure 31 can be used as an input signal line to provide an input signal to the first electrode 211 of the first thin film transistor 21, and can also play a shielding role, shielding the signal interference between the conductive components of the thin film transistor layer and the conductive components located on the side of the conductive structure 31 away from the substrate, which helps to improve the recognition accuracy of the texture recognition module.

[0100] In one embodiment, the texture recognition module 100 also includes a second capacitor plate 43 arranged opposite to the first capacitor plate 41, and a photoelectric material layer 42 located between the first capacitor plate 41 and the second capacitor plate 43. The input signal is a low-level electrical signal, and the second capacitor plate 43 is connected to a high-level electrical signal. That is, the first capacitor plate 41, the photoelectric material layer 42 and the second capacitor plate 43 form a photoelectric sensor 40, and the fingerprint recognition module is an optical fingerprint recognition module. Each texture recognition unit includes a photoelectric sensor 40. The light reflected by the texture to be identified is incident on the photoelectric sensor, and the photoelectric sensor converts the light signal into an electrical signal. The size of the input signal provided by the second thin film transistor to the first capacitor plate 41 can be adjusted, so that the voltage difference between the first capacitor plate 41 and the second capacitor plate 43 can be set larger, which helps to improve the detection accuracy of the texture recognition module.

[0101] In one embodiment, see Figure 8 The output signal line 62 can be electrically connected to the input end of the AFE862, and the output end of the AFE862 is electrically connected to the ADC861. The AFE862 converts the electrical signal output by the output signal line 62 into a voltage signal, and the ADC861 converts the analog signal output by the AFE into a digital signal, that is, a texture image signal. The controller performs texture recognition according to the texture image signal. The processing chip 860 may also include a switch device 863.

[0102] In one embodiment, see Figure 8 ,The working process of the texture recognition module is as follows:

[0103] In the T1 time period: the first scanning line G1 provides a scanning signal to the first gate electrode 214 of the first thin film transistor 21, the first thin film transistor 21 is turned on, and the first thin film transistor 21 inputs the input signal received by the first electrode 211 to the first capacitor plate 41 through the second electrode 212, and the input signal is a low-level electrical signal; at the same time, the second capacitor plate 43 writes a high-level electrical signal, so that a voltage difference is generated between the first capacitor plate 41 and the second capacitor plate 43. In this process, the second thin film transistor 22 is in a cut-off state, and the switch device 863 is in a closed state.

[0104] Fig. 9 In the figure, the high and low levels of the signal line G3 signal represent the closing and opening of the switch device 863. When the signal line G3 signal is a high level signal, it represents that the switch device 863 is closed; when the signal line G3 signal is a low level signal, it represents that the switch device 863 is opened.

[0105] In the T2 time period: the first scanning line G1 stops providing the scanning signal to the first gate electrode 214 of the first thin film transistor 21, so that the first thin film transistor 21 is turned off, the switching device 863 remains turned on, the second thin film transistor 22 is in the off state, the photoelectric sensor 40 receives the light reflected by the pattern to be identified, and converts the light signal into an electrical signal, and charge is accumulated between the first capacitor plate 41 and the second capacitor plate 43 of the photoelectric sensor 40.

[0106] In the T3 time period: the second scanning line G2 provides a scanning signal to the second gate electrode 224 of the second thin film transistor 22, so that the second thin film transistor 22 is turned on, and the switch device 863 is turned off, and the AFE862 is in an integration state. The second thin film transistor 22 outputs the electrical signal between the first capacitor plate 41 and the second capacitor plate 43 to the AFE862, and the AFE862 inputs the analog signal obtained by integration to the ADC861, and the ADC861 converts the input analog signal into a digital signal.

[0107] In one embodiment, see again Figure 5 and Figure 6 , the output signal line 62 is electrically connected to the third electrode 221, the output signal line 62 is located on the side of the conductive layer 30 away from the substrate 10, and the orthographic projection of the output signal line 62 on the substrate 10 overlaps with the orthographic projection of the conductive structure 31 on the substrate 10. In this way, the conductive structure 31 can shield the signal interference between the output signal line 62 and the conductive components in the thin film transistor structure layer 20, improve the accuracy of the output signal of the output signal line 62, and further improve the accuracy of texture recognition.

[0108] Furthermore, the output signal line 62 is located on a side of the conductive layer 30 facing away from the substrate 10 , and an orthographic projection of the output signal line 62 on the substrate 10 falls within an orthographic projection of the conductive structure 31 on the substrate 10 .

[0109] In one embodiment, see Figure 5 and Figure 6 The first gate electrode 214 is located on the side of the first active layer 213 close to the substrate 10, the second gate electrode 224 is located on the side of the second active layer 223 close to the substrate 10, the insulating layer 82 is provided with a through hole, a conductive column 94 is formed in the through hole, and the conductive structure 31 is electrically connected to the first electrode 211 of the first thin film transistor 21 through the conductive column 94. The conductive column 94 and the conductive layer 30 can be formed in one patterning process.

[0110] In one embodiment, the pattern recognition module further includes an insulating layer 83 located between the conductive layer 30 and the output signal line 62. The output signal line 62 is electrically connected to the third electrode 221 of the second thin film transistor 22 through the conductive pillar 92 and the conductive pillar 91 in sequence, and the conductive pillar 92 penetrates the insulating layer 83 and the conductive layer 30 and does not contact the conductive layer 30. The conductive pillar 91 penetrates the insulating layer 82, and the conductive pillar 91, the conductive pillar 92 and the output signal line 62 can be formed in one patterning process.

[0111] In one embodiment, Figure 5 As shown, the first capacitor plate 41 is located on the side of the photoelectric material layer 42 close to the substrate 10, and the texture recognition module also includes an insulating layer 84 located between the first capacitor plate 41 and the output signal line 62. The second pole 212 and the fourth pole 222 are electrically connected to the first capacitor plate 41 through the conductive column 97, the conductive column 96, the switching component 95 and the conductive column 93 respectively. The conductive column 93 penetrates the insulating layer 84, the conductive column 96 penetrates the insulating layer 83 and the conductive layer 30, the switching component 95 is located between the insulating layer 83 and the insulating layer 84, and the switching component 95, the output signal line 62, the conductive column 96 and the conductive column 97 can be formed in a single patterning process. Further, the switching component 95, the output signal line 62, the conductive column 96 and the conductive column 97 and the output signal line 62 can be formed in a single patterning process. The conductive column 93 and the first capacitor plate 41 can be formed in a single patterning process.

[0112] In another embodiment, if Figure 6 As shown, the second electrode 212 and the fourth electrode 222 are electrically connected to the first capacitor plate 41 through the conductive pillars 97, 96 and 93. The conductive pillars 97, 96, 93 and the first capacitor plate 41 can be formed in one patterning process.

[0113] In one embodiment, Figure 5 , Figure 6 , Fig.10 and Fig.11 As shown, the texture recognition module further includes a light-emitting layer 70. The light-emitting layer 70 includes a plurality of sub-pixels 701. The plurality of sub-pixels include sub-pixels of at least three different colors, for example, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The sub-pixel of the light-emitting layer includes a first electrode 71, an organic light-emitting material layer 72 located on a side of the first electrode 71 away from the substrate, and a second electrode 73 located on a side of the organic light-emitting material layer 72 away from the substrate. The first electrode 71 may be an anode, and the second electrode 73 may be a cathode.

[0114] In one embodiment, Fig.11As shown, the first capacitor plate 41 of the photoelectric sensor 40, the photoelectric material layer 42 and the second capacitor plate 43 are respectively located on the side of the light-emitting layer 70 close to the substrate 10. In this embodiment, the light-emitting layer 70 may not be provided with sub-pixels in the area opposite to the photoelectric sensor 40 in the stacking direction of the film layer, so as to ensure that the light reflected by the texture can smoothly enter the photoelectric sensor 40; or, the sub-pixels in the area opposite to the photoelectric sensor 40 in the stacking direction of the film layer of the light-emitting layer 70, the first electrode and the second electrode are transparent electrodes respectively.

[0115] Further, see Fig.11 , the texture recognition module may further include a collimating structure 44 located between the light-emitting layer 70 and the photoelectric sensor 40. The collimating structure 44 is configured to filter the light reflected by the texture, so that the detection light with a scattering angle within a preset range passes through. The collimating structure 44 filters the reflected light, so that the detection light with a scattering angle within the preset range passes through, and the detection light with a scattering angle not within the preset range cannot pass through, and cannot be received by the photoelectric sensor 40. Optionally, the photoelectric sensor 40 only receives the light reflected by the texture directly above it, which can avoid the photoelectric sensor 40 receiving interference signals and affecting the texture recognition, thereby improving the accuracy of the texture recognition.

[0116] Further, see Fig.11 The texture recognition module may further include a pixel driving circuit layer 45, which may be located between the collimating structure 44 and the light emitting layer 70. The pixel driving circuit layer includes a pixel circuit for driving the sub-pixel 701. The pixel driving circuit layer 45 has a higher light transmittance in a region opposite to the photoelectric sensor 40 in the stacking direction of the film layers.

[0117] For further information, see Fig.11 The texture recognition module may further include an encapsulation layer 74 , a polarizer 75 , an optical adhesive 76 and a cover plate 77 which are sequentially stacked on the side of the light-emitting layer 70 away from the substrate 10 .

[0118] In another embodiment, see Figure 5 , Figure 6 and Fig.10 The second capacitor plate 43 is located on the side of the first capacitor plate 41 away from the substrate 10; the first capacitor plate 41 and the first electrode 71 are arranged on the same layer; the second capacitor plate 43 and the second electrode 73 are arranged on the same layer. Such an arrangement helps to reduce the thickness of the texture recognition module.

[0119] Further, the first capacitor plate 41 and the first electrode 71 are formed in the same patterning process, and the second capacitor plate 43 is electrically connected to the second electrode 73. In this way, the first capacitor plate 41 and the first electrode 71 can be formed in one process step, and the second capacitor plate 43 and the second electrode 73 can be formed in one process step, which helps to simplify the preparation process. And the second capacitor plate 43 and the second electrode 73 can provide a level signal by the same signal line, which can reduce the complexity of the signal line in the texture recognition module. In other embodiments, the second capacitor plate 43 and the second electrode 73 can also be spaced apart, which is not limited in this application.

[0120] Furthermore, the first electrode 71 and the first capacitor plate 41 may be connected to form a whole-surface electrode.

[0121] Furthermore, a pixel circuit for driving a sub-pixel may be provided in the thin film transistor structure layer 20 .

[0122] In one embodiment, Fig.10 As shown, the texture recognition module may further include an encapsulation layer 74 , a collimating structure 44 , a polarizer 75 , an optical adhesive 76 and a cover plate 77 which are sequentially stacked on the side of the light-emitting layer 70 facing away from the substrate 10 .

[0123] In one embodiment, the texture recognition module is Figure 5 When the structure shown in FIG. 1 is used, the preparation process of the texture recognition module can be as follows:

[0124] First, a substrate 10 is provided.

[0125] Subsequently, a first conductive film is deposited on the substrate, and the first conductive film is patterned by a patterning process to form a first gate electrode 214 and a second gate electrode 224 .

[0126] Subsequently, a gate insulating layer 51 and an active layer thin film are sequentially deposited on the substrate, and the active layer thin film is patterned by a patterning process to form a first active layer 213 and a second active layer 223 .

[0127] Subsequently, a second conductive film is deposited and patterned to form a first electrode 211 , a second electrode 212 , a third electrode 221 and a fourth electrode 222 .

[0128] Subsequently, an insulating layer 82 is deposited and etched to form a fifth through hole penetrating the insulating layer 82 . The orthographic projection of the fifth through hole on the substrate is located within the orthographic projection of the first pole 211 on the substrate.

[0129] Subsequently, a third conductive film is deposited and patterned by a patterning process to form a conductive layer 30 and a conductive column 94 located in the fifth through hole.

[0130] Subsequently, an insulating layer 83 is deposited, and the insulating layer 83 and the insulating layer 82 are etched to form a sixth through hole penetrating the insulating layer 83 , the conductive layer 30 , and the insulating layer 82 .

[0131] Subsequently, a fourth conductive film is deposited and patterned to form the conductive pillars 92 and 91 located in the sixth through hole, the output signal line 62 and the transfer component 95 .

[0132] Subsequently, an insulating layer 84 is deposited and etched to form a plurality of seventh through holes penetrating the insulating layer 84 . The orthographic projections of the seventh through holes on the substrate are located within the orthographic projections of the transfer component 95 on the substrate.

[0133] Subsequently, a fifth conductive film is deposited and patterned to form a conductive column 93 , a first electrode 71 , and a first capacitor plate 41 in the seventh through hole.

[0134] Subsequently, an organic light-emitting material layer 72 and a photoelectric material layer 42 are formed in sequence. The organic light-emitting material layer 72 may be formed first, and then the photoelectric material layer 42; or the photoelectric material layer 42 may be formed first, and then the organic light-emitting material layer 72.

[0135] Then, a sixth conductive film is deposited to obtain the second electrode 73 and the second capacitor plate 43 .

[0136] In one embodiment of the present application, each conductive pillar may be a columnar structure, filling the through hole where it is located. Alternatively, the structure of each conductive pillar may also be as follows: Figure 6 The structure of the conductive pillar 94 shown in FIG. 8 is that the conductive pillar may be located only on the surface of the through hole where the conductive pillar is located, and overlap the conductive component thereunder.

[0137] In one embodiment, the texture recognition unit of the texture recognition module may be an external plug-in type, or the preparation process of the texture recognition unit may be compatible with the preparation process of the light-emitting layer, and the texture recognition unit and the light-emitting layer may be formed in the same preparation process flow.

[0138] An embodiment of the present application further provides a display device, which includes the texture recognition module described in any of the above embodiments.

[0139] The display device may further include a housing, and the display panel may be embedded in the housing.

[0140] The display device in this embodiment can be: electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, or any other product or component with a display function.

[0141] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0142] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0143] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A texture recognition module, characterized in that: The texture recognition module includes a substrate, a thin film transistor structure layer located on the substrate, a conductive layer located on a side of the thin film transistor structure layer away from the substrate, and at least one first capacitor plate located on a side of the conductive layer away from the substrate; The texture recognition module includes a plurality of texture recognition units, which are arranged in a plurality of rows and columns; at least one of the texture recognition units includes the first capacitor plate, and a first thin film transistor and a second thin film transistor located in the thin film transistor structure layer; the first thin film transistor includes a first electrode and a second electrode, and the first electrode is configured to receive an input signal; The second thin film transistor includes a third electrode and a fourth electrode, and the third electrode is configured to output the collected texture signal; in at least one of the texture recognition units, the second electrode and the fourth electrode are electrically connected to the first capacitor plate respectively; The conductive layer includes at least one conductive structure and a switching part, and the conductive structure is connected to a constant electrical signal; at least one of the texture recognition units also includes a switching part; in at least one of the texture recognition units, the second pole and the fourth pole are electrically connected to the first capacitor plate through the switching part.

2. The texture recognition module according to claim 1, characterized in that: In at least one of the texture recognition units, the second electrode and the fourth electrode are electrically connected to the first capacitor plate through different adapters.

3. The texture recognition module according to claim 1, characterized in that: In at least one of the texture recognition units, the second electrode and the fourth electrode are electrically connected to the first capacitor plate through the same adapter.

4. The texture recognition module according to claim 1, characterized in that: The transfer portion and the conductive structure are formed in one patterning process.

5. The texture recognition module according to claim 1, characterized in that: The texture recognition module also includes a first input signal line, a second input signal line and an output signal line arranged in the same layer, and the output signal line is located between the first input signal line and the second input signal line; the first input signal line or the second input signal line is electrically connected to the first pole, and the output signal line is electrically connected to the third pole.

6. The texture recognition module according to claim 5, characterized in that: The texture recognition module further includes a connection portion, which is located on a side of the first input signal line close to the substrate, and at least one of the first input signal lines is electrically connected to at least one of the second input signal lines through the connection portion.

7. The texture recognition module according to claim 6, characterized in that: The first thin film transistor includes a first gate electrode, the second thin film transistor includes a second gate electrode, and the connecting portion, the first gate electrode, and the second gate electrode are formed in one patterning process.

8. The texture recognition module according to claim 6, characterized in that: The texture recognition module also includes a shielding layer, which is located between the connecting part and the output signal line. The overlapping part of the orthographic projection of the connecting part on the substrate and the orthographic projection of the output signal line on the substrate overlap with the orthographic projection of the shielding layer on the substrate.

9. The texture recognition module according to claim 8, characterized in that: The orthographic projection of the output signal line on the substrate falls within the orthographic projection of the shielding layer on the substrate, and / or the orthographic projection of the connecting portion on the substrate falls within the orthographic projection of the shielding layer on the substrate.

10. The texture recognition module according to any one of claims 1 to 9, characterized in that: The first capacitor plate is configured to form a capacitor with the pattern to be identified.

11. The texture recognition module according to claim 1, characterized in that: The conductive structure is electrically connected to the first electrode and provides the input signal to the first electrode.

12. The texture recognition module according to claim 11, characterized in that: The texture recognition module further includes a second capacitor plate disposed opposite to the first capacitor plate, and a photoelectric material layer located between the first capacitor plate and the second capacitor plate.

13. The texture recognition module according to claim 12, characterized in that: The texture recognition module further includes an output signal line, the output signal line is electrically connected to the third electrode, and an orthographic projection of the output signal line on the substrate overlaps with an orthographic projection of the conductive structure on the substrate.

14. The texture recognition module according to claim 12, characterized in that: The texture recognition module further includes a light-emitting layer, the light-emitting layer includes a plurality of sub-pixels, and the first capacitor plate, the photoelectric material layer and the second capacitor plate are respectively located on a side of the light-emitting layer close to the substrate.

15. The texture recognition module according to claim 12, characterized in that: The texture recognition module further includes a light-emitting layer, the light-emitting layer includes a plurality of sub-pixels, the light-emitting layer includes a first electrode, a light-emitting material layer located on a side of the first electrode away from the substrate, and a second electrode located on a side of the light-emitting material layer away from the substrate; The second capacitor plate is located on a side of the first capacitor plate facing away from the substrate; The first capacitor plate is disposed in the same layer as the first electrode; and the second capacitor plate is disposed in the same layer as the second electrode.

16. The texture recognition module according to claim 15, characterized in that: The second capacitor plate is electrically connected to the second electrode.

17. A display device, characterized in that: The display device comprises the texture recognition module according to any one of claims 1 to 16.

Images