Memory device

Abstract

A memory device for sensing a memory cell in a memory array includes at least one first memory cell, a first sense amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sense amplifier is coupled to the at least one first memory cell. An output terminal of the first multiplexer circuit is coupled to a reference terminal of the first sense amplifier. Each of the first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. The first sense amplifier includes an output terminal and a reference terminal. The controller controls the first multiplexer circuit to select one of the first reference cells as a selected reference cell to be coupled to the reference terminal of the first sense amplifier when each read operation is performed on the at least one first memory cell.

Description

Technical Field

[0001] This disclosure relates to a technique for a sensing amplifier for a memory device, and more specifically, to a memory device, a sensing amplifier, and a method for sensing memory cells, wherein wear leveling is performed on a plurality of reference cells in the sensing amplifier. Background Technology

[0002] Because each memory cell in a memory device has a small read sensing window, most memory devices utilize a reference cell in the sense amplifier (SA) for read operations. Designing the structure of the sense amplifier (SA) in a memory device is one of the challenges facing its read functionality. Each column of the memory array has a sense amplifier with a reference cell, and the sense amplifier uses this reference cell to read memory cells located in the same column order as the corresponding reference cell. Therefore, during a read operation of the memory device, although the memory cell correctly stores data, the data read by the sense amplifier may be flipped due to an error in the reference cell. This error can be caused by a large number of accesses to the reference cell, leading to read durability and reliability issues. In other words, due to the number of reads per column of the memory array and variations in semiconductor manufacturing processes, each reference cell of the sense amplifier may have minute differences. Summary of the Invention

[0003] This disclosure provides a memory device. The memory device includes at least one first memory cell, a first sense amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sense amplifier is coupled to the at least one first memory cell. The first sense amplifier includes an output terminal and a reference terminal. The output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sense amplifier. Each of the plurality of first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. When each read operation is performed on the at least one first memory cell, the controller controls the first multiplexer circuit to sequentially and repeatedly select one of the first reference cells as the selected reference cell to couple to the reference terminal of the first sense amplifier. Attached Figure Description

[0004] A thorough understanding of the various aspects of the invention will be best achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0005] Figure 1 A detailed block diagram of the structure of a sense amplifier according to an embodiment of this disclosure is shown, wherein multiple reference cells are selected via a multiplexer by column control signals generated by a controller.

[0006] Figure 2 A detailed block diagram of the structure of a sense amplifier according to an embodiment of this disclosure is shown, wherein multiple reference cells are selected via a multiplexer by a row control signal generated by a controller.

[0007] Figure 3 A detailed block diagram of the structure of a sense amplifier according to an embodiment of the present disclosure is shown, wherein multiple reference cells are selected via a multiplexer by column control signals and row control signals generated by a controller.

[0008] Figure 4 A flowchart illustrating the steps of a read operation on at least one memory cell according to an embodiment of this disclosure is shown. Detailed Implementation

[0009] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and constructions are described below to simplify the invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature being formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. Such repetition is for the purpose of brevity and clarity, and not by virtue of indicating a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0011] Figure 1 A detailed block diagram of the structure of a sense amplifier according to an embodiment of this disclosure is shown, wherein multiple reference cells are selected via a multiplexer by a column control signal generated by a controller. The memory device 100, which performs wear leveling on the reference cells, can be implemented as a storage device or a consumer electronic device with a memory array. In the embodiment, the memory device 100 can be a flash memory device or a dynamic random access memory (DRAM) device.

[0012] Reference Figure 1 The memory device 100 includes at least one memory cell (i.e., memory cells 110-1 to 110-n) in a memory array 105, at least one sense amplifier SA (i.e., sense amplifiers 120-1 to 120-n), at least one multiplexer circuit MUX (i.e., multiplexer circuits 130-1 to 130-n), a plurality of reference cells (i.e., reference cells 140-11 to 140-1p for the column containing memory cell 110-1), and a controller 150. The value of n or p is a positive integer.

[0013] exist Figure 1In the illustrated embodiment, the memory array 105 has n columns of memory cells, multiple MUXs 130-1 to 130-n are located in the same row order, and memory cell 110-1 is represented as one of the memory cells in the column. In other words, each column of the memory device 100 has multiple memory cells (i.e., memory cell 110-1), SAs (i.e., SA 120-1), MUXs (i.e., MUX 130-1), and multiple reference cells (i.e., reference cells 140-11 to 140-1p). SA 120-1 is coupled to memory cell 110-1, and SA 120-1 includes an output terminal ON1 and a reference terminal RN1. The output terminal of MUX 130-1 is coupled to the reference terminal RN1 of SA 120-1, and each of the reference cells 140-11 to 140-1p is coupled to each input node of MUX 130-1. Controller 150 is coupled to the control terminal CN1 of MUX 130-1.

[0014] In response to each read operation performed on at least one memory cell (i.e., memory cells 110-1 to 110-n), controller 150 controls MUX 130-1 to sequentially and repeatedly select one of reference cells 140-11 to 140-1p as the selected reference cell to be coupled to reference terminal RN1 of SA 120-1. Specifically, controller 150 may be a processor, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or any integrated programmable chip. Controller 150 may have multiple output terminals, each output terminal coupled to a selector terminal of each multiplexer (i.e., MUX 130-1 to MUX130-n). Controller 150 generates at least one column control signal to select one reference cell from a plurality of reference cells arranged in column order. For example, controller 150 generates a first column control signal to select a reference cell 140-11 from a plurality of reference cells 140-11 to 140-1p via selector terminal CN1 of multiplexer MUX 130-1. Reference cell 140-11 is located in the first row of the plurality of reference cells 140-11 to 140-1p arranged in column order. Therefore, controller 150 can select a reference cell from the plurality of reference cells 140-11 to 140-1p arranged in column order via column control signal through MUX 130-1. For example, during a first read operation, controller 150 selects reference cell 140-11 via the first column control signal. Then, during a second read operation, controller 150 selects reference cell 140-12 via the second column control signal. Then, during the p-th read operation, controller 150 selects reference cell 140-1p via the p-th column control signal. The process can then be repeated by selecting reference cell 140-11 in the next read operation. In other words, simply put, reference cells 140-11 to 140-1p can be used sequentially and repeatedly during a read operation. Therefore, reference cells 140-11 to 140-1p can avoid being stressed or subjected to a large number of accesses in response to a read operation, and the values ​​of reference cells 140-11 to 140-1p can remain equal.

[0015] In some embodiments disclosed herein, controller 150 controls MUX 130-2 to sequentially and repeatedly select one of reference cells 140-21 to 140-2p as the selected reference cell to couple to reference terminal RN2 of SA 120-2 in response to each read operation performed on at least one memory cell (i.e., memory cells 110-1 to 110-n). Controller 150 generates a second set of control signals to select one reference cell 140-21 from the plurality of reference cells 140-21 to 140-2p via selector terminal CN2 of multiplexer MUX 130-2. Therefore, reference cells 140-21 to 140-2p can be used sequentially and repeatedly during read operations. Thus, reference cells 140-21 to 140-2p can avoid being subjected to stress or excessive access in response to read operations, and the values ​​of reference cells 140-21 to 140-2p can remain equal.

[0016] In some embodiments disclosed herein, MUX 130-1 performs selection from its input terminals to its output terminals based on column control signals from controller 150. MUX 130-2 performs selection from its input terminals to its output terminals based on column control signals from controller 150. MUX 130-n performs selection from its input terminals to its output terminals based on column control signals from controller 150. The input terminals of MUX 130-n perform selection from its input terminals to its output terminals based on column control signals from controller 150. The input terminals of MUX 130-1 are coupled to reference units 140-11 to 140-1p. Selector terminals CN1 of MUX 130-1, CN2 of MUX 130-2, and CNn of MUX 130-n are coupled to controller 150. The output terminal of MUX 130-1 is coupled to the input terminal RN1 of SA 120-1, the output terminal of MUX 130-2 is coupled to the input terminal RN2 of SA 120-2, and the output terminal of MUX 130-n is coupled to the input terminal RNn of SA 120-n. On the other hand, the reference terminals RN1 to RNn of SA 120-1 to 120-n are coupled to each other. For example, the reference terminal RN1 of MUX 130-1 is coupled to the reference terminal RN2 of MUX 130-2.

[0017] Therefore, SA 120-1 to 120-n have the same reference voltage according to the parallel structure of the selected reference cells controlled by controller 150. For example, controller 150 selects reference cell 140-11 from a plurality of reference cells 140-11 to 140-1p via MUX 130-1. Since the output terminal of MUX 130-1 is coupled to the reference terminals RN1 of SA 120-1 to RNn of SA 120-n, SA 120-1 to 120-n utilize reference cell 140-11 as a common reference cell during read operations. In another example, controller 150 selects reference cell 140-21 from a plurality of reference cells 140-21 to 140-2p via MUX 130-2. Because the output terminals of MUX 130-2 are coupled to reference terminals RN1 of SA120-1 to RNn of SA 120-n, SA 120-1 to 120-n utilize reference unit 140-21 as a common reference unit during read operations. In another example, controller 150 selects reference unit 140-11 from a plurality of reference units 140-11 to 140-1p via MUX 130-1, and selects reference unit 140-21 from a plurality of reference units 140-21 to 140-2p via MUX 130-2. Because the output terminals of MUX 130-1 and MUX 130-2 are coupled to reference terminals RN1 of SA 120-1 to RNn of SA 120-n, SA 120-1 to 120-n utilize reference units 140-11 and 140-21 as a common reference unit during read operations. In cases where controller 150 selects more than one reference unit, and each reference unit is selected from multiple reference units connected to the same multiplexer, the value of the common reference unit is averaged. For example, if the selected reference units 140-11 and 140-21 have values ​​A and B respectively, the average value can be (A+B) / 2. Therefore, by applying this configuration, error readings caused by small differences in the values ​​of each reference unit can be avoided by averaging the values ​​of the selected reference units.

[0018] In some embodiments disclosed herein, SA 120-1 to 120-n may be comparators. SA 120-1 to 120-n may be implemented using a combination of transistors, resistors, and capacitors. SA 120-1 may perform a comparison between at least one memory cell 110-1 and a reference cell 140-11 selected by the controller 150 via MUX 130-1 from a plurality of reference cells 140-11 to 140-1p. SA 120-2 may perform a comparison between at least one memory cell 110-2 and a reference cell 140-21 selected by the controller 150 via MUX 130-2 from a plurality of reference cells 140-21 to 140-2p. SA 120-1 may perform a comparison between at least one memory cell 110-1 and more than one reference cell. Each reference cell can be selected from one of a plurality of reference cells 140-11 to 140-1p via MUX 130-1 and from one of a plurality of reference cells 140-21 to 140-2p via MUX 130-2. By applying various combinations as described above, the plurality of reference cells 140-11 to 140-1p, the plurality of reference cells 140-21 to 140-2p, and the plurality of reference cells 140-n1 to 140-np can be accessed equally and repeatedly to avoid stress or excessive access to the reference cells during read operations. Therefore, the lifetime of the memory device can be optimized.

[0019] Figure 2 A detailed block diagram of the structure of a sense amplifier according to an embodiment of the present disclosure is shown, wherein multiple reference units are selected via a multiplexer by a row control signal generated by a controller.

[0020] exist Figure 1 In the illustrated embodiment, multiple reference units are arranged in a column. Figure 2 In the illustrated embodiment, multiple reference units are arranged in a row.

[0021] In this exemplary embodiment, controller 150 controls MUX 130-1 to sequentially and repeatedly select one of reference cells 140-11 to 140-1q as the selected reference cell and couple it to reference terminal RN1 of SA 120-1 in response to performing each read operation on at least one memory cell (i.e., memory cells 110-1 to 110-n). Controller 150 may have multiple output terminals, each output terminal coupled to the selector terminal of each multiplexer (i.e., MUX 130-1 to MUX 130-n). Controller 150 generates at least one row control signal to select one reference cell from a plurality of reference cells arranged in row order. For example, controller 150 generates a first row control signal to select one reference cell 140-11 from the plurality of reference cells 140-11 to 140-1q via selector terminal CN1 of multiplexer MUX 130-1. Reference units 140-11 are located in the first column of a plurality of reference units 140-11 to 140-1q arranged in row order. Therefore, controller 150 can select one reference unit from the plurality of reference units 140-11 to 140-1q arranged in row order via MUX 130-1 using row control signals. For example, during a first read operation, controller 150 selects reference unit 140-11 via the first row control signal. Then, during a second read operation, controller 150 selects reference unit 140-12 via the second row control signal. Then, during a q-th read operation, controller 150 selects reference unit 140-1q via the q-th row control signal. This process can then be repeated by selecting reference unit 140-11 in the next read operation. In other words, simply put, reference units 140-11 to 140-1q can be used sequentially and repeatedly during read operations. Therefore, reference cells 140-11 to 140-1q can avoid being stressed or subjected to a large number of accesses in response to read operations, and the values ​​of reference cells 140-11 to 140-1q can remain equal.

[0022] In some embodiments disclosed herein, controller 150 controls MUX 130-2 to sequentially and repeatedly select one of reference cells 140-21 to 140-2q as the selected reference cell to couple to reference terminal RN2 of SA 120-2 in response to each read operation performed on at least one memory cell (i.e., memory cells 110-1 to 110-n). Controller 150 generates a second line of control signals to select one reference cell 140-21 from the plurality of reference cells 140-21 to 140-2q via selector terminal CN2 of multiplexer MUX 130-2. Therefore, reference cells 140-21 to 140-2q can be used sequentially and repeatedly during read operations. Thus, reference cells 140-21 to 140-2q can avoid being subjected to stress or excessive access in response to read operations, and the values ​​of reference cells 140-21 to 140-2q can remain equal.

[0023] In some embodiments disclosed herein, MUX 130-1 performs canalization from its input terminals to its output terminals according to a row control signal from controller 150. MUX 130-2 performs canalization from its input terminals to its output terminals according to a row control signal from controller 150. MUX 130-n performs canalization from its input terminals to its output terminals according to a row control signal from controller 150. MUX 130-n performs canalization from its input terminals to its output terminals according to a row control signal from controller 150. The input terminals of MUX 130-1 are coupled to reference units 140-11 to 140-1q. Selector terminals CN1 of MUX 130-1, CN2 of MUX 130-2, and CNn of MUX 130-n are coupled to controller 150. The output terminal of MUX 130-1 is coupled to the input terminal RN1 of SA 120-1, the output terminal of MUX 130-2 is coupled to the input terminal RN2 of SA 120-2, and the output terminal of MUX 130-n is coupled to the input terminal RNn of SA 120-n. On the other hand, the reference terminals RN1 to RNn of SA 120-1 to 120-n are coupled to each other. For example, the reference terminal RN1 of MUX 130-1 is coupled to the reference terminal RN2 of MUX 130-2.

[0024] By utilizing the row control signal generated by the controller 150, the controller 150 can select one reference cell 140-11, 140-21, or 140-2n from a plurality of reference cells 140-11 to 140-1q, 140-21 to 140-2q, or 140-n1 to 140-nq arranged in row order, located in the first column. The controller 150 can also select more than one reference cell (i.e., 140-11 and 140-21) from the plurality of reference cells arranged in row order (140-11 to 140-1q and 140-21 to 140-2q). Furthermore, the controller 150 can select a plurality of reference cells 140-11 to 140-1q, 140-21 to 140-2q, or 140-n1 to 140-nq arranged in column order, row order, or in combination.

[0025] Figure 3 A detailed block diagram of the structure of a sense amplifier according to an embodiment of the present disclosure is shown, wherein multiple reference cells are selected via a multiplexer by column control signals and row control signals generated by a controller.

[0026] exist Figure 1 In the illustrated embodiment, multiple reference units are arranged in a column. Figure 2 In the illustrated embodiment, multiple reference units are arranged in a row. Figure 3 In the illustrated embodiment, multiple reference units are arranged in a matrix with multiple columns and rows.

[0027] In this exemplary embodiment, controller 150 controls MUX 130-1 to sequentially and repeatedly select one of reference cells 140-1[1,1] to 140-1[p,q] as the selected reference cell to couple to reference terminal RN1 of SA 120-1 in response to each read operation performed on at least one memory cell (i.e., memory cells 110-1 to 110-n). Controller 150 may have multiple output terminals, each output terminal coupled to the selector terminal of each multiplexer (i.e., MUX 130-1 to MUX 130-n). Controller 150 generates at least one column and row control signal to select one reference cell from a plurality of reference cells arranged in a matrix having multiple columns and multiple rows. For example, controller 150 generates first column and row control signals to select one reference cell 140-1[1,1] from a plurality of reference cells 140-1[1,1] to 140-1[p,q] via selector terminal CN1 of multiplexer MUX 130-1. Reference cell 140-1[1,1] is located in the first row and first column of the plurality of reference cells 140-1[1,1] to 140-1[p,q] arranged in a matrix. Therefore, controller 150 can select one reference cell from the plurality of reference cells 140-1[1,1] to 140-1[p,q] arranged in a matrix via MUX 130-1 using column and row control signals. For example, during a first read operation, controller 150 selects reference cell 140-1[1,1] via the first column and row control signals. Then, during a second read operation, controller 150 selects reference cell 140-1[2,1] via the second column and row control signals. Then, during the p-th read operation, the controller 150 selects reference unit 140-1 [p,1] via the p-th column and row control signals. Then, during the (p+1)-th read operation, the controller 150 selects reference unit 140-1 [1,2] via the (p+1)-th column and row control signals. Then, during the (p+2)-th read operation, the controller 150 selects reference unit 140-1 [2,2] via the (p+2)-th column and row control signals. Then, during the (2*p)-th read operation, the controller 150 selects reference unit 140-1 [p,2] via the (2*p)-th column and row control signals. Then, during the ((q-1)*p+1)-th read operation, the controller 150 selects reference unit 140-1 [1,q] via the ((q-1)*p+1)-th column and row control signals. Then, during the ((q-1)*p+2)th read operation, the controller 150 selects the reference unit 140-1[2,q] via the ((q-1)*p+2)th column and row control signals. Then, during the (q*p)th read operation, the controller 150 selects the reference unit 140-1[p,q] via the (q*p)th column and row control signals.The process can then be repeated by selecting reference cell 140-1[1,1] in the next read operation. In other words, simply put, reference cells 140-1[1,1] to 140-1[p,q] can be used sequentially and repeatedly during the read operation. Therefore, reference cells 140-1[1,1] to 140-1[p,q] can avoid being stressed or subjected to a large number of accesses in response to the read operation, and the values ​​of reference cells 140-1[1,1] to 140-1[p,q] can remain equal.

[0028] In some embodiments disclosed herein, controller 150 controls MUX 130-2 to sequentially and repeatedly select one of reference cells 140-2[1,1] to 140-2[p,q] as the selected reference cell to couple to reference terminal RN2 of SA 120-2 in response to each read operation performed on at least one memory cell (i.e., memory cells 110-1 to 110-n). Controller 150 generates second column and row control signals to select one reference cell 140-2[1,1] from the plurality of reference cells 140-2[1,1] to 140-2[p,q] via selector terminal CN2 of multiplexer MUX 130-2. Therefore, reference cells 140-2[1,1] to 140-2[p,q] can be used sequentially and repeatedly during read operations. Therefore, reference cells 140-2[1,1] to 140-2[p,q] can avoid being stressed or subjected to a large number of accesses in response to read operations, and the values ​​of reference cells 140-2[1,1] to 140-2[p,q] can remain equal.

[0029] In some embodiments disclosed herein, controller 150 controls MUX 130-1 to sequentially and repeatedly select one of reference cells 140-1[1,1] to 140-1[p,q] as the selected reference cell to couple to reference terminal RN2 of SA 120-2 in response to each read operation performed on at least one memory cell (i.e., memory cells 110-1 to 110-n). Controller 150 generates second column and row control signals to select one reference cell 140-1[1,1] from the plurality of reference cells 140-1[1,1] to 140-2[p,q] via selector terminal CN1 of multiplexer MUX 130-1. Therefore, during a read operation, SA 120-2 can utilize one of the plurality of reference cells 140-1[1,1] to 140-1[p,q] via MUX 130-1. In other words, simply put, SA can utilize any of the reference cells with a different column order than SA.

[0030] In some embodiments disclosed herein, MUX 130-1 performs selection from any of its input terminals to its output terminal based on column and row control signals from controller 150. MUX 130-2 performs selection from any of its input terminals to its output terminal based on column and row control signals from controller 150. MUX 130-n performs selection from any of its input terminals to its output terminal based on column and row control signals from controller 150. MUX 130-n performs selection from any of its input terminals to its output terminal based on column and row control signals from controller 150. The input terminals of MUX 130-1 are coupled to reference units 140-1[1,1] to 140-1[p,q]. Selector terminals CN1 of MUX 130-1, CN2 of MUX 130-2, and CNn of MUX 130-n are coupled to controller 150. The output terminal of MUX 130-1 is coupled to the input terminal RN1 of SA 120-1, the output terminal of MUX 130-2 is coupled to the input terminal RN2 of SA 120-2, and the output terminal of MUX 130-n is coupled to the input terminal RNn of SA 120-n. On the other hand, the reference terminals RN1 to RNn of SA 120-1 to 120-n are coupled to each other. For example, the reference terminal RN1 of MUX 130-1 is coupled to the reference terminal RN2 of MUX 130-2.

[0031] By utilizing column and row control signals generated by controller 150, controller 150 can select one reference cell 140-1[1,1], 140-2[1,1], or 140-n[1,1] located in the first row and first column from a plurality of reference cells 140-1[1,1] to 140-1[p,q], 140-2[1,1] to 140-2[p,q], or 140-n[1,1] to 140-n[p,q] arranged in a matrix. Controller 150 can also select more than one reference cell (i.e., 140-1[1,1] and 140-2[1,1]) from the plurality of reference cells arranged in a matrix (140-1[1,1] to 140-1[p,q] and 140-2[1,1] to 140-2[p,q]). Furthermore, the controller 150 can select multiple reference units 140-1[1,1] to 140-1[p,q], 140-2[1,1] to 140-2[p,q] or 140-n[1,1] to 140-n[p,q] arranged in column order, in row order, or in a matrix form with multiple columns and multiple rows.

[0032] Figure 4 A flowchart illustrating the steps of a read operation on at least one memory cell according to an embodiment of this disclosure is shown.

[0033] Reference Figure 4 , for example Figures 1 to 3 The read operation of at least one memory cell selected from the plurality of memory cells 110-1 to 110-n shown can be performed by, for example, Figures 1 to 3 The execution can be performed by any of the multiple SA120-1 to 120-n shown, but is not limited to this.

[0034] In this exemplary embodiment, a setting is provided from such Figures 1 to 3 The multiple SAs shown are any one of the SAs selected from 120-1 to 120-n, and those in the same column order as the selected SAs, such as... Figure 1 The multiple reference elements 140-11 to 140-np shown, or as... Figure 2 The multiple reference elements 140-11 to 140-nq shown or as... Figure 3 The multiple reference units 140-1[1,1] to 140-n[p,q] are shown. For example, referencing... Figure 1 and Figure 4 The controller 150 sets SA 120-1 and a plurality of reference units 140-11 to 140-1p. In another embodiment, the reference... Figure 2 and Figure 4 The controller 150 sets SA 120-1 and a plurality of reference units 140-11 to 140-1q. In another embodiment, the reference... Figure 3 and Figure 4 The controller 150 sets SA 120-1 and multiple reference units 140-1[1,1] to 140-1[p,q].

[0035] In step S501, the controller, as shown in the example... Figure 1 The multiple reference elements 140-11 to 140-np shown, or in, for example Figure 2 The multiple reference elements 140-11 to 140-nq shown, or in, for example Figure 3 A reference element is selected from the plurality of reference elements 140-1[1,1] to 140-n[p,q] shown. For example, referencing Figure 1 and Figure 4 In response to the controller 150 setting SA 120-1 and a plurality of reference units 140-11 to 140-1p, the controller 150 selects one reference unit 140-11 from the plurality of reference units 140-11 to 140-1p. In another embodiment, referring to Figure 2 and Figure 4In response to the controller 150 setting SA120-1 and a plurality of reference units 140-11 to 140-1q, the controller 150 selects one reference unit 140-11 from the plurality of reference units 140-11 to 140-1q. In another embodiment, referring to Figure 3 and Figure 4 In response to the controller 150 setting SA 120-1 and a plurality of reference units 140-1[1,1] to 140-1[p,q], the controller 150 selects one reference unit 140-1[1,1] from the plurality of reference units 140-1[1,1] to 140-1[p,q]. That is, the controller 150 selects one of the reference units that is in the same column order as SA set by the controller 150.

[0036] The selected reference unit leads to the output terminal of the multiplexer. For example, the reference... Figure 1 The selected reference unit 140-11 is connected to the output terminal of MUX 130-1. Since the output terminal of MUX 130-1 is coupled to the reference terminal RN1 of SA 120-1, SA 120-1 uses the selected reference unit 140-11 to generate a reference voltage.

[0037] In step S502, one of the plurality of SAs 120-1 to 120-n is determined according to... Figure 1 Among the multiple reference elements 140-11 to 140-np shown, or as... Figure 2 Among the multiple reference elements 140-11 to 140-nq shown, or as... Figure 3 The selected reference cell among the plurality of reference cells 140-1[1,1] to 140-n[p,q] shown reads at least one memory cell among the plurality of memory cells 110-1 to 110-n. For example, referencing Figure 1 and Figure 4In response to controller 150 selecting reference unit 140-11 via MUX 130-1, SA 120-1 reads at least one memory unit 110-1. In another embodiment, in response to controller 150 selecting reference unit 140-21 via MUX 130-2, SA 120-1 reads at least one memory unit 110-1. In another embodiment, in response to controller 150 selecting reference unit 140-11 via MUX 130-1 and selecting reference unit 140-21 via MUX 130-2, SA 120-1 reads at least one memory unit 110-1. That is, controller 150 performs the step of reading the at least one memory unit based on a selected reference unit located in the same column order relative to the at least one memory unit. Controller 150 may perform the step of reading the at least one memory unit based on a selected reference unit located in a different column order relative to the at least one memory unit. Controller 150 may perform the step of reading the at least one memory unit based on more than one selected reference unit located in any column order relative to the at least one memory unit.

[0038] The reading process of step S502 can be performed in two steps (step S503 and step S504). Step S503 is performed by comparing the data voltage of at least one first memory cell with the reference voltage of the selected reference cell. The reference voltage of the selected reference cell can be generated by the current (any one of currents Iref1 to Irefn) flowing through the reference cell (reference cells 140-11 to 140-np, 140-11 to 140-nq, or 140-1[1,1] to 140-n[p,q]).

[0039] In step S504, one of the plurality of SAs 120-1 to 120-n obtains data from at least one of the plurality of memory cells 110-1 to 110-n at the output terminal of said one of the plurality of SAs 120-1 to 120-n. The data obtained at the output terminal of said one of the plurality of SAs 120-1 to 120-n is generated based on a comparison of the data voltage of said at least one first memory cell with a reference voltage of a selected reference cell. For example, referring to... Figure 1 and Figure 4SA120-1 obtains data from at least one memory cell 110-1 at its output terminal ON1. The process of obtaining data involves amplifying the difference between the data voltage of the at least one memory cell from a plurality of memory cells 110-1 to 110-n and the reference voltage of a selected reference cell from a plurality of reference cells 140-11 to 140-np, 140-11 to 140-nq, or 140-1[1,1] to 140-n[p,q] to a readable data output. The process of amplifying data using any of SA 120-1 to 120-n involves multiplying the difference between the data voltage of the at least one memory cell from a plurality of memory cells 110-1 to 110-n and the reference voltage of a selected reference cell from a plurality of reference cells 140-11 to 140-np, 140-11 to 140-nq, or 140-1[1,1] to 140-n[p,q] by a value k, where k is a positive integer. The difference between the data voltage of at least one of the plurality of memory cells 10-1 to 110-n and the reference voltage of a selected reference cell among the plurality of reference cells 140-11 to 140-np, 140-11 to 140-nq, or 140-1[1,1] to 140-n[p,q] can be positive or negative. The readable data output can be a data output that can be read by another hardware circuitry within or outside the memory device 100. The readable data output can be ±3 volts or ±5 volts, but is not limited to these.

[0040] Based on the above, the structure of the memory device 100 that performs wear-leveling access is designed to have, for example, Figure 1 The multiple reference elements 140-11 to 140-np shown, or as... Figure 2 The memory device 200 shows a plurality of reference cells 140-11 to 140-nq or such as Figure 3The memory device 300 includes a plurality of reference cells 140-1[1,1] to 140-n[p,q]. A plurality of reference cells 140-11 to 140-1p, a plurality of first reference cells 140-11 to 140-1q, or a plurality of reference cells 140-1[1,1] to 140-1[p,q] may be coupled to a MUX 130-1, which is coupled to a reference terminal RN1 of an SA 120-1 configured to read at least one memory cell 110-1. In another embodiment, a plurality of reference units 140-21 to 140-2p, a plurality of first reference units 140-21 to 140-2q, or a plurality of reference units 140-2[1,1] to 140-2[p,q] may be coupled to MUX 130-2, MUX 130-2 being coupled to reference terminal RN2 of SA 120-2, SA 120-2 being configured to read at least one memory unit 110-2. In another embodiment, a plurality of reference units 140-21 to 140-2p, a plurality of first reference units 140-21 to 140-2q, or a plurality of reference units 140-2[1,1] to 140-2[p,q] may be coupled to MUX 130-2, MUX 130-2 being coupled to reference terminal RN1 of SA 120-1, SA 120-1 being configured to read at least one memory unit 110-1. In another embodiment, a plurality of reference units 140-11 to 140-1p and 140-21 to 140-2p, a plurality of first reference units 140-11 to 140-1q and 140-21 to 140-2q, or a plurality of reference units 140-1[1,1] to 140-1[p,q] and 140-2[1,1] to 140-2[p,q] may be coupled to MUX 130-1 and MUX 130-2, respectively. MUX 130-1 and MUX 130-2 are coupled to reference terminal RN1 of SA120-1, which is configured to read at least one memory unit 110-1. Reference terminals RN1 to RNn of SA 120-1 to 120-n are coupled to each other. When performing each read operation on at least one of the plurality of memory cells 110-1 to 110-n, each of the plurality of reference cells 140-21 to 140-2p, 140-21 to 140-2q, or 140-2[1,1] to 140-2[p,q] is selected sequentially and repeatedly. The number of SA, MUX, plurality of reference cells, and memory cells is not limited to one or two. The number of SA, MUX, plurality of reference cells, and memory cells may be more than two, but is not limited thereto. Therefore, by utilizing the above-described structure of the memory device 100, the number of accesses to a particular reference cell can be reduced. Therefore, each reference cell can be accessed evenly and repeatedly.

[0041] According to some embodiments, a memory device is provided. The memory device includes at least one first memory cell, a first sense amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sense amplifier is coupled to the at least one first memory cell. The first sense amplifier includes an output terminal and a reference terminal. The output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sense amplifier. Each of the plurality of first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. When each read operation is performed on the at least one first memory cell, the controller controls the first multiplexer circuit to sequentially and repeatedly select one of the first reference cells as the selected reference cell to couple to the reference terminal of the first sense amplifier.

[0042] According to some embodiments, the memory device further includes at least one second memory cell, a second sense amplifier, a second multiplexer circuit, a plurality of second reference cells, and the controller. The second sense amplifier is coupled to the at least one second memory cell. The second sense amplifier includes an output terminal and a reference terminal. The output terminal of the second multiplexer circuit is coupled to the reference terminal of the second sense amplifier. Each of the plurality of second reference cells is coupled to each input node of the second multiplexer circuit. The controller is coupled to a control terminal of the second multiplexer circuit. When each read operation is performed on the at least one second memory cell, the controller controls the second multiplexer circuit to sequentially and repeatedly select one of the second reference cells as the selected reference cell to couple to the reference terminal of the second sense amplifier.

[0043] According to some embodiments, the reference terminal of the second sensing amplifier is coupled to the reference terminal of the first sensing amplifier. According to some embodiments, the plurality of first reference cells are arranged in a column. According to some embodiments, the plurality of first reference cells are arranged in a row. According to some embodiments, the plurality of first reference cells are arranged in a matrix having multiple columns and rows. According to some embodiments, the at least one first memory cell is a column of a memory array. According to some embodiments, the first sensing amplifier generates data for the at least one first memory cell at its output terminal by comparing the data voltage of the at least one first memory cell with the reference voltage of the selected reference cell.

[0044] According to some embodiments, a sense amplifier is provided. The sense amplifier is coupled to at least one memory cell. The sense amplifier, which performs loss equalization on reference cells, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells. The output terminal of the multiplexer circuit is coupled to the reference terminal of the sense amplifier. Each of the plurality of reference cells is coupled to each input node of the multiplexer circuit. When each read operation is performed on the at least one memory cell, the multiplexer circuit is controlled by a control signal to sequentially and repeatedly select one of the reference cells as the selected reference cell to couple to the reference terminal of the sense amplifier.

[0045] According to some embodiments, the plurality of reference cells are arranged in a column. According to some embodiments, the plurality of reference cells are arranged in a row. According to some embodiments, the plurality of reference cells are arranged in a matrix having multiple columns and multiple rows. According to some embodiments, the at least one memory cell is a column of a memory array. According to some embodiments, the sense amplifier generates data for the at least one memory cell at the output terminal of the sense amplifier by comparing the data voltage of the at least one memory cell with the reference voltage of the selected reference cell.

[0046] According to some embodiments, a method for sensing a memory cell is provided. The method for sensing a memory cell includes: when performing each read operation on at least one first memory cell, selecting one of the first reference cells as the selected reference cell to be coupled to a reference terminal of a first sensing amplifier; and performing a read operation on the at least one first memory cell according to the selected reference cell, wherein performing the read operation on the at least one first memory cell according to the selected reference cell includes: comparing a data voltage of the at least one first memory cell with a reference voltage of the selected reference cell; and obtaining data of the at least one first memory cell at an output terminal of the first sensing amplifier based on the comparison result between the data voltage of the at least one first memory cell and the reference voltage of the selected reference cell.

[0047] According to some embodiments, the method further includes: when performing each read operation on at least one second memory cell, selecting one of the second reference cells as the selected reference cell to be coupled to a reference terminal of the second sense amplifier; and performing a read operation on the at least one second memory cell according to the selected reference cell, wherein the step of performing the read operation on the at least one second memory cell according to the selected reference cell includes: comparing the data voltage of the at least one second memory cell with the reference voltage of the selected reference cell; and obtaining the data of the at least one second memory cell at the output terminal of the second sense amplifier based on the comparison result of the data voltage of the at least one second memory cell with the reference voltage of the selected reference cell.

[0048] According to some embodiments, the reference terminal of the second sensing amplifier is coupled to the reference terminal of the first sensing amplifier. According to some embodiments, the plurality of first reference cells are arranged in a column, a row, or a matrix having multiple columns and rows. According to some embodiments, the at least one first memory cell is a column of a memory array.

[0049] According to some embodiments, the method further includes: in response to performing a next read operation on at least one second memory cell, sequentially and repeatedly selecting another of the second reference cells as the selected reference cell to couple to a reference terminal of the second sense amplifier.

[0050] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand the detailed description above. Those skilled in the art will understand that they can easily use this invention as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of the invention.

[0051] [Explanation of Symbols]

[0052] 100: Memory device

[0053] 105: Memory Array

[0054] 110-1, 110-2, ..., 110-n: Memory cells

[0055] 120-1, 120-2, ..., 120-n: Sensing amplifier / SA

[0056] 130-1, 130-2, ..., 130-n: Multiplexer circuit / Multiplexer / MUX

[0057] 140-11, ..., 140-1p, 140-1q, 140-21, ..., 140-2p, 140-2q, 140-n1, ..., 140-np, 140-nq, 140-1[1,1], ..., 140-1[p,1], 140-1[1,q], ..., 140-1[p,q], 140-2[1,1], ..., 140-2[p,1], 140-2[1,q], ..., 140-2[p,q], 140-n[1,1], ..., 140-n[p,1], 140-n[1,q], ..., 140-n[p,q]: Reference unit

[0058] 150: Controller

[0059] CN1, CN2, ..., CNn: Control terminals / selector terminals

[0060] Iref1, Iref2, ..., Irefn: Current

[0061] MUX: Multiplexer circuit / Multiplexer

[0062] ON1, ON2, ..., ONn: Output terminals

[0063] RN1, RN2, ..., RNn: Reference terminals / input terminals

[0064] S501, S502, S503, S504: Steps

[0065] SA: Sensing Amplifier

Claims

1. A memory device, comprising: At least one first memory unit; A first sensing amplifier is coupled to the at least one first memory cell, and the first sensing amplifier includes an output terminal and a reference terminal. A first multiplexer circuit, wherein the output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sensing amplifier; A plurality of first reference units, the plurality of first reference units having the same value, each of the plurality of first reference units being coupled to each input node of the first multiplexer circuit; as well as The controller is coupled to the control terminal of the first multiplexer circuit. When performing each read operation on the at least one first memory cell, the controller controls the first multiplexer circuit to select one of the plurality of first reference cells as the selected reference cell to couple to the reference terminal of the first sense amplifier. The plurality of first reference units are selected sequentially and repeatedly, and one of the plurality of first reference units is selected for a single read operation on the at least one first memory unit.

2. The memory device according to claim 1, further comprising: At least one second memory unit; A second sensing amplifier is coupled to the at least one second memory cell, and the second sensing amplifier includes an output terminal and a reference terminal. A second multiplexer circuit, the output terminal of which is coupled to the reference terminal of the second sensing amplifier; as well as Multiple second reference units, each of which is coupled to each input node of the second multiplexer circuit. When each read operation is performed on the at least one second memory cell, the controller controls the second multiplexer circuit to select one of the second reference cells as the selected reference cell to couple to the reference terminal of the second sense amplifier.

3. The memory device of claim 2, wherein the reference terminal of the second sense amplifier is coupled to the reference terminal of the first sense amplifier.

4. The memory device of claim 1, wherein the plurality of first reference cells are arranged in a column.

5. The memory device of claim 1, wherein the plurality of first reference cells are arranged in a row.

6. The memory device of claim 1, wherein the plurality of first reference cells are arranged in a matrix having multiple columns and multiple rows.

7. The memory device of claim 1, wherein the at least one first memory cell is a column of a memory array.

8. The memory device of claim 1, wherein the first sense amplifier generates data of the at least one first memory cell at the output terminal of the first sense amplifier by comparing the data voltage of the at least one first memory cell with the reference voltage of the selected reference cell.

9. A sensing amplifier coupled to at least one memory cell, The sensing amplifier includes: Output terminals and reference terminals; A multiplexer circuit, wherein the output terminal of the multiplexer circuit is coupled to the reference terminal of the sense amplifier; as well as Multiple reference units, each having the same value, are coupled to each input node of the multiplexer circuit. When each read operation is performed on the at least one memory cell, the multiplexer circuit is controlled by a control signal to select one of the reference cells as the selected reference cell to be coupled to the reference terminal of the sense amplifier. The plurality of reference cells are selected sequentially and repeatedly, and one of the plurality of reference cells is selected for a single read operation on the at least one memory cell.

10. The sensing amplifier of claim 9, wherein the plurality of reference units are arranged in a column.

11. The sensing amplifier of claim 9, wherein the plurality of reference units are arranged in a row.

12. The sensing amplifier of claim 9, wherein the plurality of reference units are arranged in a matrix having multiple columns and multiple rows.

13. The sensing amplifier of claim 9, wherein the at least one memory cell is a column of a memory array.

14. The sensing amplifier of claim 9, wherein the sensing amplifier generates data of the at least one first memory cell at the output terminal of the sensing amplifier by comparing the data voltage of the at least one memory cell with the reference voltage of the selected reference cell.

15. A method for sensing memory cells, comprising: When each read operation is performed on at least one first memory cell, one of a plurality of first reference cells is selected as the selected reference cell and coupled to the reference terminal of the first sense amplifier, wherein the plurality of first reference cells have the same value; and A read operation is performed on the at least one first memory cell based on the selected reference cell. The step of performing the read operation on the at least one first memory cell according to the selected reference cell includes: The data voltage of the at least one first memory cell is compared with the reference voltage of the selected reference cell; and The data of the at least one first memory cell is obtained at the output terminal of the first sense amplifier by comparing the data voltage of the at least one first memory cell with the reference voltage of the selected reference cell. The plurality of first reference units are selected sequentially and repeatedly, and one of the plurality of first reference units is selected for a single read operation on the at least one first memory unit.

16. The method of claim 15, further comprising: When each read operation is performed on at least one second memory cell, one of a plurality of second reference cells is selected as the selected reference cell and coupled to the reference terminal of the second sense amplifier. as well as A read operation is performed on the at least one second memory cell based on the selected reference cell. The step of performing the read operation on the at least one second memory cell based on the selected reference cell includes: The data voltage of the at least one second memory cell is compared with the reference voltage of the selected reference cell; as well as The data of the at least one second memory cell is obtained at the output terminal of the second sense amplifier by comparing the data voltage of the at least one second memory cell with the reference voltage of the selected reference cell.

17. The method of claim 16, wherein the reference terminal of the second sensing amplifier is coupled to the reference terminal of the first sensing amplifier.

18. The method of claim 15, wherein the plurality of first reference units are arranged in a column, a row, or a matrix having multiple columns and multiple rows.

19. The method of claim 15, wherein the at least one first memory cell is a column of a memory array.

20. The method of claim 16, further comprising: In response to performing a next read operation on at least one second memory cell, another of the second reference cells is sequentially and repeatedly selected as the selected reference cell to be coupled to the reference terminal of the second sense amplifier.

21. A controller for a multiplexer circuit for sensing memory cells, wherein the controller is configured to: When each read operation is performed on at least one first memory cell, one of a plurality of first reference cells is selected as the selected reference cell and coupled to the reference terminal of the first sense amplifier, wherein the plurality of first reference cells have the same value; and A read operation is performed on the at least one first memory cell based on the selected reference cell. The controller performing the read operation on the at least one first memory cell based on the selected reference cell further includes: The data voltage of the at least one first memory cell is compared with the reference voltage of the selected reference cell; as well as The data of the at least one first memory cell is obtained at the output terminal of the first sense amplifier by comparing the data voltage of the at least one first memory cell with the reference voltage of the selected reference cell. The plurality of first reference units are selected sequentially and repeatedly, and one of the plurality of first reference units is selected for a single read operation on the at least one first memory unit.

22. The controller according to claim 21, further configured to: When each read operation is performed on at least one second memory cell, one of a plurality of second reference cells is selected as the selected reference cell and coupled to the reference terminal of the second sense amplifier. as well as A read operation is performed on the at least one second memory cell based on the selected reference cell. The controller, configured to perform the read operation on the at least one second memory cell based on the selected reference cell, further includes: The data voltage of the at least one second memory cell is compared with the reference voltage of the selected reference cell; as well as The data of the at least one second memory cell is obtained at the output terminal of the second sense amplifier by comparing the data voltage of the at least one second memory cell with the reference voltage of the selected reference cell.

23. The controller of claim 22, wherein the reference terminal of the second sensing amplifier is coupled to the reference terminal of the first sensing amplifier.

24. The controller of claim 21, wherein the plurality of first reference units are arranged in a column.

25. The controller of claim 21, wherein the plurality of first reference units are arranged in a row.

26. The controller of claim 21, wherein the plurality of first reference units are arranged in a matrix having multiple columns and multiple rows.

27. The controller of claim 21, wherein the at least one first memory unit is a column of a memory array.

28. The controller of claim 21, wherein the controller controls the first sensing amplifier to generate data of the at least one first memory cell at the output terminal of the first sensing amplifier by comparing the data voltage of the at least one first memory cell with the reference voltage of the selected reference cell.

29. A method for sensing memory cells, comprising: In response to each read operation performed on at least one first memory cell, one of a plurality of first reference cells is selected as the selected reference cell and coupled to the first sense amplifier, wherein the plurality of first reference cells have the same value; and A read operation is performed on the at least one first memory cell based on the selected reference cell. In response to each read operation performed on at least one first memory cell, the plurality of first reference cells are selected sequentially and repeatedly, and one of the plurality of first reference cells is selected for a single read operation on the at least one first memory cell. The method further includes: In response to each read operation performed on at least one second memory cell, one of a plurality of second reference cells is selected as the selected reference cell and coupled to the second sense amplifier; and A read operation is performed on the at least one second memory cell based on the selected reference cell. The step of performing the read operation on the at least one second memory cell based on the selected reference cell includes: The data voltage of the at least one second memory cell is compared with the reference voltage of the selected reference cell; and The data of the at least one second memory cell is obtained at the output terminal of the second sense amplifier by comparing the data voltage of the at least one second memory cell with the reference voltage of the selected reference cell.

30. The method of claim 29, wherein the step of performing the read operation on the at least one first memory cell according to the selected reference cell comprises: The data voltage of the at least one first memory cell is compared with the reference voltage of the selected reference cell; as well as The data of the at least one first memory cell is obtained at the output terminal of the first sense amplifier by comparing the data voltage of the at least one first memory cell with the reference voltage of the selected reference cell.

31. The method of claim 29, wherein the reference terminal of the second sensing amplifier is coupled to the reference terminal of the first sensing amplifier.

32. The method of claim 29, wherein the plurality of first reference units are arranged in a column, a row, or a matrix having multiple columns and multiple rows.

33. The method of claim 29, further comprising: In response to performing a next read operation on at least one second memory cell, another of the second reference cells is sequentially and repeatedly selected as the selected reference cell to be coupled to the reference terminal of the second sense amplifier.

34. A controller for a multiplexer circuit for sensing memory cells, The controller is configured to: In response to each read operation performed on at least one first memory cell, one of a plurality of first reference cells is selected as the selected reference cell and coupled to the first sense amplifier, wherein the plurality of first reference cells have the same value; and A read operation is performed on the at least one first memory cell based on the selected reference cell. in, In response to each read operation performed on at least one first memory cell, the plurality of first reference cells are selected sequentially and repeatedly, and one of the plurality of first reference cells is selected for a single read operation on the at least one first memory cell. The controller is also configured to: In response to each read operation performed on at least one second memory cell, one of a plurality of second reference cells is selected as the selected reference cell and coupled to the reference terminal of the second sense amplifier; as well as A read operation is performed on the at least one second memory cell based on the selected reference cell. The controller, configured to perform the read operation on the at least one second memory cell based on the selected reference cell, further includes: The data voltage of the at least one second memory cell is compared with the reference voltage of the selected reference cell; as well as The data of the at least one second memory cell is obtained at the output terminal of the second sense amplifier by comparing the data voltage of the at least one second memory cell with the reference voltage of the selected reference cell.

35. The controller of claim 34, wherein the reference terminal of the second sensing amplifier is coupled to the reference terminal of the first sensing amplifier.

36. The controller of claim 34, wherein the plurality of first reference units are arranged in a column.

37. The controller of claim 34, wherein the plurality of first reference units are arranged in a row.

38. The controller of claim 34, wherein the plurality of first reference units are arranged in a matrix having multiple columns and multiple rows.

39. The controller of claim 34, wherein the at least one first memory unit is a column of a memory array.

40. The controller of claim 34, wherein the controller controls the first sensing amplifier to generate data of the at least one first memory cell at the output terminal of the first sensing amplifier by comparing the data voltage of the at least one first memory cell with the reference voltage of the selected reference cell.

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