Method of manufacturing a semiconductor device and semiconductor device

Abstract

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed over the first work function adjustment material layer, a mask layer including an anti-reflective organic material layer is formed over the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etch mask. The adhesion enhancement layer has a higher adhesion strength to the anti-reflective organic material layer than to the first work function adjustment material layer. Embodiments of the present application also relate to semiconductor devices.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a method of manufacturing a semiconductor device and a semiconductor device. BACKGROUND

[0002] With increasing scaling of integrated circuits and increasingly stringent requirements on the speed of integrated circuits, transistors are required to have increasingly larger drive current at increasingly smaller sizes. Accordingly, three-dimensional field effect transistors (FETs) have been developed. A three-dimensional (3D) FET includes a vertical semiconductor nanostructure (such as a fin, nanowire, nanosheet, etc.) located above a substrate. The semiconductor nanostructure is used to form a source region and a drain region and a channel region between the source and drain regions. A shallow trench isolation (STI) region is formed to define the semiconductor nanostructure. The 3D FET also includes a gate stack formed on sidewalls and a top surface of the semiconductor fin or on all sides of the nanowire, nanosheet. Since the 3D FET has a three-dimensional channel structure, ion implantation processes on the channel need to be extra careful to reduce any geometric effects. With increasing scaling of integrated circuits, spacing between nearby devices is reduced and different threshold voltage devices are brought close together, resulting in threshold voltage shifts due to various process and / or structural issues. SUMMARY

[0003] Some embodiments of the present application provide a semiconductor device, comprising: a first field effect transistor (FET) comprising a first gate structure arranged above a first channel region; and a second field effect transistor having a different conductivity type than the first field effect transistor and comprising a second gate structure arranged above a second channel region, wherein: the first gate structure comprises: a first gate dielectric layer above the first channel region; a first work function adjusting material layer above the first gate dielectric layer; a bond-enhancing layer arranged above the first work function adjusting material layer; and a first metal gate electrode layer, the second gate structure comprises: a second gate dielectric layer above the second channel region; a second work function adjusting material layer above the second gate dielectric layer; and a second metal gate electrode layer, and the first work function adjusting material layer is nitrogen-free or contains nitrogen in an amount less than 50 atomic percent, and the bond-enhancing layer contains nitrogen in a range of 55 atomic percent to 75 atomic percent, and the second gate structure does not include the bond-enhancing layer.

[0004] Some embodiments of the present application provide a semiconductor device comprising: a first gate dielectric layer disposed over a channel region; a second gate dielectric layer disposed over the first gate dielectric layer; an adhesion enhancement layer disposed over the second gate dielectric layer; one or more work function adjustment material layers disposed over the adhesion enhancement layer; and a body gate electrode layer disposed over the one or more work function adjustment material layers, wherein: the second gate dielectric layer is an oxide of one or more of La, Lu, Sc, Sr, Zr, Y, Dy, Eu, or Y, and the adhesion enhancement layer comprises one or more of TiN, TiSiN, SiN, AlN, or AI2O3 x , wherein x is 1.1 to 1.5.

[0005] Some embodiments of the present application provide a method of manufacturing a semiconductor device comprising: forming a gate dielectric layer over a channel region made of a semiconductor material; forming a first work function adjustment material layer over the gate dielectric layer; forming an adhesion enhancement layer over the first work function adjustment material layer; forming a mask layer over the adhesion enhancement layer, the mask layer comprising an anti-reflective organic material layer; and patterning the adhesion enhancement layer and the first work function adjustment material layer by using the mask layer as an etch mask, wherein the adhesion enhancement layer has a higher adhesion strength to the anti-reflective organic material layer than to the first work function adjustment material layer, and the first work function adjustment material layer is nitrogen-free or contains nitrogen in an amount of less than 50 atomic percent, and the adhesion enhancement layer contains nitrogen in a range of 55 atomic percent to 75 atomic percent. BRIEF DESCRIPTION OF DRAWINGS

[0006] The application can best be understood by reference to the following detailed description when considered in connection with the accompanying drawings. It should be noted that various components have not been drawn to scale and certain components have been arbitrarily enlarged or reduced in order to highlight work product details. In actual practice, the dimensions of various components can be arbitrarily increased or decreased regardless of what is shown in the accompanying drawings.

[0007] Figure 1A shows a cross-sectional view of a semiconductor device according to embodiments of the present application, and Figure 1B shows a perspective view of the semiconductor device.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F shows a cross-sectional view of various stages of a sequential manufacturing process of a semiconductor device according to embodiments of the present application.

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F shows cross-sectional views of various stages of a sequential manufacturing process of a semiconductor device according to embodiments of the present application. Figure 3G shows a process flow of manufacturing a semiconductor device according to embodiments of the present application.

[0010] Figure 4A shows gate structures for multiple FETs with different threshold voltages according to embodiments of the present application. Figure 4B and Figure 4C shows various work function adjusting material layers and high-k gate dielectric layers for multiple FETs with different threshold voltages according to embodiments of the present application.

[0011] Figure 5A shows a plan view (layout) of a CMOS circuit according to embodiments of the present application, Figure 5B shows a cross-sectional view of region Al corresponding to Figure 5A , and Figure 5C shows an enlarged view of region Bl of Figure 5B .

[0012] Figure 6A shows a plan view (layout) of a CMOS circuit according to embodiments of the present application, Figure 6B shows a cross-sectional view of region Al corresponding to Figure 6A , and Figure 6C shows an enlarged view of region Bl of Figure 6B .

[0013] Figure 7 shows a process flow of manufacturing a semiconductor device according to embodiments of the present application.

[0014] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F shows cross-sectional views of various stages of a sequential manufacturing process of a semiconductor device according to embodiments of the present application.

[0015] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G and Figure 9H shows cross-sectional views of various stages of a sequential manufacturing process of a semiconductor device according to embodiments of the present application.

[0016] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H and Figure 10I shows cross-sectional views of various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present application.

[0017] Figure 11 shows a process flow of manufacturing a semiconductor device according to an embodiment of the present application.

[0018] Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E and Figure 12F shows cross-sectional views of various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application from that described. For example, dimensions of the elements can depend on the process conditions and / or the desired characteristics of the device. Moreover, in the following description, forming a first component over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. For simplicity and clarity, various components can be shown in different proportions to one another in the drawings. In the drawings, layers / elements can be omitted for simplicity and clarity.

[0020] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that the terms "by", "comprising", "including", "comprises", "comprised of", "comprising" and the like, are open-ended terms, and should be interpreted in the same manner as "including" or "comprising". Additionally, the term "coupled" and variations thereof, as used herein, can mean coupled whether directly or indirectly through another object, and can include wired and / or wireless coupling. Furthermore, the term "or" as used herein is used to mean "and / or", unless otherwise indicated. In addition, the term "exemplary" as used herein means "serving as an example, instance, or illustration", and should not be construed as applicable only to embodiments that are perfectly exemplary. In the following embodiments, materials, configurations, dimensions, processes, and / or operations as described for one embodiment (e.g., one or more figures) can be employed in other embodiments, and detailed descriptions thereof can be omitted.

[0021] The disclosed embodiments relate to semiconductor devices, and in particular to gate structures of field effect transistors (FETs) and methods of manufacturing the same. Embodiments such as disclosed herein are generally applicable not only to planar FETs, but also to finFETs, dual-gate FETs, fully- wrapped gate FETs, Omega-gate FETs, or fully-wrapped gate (GAA) FETs (such as lateral fully-wrapped gate FETs or vertical fully-wrapped gate FETs) and / or any suitable device having one or more of the gate structures, nanowire transistors, nanosheet transistors, nanotaper transistors, nanoplate transistors, or work function material (WFM) layers.

[0022] As technology scales down, semiconductor devices (e.g., transistors) are arranged closer together, and proximity effects (damage to nearby devices) are a growing concern. In FET structures, constructing multiple Vt devices with low Vt values ​​is crucial for reducing power consumption and improving device performance. The composition and thickness of the metal gate film play a vital role in defining the device's work function. Multiple FETs with different threshold voltages can be realized by adjusting the material and / or thickness of one or more work function adjustment material layers (WFMs) arranged between the gate dielectric layer and the body metal gate electrode layer (e.g., W layer). Furthermore, high-k dipole layers are used to form different Vt devices. Various patterning operations are performed when forming the gate structures for different Vt devices (and for devices with different conductivity types). In photolithography, a bottom anti-reflective layer (BARC) is used in conjunction with a photoresist layer. However, BARC layers made of organic materials may have low adhesion strength to underlying layers such as high-k dielectrics, dipole layers, or work function adjustment material layers. Therefore, at the metal boundary region, wet chemicals used in etching operations can penetrate into the interface between the BARC layer and the underlying layer, damaging the underlying layer. Furthermore, plasma processes used for patterning and removing the BARC layer can also damage the underlying layer. Additionally, wet chemicals used during cleaning processes or moisture in the atmosphere can also damage the high-k dipole layer and WFM layer.

[0023] This invention relates to the use of an adhesive layer above a power-function-adjustable metal layer and / or a high-k dielectric layer to improve the adhesion of a bottom anti-reflective layer.

[0024] Figure 1A A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown.

[0025] In some embodiments, the semiconductor device includes a gate stack 80 disposed over a channel region of the fin structure 20. The gate stack 80 includes an interface layer 81, a gate dielectric layer 82, a first conductive layer 83 as a protective layer, a second conductive layer 84 as a first barrier layer, a power function adjustment material layer or power function adjustment layer (WFM layer 86), a binder layer 87, and a body gate electrode layer 88, such as... Figure 1A As shown. In some embodiments, the fin structure 20 is disposed above the substrate 10 and protrudes from the insulating layer 30. Furthermore, gate sidewall spacers 46 are disposed on opposite sides of the gate stack 80, and one or more dielectric layers 50 are formed to cover the gate sidewall spacers 46. In some embodiments, an insulating material 42 is disposed between the gate sidewall spacers 46 and the insulating layer 30. Furthermore, as... Figure 1B As shown, a source / drain epitaxial layer 60 is formed above the recessed fin structure. Although Figure 1A Two fin structures are shown and Figure 1B Three fin structures are shown, but the number of fin structures is not limited to this. Figure 1Aand Figure 1B The number of layers is shown.

[0026] In some embodiments, the fin structure (channel region) is made of Si for n-type FETs and of SiGe for p-type FETs. In some embodiments, the Ge concentration of the SiGe is in the range of about 20 atomic % to 60 atomic % and in other embodiments in the range of about 30 atomic % to 50 atomic %. In some embodiments, the channel region of the n-type FET includes Ge in an amount less than the SiGe channel of the p-type FET. In other embodiments, the channel region of both the p-type FET and the n-type FET are made of Si or a compound semiconductor.

[0027] In some embodiments, the first conductive layer 83 includes a metal nitride such as WN, TaN, TiN, and TiSiN. In some embodiments, TiN is used. In some embodiments, the thickness of the first conductive layer 83 is in the range of about 0.3 nm to about 30 nm and in other embodiments in the range of about 0.5 nm to about 25 nm. In some embodiments, the first conductive layer 83 is crystalline with, for example, columnar grains. In some embodiments, the first conductive layer 83 is not formed. In some embodiments, the first conductive layer 83 is formed and then removed after an anneal operation with a wet etch process.

[0028] In some embodiments, the second conductive layer 84 includes a metal nitride such as WN, TaN, TiN, and TiSiN. In some embodiments, TaN is used. In some embodiments, the thickness of the second conductive layer 84 is in the range of about 0.3 nm to about 30 nm and in other embodiments in the range of about 0.5 nm to about 25 nm. In some embodiments, the second conductive layer 84 is used as a barrier or etch stop layer. In some embodiments, the second conductive layer 84 is thinner than the first conductive layer 83. In some embodiments, the second conductive layer 84 is not formed.

[0029] In some embodiments, the WFM layer 86 is made of a conductive material such as a single layer of TiN, WN, WCN, Ru, W, TaAlC, TiC, TaAl, TaC, Co, Al, TiAl, or TiAlC or two or more layers of these materials. For n-type FETs with Si channels, an aluminum-containing layer such as TiAl, TiAlC, TaAl, and / or TaAlC is used, optionally with one or more of TaN, TiN, WN, TiC, WCN, MoN, and / or Co formed underneath. For p-type FETs with SiGe channels, one or more of TaN, TiN, WN, TiC, WCN, MoN, and / or Co is used, optionally with one or more of TiAl, TiAlC, TaAl, and TaAlC formed on top.

[0030] In some embodiments, the adhesive layer 87 is made of one or more of TiN, Ti, and Co. In some embodiments, the body gate electrode layer 88 comprises one or more conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0031] As described above, in some embodiments, the first conductive layer 83 and the second conductive layer 84 are not formed. In this case, one or more WFM layers are formed directly on the gate dielectric layer 82.

[0032] Figures 2A to 3F Cross-sectional views are shown of the various stages of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. Figure 3G The diagram illustrates a process flow for manufacturing a semiconductor device according to an embodiment of the present invention. It can be understood that in a sequential manufacturing process, [the following steps can be taken]. Figures 2A to 3F One or more additional operations are provided before, during, and after the stages shown, and for additional embodiments of the method, some operations described below may be substituted or eliminated. The order of operations / processes may be interchanged.

[0033] like Figure 2A As shown, one or more fin structures 20 are fabricated above substrate 10. Substrate 10 is, for example, a p-type silicon substrate with an impurity concentration between about 1 × 10⁻⁶. 15 cm -3 To approximately 1×10 18 cm -3 Within the range. In other embodiments, substrate 10 is an n-type silicon substrate with an impurity concentration between approximately 1 × 10⁻⁶. 15 cm -3 To approximately 1×10 18 cm -3 Within the range of [specific parameters]. Optionally, substrate 10 may include another basic semiconductor such as germanium; such as germanium; compound semiconductors, including group IV-IV compound semiconductors such as SiC and SiGe, group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. In one embodiment, substrate 10 is a silicon layer of an SOI (silicon-on-insulator) substrate. Amorphous substrates such as amorphous silicon or amorphous SiC, or insulating materials such as silicon oxide, may also be used as substrate 10. Substrate 10 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity).

[0034] In some embodiments, a portion of the substrate 10 for the p-type FET is recessed by etching, and a SiGe layer is formed over the recess. Figures 2A to 3F An n-FET case is shown, but for a p-type FET, most of the fabrication process is essentially the same.

[0035] The fin structures 20 can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fin structures 20, including a double patterning or multiple patterning process. Generally, a double patterning or multiple patterning process combines photolithography with a self-alignment process, allowing for the creation of patterns with, for example, a pitch that is less than that obtained using a single direct photolithography approach. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structures 20.

[0036] As Figure 2A shown, two fin structures 20 extending in the Y direction are arranged next to each other in the X direction. However, the number of fin structures is not limited to two. The number can be one, three, four, or five or more. Additionally, one of a plurality of dummy fin structures can be arranged adjacent to both sides of the fin structures 20 to improve pattern fidelity in the patterning process. The width of the fin structures 20 is in some embodiments in a range of about 5 nm to about 40 nm, and in certain embodiments in a range of about 7 nm to about 15 nm. The height of the fin structures 20 is in some embodiments in a range of about 100 nm to about 300 nm, and in other embodiments in a range of about 50 nm to 100 nm. The spacing between the fin structures 20 is in some embodiments in a range of about 5 nm to about 80 nm, and in other embodiments in a range of about 7 nm to 15 nm. However, those skilled in the art will recognize that the dimensions and values described throughout the specification are merely examples, and can be varied to suit different scales of integrated circuits.

[0037] After the fin structures 20 are formed, an isolation insulating layer 30 is formed over the fin structures 20, as Figure 2B shown.

[0038] The isolation insulating layer 30 includes one or more layers of insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride, formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, a dielectric material other than silicon oxide is deposited. As the name implies, the flowable dielectric material can "flow" during deposition to fill gaps or spaces with high aspect ratios. Typically, various chemical methods are added to the silicon-containing precursor to make the deposited film flow. In some embodiments, hydrogen-nitrogen bonds are added. Examples of flowable dielectric precursors, and in particular, flowable silicon oxide precursors, include silicates, siloxanes, methylsilsesquioxane (MSQ), hydrosilsesquioxane (HSQ), mixtures of MSQ and HSQ, perhydrosilazane (TCPS), perhydropolysilazane (PSZ), tetraethyl orthosilicate (TEOS), or silyl amines, such as trisilylamine (TSA). These, silicon oxide materials are formed in a multi-step process. After the flowable film is deposited, it is cured, and then annealed to remove undesirable elements to form silicon oxide. The flowable film can be doped with boron and / or phosphorous. In some embodiments, the isolation insulating layer 30 can be formed from one or more layers of spin-on glass (SOG), SiO, SiON, SiOCN, and / or fluorine-doped silicate glass (FSG).

[0039] After the isolation insulating layer 30 is formed over the fin structures 20, a planarization operation is performed to remove portions of the isolation insulating layer 30 and the mask layer (e.g., the pad oxide layer and the silicon nitride mask layer formed over the pads). The planarization operation can include chemical mechanical polishing (CMP) and / or a etch-back process. Then, the isolation insulating layer 30 is further removed so that an upper portion of the fin structures 20 that will become the channel layer is exposed, as shown in Figure 2B

[0040] In certain embodiments, the partial removal of the isolation insulating layer 30 is performed using a wet etching process, such as by immersing the substrate in hydrofluoric acid (HF). In another embodiment, the partial removal of the isolation insulating layer 30 is performed using a dry etching process. For example, a dry etching process using CHF3or BF3as the etching gas can be used.

[0041] After the isolation insulating layer 30 is formed, a thermal process, such as an annealing process, can be performed to improve the quality of the isolation insulating layer 30. In certain embodiments, the thermal process is performed by using rapid thermal annealing (RTA) at a temperature of about 900 °C to about 1050 °C for about 1.5 seconds to about 10 seconds in an inert gas environment, such as an N2, Ar, or He environment.

[0042] A dummy gate structure 40 is then formed over the partial fin structures 20, as shown in Figure 2C

[0043] ​​A dielectric layer and a polysilicon layer are formed over the isolation insulating layer 30 and the exposed fin structure 20, and then a patterning operation is performed to obtain a dummy gate structure including a dummy gate electrode layer 44 made of polysilicon and a dummy gate dielectric layer 42. In some embodiments, the patterning of the polysilicon layer is performed by using a hard mask including a silicon nitride layer and an oxide layer. The dummy gate dielectric layer 42 can be silicon oxide formed by CVD, PVD, ALD, e-beam evaporation, or other suitable process. In some embodiments, the dummy gate dielectric layer 42 includes one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. In some embodiments, the thickness of the dummy gate dielectric layer is in a range from about 1 nm to about 5 nm.

[0044] In some embodiments, the dummy gate electrode layer 44 is polysilicon doped with uniform or non-uniform doping. In this embodiment, the width of the dummy gate electrode layer 44 is in a range from about 30 nm to about 60 nm. In some embodiments, the thickness of the dummy gate electrode layer is in a range from about 30 nm to about 50 nm. Additionally, one of the plurality of dummy gate structures can be disposed adjacent to both sides of the dummy gate structure 40 to improve pattern fidelity in the patterning process. In some embodiments, the width of the dummy gate structure 40 is in a range from about 5 nm to about 40 nm, and in certain embodiments, in a range from about 7 nm to about 15 nm.

[0045] Further, as shown in FIG. 4B, a dummy gate structure 40 is formed over the isolation insulating layer 30 and the exposed fin structure 20. The dummy gate structure 40 includes a dummy gate dielectric layer 42 and a dummy gate electrode layer 44. In some embodiments, the dummy gate dielectric layer 42 is formed by CVD, PVD, ALD, e-beam evaporation, or other suitable process. In some embodiments, the dummy gate dielectric layer 42 includes one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. In some embodiments, the thickness of the dummy gate dielectric layer is in a range from about 1 nm to about 5 nm. Figure 2C and Figure 2D As shown in FIG. 4B, a dummy gate structure 40 is formed over the isolation insulating layer 30 and the exposed fin structure 20. The dummy gate structure 40 includes a dummy gate dielectric layer 42 and a dummy gate electrode layer 44. In some embodiments, the dummy gate dielectric layer 42 is formed by CVD, PVD, ALD, e-beam evaporation, or other suitable process. In some embodiments, the dummy gate dielectric layer 42 includes one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. In some embodiments, the thickness of the dummy gate dielectric layer is in a range from about 1 nm to about 5 nm. Figure 2D is a cross-section on the y-x plane. An insulating material layer for the sidewall spacer 46 is formed over the dummy gate structure 40. The insulating material layer is deposited in a conformal manner such that it is formed to have substantially equal thicknesses on vertical surfaces, such as sidewalls, horizontal surfaces, and top of the dummy gate structure 40, respectively. In some embodiments, the thickness of the insulating material layer is in a range from about 5 nm to about 20 nm. The insulating material layer includes one or more of SiN, SiON, and SiCN, or any other suitable dielectric material. The insulating material layer can be formed by ALD or CVD or any other suitable method. Next, the bottom of the insulating material layer is removed by anisotropic etching, thereby forming the gate sidewall spacer 46. In some embodiments, the sidewall spacer 46 includes two to four layers of different insulating materials. In some embodiments, a portion of the dummy gate dielectric layer 42 is disposed between the sidewall spacer 46 and the isolation insulating layer 30. In other embodiments, no portion of the dummy gate dielectric layer 42 is disposed between the sidewall spacer 46 and the isolation insulating layer 30.

[0046] Subsequently, in some embodiments, the source / drain regions of the fin structure 20 not covered by the dummy gate structure 40 are etched (recessed) to form source / drain trenches. After forming the source / drain trenches, one or more source / drain epitaxial layers 60 are formed in the source / drain trenches (see...). Figure 1B In some embodiments, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer are formed. In other embodiments, no groove is formed, and an epitaxial layer is formed over the fin structure.

[0047] In some embodiments, the first epitaxial layer comprises SiP or SiCP for n-type FinFETs and B-doped SiGe or Ge for p-type FinFETs. In some embodiments, the amount of P (phosphorus) in the first epitaxial layer is between about 1 × 10⁻⁶. 18 atoms / cm 3 To approximately 1×10 20 atoms / cm 3 Within the range of [specific parameters]. In some embodiments, the thickness of the first epitaxial layer is in the range of about 5 nm to 20 nm, and in other embodiments it is in the range of about 5 nm to about 15 nm. When the first epitaxial layer is SiGe, in some embodiments the amount of Ge is about 25 atomic% to about 32 atomic%, and in other embodiments it is about 28 atomic% to about 30 atomic%. In some embodiments, the second epitaxial layer comprises SiP or SiCP for n-type FinFET and B-doped SiGe for p-type FinFET. In some embodiments, the amount of phosphorus in the second epitaxial layer is higher than that in the first epitaxial layer, and is between about 1 × 10 [specific parameters]. 20 atoms / cm 3 Approximately 2×10 20 atoms / cm 3 Within the range of [specific range]. In this embodiment, the thickness of the second epitaxial layer is between about 20 nm and 40 nm, or between about 25 nm and about 35 nm in other embodiments. When the second epitaxial layer is SiGe, in some embodiments, the amount of Ge is between about 35 atomic% and about 55 atomic%, in other embodiments it is between about 41 atomic% and about 46 atomic%. In some embodiments, the third epitaxial layer comprises a SiP epitaxial layer. The third epitaxial layer is a sacrificial layer for forming silicides in the source / drain. In some embodiments, the amount of phosphorus in the third epitaxial layer is less than the amount of phosphorus in the second epitaxial layer, and is between about 1 × 10 [specific values]. 18 atoms / cm 3 To approximately 1×10 21 atoms / cm 3 Within the range. When the third epitaxial layer is SiGe, in some embodiments the amount of Ge is less than about 20 atomic%, and in other embodiments the amount of Ge is less than about 1 atomic% to about 18 atomic%.

[0048] In at least one embodiment, the epitaxial layer 60 is epitaxially grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition, or any other suitable method. The LPCVD process is performed at a temperature of about 400 to 850 °C and a pressure of about 1 to 200 Torr using a silicon source gas such as SiH4, Si2H6, or Si3H8; a germanium source gas such as GeH4or G2H6; a carbon source gas such as CH4or SiH3CH3; and a phosphorous source gas such as PH3.

[0049] Then, as shown in Figure 2C and Figure 2D , an interlayer dielectric (ILD) layer 50 is formed over the S / D epitaxial layer 60 and the dummy gate structure 40. The material for the ILD layer 50 includes compounds such as Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 50.

[0050] After the ILD layer 50 is formed, a planarization operation such as CMP is performed, thereby exposing the top of the dummy gate electrode layer 44, as shown in Figure 2C and Figure 2D In some embodiments, a contact etch stop layer such as a silicon nitride layer or a silicon oxynitride layer is formed prior to the formation of the ILD layer 50.

[0051] Then, the dummy gate electrode layer 44 and the dummy gate dielectric layer 42 are removed, thereby forming gate spacers 47 as shown in Figure 2E and Figure 2F . Figure 2F is a cross-section on the y-x plane. Plasma dry etching and / or wet etching can be used to remove the dummy gate structure. When the dummy gate electrode layer 44 is polysilicon and the ILD layer 40 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the dummy gate electrode layer 44. Thereafter, plasma dry etching and / or wet etching is used to remove the dummy gate dielectric layer 42.

[0052] Figure 3A The structure after the channel region of the fin structure 20 is exposed in the gate spacers 47 is shown. In Figures 3A to 3F , the sidewall spacers 46 and the ILD layer 50 are omitted.

[0053] As shown in Figure 3B , at S301 of Figure 3G , an interface layer 81 is formed on the fin structure 20, and at Figure 3GAt S303, a gate dielectric layer 82 is formed on the interface layer 81. In some embodiments, the interface layer is formed by chemical oxidation. In some embodiments, the interface layer 81 comprises one of silicon oxide, silicon nitride, and silicon germanium oxide. In some embodiments, when the channel is made of Si, the interface layer is a silicon oxide layer 81N, and when the channel is made of SiGe, the interface layer is a silicon germanium oxide layer 81P (see...). Figure 4A In some embodiments, the thickness of the interface layer 81 ranges from about 0.6 nm to about 2 nm. In some embodiments, the gate dielectric layer 82 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, La2O3, HfO2-La2O3, Y2O3, Dy2O3, Sc2O3, MgO, or other suitable high-k dielectric materials and / or combinations thereof. The gate dielectric layer 82 may be formed by CVD, ALD, or any suitable method. In one embodiment, a highly conformal deposition process such as ALD is used to form the gate dielectric layer 82 to ensure that a gate dielectric layer with a uniform thickness is formed around each channel layer. In one embodiment, the thickness of the gate dielectric layer 82 is in the range of about 1 nm to about 30 nm. In some embodiments, one or more high-k dipole layers are formed on the gate dielectric layer 82 as described below. In some embodiments, an annealing operation is performed after the formation of the dipole layer. Furthermore, in some embodiments, a cleaning operation is performed to remove any residues of the dipole layer generated during the patterning operation of the dipole layer.

[0054] Then, as Figure 3C As shown, in Figure 3G A first conductive layer 83 is formed at position S305. In some embodiments, the first conductive layer 83 may be formed by CVD, ALD, or any suitable method. In some embodiments, the first conductive layer 83 is made of TiN or TiSiN. In some embodiments, the first conductive layer 83 is not formed.

[0055] In some embodiments, Figure 3GAt S307, after forming the first conductive layer 83, a first anneal operation is performed at a temperature of 600 °C to about 950 °C for about 1 nsec (spike anneal, such as laser anneal and / or isothermal anneal) to about 360 sec in some embodiments. The first anneal can help to densify the gate dielectric layer 82 and incorporate nitrogen into the gate dielectric layer 82. The nitrogen helps to passivate oxygen vacancies, reduce leakage, and improve device reliability. The first anneal can also help to form a stable mixed layer, which helps to provide a stable platform for subsequent deposition of a metal gate film onto the dielectric layer. When the temperature is too high, the first anneal can cause crystallization and grain boundaries to form in the high-k gate dielectric layer 82, which affects the leakage performance and regrowth of the interface layer 81, thereby reducing device speed. Conversely, when the temperature is too low, the first anneal can not provide sufficient densification and / or nitridation in the high-k gate dielectric layer and cause instability / variation in the device in subsequent metal gate deposition processes. In some embodiments, when the first conductive layer 83 is not formed, no anneal operation is performed at this stage. In some embodiments, the first conductive layer 83 is formed, then the anneal operation is performed, and after that the first conductive layer 83 is removed by a wet etch process.

[0056] In some embodiments, the stack structure including the interface layer 81, the gate dielectric layer 82, and the first conductive layer 83 is immersed in a fluorine-containing gas (e.g., F2 and / or NF3) at a temperature of about room temperature (25 °C) to about 550 °C for about 4 seconds to about 15 minutes in some embodiments. The incorporation of fluorine helps to improve work function tuning, reduce PMOS device V toxide, reducing leakage and dangling bonds in the gate dielectric layer. Thereafter, a capping layer made of, for example, crystalline, poly- or amorphous silicon is formed over the first conductive layer 83, and a second anneal operation is performed at a temperature of about 550 °C to about 1300 °C for about 1 nsec (spike anneal, such as laser anneal) to 360 sec in some embodiments. In some embodiments, the anneal temperature is 900 °C to 1100 °C. In some embodiments, this results in diffusion of fluorine into the capping layer, the first conductive layer 83 and the gate dielectric layer 82. After the second anneal operation, the capping layer is removed. The second anneal with a silicon capping layer also helps to improve the quality of the gate dielectric layer 82. The gate dielectric layer, such as a high-k dielectric layer, is formed at a relatively low temperature to avoid crystallization and grain boundary formation, while the metal gate film is deposited at a relatively high temperature. Therefore, it is desirable to make the high-k dielectric layer more thermally stable before the metal gate is deposited. The second anneal with a capping layer at a temperature range as described above can densify and thermally stabilize the high-k dielectric layer without any thermal oxide reversion during the metal gate deposition. The second anneal also helps to thermally diffuse fluorine from the outer layer (e.g., capping layer) into the first conductive layer 83, the gate dielectric layer 82 and the interface layer 81. The capping layer serves to protect the gate dielectric layer 82 and the first conductive layer 83 from undesirable oxidation damage and to isolate these films from the anneal atmosphere. After the gate dielectric is thermally stabilized, the capping layer is no longer needed in the final device structure and is therefore removed.

[0057] In other embodiments, the fluorine soak operation that accompanies the formation of the Si capping layer and the second anneal operation is not performed.

[0058] Subsequently, at S309 of the method 300, a second conductive layer is formed as a first barrier layer 84, and then at S311 of the method 300, one or more WFM layers 86 are formed. In some embodiments, the second conductive layer 84 is made of TaN and serves as an etch stop barrier layer. The barrier layer 86 serves as a wet etch stop layer during subsequent patterning to form p-type and n-type WFM layers that form multiple Vt devices. In some embodiments, the second conductive layer 84 is not formed. Figure 3G Figure 3G At S313 of the method 300, a metal gate layer including an adhesive layer 87 and a bulk metal layer (gate electrode layer) 88 is formed over the work function adjustment layer 86. Figure 3G

[0059] In some embodiments, the second conductive layer 84 is made of TaN and serves as an etch stop barrier layer. The barrier layer 86 serves as a wet etch stop layer during subsequent patterning to form p-type and n-type WFM layers that form multiple Vt devices. In some embodiments, the second conductive layer 84 is not formed.

[0060] ​​The work function material (WFM) layer 86 can be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the WFM layer can be formed separately for n-channel FETs and p-channel FETs that can use different metal layers. The gate electrode layer (bulk metal layer) 88 and the glue layer 87 can be formed by CVD, ALD, electroplating, or other suitable methods. When the first and second conductive layers are not formed, the WFM layer 86 is formed directly on the gate dielectric layer 82. In some embodiments, the first conductive layer 83 is formed and removed after the anneal operation S307, after which the second conductive layer is not formed and the WFM layer 86 is formed directly on the gate dielectric layer 82.

[0061] Figure 4A A cross-sectional view of a gate structure of FETs with different threshold voltages is shown, according to an embodiment of the application. Figure 4B and Figure 4C Various work function material layers for multiple FETs with different threshold voltages are shown, according to an embodiment of the application.

[0062] In some embodiments, the semiconductor device includes a first n-type FET N1 having a WFM layer structure WF1, a second n-type FET N2 having a WFM layer structure WF2, a third n-type FET N3 having a WFM layer structure WF3, a first p-type FET P1 having a WFM layer structure WF3, a second p-type FET P2 having a WFM layer structure WF2, and a third p-type FET P3 having a WFM layer structure WF1. The absolute value of the threshold voltage of the first n-type FET N1 (ultra-low voltage FET) is less than the threshold voltage of the second n-type FET N2 (low voltage FET), and the absolute value of the threshold voltage of the second n-type FET N2 is less than the threshold voltage of the third n-type FET N3 (standard voltage FET). Similarly, the absolute value of the threshold voltage of the first n-type FET P1 (ultra-low voltage FET) is less than the threshold voltage of the second p-type FET P2 (low voltage FET), and the absolute value of the threshold voltage of the second p-type FET P2 is less than the threshold voltage of the third p-type FET P3 (standard voltage FET). The threshold voltage in the absolute value of the first n-type FET N1 is designed to have the same threshold voltage as the threshold voltage in the absolute value of the first p-type FET P1, the threshold voltage in the absolute value of the second n-type FET N2 is designed to have the same threshold voltage as the second p-type FET P2 in the absolute value, and the threshold voltage in the absolute value of the third n-type FET N3 is designed to have the same threshold voltage as the third p-type FET P3 in the absolute value.

[0063] In some embodiments, WFM layer structure WF1 includes a first WFM layer 100, WFM layer structure WF2 includes a second WFM layer 89-2 closer to the gate dielectric layer 82 and the first WFM layer 100, and third WFM layer structure WF3 includes a third WFM layer 89-1, a second WFM layer 89-2 and the first WFM layer 100 closer to the gate dielectric layer 82, as shown below. Figure 4A As shown.

[0064] exist Figure 4B In this embodiment, the semiconductor device includes three different threshold voltage levels. In other embodiments, such as... Figure 4C As shown, more than three, for example eight, different threshold voltages are used for both n-type and p-type FETs. Figure 4C In this process, not only the WFM layer structure is adjusted, but also the configuration of the gate dielectric layers 82, HK1, HK2, and HK3 (e.g., material, thickness, etc.), is adjusted to obtain the desired threshold voltage. HK1, HK2, and HK3 are composed of different materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, La2O3, HfO2-La2O3, Y2O3, Dy2O3, Sc2O3, MgO, or other suitable high-k dielectric materials and / or combinations thereof. In some embodiments, HK1, HK2, and HK3 are composed of high-k dielectrics with different concentrations of rare earth metals and / or group III dopants (such as La, Al, Mg, Sc, Dy, Y, Ti, Lu, Sr, etc.). In some embodiments, HK3 is composed of HfOx, HK2 is composed of HfLaOx (or HfYOx, HfLuOx, HfSrOx, HfScOx, HfDyOx), and HK1 is composed of HfLaOx (or HfYOx, HfLuOx, HfSrOx, HfScOx, HfDyOx), such that the amount of La (or Y, Lu, Sr, Sc, Dy) in HK1 is higher than that in HK2. In some embodiments, HK1 is composed of HfOx, HK2 is composed of HfAlOx (or HfZrOx, HfTiOx), and HK3 is composed of HfAlOx (or HfZrOx, HfTiOx), such that the amount of Al (or Zr, Ti) in HK3 is higher than that in HK2. In some embodiments, HK2 is composed of HfOx, HK1 is composed of HfLaOx (or HfYOx, HfLuOx, HfSrOx, HfScOx, HfDyOx), and HK3 is composed of HfAlOx (or HfZrOx, HfTiOx). In some embodiments, the thicknesses of HK1, HK2, and HK3 are in the range of about 0.6 nm to about 30 nm. In some embodiments, more than three different high-k dielectric films are used.

[0065] In CMOS devices, gate electrodes are typically used for both n-type and p-type FETs (shared by them), and thus n-type and p-type FETs with substantially the same threshold voltage are selected. For example, a CMOS device with an ultra-low voltage FET includes a first n-type FET N1 and a first p-type FET P1. Figure 5A This shows a plan view (layout) of such a CMOS device.

[0066] like Figure 5A As shown, the gate electrode 80 is disposed above one or more fin structures 20 (channel regions). In some embodiments, each of the n-type FET (NFET) and p-type FET (PFET) includes two fin structures. In other embodiments, the number of fin structures for each FET is one or three or more (e.g., up to 10). Figure 5B Showing the corresponding Figure 5A A cross-sectional view of area A1, and Figure 5C Show Figure 5B A magnified view of area B1. Figure 5B and Figure 5C In the figure, the adhesive layer 87 and the bulk metal layer 88 are omitted (shown as dashed lines).

[0067] As described above, the n-type FET (NFET, e.g., N1) has a WFM layer structure WF1 (only) with a first WFM layer 100, and the p-type FET (e.g., P1) has a second WFM layer and a third WFM layer (89-2 and 89-1, in...). Figure 5B The WFM layer structure WF3 is collectively referred to as 89) and the first WFM layer 100. Therefore, the second and third WFM layers 89 are discontinuously formed at the boundary MB between the n-type FET (NFET) and the p-type FET (PFET).

[0068] Similarly, in Figures 6A to 6C In this context, CMOS devices with a threshold voltage Vt3 include n-type FETs with a WFM layer structure WF2 and p-type FETs with a WFM layer structure WF3 (see [link to documentation]). Figure 4C ). Figure 6B Showing the corresponding Figure 6A A cross-sectional view of area A2, and Figure 6C Show Figure 6B A magnified view of area B2. Figure 6B and Figure 6C In the original text, the adhesive layer 87 and the bulk metal layer 88 are omitted.

[0069] like Figure 6AAs shown, the gate electrode 80 is disposed over one or more fin structures 20 (channel regions). As noted above, the n-type FET NFET has a WFM layer structure WF2 with a first WFM layer 100 and a second WFM layer 89-2, and the p-type FET PFET has a WFM layer structure WF3 with a second WFM layer and a third WFM layer, and the first WFM layer 100. Thus, at the boundary MB between the n-type FET NFET and the p-type FET PFET, the third WFM layer 89-1 is discontinuously formed.

[0070] In some embodiments, the thickness of the gate dielectric layer 82 on the top (channel region) of the fin structure and on the sides of the fin structure are substantially equal to each other (e.g., differ by less than about 0.2 nm, or vary by about 0.5% to about 5%). In some embodiments, the composition of the gate dielectric layer 82 on the top (channel region) of the fin structure and on the sides of the fin structure are substantially equal to each other (e.g., vary by about 0.5% to about 5% in O / Hf ratio). In some embodiments, the thickness of the conductive layer (e.g., WFM layer) on the top of the fin structure and on the sides of the fin structure are substantially equal to each other (e.g., differ by less than about 0.2 nm, or vary by about 0.5% to about 5%). In some embodiments, the thickness of the conductive layer (e.g., WFM layer) on one side of the fin structure facing the metal boundary and on the other side of the fin structure are substantially equal to each other (e.g., differ by less than about 0.2 nm, or vary by about 0.5% to about 5%). In some embodiments, the thickness of the gate dielectric layer 82 on the fin structure and the thickness of the sidewall at the metal boundary are substantially equal to each other (e.g., differ by less than about 0.3 nm, or vary by about 0.5% to about 7.5%). In some embodiments, the thickness of the conductive layer (e.g., WFM layer) on the fin structure and the thickness of the sidewall at the metal boundary are substantially equal to each other (e.g., differ by less than about 0.3 nm, or vary by about 0.5% to about 7.5%). In some embodiments, the surface roughness Ra of the conductive layer (e.g., WFM layer) is greater than 0 nm and less than 0.8 nm, and the surface roughness of the gate dielectric layer is greater than 0 nm and less than about 0.7 nm.

[0071] In forming the gate structures for different Vt devices (as well as for different conductivity type devices), various patterning operations are performed. In the photolithography operation, a bottom anti-reflective layer (BARC) is used with the photoresist layer.

[0072] However, BARC layers made of organic materials may exhibit low adhesion strength to underlying layers such as high-k dipole dielectrics or work function modulating materials. Therefore, at metal boundaries, wet chemicals used in etching operations can penetrate into the interface between the BARC layer and the underlying fins, damaging the underlying layers. Furthermore, plasma processes used for patterning and removing the BARC layer can also damage the underlying layers and fin structures. Additionally, wet chemicals used during cleaning processes or moisture in the atmosphere can damage the high-k dipole layer and the WFM layer. In this invention, an adhesion reinforcement layer is employed beneath the BARC layer, as described below.

[0073] Figure 7 The process flow for manufacturing a semiconductor device according to an embodiment of the present invention is shown, and Figures 8A to 8F A cross-sectional view is shown. It can be considered that in a sequential manufacturing process, [the following can be achieved]... Figure 7 and Figures 8A to 8F One or more additional operations are provided before, during, and after the stages shown, and for additional embodiments of the method, some operations described below may be substituted or eliminated. The order of operations / processes can be interchanged. The following embodiments may employ... Figures 1A to 8B The embodiments described herein include materials, configurations, dimensions, processes, and / or operations, and their detailed descriptions may be omitted. Although Figures 8A to 8F Showing about Figure 7 and Figure 8A The WFM layer 100 is explained, but Figure 8C , Figure 8E and Figure 8B Any of the structures shown can be used as WFM layer 100.

[0074] exist Figure 7 In S701, the channel regions of the exposed fin structure are used for the first n-type FET N1, the second n-type FET N2, the third n-type FET N3, the first p-type FET P1, the second p-type FET P2, and the third p-type FET P3. In some embodiments, the channel regions for the n-type FETs are made of Si, and the channel regions for the p-type FETs are made of SiGe.

[0075] exist Figure 7 At S702, an interface layer 81N and 81P are formed on each channel region 20 using a chemical oxidation method. In some embodiments, when the channel is made of Si, the interface layer is a silicon oxide layer 81N, and when the channel is made of SiGe, the interface layer is a silicon germanium oxide layer 81P. Figure 7 At S703, a gate dielectric layer (e.g., a high-k gate dielectric layer) 82 is formed on the interface layer 81N / 81P. In some embodiments, different gate dielectric layers are formed at different FET devices. In some embodiments, at Figure 7At S704, a protective layer 83 is formed on the gate dielectric layer 82, followed by an anneal operation at S705, and at Figure 7 S706, a barrier layer 84 is formed on the protective layer 83. In other embodiments, the protective and barrier layers are not formed. In other embodiments, the protective layer is formed, the anneal is performed, and then the protective layer is removed and the barrier layer is not formed.

[0076] At S707, a third WFM layer 89-1 is formed on the gate dielectric layer 82, as shown in Figure 7 At S708, a first patterning operation is performed to remove the third WFM layer 89-1 from the regions for the first n-type FET N1, the second n-type FET N2, the second p-type FET P2, and the third p-type FET P3. In some embodiments, a bottom anti-reflective coating (BARC) layer 200 made of an organic material is formed on the third WFM layer 89-1, and a photoresist layer 205 is formed on the bottom anti-reflective coating layer 200, as shown in Figure 8A The photoresist layer 205 is patterned by using one or more photolithography operations to expose the bottom anti-reflective coating layer 200 at the regions for the first and second n-type FETs and the second and third p-type FETs. The exposed bottom anti-reflective coating layer 200 is then removed by one or more plasma etching operations to expose the third WFM layer 89-1 at the regions for the first and second n-type FETs and the second and third p-type FETs, as shown in

[0077] At S709, a second patterning operation is performed to remove the third WFM layer 89-1 from the regions for the first n-type FET N1 and the second p-type FET P2. In some embodiments, a BARC layer 200 made of an organic material is formed on the third WFM layer 89-1, and a photoresist layer 205 is formed on the BARC layer 200, as shown in Figure 7 The photoresist layer 205 is patterned by using one or more photolithography operations to expose the BARC layer 200 at the regions for the first n-type FET N1 and the second p-type FET P2. The exposed BARC layer 200 is then removed by one or more plasma etching operations to expose the third WFM layer 89-1 at the regions for the first n-type FET N1 and the second p-type FET P2, as shown in Figure 8A Figure 8A Subsequently, the third WFM layer 89-1 in the first and second n-type FETs and the second and third p-type FETs is removed by appropriate etching operations, as shown in

[0078] At S710, a fourth WFM layer 89-2 is formed on the gate dielectric layer 82, as shown in Figure 8B ​As shown. In some embodiments, the etching operation includes a wet etching operation. The etching solution (etchant) includes an aqueous solution of HCl and H2O2, an aqueous solution of a combination of NH4OH and H2O2, an aqueous solution of a combination of HCl, NH4OH and H2O2, an aqueous solution of HF, NH4OH and H2O2, and / or an aqueous solution of H3PO4 and H2O2.

[0079] exist Figure 7 At S709, a second WFM layer 89-2 is formed on the gate dielectric layer 82 in the regions for the first and second n-type FETs and the second and third p-type FETs, and on the third WFM layer 89-1 in the regions for the third n-type FET and the first p-type FET, as shown. Figure 8C As shown. The second WFM layer 89-2 comprises WN, WCN, W, Ru, TiN, or TiSiN formed by, for example, CVD, ALD, PVD, or any other suitable film formation method. In some embodiments, the thickness of the second WFM layer 89-2 is in the range of about 0.5 nm to about 20 nm, and in other embodiments it is in the range of about 1 nm to about 10 nm. In some embodiments, the second and third WFM layers are made of the same material.

[0080] exist Figure 7 At S710, a second patterning operation is performed to remove the second WFM layer 89-2 from the region used for the first n-type FET N1 and the third p-type FET P3. The second patterning operation is substantially the same as or similar to the first patterning operation. Figure 8D The structure after removing the second WFM layer 89-2 from the region of the first n-type FET N1 and the third p-type FET P3 is shown.

[0081] exist Figure 7 At S711, a first WFM layer 100 is formed on the gate dielectric layer 82 in the region for the first n-type FET and the third p-type FET, and on the second WFM layer 89-2 in the region for the second and third n-type FETs and the first and second p-type FETs, as shown. Figure 8E As shown. In some embodiments, a first WFM layer 100 is formed, for example, by an ALD. In some embodiments, the thickness of the first WFM layer 100 is in the range of about 0.6 nm to about 40 nm, and in other embodiments it is in the range of about 1 nm to about 20 nm. In some embodiments, the thickness of the first WFM layer 100 is greater than that of each of the second and third WFM layers.

[0082] exist Figure 7At point S712, a protective layer 110 is formed on the first WFM layer 100. In some embodiments, the protective layer 110 includes one or more metal nitride layers, such as TiN, TaN, TaTiN, WN, TiSiN, WCN, and MoN. In other embodiments, no protective layer is formed.

[0083] exist Figure 7 At S713, an adhesive layer 87 is formed, and then... Figure 7 A bulk gate metal layer 88 is formed at S714, such as Figure 8F As shown. In some embodiments, the adhesive layer 87 is made of TiN, Ti, and / or Co. In some embodiments, the body metal layer 88 is made of W, Al, Co, or any other suitable metallic material.

[0084] like Figures 8A to 8F As shown, a bottom antireflective coating (BARC) layer 200 is used to pattern underlying layers such as a WFM layer. In some embodiments, the BARC layer 200 is made of an organic material and has low adhesion strength to metal nitride layers such as TiN, TaN, TaTiN, WN, TiSiN, WCN, and MoN or Ru, which are used as the second WFM layer 89-1 and the third WFM layer 89-2. Furthermore, the BARC layer 200 has low adhesion strength to TiAl, TiAlC, TaAl, and TaAlC, which are used as the first WFM layer 100. According to an embodiment of the invention, an adhesion reinforcement layer is used below the BARC layer 200.

[0085] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G and Figure 9H Cross-sectional views are shown of various stages of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. It can be understood that in the sequential manufacturing process, [the following steps can be taken]. Figures 9A to 9H One or more additional operations are provided before, during, and after the stages shown, and for additional embodiments of the method, some operations described below may be substituted or eliminated. The order of operations / processes can be interchanged. The following embodiments may employ... Figures 1A to 8F The embodiments describe the materials, configurations, dimensions, processes and / or operations, and their detailed descriptions may be omitted.

[0086] exist Figures 9A to 9HIn some embodiments, regions A and B are formed in a single continuous region across the metal border MB, and a common gate electrode is formed over the n-type and p-type regions in a subsequent manufacturing operation. In some embodiments, region A is used for one or more n-type FETs, and region B is used for one or more p-type FETs. In some embodiments, region A is used for one or more p-type FETs, and region B is used for one or more n-type FETs.

[0087] As shown in FIG. 5A, a WFM layer 89 is formed over the gate dielectric layer 82. In some embodiments, the WFM layer 89 is formed over the adhesion enhancement layer 500. In some embodiments, the WFM layer 89 is formed over the BARC layer 88. In some embodiments, the WFM layer 89 is formed over the BARC layer 88 and the adhesion enhancement layer 500. In some embodiments, the WFM layer 89 is formed over the BARC layer 88 and the adhesion enhancement layer 500, and the adhesion enhancement layer 500 is formed over the BARC layer 88. Figure 9A As shown in FIG. 5A, a WFM layer 89 is formed over the gate dielectric layer 82. In some embodiments, the WFM layer 89 is formed over the adhesion enhancement layer 500. In some embodiments, the WFM layer 89 is formed over the BARC layer 88. In some embodiments, the WFM layer 89 is formed over the BARC layer 88 and the adhesion enhancement layer 500. In some embodiments, the WFM layer 89 is formed over the BARC layer 88 and the adhesion enhancement layer 500, and the adhesion enhancement layer 500 is formed over the BARC layer 88. In some embodiments, the adhesion enhancement layer 500 has a higher adhesion strength to the BARC layer than the WFM layer 89. In some embodiments, the adhesion enhancement layer 500 is a nitrogen-rich layer having a higher nitrogen concentration than the WFM layer 89. In some embodiments, the WFM layer 89 is nitrogen-free (does not contain nitrogen) or contains nitrogen in an amount less than about 50 atomic %. In some embodiments, the adhesion enhancement layer 500 contains nitrogen in a range of 50 atomic % to 80 atomic %, and in other embodiments, the adhesion enhancement layer 500 contains nitrogen in a range of 55 atomic % to 75 atomic %. The adhesion enhancement layer 500 includes one or more of TiNx (where x is about 1.1 to 1.5), TiSiN, silicon nitride (SiN), AIN, aluminum oxide (AIOx or AI2O3), cobalt oxide (CoOx), or titanium oxide (TiOx or TiO2). In some embodiments, the TiNx layer includes Ti in an amount of about 22 atomic % to about 35 atomic % and N in an amount of about 24 atomic % to about 51 atomic % (remainder is C and / or O). In some embodiments, the adhesion enhancement layer 500 has a thickness in a range of about 0.2 nm to about 2 nm, and in other embodiments, in a range of about 0.3 nm to about 1.5 nm. If the thickness exceeds this range, the adhesion enhancement layer 500 can affect the work function, and if the thickness is less than this range, the adhesion enhancement can be insufficient. In some embodiments, the adhesion enhancement layer 500 includes a combination of AI2O3 and AIN layers. In some embodiments, the adhesion enhancement layer 500 includes a combination of AI2O3 and TiN layers. In some embodiments, the adhesion enhancement layer 500 includes HMDS, a Ti-based primer, or a Si-based organic compound (e.g., a diphenylsilanediol-based compound). When a Si-based organic material is used as the adhesion enhancement layer 500, the adhesion enhancement layer 500 is subsequently removed, but in some embodiments, some silicon remains on the WFM layer in an amount greater than about 0.5 atomic % to less than about 11 atomic %, and carbon also remains in an amount greater than about 0.1 % to less than about 1.5 %.

[0088] In some embodiments, the adhesion enhancement layer 500 is formed by CVD, ALD, or any other suitable film formation method. In other embodiments, the adhesion enhancement layer 500 is formed by nitridation of the underlying layer (WFM layer 89). In some embodiments, N2and / or NH3is used as the nitrogen source gas. In some embodiments, a plasma is used. When the adhesion enhancement layer 500 is formed by nitridation of the underlying layer, the adhesion enhancement layer 500 has a higher nitrogen concentration than the underlying layer (WFM layer 89).

[0089] Then, as shown in Figure 9B the adhesion enhancement layer in both region A and region B. In some embodiments, the BARC layer 200 has a thickness in a range from about 50 nm to about 2000 nm, and in other embodiments, in a range from about 100 nm to about 200 nm.

[0090] Next, the photoresist layer 205 is patterned and removed from region A by using one or more photolithography operations, as shown in Figure 9C Furthermore, the BARC layer 200 is patterned and removed from region A by using one or more etching operations (e.g., dry etching) by etching the patterned photoresist layer 205 as an etch mask, as shown in Figure 9D

[0091] Then, as shown in Figure 9E ​As shown, the adhesion enhancement layer 500 and the WFM layer 89 are etched from region A. In some embodiments, wet etching is used to remove the adhesion enhancement layer 500 and the WFM layer 89 from region A. The adhesion layer 500 improves the adhesion strength between the WFM layer 89 and the BARC layer 200, prevents the BARC layer from penetrating into region B from the metal boundary across region A and region B via the interface below the BARC layer, and also inhibits etching below the BARC layer 200 in region B. Subsequently, the photoresist layer 205 and the BARC layer 200 are removed from region B. In some embodiments, a plasma ashing operation is performed to remove the BARC layer 200 from region B, and a wet ashing cleaning using a mixture of one or more of water, HF, HCl, and NH4OH is performed to remove BARC residue. Because the adhesion enhancement layer 500 covers the WFM layer 89 in region B, the loss of the WFM layer from the top of the fin structure is prevented. Due to its good bonding, the BARC layer 200 can be conformally deposited on complex structures, thus effectively protecting the gate dielectric layer and fin structure during plasma etching and ashing processes. It should be noted that in the absence of the adhesion enhancement layer 500, the adhesion between the BARC layer 200 and the WFM layer 89 may be insufficient at region B, and wet chemicals (used during the removal of the WFM layer 89 from region A) may penetrate through the gap at this poorly bonded BARC-WFM layer interface, cross the metal boundary MB, and enter region B, potentially causing unwanted damage or etching of the WFM layer 89 from region B.

[0092] Subsequently, as Figure 9G As shown, in Figure 9F A WFM layer 100 is formed on top of the structure. In some embodiments, instead of the WFM layer 100, another WFM layer 89 (89-2) with the same or similar composition as the WFM layer 89 (89-1) is formed.

[0093] In other embodiments, the adhesive reinforcement layer 500 is removed, and then as follows: Figure 9H The WFM layer 100 is shown to be formed. Specifically, when the adhesive reinforcement layer 500 is made of an insulating material (SiN, AlO...) x CoO x or TiO x When it is made, remove the adhesive reinforcement layer 500.

[0094] like Figure 8A and Figure 8B As shown, the adhesive reinforcement layer 500 is used to pattern the WFM layer 89-1, such as... Figure 8C and Figure 8D As shown, the adhesive reinforcement layer 500 is also used to pattern the WFM layer 89-2. Furthermore, when patterning the WFM layer 100, an adhesive reinforcement layer is applied above the WFM layer 100.

[0095] Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E 、 Figure 10F 、 Figure 10G 、 Figure 10H and Figure 10I show cross-sectional views of various stages of a sequential fabrication process of a semiconductor device according to embodiments of the application. It is to be appreciated that one or more additional operations can be provided before, during, and after the stages shown in Figures 10A to 10H and that some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations / processes can be interchanged. Materials, configurations, dimensions, processes and / or operations described with respect to embodiments of Figures 1A to 9H may be employed in the following embodiments, and detailed descriptions thereof can be omitted.

[0096] As shown in Figure 10A , the semiconductor device includes three regions R1, R2 and R3, for example, for FETs with different threshold voltages. In some embodiments, two or three FETs are controlled by the same gate electrode (e.g., the gate electrode extends over two or three regions), and thus the two or three regions are formed contiguously. In other embodiments, the regions are formed separately.

[0097] In some embodiments, an adhesion enhancement layer is used to pattern the high-k gate dielectric layer. In some embodiments, the gate dielectric layer includes multiple layers having a base high-k dielectric layer 82 and one or more dipole high-k dielectric layers 182, 282 disposed on the base high-k dielectric layer 82. In some embodiments, the dipole high-k dielectric layer includes one of La2O3, Lu2O3, Sc2O3, SrO, ZrO2, Y2O3, D y O x , EuO x and Yb2O3. In some embodiments, the semiconductor device includes FETs with high-k dielectric layers, FETs with high-k dielectric layers and a dipole high-k dielectric layer on the high-k dielectric layer, and FETs with high-k dielectric layers and two dipole high-k dielectric layers on the high-k dielectric layer. These FETs formed thereby provide different threshold voltages. In some embodiments, after the anneal operation, an optional wet etch is performed to partially or completely remove the 182 and 282 layers. In some embodiments, after the anneal operation, the wet etch operation is not performed and the 182 and 282 layers are maintained in the gate stack of the final FET device.

[0098] In some embodiments, as shown in Figure 10AAs shown, a first high-k dipole layer 182 is formed above a high-k dielectric layer 82, and an adhesion reinforcement layer 510 is formed above the first dipole high-k dielectric layer 182. In some embodiments, the adhesion reinforcement layer has a higher adhesion strength to the BARC layer than the first high-k dipole layer 182. In some embodiments, the adhesion reinforcement layer 510 has a higher nitrogen concentration than the first high-k dipole layer 182.

[0099] In some embodiments, the adhesive reinforcement layer 510 includes TiN x (where x is about 1.1 to 1.5), one or more of TiSiN, SiN, AlN, and Al2O3. In some embodiments, the TiNx layer comprises about 22 atomic% to about 35 atomic% of Ti and about 24 atomic% to about 51 atomic% of N (the remainder being C and / or O). In some embodiments, the thickness of the adhesion reinforcement layer 510 is in the range of about 0.2 nm to about 2 nm, and in other embodiments it is in the range of about 0.3 nm to about 1.5 nm. In some embodiments, the adhesion reinforcement layer 510 comprises a combination of Al2O3 and AlN layers. In some embodiments, the adhesion reinforcement layer 510 comprises a combination of Al2O3 and TiN layers.

[0100] Then, as Figure 10B As shown, a BARC layer 202 and a photoresist layer 207 are formed over the adhesion enhancement layer. In some embodiments, the thickness of the BARC layer 202 is in the range of about 50 nm to about 2000 nm, and in other embodiments it is in the range of about 100 nm to about 200 nm.

[0101] Next, the photoresist layer 207 will be patterned using one or more photolithography operations, such as... Figure 10C As shown. Furthermore, the BARC layer 202 is patterned by using a patterned photoresist layer 205 as an etching mask through one or more etching operations (e.g., dry etching), as... Figure 10D As shown.

[0102] Then, as Figure 10EAs shown, the adhesive reinforcement layer 510 and the first dipole high-k dielectric layer 182 are etched from regions R1 and R2. In some embodiments, wet etching is used to remove the adhesive reinforcement layer 510 and the first dipole high-k dielectric layer 182 from regions R1 and R2. Since the adhesive layer 510 increases the adhesion strength between the first dipole high-k dielectric layer 182 and the BARC layer 202, it prevents the peeling of the BARC layer at the metal boundary between regions R3 and R2 or between regions R3 and R1, and also suppresses etching below the BARC layer 202 at region R3. It should be noted that in the absence of the adhesion reinforcement layer 510, the adhesion between the BARC layer 202 and the first dipole high-k dielectric layer 182 at region R3 may be insufficient, and wet chemicals (used during the removal of the high-k dielectric layer 182 from regions R1 and R2) may penetrate this poorly bonded BARC-first dipole high-k dielectric layer interface, cross the metal boundary into region R3, and may cause unnecessary damage or etching of the first dipole high-k dielectric layer 182 from region R3. Subsequently, the photoresist layer 207 and the BARC layer 202 are removed from region R3. In some embodiments, a plasma ashing operation is performed, followed by a wet cleaning operation to remove BARC residue from region R3. Because the adhesion reinforcement layer 510 covers the first dipole high-k dielectric layer 182 at region R3, any damage or loss to the first dipole high-k dielectric layer 182 on region R3 is prevented by atmospheric moisture, plasma from the ashing process, or wet cleaning process chemicals on top of the fin structure. It should be noted that, without the adhesive reinforcement layer 510, the dipole high-k dielectric layers 182, 282 are inherently highly hygroscopic and may therefore readily react with moisture and / or water during water-based wet cleaning (e.g., during ash cleaning processes). Moisture forms hydroxides (e.g., La(OH)3), which have a much lower k-value than oxides and thus degrade the k-value, speed, and / or performance of the FET device.

[0103] Furthermore, in some embodiments, such as Figure 10G As shown, a second dipole high-k dielectric layer 282 is formed. This is achieved by using, as... Figures 10B to 10F A similar technique is shown to pattern the second dipole high-k dielectric layer 282, such as... Figure 10H As shown. In the formation Figure 10H Following the structure shown, one or more work function modulating material layers and body gate electrode layers as described above are formed. In some embodiments, an annealing operation is performed at a temperature between 400°C and 700°C for about 2 seconds to about 100 seconds to introduce dipole dopant elements from dipole high-k dielectric layers 182, 282 into the substrate high-k dielectric layer 82 to form high-k dielectric layers 821 and 822 with different doping doses, such as... Figure 10IIn some embodiments, the dipole doping elements include one or more of La, Lu, Sc, Sr, Zr, Y, Dy, Eu, and Yb, which are included in the dipole high-k dielectric layers 182, 282. In some embodiments, the diffusion layers 821 and 822 are formed at a portion of the high-k dielectric layer 82, and in other embodiments, the high-k dielectric layer 82 is completely converted to the diffusion layers 821 and 822. The amount of dipole doping elements diffused into the gate dielectric layer 82 depends on the thickness and / or number of dipole high-k dielectric layers. In some embodiments, the FETs with a high-k dielectric layer and two dipole high-k dielectric layers on the high-k dielectric layer have the highest concentration of dopant elements than the FETs with a high-k dielectric layer and one dipole high-k dielectric layer, and the FETs with a high-k dielectric layer and no dipole high-k dielectric layer. In some embodiments, an optional wet etch is performed to partially or completely remove the remnants of the dipole layers 182 and 282 after the anneal operation. In some embodiments, the wet etch operation is not performed so that the dipole high-k dielectric layers 182, 282 remain in the final gate structure of the FET device.

[0104] In some embodiments, the adhesion enhancement layer 510 is removed, and in other embodiments, the adhesion enhancement layer 510 is not removed and remains as part of the gate dielectric layer.

[0105] Figure 11 A process flow for fabricating a semiconductor device in accordance with an embodiment of the present application is shown. Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 12E and Figure 12F Cross-sectional views of various stages in a sequential manufacturing process of a semiconductor device in accordance with an embodiment of the present application are shown. It is to be appreciated that one or more additional operations can be provided before, during, and after the stages shown, and that some operations described can be combined. The sequence of operations / processes can be altered with Figures 12A to 12F additional embodiments of the method. The order of the operations / processes can be interchanged. Materials, configurations, dimensions, processes, and / or operations described with respect to embodiments of Figures 1A to 10I may be employed in the following embodiments, and detailed descriptions thereof can be omitted.

[0106] In Figures 12A to 12E , three n-type FETs with different threshold voltages (N1’, N2’, and N3’) and three p-type FETs with different threshold voltages (P1’, P2’, and P3’) are provided. At S1101 of Figure 11 , similar to Figure 7S701, the channel regions of the fin structures are exposed for the first n-type FET N1', the second n-type FET N2', the third n-type FET N3', the first p-type FET P1', the second p-type FET P2', and the third p-type FET P3'. In some embodiments, the channel regions for the n-type FETs are made of Si, and the channel regions for the p-type FETs are made of SiGe.

[0107] At Figure 11 S1102, similar to Figure 7 S702, an interface layer 81N and 81P is formed on each channel region 20 using a chemical oxidation method. In Figure 11 S1103, similar to Figure 7 S703, a gate dielectric layer (e.g., a high-k gate dielectric layer) 82 is formed on the interface layer 81N / 81P.

[0108] At Figure 11 S1104, as Figure 12A illustrated, a first high-k dipole layer 182 is formed over the high-k gate dielectric layer 82, and at Figure 11 S1105, an adhesion enhancement layer 510 is formed over the first dipole high-k dielectric layer 182. Then, as Figure 12A illustrated, a BARC layer 200 and a photoresist layer 205 are formed and patterned to leave a patterned photoresist layer 205 and BARC layer 200 in regions N3' and P1'.

[0109] Then, as Figure 12B illustrated, the adhesion enhancement layer 510 and the first dipole layer 182 are removed by one or more etching operations. In addition, the photoresist layer 205, the BARC layer 200, and the adhesion enhancement layer 510 are removed from regions N3' and P1'. In some embodiments, the adhesion enhancement layer 510 is not removed from regions N3' and P1'. Next, at Figure 11 S1106, as Figure 12C illustrated, a second dipole layer 282 is formed in regions N1', N2', N3', P1', P2', and P3'. In addition, the second dipole layer 282 is removed from regions N1' and P3' by using one or more lithography and etching operations, as Figure 12D illustrated. In some embodiments, similar to the operations explained with respect to Figure 12A and Figure 12B , an adhesion enhancement layer is formed on the second dipole layer and a double layer of BARC and photoresist of

[0110] Then, at Figure 11 S1107, as Figure 12EThe annealing operation is performed as shown. In some embodiments, the annealing operation is performed for about 2 seconds to about 100 seconds at a temperature ranging from about 400°C to about 700°C to introduce dipole dopant elements from dipole high-k dielectric layers 182, 282 into high-k dielectric layer 82 to form high-k dielectric layers 821 and 822 with different doping doses, as shown. Figure 12E As shown. In some embodiments, the dipole dopant element includes one or more of La, Lu, Sc, Sr, Zr, Y, Dy, Eu, and Yb, which are contained in the dipole high-k dielectric layers 182 and 282. In some embodiments, diffusion layers 821 and 822 are formed on a portion of the high-k dielectric layer 82, and in other embodiments, the high-k dielectric layer 82 is completely converted into diffusion layers 821 and 822. The amount of dipole dopant element diffused into the gate dielectric layer 82 depends on the thickness and / or number of dipole high-k dielectric layers. In some embodiments, a FET having a high-k dielectric layer and two dipole high-k dielectric layers on a high-k dielectric layer has the highest concentration of dopant element than a FET having a high-k dielectric layer and one dipole high-k dielectric layer and a FET having a high-k dielectric layer and no dipole high-k dielectric layer. In some embodiments, after the annealing operation, in Figure 11 At S1108, an optional wet etching is performed to partially or completely remove any residue from dipole layers 182 and 282, such as... Figure 12F As shown. In some embodiments, a wet etching operation is not performed so that the dipole high-k dielectric layers 182, 282 remain in the final gate structure of the FET device. Subsequently, in Figure 11 At point S1109, similar to the one about Figures 7 to 9H The described operations form one or more WFM layers. Additionally, a protective layer may optionally be formed, and... Figure 11 A glue layer is formed at S1110, and then similar to... Figure 7 The S712-S714, in Figure 11 A bulk gate metal layer 88 is formed at S1111.

[0111] It will be understood that not all advantages need to be discussed herein, no particular advantage is necessary for all embodiments, and other embodiments may provide different advantages.

[0112] According to one aspect of the present application, a semiconductor device includes a first field effect transistor (FET) including a first gate structure disposed over a first channel region, and a second FET having a different conductivity type than the first FET and including a second gate structure disposed over a second channel region. The first gate structure includes a first gate dielectric layer over the first channel region, a first work function adjusting material layer over the first gate dielectric layer, a bond enhancement layer disposed over the first work function adjusting material layer, and a first metal gate electrode layer. The second gate structure includes a second gate dielectric layer over the second channel region, a second work function adjusting material layer over the second gate dielectric layer, and a second metal gate electrode layer, and the second gate structure does not include the bond enhancement layer. The first work function adjusting material layer is nitrogen-free or contains nitrogen in an amount less than 50 atomic %, and the bond enhancement layer contains nitrogen in an amount in a range of 55 atomic % to 75 atomic %. In one or more of the foregoing and following embodiments, the bond enhancement layer has a higher nitrogen concentration than the first work function adjusting material layer. In one or more of the foregoing and following embodiments, the bond enhancement layer includes one or more of TiN, TiSiN, or AlN, where x is about 1.1 to 1.5. In one or more of the foregoing and following embodiments, the first work function adjusting material layer includes one or more of WN, WCN, MoN, and Ru. In one or more of the foregoing and following embodiments, the second work function adjusting material layer includes one or more of TaAl, TaAlC, TiAl, and TiAlC. In one or more of the foregoing and following embodiments, the bond enhancement layer has a thickness in a range of 0.2 nm to 2 nm. In one or more of the foregoing and following embodiments, the first gate structure further includes a third work function adjusting material layer made of the same material as the second work function adjusting material layer and disposed over the bond enhancement layer. In one or more of the foregoing and following embodiments, a thickness of each of the first gate dielectric layer, the first work function adjusting material layer, and the bond enhancement layer of the first channel region varies by more than 0.5% and less than 5.0%. In one or more of the foregoing and following embodiments, a thickness and composition of all layers in the first gate structure are constant throughout the first FET. x

[0113] ​According to another aspect of the present invention, a semiconductor device includes: a first gate dielectric layer disposed over a channel region; a second gate dielectric layer disposed over the first gate dielectric layer; an adhesion enhancement layer disposed over the second gate dielectric layer; one or more work function adjustment material layers disposed over the adhesion enhancement layer; and a body gate electrode layer disposed over the one or more work function adjustment material layers. The second gate dielectric layer is an oxide of one or more of La, Lu, Sc, Sr, Zr, Y, Dy, Eu, or Y, and the adhesion enhancement layer comprises TiN. x The first gate dielectric layer comprises one or more of TiSiN, SiN, AlN, and Al2O3, wherein x is about 1.1 to 1.5. In one or more of the foregoing and following embodiments, the first gate dielectric layer comprises a high-k dielectric material different from the second gate dielectric layer. In one or more of the foregoing and following embodiments, the one or more first work function adjustment material layers comprise one or more of WN, WCN, MoN, and Ru. In one or more of the foregoing and following embodiments, the one or more work function adjustment material layers comprise one or more of TaAl, TaAlC, TiAl, and TiAlC. In one or more of the foregoing and following embodiments, the one or more work function adjustment material layers comprise one or more of TiN, TiSiN, TaN, and TaSiN. In one or more of the foregoing and following embodiments, the thickness of the adhesion enhancement layer is in the range of 0.3 nm to 1.5 nm. In one or more of the foregoing and following embodiments, the semiconductor device further comprises: a third gate dielectric layer disposed between the second gate dielectric layer and the one or more work function adjustment material layers.

[0114] According to another aspect of the present invention, a semiconductor device includes a gate structure disposed over a channel region and a source / drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. An adhesion enhancement layer is disposed between adjacent first work function adjustment material layers. In one or more of the foregoing and following embodiments, the adhesion enhancement layer has a higher nitrogen concentration than the work function adjustment material layer disposed closer to the gate dielectric layer. In one or more of the foregoing and following embodiments, the adhesion enhancement layer comprises TiN. xone or more of TiN, TiSiN, SiN, AlN, and AI2O3, where x is about 1.1 to 1.5. In one or more of the foregoing and following embodiments, the work function adjusting material layer includes a first layer made of one or more of WN, WCN, MoN, and Ru, and the adhesion enhancing layer is disposed above the first layer. In one or more of the foregoing and following embodiments, the work function adjusting material layer includes a first layer made of one or more of TaAl, TaAlC, TiAl, and TiAlC, and the adhesion enhancing layer is disposed below the first layer. In one or more of the foregoing and following embodiments, the adhesion enhancing layer has a thickness in a range of 0.2 nm to 2 nm.

[0115] In accordance with another aspect of the present application, in a method of fabricating a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjusting material layer is formed over the gate dielectric layer, an adhesion enhancing layer is formed over the first work function adjusting material layer, a mask layer including an anti-reflective organic material layer is formed over the adhesion enhancing layer, and the adhesion enhancing layer and the first work function adjusting material layer are patterned by using the mask layer as an etch mask. The adhesion enhancing layer has a higher adhesion strength to the anti-reflective organic material layer than to the first work function adjusting material layer. In one or more of the foregoing and following embodiments, the first work function adjusting material layer is nitrogen-free or contains nitrogen in an amount less than 50 atomic %, and the adhesion enhancing layer contains nitrogen in a range of 55 atomic % to 75 atomic %. In one or more of the foregoing and following embodiments, the adhesion enhancing layer has a higher nitrogen concentration than the first work function adjusting material layer. In one or more of the foregoing and following embodiments, the adhesion enhancing layer includes one or more of TiN x , TiSiN, or AlN, where x is about 1.1 to 1.5. In one or more of the foregoing and following embodiments, the mask layer is removed, and a second work function adjusting material layer is formed over the adhesion enhancing layer. In one or more of the foregoing and following embodiments, the adhesion enhancing layer includes TiN x , TiSiN, SiN, AlN, and AI2O3, where x is about 1.1 to 1.5. In one or more of the foregoing and following embodiments, the mask layer is removed, and the adhesion enhancing layer is removed, and a second work function adjusting material layer is formed over the first work function adjusting material layer. In one or more of the foregoing and following embodiments, the adhesion enhancing layer is formed by nitridating a surface region of the first work function adjusting material layer. In one or more of the foregoing and following embodiments, the adhesion enhancing layer has a thickness in a range of 0.2 nm to 2 nm.

[0116] According to another aspect of the present invention, in a method of manufacturing a semiconductor device, a first gate dielectric layer is formed over a channel region made of a semiconductor material, a second gate dielectric layer is formed over the first gate dielectric layer, an adhesion reinforcement layer is formed over the second gate dielectric layer, a mask layer comprising an organic material is formed on the adhesion reinforcement layer, and the adhesion reinforcement layer and the second gate dielectric layer are patterned by using the mask layer as an etching mask. The adhesion reinforcement layer comprises TiN. x The second gate dielectric layer comprises one or more of La, Lu, Sc, Sr, Zr, Y, Dy, Eu, and Y, wherein x is about 1.1 to 1.5. In one or more of the foregoing and following embodiments, the second gate dielectric layer comprises an oxide of one or more of La, Lu, Sc, Sr, Zr, Y, Dy, Eu, and Y. In one or more of the foregoing and following embodiments, the mask layer is removed, and the adhesion reinforcement layer is also removed. In one or more of the foregoing and following embodiments, a third gate dielectric layer is formed over the second gate dielectric layer after the adhesion reinforcement layer is removed. In one or more of the foregoing and following embodiments, the second gate dielectric layer and the third gate dielectric layer each comprise an oxide of one or more of La, Lu, Sc, Sr, Zr, Y, Dy, Eu, and Y. In one or more of the foregoing and following embodiments, the mask layer is removed, and a third gate dielectric layer is formed over the adhesion reinforcement layer.

[0117] According to another aspect of the present invention, in a method of manufacturing a semiconductor device, a first layer is formed over a channel region made of a semiconductor material; an adhesion enhancement layer is formed over the first layer; a bottom anti-reflective layer made of an organic material is formed over the adhesion enhancement layer; a photoresist pattern is formed over the bottom anti-reflective layer; a portion of the bottom anti-reflective layer is patterned by using the photoresist pattern as an etching mask; a portion of the first layer is patterned by using the patterned bottom anti-reflective layer as an etching mask; the photoresist pattern and the patterned bottom anti-reflective layer are removed; and a second layer is formed over the first layer. In one or more of the foregoing and following embodiments, the adhesion enhancement layer has a higher nitrogen concentration than the first layer. In one or more of the foregoing and following embodiments, the first layer is an oxide layer. In one or more of the foregoing and following embodiments, the first layer is a conductive layer.

[0118] The foregoing summary of some embodiments has been presented with sufficient particularity by way of exemplification and not limitation, and other embodiments can be realized and achieved by making a few of the appropriate substitutions and modifications to the embodiments described in detail above. It is therefore intended that the scope of the application be determined by the following claims rather than by the embodiments presented above, which should be regarded as merely illustrative in nature.

Claims

1. A semiconductor device, comprising: The first field-effect transistor (FET) includes a first gate structure disposed above the first channel region; as well as The second field-effect transistor has a different conductivity type than the first field-effect transistor and includes a second gate structure disposed above the second channel region, wherein: The first gate structure includes: A first gate dielectric layer is located above the first channel region; The first power function adjustment material layer is located above the first gate dielectric layer; An adhesive reinforcement layer is disposed above the first work function adjustment material layer; and First metal gate electrode layer The second gate structure includes: The second gate dielectric layer is located above the second channel region; A second work function adjustment material layer is located above the second gate dielectric layer; and The second metal gate electrode layer, and The first work function adjusting material layer is nitrogen-free or contains less than 50 atomic percent nitrogen, and the adhesive reinforcement layer contains nitrogen in the range of 55 atomic percent to 75 atomic percent, and The second gate structure does not include the adhesive reinforcement layer.

2. The semiconductor device according to claim 1, wherein, The adhesive reinforcement layer has a higher nitrogen concentration than the first work function adjustment material layer.

3. The semiconductor device according to claim 1, wherein, The adhesive reinforcement layer includes TiN. x One or more of TiSiN or AlN, wherein x is 1.1 to 1.

5.

4. The semiconductor device according to claim 1, wherein, The first work-function modulating material layer includes one or more of WN, WCN, MoN, or Ru.

5. The semiconductor device according to claim 1, wherein, The second function-adjusting material layer includes one or more of TaAl, TaAlC, TiAl, or TiAlC.

6. The semiconductor device according to claim 1, wherein, The thickness of the adhesive reinforcement layer is in the range of 0.2 nm to 2 nm.

7. The semiconductor device according to claim 1, wherein, The first gate structure further includes a third power function adjustment material layer, which is made of the same material as the second power function adjustment material layer and is disposed above the adhesive reinforcement layer.

8. The semiconductor device according to claim 1, wherein, The thickness variation of each of the first gate dielectric layer, the first power function adjustment material layer, and the adhesive reinforcement layer in the first channel region is greater than 0.5% and less than 5.0%.

9. A semiconductor device, comprising: The first gate dielectric layer is disposed above the channel region; The second gate dielectric layer is disposed above the first gate dielectric layer; The first power function adjustment material layer is arranged above the second gate dielectric layer; An adhesive reinforcement layer is disposed above the first work function adjustment material layer; One or more second functional adjustment material layers are disposed above the adhesive reinforcement layer; as well as A bulk gate electrode layer is disposed above the one or more second work function adjustment material layers, wherein: The second gate dielectric layer is an oxide of one or more of La, Lu, Sc, Sr, Zr, Dy, Eu, or Y, and The adhesive reinforcement layer includes TiN. x One or more of TiSiN, SiN, AlN, or Al2O3, wherein x is 1.1 to 1.

5. The first function adjustment material layer is nitrogen-free or contains less than 50 atomic percent of nitrogen, and the adhesive reinforcement layer contains nitrogen in the range of 55 atomic percent to 75 atomic percent.

10. The semiconductor device according to claim 9, wherein, The first gate dielectric layer comprises a high-k dielectric material that is different from that of the second gate dielectric layer.

11. The semiconductor device according to claim 9, wherein, The first work-function modulating material layer includes one or more of WN, WCN, MoN, or Ru.

12. The semiconductor device according to claim 9, wherein, The one or more second work function adjustment material layers include one or more of TaAl, TaAlC, TiAl, or TiAlC.

13. The semiconductor device according to claim 9, wherein, The thickness of the adhesive reinforcement layer is in the range of 0.3 nm to 1.5 nm.

14. The semiconductor device according to claim 9, further comprising: A third gate dielectric layer is disposed between the second gate dielectric layer and the one or more second work function adjustment material layers.

15. A method for manufacturing a semiconductor device, comprising: A gate dielectric layer is formed above the channel region made of semiconductor material; A first work function adjustment material layer is formed above the gate dielectric layer; An adhesive reinforcement layer is formed above the first work function adjustment material layer; A mask layer is formed over the adhesive reinforcement layer, the mask layer comprising an anti-reflective organic material layer; as well as The adhesive reinforcement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. Wherein, the adhesion strength of the adhesive reinforcement layer to the antireflective organic material layer is higher than the adhesion strength to the first work function adjusting material layer, and The first function adjustment material layer is nitrogen-free or contains less than 50 atomic percent of nitrogen, and the adhesive reinforcement layer contains nitrogen in the range of 55 atomic percent to 75 atomic percent.

16. The method according to claim 15, wherein, The nitrogen concentration of the adhesive reinforcement layer is higher than that of the first work function adjustment material layer.

17. The method according to claim 15, wherein, The adhesive reinforcement layer includes TiN. x One or more of TiSiN or AlN, wherein x is 1.1 to 1.

5.

18. The method of claim 17, further comprising: Remove the mask layer; as well as A second work function adjustment material layer is formed above the adhesive reinforcement layer.

19. The method according to claim 15, wherein, The adhesive reinforcement layer includes TiN. x One or more of TiSiN, SiN, AlN or Al2O3, wherein x is 1.1 to 1.

5.

20. The method of claim 19, further comprising: Remove the mask layer; Remove the adhesive reinforcement layer; as well as A second power function adjustment material layer is formed above the first power function adjustment material layer.

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