Device abnormality protection circuit and electronic device

Abstract

The present invention relates to a device abnormality protection circuit and an electronic device, comprising: a power supply unit, a switch unit connecting a device working power supply circuit and a device working circuit; a first level generating unit connected to a device startup circuit and outputting a first level when the device startup circuit is started; a WDI signal generating unit periodically outputting a WDI signal when the device program is normal; a second level generating unit connected to the WDI signal generating unit and outputting a second level when the WDI signal is normal; a third level generating unit outputting a third level when the state configuration of the device is normal; a logic judgment unit connected to the first, second and third level generating units, outputting a fourth level when the first, second and third levels are received at the same time, otherwise outputting a fifth level; a switch unit connected to the logic judgment unit, turned on when receiving the fourth level, and turned off when receiving the fifth level. The implementation of the present invention can cut off the input of large current when an abnormality occurs, thereby improving the reliability of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more specifically, to a device abnormality protection circuit and an electronic device. Background Art

[0002] In current electronic devices such as floor scrubbers and other cleaning equipment or electronic circuit products, the process for handling abnormal operation of internal programs usually uses a manual trigger switch to restart the entire circuit. Some products also use watchdog reset software to power on the entire circuit. This process generates a large current shock to the electronic equipment or product, which is prone to secondary damage. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a device abnormality protection circuit and an electronic device in view of the above-mentioned technical defects of the prior art.

[0004] The technical solution adopted by the present invention to solve the technical problem is: constructing a device abnormality protection circuit, including: a power supply unit, and

[0005] A switch unit for connecting the equipment working power supply circuit and the equipment working circuit;

[0006] A first level generating unit connected to a device startup circuit and configured to output a first level when the device startup circuit is triggered to start, and to turn off the first level when the device startup circuit is turned off;

[0007] a WDI signal generating unit configured to periodically output a WDI signal when a program of the device runs normally;

[0008] A second level generating unit connected to the WDI signal generating unit, configured to receive the WDI signal to output a second level, and to turn off the second level when the WDI signal off time exceeds a preset time;

[0009] a third level generating unit configured to output a third level when the state configuration of the device operates normally, and to turn off the third level when the state configuration of the device is abnormal;

[0010] a logic judgment unit connected to the first level generating unit, the second level generating unit and the third level generating unit, wherein the logic judgment unit is configured to output a fourth level when the first level, the second level and the third level are received simultaneously, and output a fifth level otherwise;

[0011] The switch unit is also connected to the logic determination unit, and is configured to be turned on when receiving the fourth level and to be turned off when receiving the fifth level.

[0012] Preferably, the second level generating unit comprises: a WDI chip U9 and a D flip-flop U1;

[0013] The first pin of the WDI chip U9 is connected to the third pin of the D flip-flop U1, the second pin of the WDI chip U9 is grounded, the fourth pin of the WDI chip U9 is connected to the WDI signal generating unit, the fifth pin of the WDI chip U9 is connected to the power supply unit, the first pin of the D flip-flop U1 is connected to the WDI signal generating unit and the power supply unit, the second pin and the fourth pin of the D flip-flop U1 are respectively connected to the power supply unit; the sixth pin of the D flip-flop U1 is connected to the logic judgment unit.

[0014] Preferably, the logic judgment unit includes a first AND gate circuit and a second AND gate circuit;

[0015] The first input end of the first AND gate circuit is connected to the second level generating unit, the second input end of the first AND gate circuit is connected to the third level generating unit, the output end of the first AND gate circuit is connected to the first input end of the second AND gate circuit, the second input end of the second AND gate circuit is connected to the first level generating unit, and the output end of the second AND gate circuit is connected to the switch unit.

[0016] Preferably, the first AND gate circuit and the second AND gate circuit are integrated into a dual-path dual-input AND gate chip U10.

[0017] Preferably, the first level generating unit includes a first switch tube Q1, a first resistor R36 and a second resistor R37;

[0018] The first end of the first switch tube Q1 is used to receive a start signal of the device start circuit, the first end of the first switch tube Q1 is also connected to the first end of the first resistor R36, the second end of the first resistor R36 is grounded, the second end of the first switch tube Q1 is connected to the power supply unit, the third end of the first switch tube Q1 is connected to the second input end of the second AND gate circuit and the first end of the second resistor R37, and the second end of the second resistor R37 is grounded.

[0019] Preferably, the first level generating unit further includes a TVS tube TVS1, a cathode of the TVS tube TVS1 is connected to the third end of the first switch tube Q1, and an anode of the TVS tube TVS1 is grounded; and / or

[0020] The first switch tube Q1 includes a first MOS tube, a gate of the first MOS tube is connected to the device startup circuit, a source of the first MOS tube is connected to the second input end of the second AND gate circuit and the first end of the second resistor R37, and a drain of the first MOS tube is connected to the power supply unit.

[0021] Preferably, the switch unit comprises a first sub-switch unit, a second sub-switch unit and a third sub-switch unit;

[0022] The first end of the first sub-switch unit is connected to the output end of the logic judgment unit, the second end of the first sub-switch unit is connected to the first end of the second sub-switch unit, the third end of the first sub-switch unit is grounded, the second end of the second sub-switch unit is connected to the power supply unit, the third end of the second sub-switch unit is connected to the first end of the third sub-switch unit, the second end of the third sub-switch unit is grounded, the third end of the third sub-switch unit is connected to the device working power supply circuit, and the fourth end of the third sub-switch unit is connected to the device working circuit.

[0023] Preferably, the first sub-switch unit includes a second switch tube Q12, a third resistor R60 and a fourth resistor R62;

[0024] A first end of the second switch tube Q12 is connected to a first end of the third resistor R60 and a first end of the fourth resistor R62, a second end of the third resistor R60 is connected to an output end of the logic judgment unit, a second end of the fourth resistor R62 is grounded, a second end of the second switch tube Q12 is connected to a first end of the second sub-switch unit, and a third end of the second switch tube Q12 is grounded.

[0025] Preferably, the second switch tube Q12 includes a transistor, the base of the transistor is connected to the first end of the third resistor R60 and the first end of the fourth resistor R62, the emitter of the transistor is grounded, and the collector of the transistor is connected to the first end of the second sub-switch unit.

[0026] Preferably, the second sub-switch unit includes a third switch tube Q13, a fifth resistor R164 and a sixth resistor R65;

[0027] The first end of the third switch tube Q13 is connected to the first end of the fifth resistor R164 and the first end of the sixth resistor R65, the second end of the fifth resistor R164 is connected to the second end of the first sub-switch unit, the second end of the third switch tube Q13 is connected to the second end of the sixth resistor R65 and the power supply unit, and the third end of the third switch tube Q13 is connected to the first end of the third sub-switch unit.

[0028] Preferably, the third switch tube Q13 includes a second MOS tube, a gate of the second MOS tube is connected to the first end of the fifth resistor R164 and the first end of the sixth resistor R65, a drain of the second MOS tube is connected to the first end of the third sub-switch unit, and a source of the second MOS tube is connected to the second end of the sixth resistor R65 and the power supply unit.

[0029] Preferably, the third sub-switch unit comprises a contactor switch and a current absorption circuit;

[0030] The first end of the coil of the contactor switch is connected to the third end of the second sub-switch unit and the first end of the current absorption circuit, the second end of the coil of the contactor switch is connected to the second end of the current absorption circuit and the ground, the first connection end of the contact of the contactor switch is connected to the device working power supply circuit, and the second connection end of the contact of the contactor switch is connected to the device working circuit.

[0031] Preferably,

[0032] The current absorption circuit includes a diode VD9, a cathode of the diode VD9 is connected to a first end of the coil of the contactor switch, and an anode of the diode VD9 is connected to a second end of the coil of the contactor switch.

[0033] Preferably, the WDI signal generating unit and the third level generating unit are integrated into a controller chip.

[0034] The present invention also constructs an electronic device, comprising the device abnormality protection circuit as described in any one of the above.

[0035] The device abnormality protection circuit and electronic equipment implementing the present invention have the following beneficial effects: they can cut off large current input when an abnormality occurs, thereby improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0037] Figure 1 It is a logic block diagram of an embodiment of a device abnormality protection circuit of the present invention;

[0038] Figure 2 It is a circuit principle diagram of a first embodiment of a device abnormality protection circuit of the present invention;

[0039] Figure 3 It is a circuit principle diagram of a first embodiment of a device abnormality protection circuit of the present invention;

[0040] Figure 4 It is a circuit principle diagram of a first embodiment of a device abnormality protection circuit of the present invention. DETAILED DESCRIPTION

[0041] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described in detail with reference to the accompanying drawings.

[0042] like Figure 1As shown, in a first embodiment of a device abnormality protection circuit 100 of the present invention, it includes: a power supply unit 110, and a switch unit 120 for connecting a device working power supply circuit 210 and a device working circuit 220, wherein the device working power supply circuit 210 supplies power to the device working circuit 220 when the switch unit 120 is turned on, and turns off the power supply when the switch unit 120 is turned off; a first level generating unit 140 for connecting a device startup circuit 230 and configured to output a first level when the device startup circuit 230 is triggered to start, and to turn off the first level when the device startup circuit 230 is turned off; a WDI signal generating unit 150 configured to periodically output a WDI signal when the program of the device runs normally; a WDI signal connecting unit 150; and a WDI signal generating unit 150 for connecting a WDI signal. The generating unit 150 is used to receive the WDI signal to output the second level, and the second level generating unit 160 is used to turn off the second level when the WDI signal is turned off for a predetermined time; the third level generating unit 170 is configured to output the third level when the state configuration of the device is running normally, and turn off the third level when the state configuration of the device is abnormal; the logic judgment unit 180 is connected to the first level generating unit 140, the second level generating unit 160 and the third level generating unit 170, and is configured to output the fourth level when the first level, the second level and the third level are received at the same time, otherwise output the fifth level; the switch unit 120 is also connected to the logic judgment unit 180, and is configured to be turned on when receiving the fourth level and turned off when receiving the fifth level. Specifically, the power supply unit 110 is used to supply power to the protection circuit. The device working power supply circuit 210 is used to supply power to the working circuit of the device. The device working circuit 220 is relative to the control circuit inside the device. It usually refers to the high-current working circuit of the device, which is mainly used to complete the specific tasks that the device needs to perform. Moreover, its control circuit can be understood as controlling the device working circuit to perform its corresponding specific tasks. The device working power supply circuit 210 can be understood as a high-current power supply circuit. The switch unit 120 connects the device working power supply circuit 210 and the device working circuit 220. When the switch unit 120 is turned on, the device working power supply circuit 210 supplies power to the device working circuit 220, and the device can perform working operations. When the switch unit 120 is turned off, the device working power supply circuit 210 turns off the power supply to the device working circuit 220, and the device working circuit 220 stops working. The device startup circuit 230 is used to power on the device, wherein the device working power supply circuit 210 can be connected to the power input through the device startup circuit 230. When the device startup circuit 230 is triggered, the power input connects the device working power supply circuit 210 through the device startup circuit 230 to power on the device. The first level generating unit 140 is connected to the device startup circuit 230 and outputs the first level when the device startup circuit 230 is normally triggered and turned on. When the device startup circuit 230 operates abnormally, that is, when it is turned off, the output of the first level is turned off.The WDI signal generating unit 150 is used to monitor the program running state of the device. When the program of the device is running, it will periodically output the WDI signal. When the WDI signal is normally output periodically, the second level generating unit 160 outputs the second level. When the program of the device is running abnormally, the WDI signal generating unit 150 will turn off the WDI signal output. At this time, the periodic WDI signal will be turned off for a long time. When the WDI signal is turned off for too long, that is, it exceeds the preset time, the second level generating unit 160 turns off the output of the second level. WDI signal abnormality generally occurs when the internal program runs away. When the device is monitored by the third level generating unit 170, it executes the operation of the state configuration of the corresponding work. When the state configuration is normal, it outputs the third level. When the state configuration is abnormal, it controls the output of the third level to be turned off. The state configuration is configured by reading the state configuration issued by the control module in the operation control of the running device. The logic judgment unit 180 is connected to the first level generating unit 140, the second level generating unit 160 and the third level generating unit 170, and makes judgments according to the inputs of the first level, the second level and the third level, and outputs the fourth level when the first level, the second level and the third level are normal, otherwise it outputs the fifth level, that is, as long as one of the first level, the second level and the third level is not output normally, the logic judgment unit 180 outputs the fifth level. The switch unit 120 is connected to the logic judgment unit 180, and is turned off or on according to the output of the logic judgment unit 180. The switch unit 120 is turned on when the logic judgment unit 180 outputs the fourth level, that is, when the device startup state, the device working state and the device program running state in the device are all normal, its device working circuit 220 can be powered by the device working power supply circuit 210 to maintain a normal working state. The switch unit 120 is turned off when the logic judgment unit 180 outputs the fifth level, that is, any one or more of the device startup state, the device working state and the device program running state in the device is abnormal, the power supply of the device working circuit 220 is turned off, and the device working circuit 220 stops working.

[0043] Optional, such as Figure 4As shown, the second level generating unit 160 includes: a WDI chip U9 and a D flip-flop U1; the first pin of the WDI chip U9 is connected to the third pin of the D flip-flop U1, the second pin of the WDI chip U9 is grounded, the fourth pin of the WDI chip U9 is connected to the WDI signal generating unit 150, the fifth pin of the WDI chip U9 is connected to the power supply unit 110, the first pin of the D flip-flop U1 is connected to the WDI signal generating unit 150 and the power supply unit 110, the second pin and the fourth pin of the D flip-flop U1 are respectively connected to the power supply unit 110; the sixth pin of the D flip-flop U1 is connected to the logic judgment unit 180. Specifically, in the second level generating unit 160, the fourth pin of the WDI chip U9 is used to receive the WDI signal generated by the WDI signal generating unit 150, the first pin of the WDI chip U9 is connected to the D flip-flop U1, and the WDI chip U9 outputs a corresponding trigger signal according to the WDI signal input from the WDI signal generating unit 150 to trigger the D flip-flop U1 to act. Specifically, when the WDI chip U9 does not have a periodic WDI signal input, it will internally generate a low-level reset signal / RESET and then return to a high level after 200ms. After receiving the rising edge, the third pin of the D flip-flop U1 maintains the output of the low level at its sixth pin, that is, the second level output is turned off. The first pin of the D flip-flop U1 is connected to the WDI signal generating unit 150. When the WDI signal generating unit 150 is powered on, the WDI signal generating unit 150 gives a low-level signal, and the output of the D flip-flop U1 is cleared by the low-level signal to prevent the D flip-flop U1 from being triggered and locked by the initial state of the WDI chip U1 during the power-on process. The second pin of the D flip-flop U1, namely the 1D pin, the third pin, namely the 1CLK / pin, and the fourth pin, namely the 1PRE / pin, can be provided with a pull-up voltage by the power supply unit 110. In a specific embodiment, the device model used by the WDI chip U9 is TPS3828-33, and the device model used by the D flip-flop U1 is SN74HC74DR.

[0044] Optionally, the logic judgment unit 180 includes a first AND gate circuit and a second AND gate circuit; the first input end of the first AND gate circuit is connected to the second level generating unit 160, the second input end of the first AND gate circuit is connected to the third level generating unit 170, the output end of the first AND gate circuit is connected to the first input end of the second AND gate circuit, the second input end of the second AND gate circuit is connected to the first level generating unit 140, and the output end of the second AND gate circuit is connected to the switch unit 120. Specifically, in the logic judgment unit 180, the second level and the third level are received through the input end of the first AND gate circuit, and the judgment level corresponding to the output or shut-off output of the second level and the third level is output, and the judgment level and the first level are received through the input end of the second AND gate circuit, and the final judgment result is output according to the judgment level and the first level.

[0045] Optional, such as Figure 3 As shown, the first AND gate circuit and the second AND gate circuit are integrated into a dual-channel dual-input AND gate chip U10. Specifically, the first level generating unit 140, the second level generating unit 160 and the third level generating unit 170 are respectively connected through a dual-channel dual-input AND gate chip U10 to finally output the judgment result based on the first level, the second level and the third level. The first level generating unit 140 is connected to the sixth pin of the dual-channel dual-input chip U10, the second level generating unit 160 is connected to the first pin of the dual-channel dual-input chip U10, the third level generating unit 170 is connected to the second pin of the dual-channel dual-input chip U10, the seventh pin of the dual-channel dual-input chip U10 is connected to its fifth pin, and the third pin of the dual-channel dual-input chip U10 is connected to the switch unit 120. In a specific embodiment, the device model used by the dual-channel dual-input AND gate chip U10 is 74HC2G08DP.

[0046] Optionally, the first level generating unit 140 includes a first switch tube Q1, a first resistor R36, and a second resistor R37; the first end of the first switch tube Q1 is used to receive a start signal of the device start circuit 230, the first end of the first switch tube Q1 is also connected to the first end of the first resistor R36, the second end of the first resistor R36 is grounded, the second end of the first switch tube Q1 is connected to the power supply unit 110, the third end of the first switch tube Q1 is connected to the second input end of the second AND gate circuit and the first end of the second resistor R37, and the second end of the second resistor R37 is grounded. Specifically, in the first level generating circuit, the first end of the first switch tube Q1 is connected to the device start circuit 230, and the start signal of the device start circuit 230 generates a driving level at the first end of the first switch tube Q1 through the first resistor R36, and the driving level drives the first switch tube Q1 to turn on. After the first switch tube Q1 is turned on, the power supply unit 110 forms a voltage, i.e., a first level, at the first end of the second resistor R37 through the turned-on first switch tube Q1. The first level is input to the input end of the second AND gate circuit.

[0047] Optionally, the first level generating unit 140 further includes a TVS tube TVS1, a cathode of the TVS tube TVS1 is connected to the third end of the first switch tube Q1, and an anode of the TVS tube TVS1 is grounded; specifically, since the start signal received by the first level generating unit 140 may come from a manual trigger signal, the TVS tube TVS1 is used to prevent the first level generating unit 140 from generating the first level with electrostatic interference.

[0048] Optionally, the first switch tube Q1 includes a first MOS tube, the gate of the first MOS tube is connected to the device startup circuit 230, the source of the first MOS tube is connected to the second input end of the second AND gate circuit and the first end of the second resistor R37, and the drain of the first MOS tube is connected to the power supply unit 110. The first switch tube Q1 can be a MOS tube, and its specific model can be NCE6003. The gate of the MOS tube is connected to the device startup circuit 230 to drive the device startup circuit 230 to conduct.

[0049] Optional, such as Figure 2 As shown, the switch unit 120 includes a first sub-switch unit 121, a second sub-switch unit 122 and a third sub-switch unit 123; the first end of the first sub-switch unit 121 is connected to the output end of the logic judgment unit 180, the second end of the first sub-switch unit 121 is connected to the first end of the second sub-switch unit 122, the third end of the first sub-switch unit 121 is grounded, the second end of the second sub-switch unit 122 is connected to the power supply unit 110, the third end of the second sub-switch unit 122 is connected to the first end of the third sub-switch unit 123, the second end of the third sub-switch unit 123 is grounded, the third end of the third sub-switch unit 123 is connected to the device working power supply circuit 210, and the fourth end of the third sub-switch unit 123 is connected to the device working circuit 220. Specifically, in the switch unit 120, the device working power supply circuit 210 and the device working circuit 220 are controlled to be turned on by the three-level sub-switch unit 120. The first sub-switch unit 121 is connected to the logic judgment unit 180, and is turned on when receiving the fourth level output by the logic judgment unit 180. The second sub-switch unit 122 is connected to the first sub-switch unit 121. When the first sub-switch unit 121 is turned on, the second sub-switch unit 122 is turned on. At this time, the power supply unit 110 powers on the third sub-switch unit 123 through the second sub-switch unit 122. After the third sub-switch unit 123 is powered on, the third sub-switch unit 123 is turned on after being powered on. The device working power supply circuit 210 supplies power to the subsequent device working circuit 220 through the turned-on third sub-switch unit 123. When the logic judgment unit 180 outputs the fifth level, the first sub-switch unit 121 is turned off, and when the first sub-switch unit 121 is turned off, the second sub-switch unit 122 is turned off, and when the second switch unit 120 is turned off, the third sub-switch unit 123 is powered off and turned off, and the device working power supply circuit 210 disconnects the power supply to the device working circuit 220, and the device working circuit 220 stops working.

[0050] Optionally, the first sub-switch unit 121 includes a second switch tube Q12, a third resistor R60 and a fourth resistor R62; the first end of the second switch tube Q12 is connected to the first end of the third resistor R60 and the first end of the fourth resistor R62, the second end of the third resistor R60 is connected to the output end of the logic judgment unit 180, the second end of the fourth resistor R62 is grounded, the second end of the second switch tube Q12 is connected to the first end of the second sub-switch unit 122, and the third end of the second switch tube Q12 is grounded. Specifically, in the first sub-switch unit 121, when the logic judgment unit 180 outputs the fourth level, for example, a high level, a voltage is generated at the first end of the second switch tube Q12 through the voltage division effect of the third resistor R60 and the fourth resistor R62, and the second switch tube Q12 is driven to turn on through the voltage division. When the second switch tube Q12 is turned on, the first end of the second sub-switch unit 122 is grounded. When the logic determination unit 180 outputs the fifth level, for example, a low level, the first end of the second switch tube Q12 is at a low level, and the second switch tube Q12 is turned off.

[0051] Optionally, the second switch tube Q12 includes a triode, the base of the triode is connected to the first end of the third resistor R60 and the first end of the fourth resistor R62, the emitter of the triode is grounded, and the collector of the triode is connected to the first end of the second sub-switch unit 122. The second switch tube Q12 can select a triode, and the base of the triode is driven by the output of the logic judgment unit 180 to drive the triode to be turned on or off.

[0052] Optionally, the second sub-switch unit 122 includes a third switch tube Q13, a fifth resistor R164, and a sixth resistor R65; a first end of the third switch tube Q13 is connected to a first end of the fifth resistor R164 and a first end of the sixth resistor R65, a second end of the fifth resistor R164 is connected to a second end of the first sub-switch unit 121, a second end of the third switch tube Q13 is connected to a second end of the sixth resistor R65 and the power supply unit 110, and a third end of the third switch tube Q13 is connected to a first end of the third sub-switch unit 123. Specifically, in the second sub-switch unit 122, when the first sub-switch unit 121 is turned on, the power supply unit 110 is grounded through the fifth resistor R164 and the sixth resistor R65 and generates a driving voltage at the first end of the third switch tube Q3 through the fifth resistor R164 and the sixth resistor R65 to drive the third switch tube Q13 to turn on, and when the third switch tube Q13 is turned on, the power supply unit 110 electrically turns on the third sub-switch unit 123. When the first sub-switch unit 121 is turned off, no voltage is generated between the fifth resistor R164 and the sixth resistor R65, the third switch tube Q13 is turned off, and the third sub-switch unit 123 is powered off and turned off.

[0053] Optionally, the third switch tube Q13 includes a second MOS tube, the gate of the second MOS tube is connected to the first end of the fifth resistor R164 and the first end of the sixth resistor R65, the drain of the second MOS tube is connected to the first end of the third sub-switch unit 123, and the source of the second MOS tube is connected to the second end of the sixth resistor R65 and the power supply unit 110. The third switch tube Q13 can be a MOS tube, for example, a PMOS tube, and a specific model can be AO4441, the gate of the MOS tube is connected to the first sub-switch unit 121, and the MOS tube is driven to be turned on or off by the first sub-switch unit 121.

[0054] In one embodiment, the third sub-switch unit 123 includes a contactor switch and a current absorption circuit; the first end of the coil of the contactor switch is connected to the third end of the second sub-switch unit 122 and the first end of the current absorption circuit, the second end of the coil of the contactor switch is connected to the second end of the current absorption circuit and the ground, the first connection end of the contact of the contactor switch is connected to the device working power supply circuit 210, and the second connection end of the contact of the contactor switch is connected to the device working circuit 220; specifically, the third sub-switch unit 123 is composed of a contactor switch 1231 and a current absorption circuit 1232, wherein the coil of the contactor switch 1231 is controlled to be powered on or off by the second sub-switch unit 122, and the contact of the contactor switch 1231 is closed and turned on or off when the coil of the contactor switch 1231 is powered on or off. The current absorption circuit is used to absorb the large current generated when the contactor coil is powered off.

[0055] In another embodiment, the current absorption circuit 1232 includes a diode VD9, the cathode of the diode VD9 is connected to the first end of the coil of the contactor switch, and the anode of the diode VD9 is connected to the second end of the coil of the contactor switch. Specifically, the large current generated when the contactor coil is powered off can be absorbed by the diode VD9. That is, when the contactor coil is powered off, it forms a loop with the diode VD9 to release the large current generated when the contactor coil is powered off.

[0056] Optionally, the WDI signal generating unit 150 and the third level generating unit 170 are integrated into a controller chip. Specifically, the WDI signal and the third level can be generated by the controller chip U21. That is, the controller chip U21 periodically outputs the WDI signal when its internal program runs normally, and turns off the WDI signal output when its internal program is abnormal. At the same time, the controller chip U21 monitors the device status configuration of its output port, outputs the third level when the device status configuration is normal, otherwise turns off the third level. In a specific embodiment, the model of the controller chip U21 that can be used is R5F52316ADFP.

[0057] In addition, an electronic device of the present invention includes a device abnormality protection circuit as described in any one of the above items. That is, the working process of the electronic device is protected by the device abnormality protection circuit. When an abnormality occurs in the device, the main circuit large circuit injection is quickly cut off. The electronic device can be various electrical appliances including cleaning equipment such as a floor scrubber.

[0058] It can be understood that the above embodiments only express the preferred implementation modes of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the patent scope of the present invention. It should be pointed out that, for ordinary technicians in this field, without departing from the concept of the present invention, the above technical features can be freely combined, and several deformations and improvements can be made, which all belong to the protection scope of the present invention. Therefore, all equivalent changes and modifications made to the scope of the claims of the present invention should belong to the scope covered by the claims of the present invention.

Claims

1. A device abnormality protection circuit, characterized in that: include: power supply unit, and A switch unit for connecting the equipment working power supply circuit and the equipment working circuit; A first level generating unit connected to a device startup circuit and configured to output a first level when the device startup circuit is triggered to start, and to turn off the first level when the device startup circuit is turned off; a WDI signal generating unit configured to periodically output a WDI signal when a program of the device runs normally; A second level generating unit connected to the WDI signal generating unit, configured to receive the WDI signal to output a second level, and to turn off the second level when the WDI signal off time exceeds a preset time; a third level generating unit configured to output a third level when the state configuration of the device is normal, and to turn off the third level when the state configuration of the device is abnormal; a logic judgment unit connected to the first level generating unit, the second level generating unit and the third level generating unit, wherein the logic judgment unit is configured to output a fourth level when the first level, the second level and the third level are received simultaneously, and output a fifth level otherwise; The switch unit is also connected to the logic judgment unit and is configured to be turned on when receiving the fourth level and turned off when receiving the fifth level; the logic judgment unit includes a first AND gate circuit and a second AND gate circuit; The first input end of the first AND gate circuit is connected to the second level generating unit, the second input end of the first AND gate circuit is connected to the third level generating unit, the output end of the first AND gate circuit is connected to the first input end of the second AND gate circuit, the second input end of the second AND gate circuit is connected to the first level generating unit, and the output end of the second AND gate circuit is connected to the switch unit; Furthermore, the WDI signal generating unit and the third level generating unit are integrated into a controller chip.

2. The device abnormality protection circuit according to claim 1, characterized in that: The second level generating unit includes: a WDI chip U9 and a D flip-flop U1; The first pin of the WDI chip U9 is connected to the third pin of the D flip-flop U1, the second pin of the WDI chip U9 is grounded, the fourth pin of the WDI chip U9 is connected to the WDI signal generating unit, the fifth pin of the WDI chip U9 is connected to the power supply unit, the first pin of the D flip-flop U1 is connected to the WDI signal generating unit and the power supply unit, the second pin and the fourth pin of the D flip-flop U1 are respectively connected to the power supply unit; the sixth pin of the D flip-flop U1 is connected to the logic judgment unit.

3. The device abnormality protection circuit according to claim 1, characterized in that: The first AND gate circuit and the second AND gate circuit are integrated into a dual-path dual-input AND gate chip U10.

4. The device abnormality protection circuit according to claim 1, characterized in that: The first level generating unit includes a first switch tube Q1, a first resistor R36 and a second resistor R37; The first end of the first switch tube Q1 is used to receive a start signal of the device start circuit, the first end of the first switch tube Q1 is also connected to the first end of the first resistor R36, the second end of the first resistor R36 is grounded, the second end of the first switch tube Q1 is connected to the power supply unit, the third end of the first switch tube Q1 is connected to the second input end of the second AND gate circuit and the first end of the second resistor R37, and the second end of the second resistor R37 is grounded.

5. The device abnormality protection circuit according to claim 4, characterized in that: The first level generating unit further includes a TVS tube TVS1, a cathode of the TVS tube TVS1 is connected to the third end of the first switch tube Q1, and an anode of the TVS tube TVS1 is grounded; and / or The first switch tube Q1 includes a first MOS tube, a gate of the first MOS tube is connected to the device startup circuit, a source of the first MOS tube is connected to the second input end of the second AND gate circuit and the first end of the second resistor R37, and a drain of the first MOS tube is connected to the power supply unit.

6. The device abnormality protection circuit according to claim 1, characterized in that: The switch unit includes a first sub-switch unit, a second sub-switch unit and a third sub-switch unit; The first end of the first sub-switch unit is connected to the output end of the logic judgment unit, the second end of the first sub-switch unit is connected to the first end of the second sub-switch unit, the third end of the first sub-switch unit is grounded, the second end of the second sub-switch unit is connected to the power supply unit, the third end of the second sub-switch unit is connected to the first end of the third sub-switch unit, the second end of the third sub-switch unit is grounded, the third end of the third sub-switch unit is connected to the device working power supply circuit, and the fourth end of the third sub-switch unit is connected to the device working circuit.

7. The device abnormality protection circuit according to claim 6, characterized in that: The first sub-switch unit includes a second switch tube Q12, a third resistor R60 and a fourth resistor R62; A first end of the second switch tube Q12 is connected to a first end of the third resistor R60 and a first end of the fourth resistor R62, a second end of the third resistor R60 is connected to an output end of the logic judgment unit, a second end of the fourth resistor R62 is grounded, a second end of the second switch tube Q12 is connected to a first end of the second sub-switch unit, and a third end of the second switch tube Q12 is grounded.

8. The device abnormality protection circuit according to claim 7, characterized in that: The second switch tube Q12 includes a transistor, a base of the transistor is connected to the first end of the third resistor R60 and the first end of the fourth resistor R62, an emitter of the transistor is grounded, and a collector of the transistor is connected to the first end of the second sub-switch unit.

9. The device abnormality protection circuit according to claim 6, characterized in that: The second sub-switch unit includes a third switch tube Q13, a fifth resistor R164 and a sixth resistor R65; The first end of the third switch tube Q13 is connected to the first end of the fifth resistor R164 and the first end of the sixth resistor R65, the second end of the fifth resistor R164 is connected to the second end of the first sub-switch unit, the second end of the third switch tube Q13 is connected to the second end of the sixth resistor R65 and the power supply unit, and the third end of the third switch tube Q13 is connected to the first end of the third sub-switch unit.

10. The device abnormality protection circuit according to claim 9, characterized in that: The third switch tube Q13 includes a second MOS tube, a gate of the second MOS tube is connected to the first end of the fifth resistor R164 and the first end of the sixth resistor R65, a drain of the second MOS tube is connected to the first end of the third sub-switch unit, and a source of the second MOS tube is connected to the second end of the sixth resistor R65 and the power supply unit.

11. The device abnormality protection circuit according to claim 6, characterized in that: The third sub-switch unit includes a contactor switch and a current absorption circuit; The first end of the coil of the contactor switch is connected to the third end of the second sub-switch unit and the first end of the current absorption circuit, the second end of the coil of the contactor switch is connected to the second end of the current absorption circuit and the ground, the first connection end of the contact of the contactor switch is connected to the device working power supply circuit, and the second connection end of the contact of the contactor switch is connected to the device working circuit.

12. The device abnormality protection circuit according to claim 11, characterized in that: The current absorption circuit includes a diode VD9, a cathode of the diode VD9 is connected to a first end of the coil of the contactor switch, and an anode of the diode VD9 is connected to a second end of the coil of the contactor switch.

13. An electronic device, characterized in that: The device comprises an abnormality protection circuit according to any one of claims 1 to 12.

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