Systems and methods relating to hybrid quantum machines, aspects of quantum information technology, and / or other features

Abstract

Systems and methods related to aspects and / or other features of quantum machines, hybrid quantum machines, quantum information technology are disclosed. In one exemplary embodiment, a system is provided that includes: a quantum register that uses qubits to store quantum information, wherein the qubits are configured to store quantum information using particles or objects arranged in a grid of quantum gates; a clock that provides clock cycles to the quantum register; and a qubit connection computing component that is coupled to the quantum register, wherein the qubit connection computing component is configured to shift quantum information between qubits. Wherein, the system uses physical mass to store qubits in different states, and the physical mass can define qubits that are configured to be quantum entangled and superposed at the same time. In addition, the quantum register can include a quantum entanglement component, and / or the qubit connection computing component can include a superposition component.

Description

[0001] Cross-reference related application information

[0002] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 62 / 769,455, filed on November 19, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology disclosed herein relates to the following fields: computer science, quantum information theory, quantum physics, computer architecture, quantum processing and / or storage components having their physical structures. Background Art

[0004] Our traditional computers are mainly based on Alan Turing's theory of computation and different architectural concepts, such as John von Neumann's concept of structure. Therefore, today's computers used for many applications in industry and commercial products are so-called Turing machines, which basically transform a set of input states (called data) into a set of output states (also called data), which are also called "results" or "solutions" to the problem. The calculations between the two that produce such data transformations are called algorithms, since Turing machines can only execute mathematical functions hardwired in the arithmetic and logic unit (ALU) of the central processing unit sequentially. Therefore, the program itself consists of a set of so-called machine codes, which simply select the functions of the ALU one after another. Mathematical problems can be encoded in such programs for Turing machines, and if the Turing machine will stop executing after a finite number of steps, the problem is solved by a finite result as another set of data.

[0005] All Turing machines (e.g. Figure 1 ) have in common that they can be physically constructed with the aid of classical mechanics. In this way, Turing machines are highly predictable and theoretically deterministic, represented by the fact that a certain set of input data will result in the same set of output data every time, regardless of how often the program is executed. Turing machines are also limited in their ability to execute program steps one after another in sequence. A large number of Turing machines can be run in parallel, but once they interact with each other through data exchange, one Turing machine must wait for the results of another.

[0006] All of the above implications lead to a class of problems "P" which represents all problems that can be encoded as a program on a Turing machine that will halt after some time that is proportional to a polynomial function on the size of the input data. In general, problems in class P can be solved by a modern Turing machine in a reasonable amount of time. However, there are many known problems for which we do not know of a program that can be solved in polynomial time, but only as an exponential function of the input size. Therefore, by increasing the input data size, the solution of such problems quickly exceeds the capabilities of any Turing machine.

[0007] The fundamental solution to the above problems is a new type of computing machine, such as a neural network or a quantum computer. A neural network can be understood as a massively parallel computing structure with a large number of logic gates that are deeply interconnected. Therefore, the above logic gates cannot be programmed with an explicit algorithm, but are taught by examples, with the result that the entire neural network itself becomes a huge algorithm, which can no longer be thoroughly formalized to solve the problem on a global scale due to the complexity of the neural network. The natural realization of a neural network is a network of neurons, such as the human brain.

[0008] Quantum computers are a completely different approach to overcoming the fundamental computational limitations of Turing machines, which are no longer based on classical deterministic mechanics, but directly on quantum mechanics. Although some theoretical concepts of such machines have been proposed and / or known for about 20 years, several major achievements are still missing in order to achieve a commercially successful implementation of quantum computers, which will be further described below.

[0009] Another important point here is that software written for Turing machines cannot run on quantum machines, and vice versa, due to the fundamental differences between quantum and classical algorithms. However, the direct commercial value of the installed base of Turing machine software for today's computers exceeds one trillion dollars, and a large portion of all businesses in industrially developed countries indirectly rely on such Turing machine software. One cannot expect to successfully sell a pure quantum machine where all software must be remade before use, while even a potentially slower Turing machine still runs well with well-known deterministic algorithms. Therefore, a hybrid quantum computer capable of implementing both quantum and sequential deterministic algorithms (e.g., as described in the following innovations) is highly desirable, if not essential in various cases. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various embodiments of the present disclosure may be further explained with reference to the accompanying drawings, in which like structures are represented by like numbers in several views. The drawings shown are not necessarily drawn to scale, but rather generally emphasize illustrating the principles of the present disclosure. Therefore, the specific structural and functional details disclosed herein should not be interpreted as limiting, but merely as a representative basis for teaching those skilled in the art to employ one or more exemplary embodiments in various ways.

[0011] Figure 1 is a block diagram of a known Turing machine.

[0012] Figure 2 is a block diagram of an exemplary universal quantum machine consistent with exemplary aspects of certain embodiments of the present disclosure.

[0013] Figure 3 is a block diagram of an exemplary hybrid quantum computer consistent with exemplary aspects of certain embodiments of the present disclosure.

[0014] Figure 4 is a block diagram of an exemplary hybrid quantum processor consistent with exemplary aspects of certain embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] As described above, although some theoretical concepts of quantum computers have been proposed and / or known about such machines, some major achievements are still missing in order to achieve commercially successful applications of quantum computers. First, for example, there is a lack of a model of a universal quantum machine that defines a technical solution to the quantum prior art problem of computing levels similar to Turing machines and their connection to computing complexity levels. Secondly, there is a lack of a physical realization of a hybrid quantum computer that also has a technical solution to the prior art problem of cache consistency between different types of processing units, while maintaining high-bandwidth data exchange between different types of processing units as needed to implement quantum information processing in practice. The technical solutions for these two innovations are further described below in Part 1 and Parts 2-3, respectively.

[0016] 1. Technical Overview of Universal Quantum Machines

[0017] The class of problems that can be solved by a Turing machine in polynomial time is called P, and the class of problems that can be solved by a universal quantum machine in polynomial time can be called QP. There is also a theoretical generalization of the class of P problems by adding a source of randomness to the Turing machine, making it also able to produce a true random number, leading to the class of problems that can be solved by this non-deterministic Turing machine in polynomial time, called NP. It should be remembered that there is no final theory of complexity levels due to the fact that we have not determined whether P is less than or equal to NP and whether NP is less than or equal to QP. In addition, we cannot yet perfectly describe a universal quantum machine from a quantum machine with limitations by the definition of being able to compute all possible quantum algorithms in the minimum possible computational time. However, quantum information theory contains information related to this confusion, and quantum computers, such as those described in this disclosure, will help us elaborate on these nuances.

[0018] The presently disclosed technology may utilize and / or involve the following exemplary aspects or schemes for a general model that is effective using any general quantum machine, such as Figure 2 As shown. In addition, aspects of the present disclosure are based on the principle / recognition that there are no other real random sources besides quantum effects, and therefore there are no quantum algorithms in the universe. With this in mind, the theoretical extension of random sources to deterministic Turing machines Turing machines ultimately leads to quantum machines with limitations. On the other hand, by definition, deterministic processes can never produce real random sources. This leads to the conclusion that P must be less than NP, since the task of generating real random numbers will never pause on a deterministic Turing machine, but can be easily achieved by Turing non-deterministic Turing machines. Since NP is a subset of QP in this sense, it can be believed that it follows that QP>NP>P.

[0019] As combined Figure 1 and Figure 2 A comparison of the structure of the Turing machine and the disclosed universal quantum machine is explained as follows. Figure 1 , the Turing machine may comprise registers 110 of regular bits which may be fed directly from an external source of symbols (groups of input symbols) and then interpreted by the machine as program instructions or data. The language is fairly easy, there are commands to move a storage tape 120 (read / write tape) connected to the registers, and commands to write or read symbols on the tape. Individual locations on the tape are well defined in computer terms, i.e. such locations are "addressable". Each processing step of a computer program is separated in time from one another by a clock 140 (cycles).

[0020] In addition to program commands to move, read and write tapes at arbitrary locations, the arithmetic and logic unit 130 (ALU) of the Turing machine can implement all necessary mathematical functions in order to perform all kinds of operations. More complex functions can be divided into a set of simpler functions. This is where the so-called deterministic Turing machine is different from the non-deterministic Turing machine. Although the deterministic Turing machine only has the function of being able to produce only one specific output from a certain input, the non-deterministic Turing machine also has the ability to associate, so it is possible to produce several versions of output from only a set of inputs. The version of the possible results selected is purely random, determined by an unpredictable random source. Therefore, the so-called non-deterministic Turing machine (NDTM) is not the opposite of the deterministic (DTM) variant, but must be understood as an extension related to it.

[0021] Returning to the disclosed technology, the innovation of the present disclosure may include and / or involve Figure 2 The system / implementation shown implements a prototype of a universal quantum machine and is capable of performing quantum and sequential deterministic operations as well as non-deterministic algorithms.

[0022] From the outside, it is a black box. Figure 2 The exemplary universal quantum machine (UQM) shown in the paper works similarly to a non-deterministic Turing machine (NDTM), which also allows for ambiguous relations. Therefore, different sets of outputs can be derived from the same set of inputs, which makes the results of the universal quantum machine partially unpredictable. There are algorithms that include quantum relations between input sets and output sets.

[0023] Regarding the difference between a universal quantum machine and a Turing machine, unlike classical information, quantum information stored in a quantum register 210 (the upper area in the figure) cannot be copied due to the non-cloning requirement imposed by quantum mechanics. This is because it is necessary to interact with the quantum machine in order to make inputs, which would cause the quantum information in the register to be invalidated, deleted, or destroyed. However, a quantum register only stores quantum states, which can be destroyed by such actions.

[0024] Thus, the quantum machine disclosed herein uses the classical read-write tape 230 not only to output computational results, but also for returning values ​​stored in registers and for including input data. In order to fully execute a quantum algorithm, appropriate "initialization" physics processes, i.e., introductions, are first employed to transfer these classical, and therefore deterministic, data sets into quantum states 260, which are referred to herein as qubits. These qubits are stored on the qubit tape 220, and then Figure 2In this way, classical bits become super-localized qubits that can be directly read, written and processed by quantum registers. The operation here is similar to that of a Turing machine, but instead of classical algorithms, quantum algorithms 270 come into play, and instead of data stored on classical bits, the information resides on the qubits. The quantum registers are able to quantum entangle the qubits, and the qubit connections provide superpositions of the qubits. Figure 2 As shown in the exemplary embodiment of , the quantum entanglement can be provided via a quantum entanglement component 212 within a quantum register 210, and the superposition can be provided via a superposition component 222 within a qubit connection computing component 220.

[0025] Here, it is also noted that although the present disclosure uses the expression "tape" for conventional reasons, such as as a technical term, such storage media may include one or more of any memory technologies other than traditional tape (e.g., magnetic) storage.

[0026] In order to generate the computation result from the quantum machine, it is not enough to read the output of the read-write tape, but the inverse process of initialization must be performed in advance, that is, Figure 2 250 of a qubit represented by the instrument symbol in . The measurement includes the random effect of the superposition state appearing in the qubit according to an intrinsic probability, which in turn is produced by the previously established quantum gates in the register and results in a partially deterministic and random, classical output quantity, called output bits. These output bits are equally written (e.g., via the previously established quantum gates mentioned above), for example, by a Turing machine on a classical storage tape 230, and are available as a result or as a classical cache memory for the algorithm of the universal quantum machine. It is therefore clear that the universal quantum machine of the present disclosure is able to execute classical algorithms and quantum algorithms, thereby enabling it to emulate a full Turing machine. In fact, most known quantum algorithms, such as Shore's algorithm, use alternating compositions of classical and quantum functions.

[0027] As can be seen, the evidence establishes that the currently disclosed quantum machines are universal, for example without any suggestion of discovering all existing quantum relations: First, all physical models describing natural quantum systems in the universe consist only of superpositions and quantum entanglement. Second, the inventors work in quantum information technology (QIT) [see, e.g., Theory of Quantum Information as the Theory of Everything, Georg Gesek, 2009-2012, which is incorporated herein by reference], whose basic graph theory shows that all possible arrangements of information stored in the universe are fully described by superpositions and quantum entanglement. Therefore, Figure 2The general properties of the architecture shown, namely a universal quantum machine, can be defined and established in the context of this paper.

[0028] 2. Physical realization of hybrid quantum computers

[0029] In order to implement and describe the implementation of a universal quantum computer in a complete and reasonably concise manner, the disclosed technology is explained based on an existing Turing machine (also called a server), and in addition, the building blocks of the quantum part are implemented in a quantum processor 360, such as Figure 3 shown.

[0030] Figure 3 is a block diagram of an exemplary hybrid quantum computer 300 consistent with exemplary aspects of certain embodiments of the present disclosure. Figure 3 , a system component including a pre-processing and post-processing unit 330 may be utilized, such as, for example, Novarion's Quanton TM The server's Turing processors provide the classical part of a universal quantum machine, with the read-write tape implemented as a so-called PCI (Peripheral Component Interconnect) Express bus 340, or PCIe. Figure 3 , which again shows a high-level exemplary block diagram of a hybrid quantum computer.

[0031] In order to add quantum computing parts by industrial means, embodiments of the present disclosure may incorporate such quantum computing parts into a quantum processing unit or QPU 360. In order to combine the classical and quantum parts of the hybrid quantum computer according to operational needs, i.e., to enable them to be smoothly interconnected and to collaborate with high performance, the classical processors and quantum processors are arranged in a memory-centric computing architecture, including a memory storage system 320, such as Figure 3 In some embodiments, such a memory storage system may be provided by Novarion's PlatinStor TM Storage system. Typically, such a memory storage system 320 may include a non-volatile memory bank configured to be directly addressed by a PCIe bus simultaneously from the pre-processing and post-processing unit 330 and from the hybrid quantum processor platform 310. In order not to damage the data when transferring the data, a key feature of such a memory storage system 320 is a built-in cache consistency, which confirms the write only when the data has been physically written and is available for a physical read operation of another device. In this way, the memory storage system 320 is specifically designed to support the memory-centric computing platform required by the present disclosure, which is critical to the overall functionality of the hybrid quantum computer introduced in the present disclosure.

[0032] Figure 3Embodiments of the exemplary architecture for a hybrid quantum computer may utilize existing industry technologies, such as different types of pre-processing and post-processing units 330 or Turing processors (e.g., Novarion's Quanton TM processor), a memory storage system 320 (e.g., a non-volatile storage such as the above-mentioned PlatinumStor TM ) and PCIe bus 340 to connect building blocks. Figure 3 As shown, the pre-processing and post-processing unit 330 or Turing processor may include Figure 1 In addition, in some embodiments, the pre-processing and post-processing unit 330 or Turing processor can be configured like a Quanton TM All different kinds of classical processing units can be utilized alike, in particular (at least but not exclusively) central processing units (CPUs), matrix processing units (MPUs), graphics processing units (GPUs) or even neural networks. Each XPU requires the use of a built-in memory controller within the pre- and post-processing unit 330, which grants the XPU components access to a centralized memory architecture provided by the memory storage system 320 via the PCIe bus.

[0033] Furthermore, it should be noted that while certain existing subcomponents of memory-centric computing platforms have been developed by the industry, aspects of the present systems and methods may involve innovations as a function of software and hardware around the PCIe bus, such as cache coherent data flow between heterogeneous processing units (XPU, QPU) via a memory-centric architecture. Furthermore, it should be noted that the pre-processing and post-processing unit 330 (e.g., Quanton TM server system) and a memory storage system 320 (e.g., PlatinumStor TM ) has been developed by Novarion for related applications.

[0034] A hybrid quantum processor 310 (also referred to as an ion computing platform) consistent with the present invention is a focus of the presently described invention and can be connected to a memory-centric computing architecture via a PCIe bus 340, such as Figure 3 As shown in FIG. 3 , the hybrid quantum processor 300 includes multiple quantum processors connected by a novel photonic quantum information interface (PQI) 350. An innovative component of the hybrid quantum processor is the quantum processor core 360, which is Figure 2 works as shown and can be Figure 4 Structure as shown.

[0035] Figure 4 is a block diagram of an exemplary hybrid quantum processor 400 consistent with exemplary aspects of certain embodiments of the present disclosure. Figure 4 , the currently disclosed architecture separates the classical computing part from the quantum machine - quantum gates, which are arithmetic and logic units (ALUs) 430 built on qubits and connected through a relatively high-performance and scalable bus system based on an industrial standard (PCIe). The hybrid quantum processor 400 of the present disclosure can be mounted and connected on a printed circuit board (PCB) - motherboard, and consists of a bus control unit 410 (BCU) implemented as an IC (integrated circuit - FPGA) and a gate creation unit 450 (GCRU), which converts electronic signals from the BCU into parameters for the ALU 430 to perform superposition and quantum entanglement on the qubits.

[0036] Since the gate creation unit 450 and the gate control unit 460 separate the bus control unit 410 from the quantum register, it represents the quantum bit connection 220 containing the quantum gate between the classical bus control unit and the quantum register 430, so the hybrid quantum processor disclosed herein, e.g. Figure 4 The hybrid quantum processor shown has important architectural differences from any other qubit implementation to date. In addition, the gate control unit 460 (GCU) performs operations on the qubits, which makes the qubits immune to perturbations that cause errors during the execution of quantum information transactions within the quantum gates 430. These qubit control functions are error correction operators that can be implemented as state of the art algorithms and programmed by the bus control unit as a firmware upgrade, for example, implemented in an existing installation of a hybrid quantum computer operating in a data center.

[0037] The qubit initialization 420 creates a set of qubits until the quantum ALU possesses 430 and passes the input quantum information to the quantum gate 430. The result of the quantum information processing will be retrieved by the qubit measurement unit 440 on the right side of the quantum ALU (Q-ALU). The measurement result is transmitted to the bus control unit 410 (BCU), where it finds a classical memory cache to be further transmitted via the PCIe bus to the classical memory-centric computing architecture and its attached classical processor. The quantum processor is synchronized by a clock 470 (cycle), which allows a large number of superposed and quantum entangled qubits to be generated, processed and measured per time unit. Therefore, the computing power of the hybrid quantum processor is highly scalable in both the number of quantum entangled and superposed qubits and the number of quantum calculations per second.

[0038] The Q-ALU (Qubit Arithmetic and Logic Unit 430) disclosed herein is capable of realizing all possible quantum entangled and superimposed states of a qubit. A qubit has quantum information, while defining a lattice of quantum gates. With these prerequisites, embodiments of the present disclosure combine representations of all possible quantum states and functions within the Q-ALU. Thus, the hybrid quantum processor of the present disclosure is in fact a universal quantum machine, as defined by the statements in Section 1.

[0039] The control unit itself is a Turing machine and is therefore able to feed back classical information to the Q-ALU via the gate control unit. This feature can be used for instantaneous error correction, and furthermore, the quantum processor can autonomously execute a whole set of quantum algorithms and return the results to the classical processor within the server. The systems and methods herein allow for efficient use of PCIe bandwidth and avoidance of latency via the PCIe bus.

[0040] Since the PCIe system of the present disclosure is a bus system, embodiments of the present disclosure can connect more than one quantum processor of this type to several and different conventional processors within a server. In addition, the integration of all the parts can be achieved on a single microchip, so that there is a high-speed connection between the quantum computing part and the classical computing part. With such integration, the solution can be used not only for servers in data centers, as described by the present disclosure by way of example, but also for personal computers, smartphones, and embedded systems in cars, airplanes, etc.

[0041] 3. Technical features / aspects for realizing hybrid quantum processors

[0042] The inventors' prior discoveries in quantum information theory explain how a quantum information system (QIS) can be used as a quantum computer. In the following, a quantum information system (QIS) is described for the first time, under which conditions a quantum information system (QIS) is realized and used as a high-performance quantum computer, and these principles are part of the present invention. Concepts denoted by capital letters are known concepts:

[0043] (1) Decoherence and isolation principle:

[0044] The QIS used here is self-contained such that other entities of the universe, except the qubit initialization unit, gate creation unit, gate control unit, and qubit measurement system, cannot affect or interact with the Q-ALU of the quantum processor.

[0045] (2) Fidelity and Limitation Principle:

[0046] According to the physical implementation of the present disclosure, the elements (particles) of the QIS carry quantum information for computation - qubits in the Q-ALU, providing physical mass, which can be superimposed and quantum entangled at the same time. Since the particles themselves are composed of quantum information, according to quantum information theory, the particles can be superimposed and quantum entangled by themselves. Therefore, the physical implementation of the qubit is carried out in such a way that the degrees of freedom of the entire QIS are limited as much as possible to the qubit operations on the selected physical parameters. This limits the possible errors during quantum computing, which is crucial to the success of such implementations.

[0047] (3) Complexity and manifold principle:

[0048] While theorists would rather describe QIS in terms of their well-known, highly functional theories, the fundamental capabilities of the quantum arithmetic and logic units of the present disclosure are not bound by manifolds on different paths of superposition and quantum entanglement. This means that current advanced quantum computing capabilities cannot be addressed by explicit theoretical formalisms, but essentially can only be addressed at a structural level, just like the description of the functionality of a neural network. Therefore, the programming of the hybrid quantum computer disclosed herein is not defined by the algorithms of software engineers, but rather mathematicians, i.e., "quantum gate developers," must build structures for the quantum arithmetic and logic units, which can then be autonomously introduced in new ways by any next step in the computation by the quantum processor disclosed heretofore. Utilizing this principle of manifolds in quantum gates, the quantum machine of the present disclosure is a hardware virtualized entity, where the hardware and software vary together with any application.

[0049] Based on the inventor’s quantum information theory, here is a new understanding of quantum entanglement and superposition phenomena:

[0050] By quantum entanglement, the inventors describe the sharing of specific quantum information between different entities (=QIS) in the universe. Thus, qubits can be quantum entangled using any physical process that changes the state of the qubit, even if such changes are performed independently on all corresponding parties, such as qubits in a universal quantum computer.

[0051] By superposition, the inventors describe the superposition of different quantum information on one entity in the universe (=QIS) as superposition. Thus, the same qubit can be used simultaneously to construct different quantum gates in a universal quantum computer.

[0052] 4. Physical building blocks for qubits

[0053] According to the given principles of physical systems used in the Q-ALU of the present disclosure in Section 3, namely isolation, confinement, and manifolds, various explicit examples of possible physical entities as building blocks for qubits are as follows:

[0054] Photons and Electrons

[0055] One of the most precise theories ever obtained is the theory of quantum electrodynamics (QED), which describes the interaction between photons and electrons. Since these two particles, according to the aforementioned QIT, represent the simplest building blocks of the universe, this plays the second principle in our hands: limits. These particles are easy to provide and easy to measure. Interestingly, the first attempts to realize quantum processing units with qubits did not choose these easy-to-handle electrons as the carriers of the qubits, but chose much more complex superconducting quantum circuits on a chip, which must be cooled to near absolute zero to more or less maintain the decoherence time of the qubits to work effectively. In addition, the second principle is also difficult to implement with the Q-ALU prototypes of IBM, Google and D-Wave, because the characteristics of the integrated circuit close to the macroscopic components alone have too many degrees of freedom. Therefore, the long-term efforts of these companies to build viable quantum processing units have not yet succeeded.

[0056] According to the embodiments herein, a physical implementation of the above-mentioned quantum arithmetic and logic unit is disclosed, which follows 3 given principles, has particles such as electrons, simple ions (such as Li+, Be+, H-, He+) held in a magnetic force field or an electric force field, and has no other connection with the environment, but can be addressed using photons, electrons, simple particles and quasiparticles.

[0057] The proton according to the aforementioned QIT is the third simplest particle in the universe, which therefore meets the fidelity requirements of the second principle. In this way, embodiments of the present disclosure can use the spin of the proton as a property to store quantum information of the qubit. The same is true for simple electrons. In order to utilize these very simple particles to meet the third principle with complexity, it is disclosed to establish a multi-reference based spin system with a complex magnetic field (the spin can not only be up and down, but also have many superposition directions). Even at room temperature, the magnetic field is easy to control within an integrated circuit and is strong enough at the microscopic distance of the magnetic field. It is shown in the above QIT that using these magnetic fields, aspects of the disclosed technology establish many superimposed and quantum entangled states on these simple and pure qubits. In this way, the qubit is better matched with the 3 principles.

[0058] Furthermore, they showed that this effect can be achieved using electrons in high-temperature superconducting materials, allowing the electrons to be easily cooled with liquid nitrogen, rather than the heavy-duty micro-Kelvin machinery required in existing solutions.

[0059] Furthermore, according to the definition of quantum entanglement and superposition in Section 3, gate creation and gate control in the Q-ALU 430 of the present disclosure are accomplished using other quantum objects (e.g., photons and quasiparticles) from outside the Q-ALU. This enables the current gate control unit to perform zero-point measurement and error correction of quantum states during quantum computation.

[0060] 5. Hybrid quantum processor platform

[0061] Currently described Figure 2 Theoretical constructions of so-called universal quantum machines and Figure 4 The block diagram of the hybrid quantum processor represents the first universal structure that has practical and actual implementation for any quantum computer. Since the structure of quantum gates can be implemented as arithmetic and logic functions in Q-ALU 430, stored in gate creation unit 450, selected by bus control unit 410 and correctly placed to be executed by gate control unit 460, a ubiquitous set of quantum gate structures will be implemented with the disclosed universal quantum computing system, which is referred to herein as a hybrid quantum processor and associated systems and platforms.

[0062] As disclosed herein, the embodiments and features of the present disclosure may be implemented by computer hardware, software and / or firmware. For example, the systems and methods disclosed herein may be implemented in various forms, including, for example, one or more data processors, such as computers, servers, etc., and may also include or access at least one database, digital electronic circuit, firmware, software, or a combination thereof. In addition, although a portion of the disclosed embodiments describes specific (e.g., hardware, etc.) components, the systems and methods consistent with the innovations herein may be implemented with any combination of hardware, software and / or firmware. In addition, the above-mentioned features and other aspects and principles of the present invention may be implemented in various environments. Such environments and related applications may be specifically configured to perform various processes and operations according to the present invention, or they may include a general-purpose computer or computing platform that is selectively activated or reconfigured by code to provide the necessary functions. The processes disclosed herein are not inherently related to any particular computer, network, architecture, environment, or other device, and may be implemented by an appropriate combination of hardware, software, and / or firmware. For example, various general-purpose machines may be used with programs written according to the teachings of the present disclosure, or it may be more convenient to construct a dedicated device or system to perform the desired methods and techniques.

[0063] In this specification, the term component, module, device, etc. may refer to any type of logic or functional device, process or block that can be implemented in a variety of ways. For example, the functions of each block can be combined with each other and / or distributed to any other number of modules. Each module can be implemented as a software program stored in or associated with the computing element disclosed above (e.g., random access memory, read-only memory, CD-ROM memory, hard disk drive), for example, read by a processing unit to implement the functions of the present disclosure. In addition, a module can be implemented as a hardware logic circuit that implements the functions included in the present disclosure. Finally, each module can be implemented using a dedicated instruction (SIMD instruction), a field programmable logic array, or any combination thereof that provides the desired level of performance and cost.

[0064] Aspects of the systems and methods described herein may be implemented as functions programmed into any of a variety of circuits, including programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electrically programmable logic and memory devices, and standard cell-based devices, as well as application specific integrated circuits. Some other possibilities for implementing aspects of the present disclosure include: memory devices, microcontrollers with memory (e.g., EEPROM), embedded microprocessors, firmware, software, etc. In addition, various aspects may be embodied in microprocessors with software-based circuit simulation, discrete logic (sequential and combinatorial), custom devices, fuzzy logic, neural networks, other AI (artificial intelligence) or machine learning systems, quantum devices, and hybrids of any of the above device types.

[0065] It should also be noted that the various logics and / or features disclosed herein may be implemented in terms of their behavior, register transfers, logic components, and / or other characteristics using hardware, firmware, and / or any number of combinations of data and / or instructions embodied in various machine-readable or computer-readable media. Computer-readable media in which formatted data and / or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic, or semiconductor storage media), but do not include transitory media.

[0066] Unless the context clearly requires otherwise, throughout this specification, the words "comprise", "include", etc. should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to", words using the singular or plural also include the plural or singular, respectively. In addition, the words "herein", "hereinafter", "above", "below" and words of similar meaning refer to this application as a whole and not to any particular part of this application. When the word "or" is used to refer to a list of two or more items, the word covers all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0067] Other embodiments of the present disclosure will be apparent to those skilled in the art in view of the practice of the innovations disclosed herein and in consideration of this specification. This specification and examples are considered to be exemplary only, and the true scope and spirit of the present invention are indicated by various relevant principles of the present disclosure and claims and, in some cases, relevant patent doctrines.

Claims

1. A hybrid quantum computer system comprising: A hybrid quantum processor comprising at least one quantum processor and a quantum information controller; a peripheral component interconnect high-speed bus coupled to the hybrid quantum processor; a memory storage system including non-volatile random access memory and coupled to the PCI high-speed bus; and a pre-processing and post-processing unit, composed of different types of processing units and coupled to the PCI high-speed bus; wherein the system is based on a memory centric computing architecture and is configured to connect the different types of processing units and the at least one quantum processor together via the peripheral component interconnect high-speed bus, wherein each of the at least one quantum processor is fully addressable, The memory-centric computing architecture includes: a non-volatile memory bank configured to be directly addressed by the PCI high-speed bus simultaneously from the pre-processing and post-processing units and from the hybrid quantum processor, The memory storage system provides built-in cache coherency that acknowledges writes only when the data has been physically written and is available for a physical read operation by another device.

2. The system of claim 1, wherein the system is configured to provide cache coherent data flow between heterogeneous processing units via the memory centric computing architecture.

3. The system of claim 1, wherein the quantum processor comprises: a quantum register that stores quantum information using qubits, the quantum register including a quantum entanglement component; wherein the qubits are configured to store the quantum information using particles or objects arranged in a grid of quantum gates; and wherein the qubit is configured to be quantum entangled with one or more different systems and / or entities external to the system; a clock that provides a clock cycle to the quantum register; and A qubit-connected computing component coupled to the quantum register, the qubit-connected computing component comprising a superposition component: wherein the qubit connection computing component is configured to shift the quantum information between the qubits; and wherein the qubit is configured to transition into a superposition state defined by a property of the particle or object; Wherein the system uses physical mass to store the qubits in different states, wherein the physical mass defines a qubit configured to be simultaneously quantum entangled and superposed.

4. The system of claim 3, wherein the qubits are configured to store the quantum information over a same time period defined by one or more cycles of the clock.

5. The system of claim 3 or 4, wherein the qubit is configured to transition to a different state per time unit defined by the clock period.

6. The system of claim 3 or 4, wherein the qubit connection computing component is coupled to the quantum register via the quantum entanglement component and the superposition component.

7. The system according to claim 3 or 4, further comprising: A gate control unit performs an operation on the qubit, and the gate control unit configures the qubit so that the qubit is not disturbed.

8. The system of claim 7, further comprising an error correction component within the gate control unit, the error correction component correcting errors in one or more of the qubits.

9. The system of claim 3 or 4, wherein the qubit connection is an additional quantum system located between a read / write tape and the quantum register.

10. The system according to claim 3 or 4, further comprising one or more additional components that implement at least one of decoherence aspects, fidelity preservation aspects and / or complexity / manifold aspects to facilitate the implementation of the quantum processing unit.

11. The system of claim 3, wherein the qubit is implemented as one or more elementary particles.

12. The system of claim 11, wherein the elementary particles are configured to store one or more states and / or properties and are restricted to prevent interaction with external elements that change the one or more states and / or properties.

13. The system of claim 11 or 12, wherein the elementary particles include one or more simple elementary particles defined as superconducting electrons, vacuum isolated protons, H- or He+.

14. A system according to claim 11 or 12, wherein the particle is one or both of the following: trapped in an artificial force field, and / or shielded from any incoming particles or quasiparticles.

15. The system of claim 14, wherein the artificial force field comprises one or more microscopic force fields.

16. The system of claim 15, wherein: The microscopic force field includes and / or involves atomic bodies in the crystal that provides electrons in the conduction band within the high temperature superconductor.

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