Display substrate and manufacturing method thereof, and display device

Abstract

The embodiment of the present disclosure provides a display substrate and a preparation method thereof, and a display device. The display substrate includes: a substrate and a plurality of sub-pixels located on one side of the substrate; the plurality of sub-pixels include: a light-emitting element and a light-emitting detection circuit for detecting the light-emitting brightness of the light-emitting element; the light-emitting detection circuit includes: an optical sensor element and a control transistor connected to the optical sensor element; and further includes: a control signal line extending along a first direction and a detection signal line extending along a second direction located on one side of the substrate; wherein the control electrodes of the plurality of control transistors are connected to the same control signal line, the first electrodes of the plurality of control transistors are connected to the same detection signal line, and the first direction intersects with the second direction.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display devices are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, OLED display devices have become the mainstream products in the current display field.

[0003] Since the brightness of the light-emitting element of an OLED display device changes during use, in order to improve the adverse effect of the brightness change of the light-emitting element on the display effect, a light detection circuit is usually set to compensate the brightness of the OLED device according to the brightness signal. However, the light detection circuit occupies a large pixel space as a whole, resulting in a low resolution that can be achieved by the OLED display device. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels located on one side of the substrate; the plurality of sub-pixels comprising: a light-emitting element and a light-emitting detection circuit for detecting the light-emitting brightness of the light-emitting element; the light-emitting detection circuit comprising: an optical sensor element and a control transistor connected to the optical sensor element;

[0006] It also includes: a control signal line extending along a first direction and a detection signal line extending along a second direction located on one side of the substrate; wherein the control electrodes of multiple control transistors are connected to the same control signal line, the first electrodes of the multiple control transistors are connected to the same detection signal line, and the first direction intersects with the second direction.

[0007] In a second aspect, an embodiment of the present disclosure provides a display device, comprising: the display substrate described in the above embodiment.

[0008] In a third aspect, an embodiment of the present disclosure provides a method for preparing a display substrate, wherein the display substrate is the above-mentioned display substrate, and the preparation method comprises:

[0009] providing a substrate;

[0010] forming a plurality of light emitting detection circuits, control signal lines extending along a first direction, and detection signal lines extending along a second direction on the substrate;

[0011] A plurality of light emitting elements are formed on the substrate on which the plurality of light emitting detection circuits are formed.

[0012] The display substrate and its preparation method and display device provided by the embodiment of the present disclosure may include: a substrate, a plurality of sub-pixels located on one side of the substrate, a control signal line extending along a first direction and a detection signal line extending along a second direction; wherein the plurality of sub-pixels include: a light-emitting element and a light-emitting detection circuit for detecting the light-emitting brightness of the light-emitting element; the light-emitting detection circuit includes: an optical sensor element and a control transistor connected to the optical sensor element; the control electrodes of the plurality of control transistors are connected to the same control signal line, the first electrodes of the plurality of control transistors are connected to the same detection signal line, and the first direction intersects with the second direction. In this way, in the display substrate, by setting the light-emitting elements in the plurality of sub-pixels and the optical sensor elements in the plurality of sub-pixels in a one-to-one correspondence relationship and the optical sensor elements in the plurality of sub-pixels and the control transistors in the plurality of sub-pixels in a one-to-one correspondence relationship, the accuracy of detecting the light-emitting brightness of the light-emitting element can be guaranteed, and by setting the control transistors in the plurality of sub-pixels to share the same control signal line and the same detection signal line, the wiring space can be saved, the occupied area of ​​the light-emitting detection circuit can be reduced, and the space utilization rate can be improved, so that high resolution can be achieved.

[0013] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the schemes described in the description and the drawings.

[0014] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0016] Figure 1A It is a structural schematic diagram of a display substrate;

[0017] Figure 1B It is a schematic diagram of a planar structure of a display substrate;

[0018] Figure 2 A schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0019] Figure 3 is a structural schematic diagram of a pixel driving circuit in an exemplary embodiment of the present disclosure;

[0020] Figure 4 is a structural schematic diagram of a light emitting detection circuit in an exemplary embodiment of the present disclosure;

[0021] Figure 5 is a top view of a display substrate in an exemplary embodiment of the present disclosure;

[0022] Figure 6 for Figure 5 A cross-sectional view of the display substrate along the AA' direction;

[0023] Fig. 7A A schematic diagram of the structure of an active layer of a control transistor in an embodiment of the present disclosure;

[0024] Figure 7B is another structural schematic diagram of the active layer of the control transistor in the embodiment of the present disclosure;

[0025] Figure 7C is another structural schematic diagram of the active layer of the control transistor in the embodiment of the present disclosure;

[0026] Fig. 8A A schematic diagram of the structure of a control electrode and a control signal line of a control transistor in an embodiment of the present disclosure;

[0027] Figure 8B Another structural schematic diagram of the control electrode and the control signal line of the control transistor in the embodiment of the present disclosure;

[0028] Fig. 9A A schematic diagram of the structure of the first electrode and the second electrode of the control transistor and the detection signal line in the embodiment of the present disclosure;

[0029] Fig. 9B Another structural schematic diagram of the first electrode and the second electrode of the control transistor and the detection signal line in the embodiment of the present disclosure;

[0030] Fig. 9C It is another structural schematic diagram of the first electrode and the second electrode of the control transistor and the detection signal line in the embodiment of the present disclosure;

[0031] Fig.10 is a schematic diagram of a display substrate after a first metal layer is formed in an exemplary embodiment of the present disclosure;

[0032] Fig.11A A schematic diagram of a display substrate after a second insulating layer is formed in an exemplary embodiment of the present disclosure;

[0033] Fig. 11B is another schematic diagram of a display substrate after a second insulating layer is formed in an exemplary embodiment of the present disclosure;

[0034] Fig. 12A A schematic diagram of a display substrate after a first conductive layer is formed in an exemplary embodiment of the present disclosure;

[0035] Fig. 12B is another schematic diagram of a display substrate after a first conductive layer is formed in an exemplary embodiment of the present disclosure;

[0036] Fig.13 A schematic diagram of a display substrate after a photoelectric conversion layer is formed in an exemplary embodiment of the present disclosure;

[0037] Fig.14 A schematic diagram of a display substrate after a second conductive layer is formed in an exemplary embodiment of the present disclosure;

[0038] Fig.15 is a schematic diagram of a display substrate after a third insulating layer is formed in an exemplary embodiment of the present disclosure;

[0039] Fig.16 is another schematic diagram of a display substrate after a first metal layer is formed in an exemplary embodiment of the present disclosure;

[0040] Fig.17 is another schematic diagram of a display substrate after a second insulating layer is formed in an exemplary embodiment of the present disclosure;

[0041] Fig.18 is another schematic diagram of a display substrate after a first conductive layer is formed in an exemplary embodiment of the present disclosure;

[0042] Fig.19 is another schematic diagram of a display substrate after a photoelectric conversion layer is formed in an exemplary embodiment of the present disclosure;

[0043] Fig. 20 is another schematic diagram of a display substrate after a second conductive layer is formed in an exemplary embodiment of the present disclosure;

[0044] Fig.21 is another schematic diagram of a display substrate after a third insulating layer is formed in an exemplary embodiment of the present disclosure;

[0045] Fig. 22 FIG. 4 is a schematic diagram of a display substrate after a second metal layer is formed in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Multiple embodiments are described herein, but the description is exemplary rather than restrictive, and there may be more embodiments and implementations within the scope of the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the exemplary embodiments, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0047] When describing representative embodiments, the specification may have presented the method or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps herein, the method or process should not be limited to the steps in the specific order. As will be appreciated by those of ordinary skill in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims for the method or process should not be limited to the steps that are performed in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0048] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0049] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0050] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to has a specific orientation, is constructed and operates in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0051] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0052] In this specification, "electrical connection" includes the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. The "element having some electrical function" can be, for example, an electrode or wiring, or a switching element such as a transistor, or other functional elements such as a resistor, inductor or capacitor.

[0053] In this specification, a transistor refers to an element including at least three terminals: a gate electrode (gate or control electrode), a drain electrode (drain electrode terminal, drain region or drain electrode), and a source electrode (source electrode terminal, source region or source electrode). The transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0054] In this specification, in order to distinguish the two poles of the transistor other than the gate electrode (gate or control electrode), one of the poles is directly described as the first pole and the other pole is the second pole, wherein the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or the case where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0055] The transistors in the embodiments of the present disclosure may be thin film transistors (TFT) or field effect transistors (FET) or other devices with the same characteristics. For example, the thin film transistors used in the embodiments of the present disclosure may include but are not limited to oxide transistors (Oxide TFT) or low temperature polysilicon thin film transistors (LTPS TFT). For example, the thin film transistor can be a bottom gate thin film transistor or a top gate thin film transistor, as long as the switching function can be realized. Here, the embodiments of the present disclosure do not limit this.

[0056] OLED brightness compensation methods can be divided into electrical compensation and optical compensation. Electrical compensation can compensate for threshold voltage and mobility changes. Optical compensation does not distinguish the causes of brightness changes, and can compensate for more factors that cause uneven brightness, making the compensation more comprehensive. In the optical compensation method, the luminescence detection circuit (including: an optical sensor element and a control transistor coupled to the optical sensor element) can detect the brightness signal of the OLED device through the optical sensor element to compensate the brightness of the OLED device according to the brightness signal. However, in the design of built-in optical compensation in pixels, in order to ensure high compensation accuracy and signal-to-noise ratio, the layout space occupied by the optical sensor element is large, which will cause the overall luminescence detection circuit to occupy a larger area, which will result in a larger pixel area, which is not conducive to achieving high resolution (Pixels Per Inch, PPI).

[0057] Figure 1A FIG. 1 is a schematic diagram of the structure of a display substrate. Figure 1A As shown, the display substrate may include: a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo) and a plurality of sub-pixels Pxij.

[0058] In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data signal driver to the data signal driver, a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver to the scan signal driver, and a clock signal, an emission stop signal, etc. suitable for the specifications of the light emitting signal driver to the light emitting signal driver. The data signal driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that a scan start signal provided in the form of a conduction level pulse is sequentially transmitted to the next level circuit under the control of a clock signal, and m may be a natural number. The luminous signal driver may generate an emission signal to be provided to the luminous signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the luminous signal driver may sequentially provide an emission signal with a cut-off level pulse to the luminous signal lines E1 to Eo. For example, the luminous signal driver may be constructed in the form of a shift register, and may generate a luminous signal in a manner that a luminous stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next level circuit under the control of a clock signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding luminous signal line, and i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0059] Figure 1B FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 1BAs shown, the display substrate may include: a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel circuit and a light-emitting structure. The pixel circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting structure. The light-emitting structures in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel circuits of the sub-pixels in which they are located, and the light-emitting structures are configured to emit light of corresponding brightness in response to the current output by the pixel circuits of the sub-pixels in which they are located.

[0060] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure. In an exemplary embodiment, the shape of the sub-pixel in the pixel unit may be rectangular, rhombus, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a herringbone manner. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a square manner, which is not limited in the present disclosure.

[0061] In an exemplary embodiment, the pixel unit may emit white light, and in this case, the pixel unit may include: WOLED. When the pixel unit includes WOLED, the display substrate realizes full colorization through a color filter.

[0062] Figure 2 Schematic diagram of the structure of the display substrate provided by the embodiment of the present disclosure. Figure 2As shown, on a plane perpendicular to the display substrate, the display substrate provided by the embodiment of the present disclosure may include: a substrate 10 and a plurality of sub-pixels located on one side of the substrate 10; the plurality of sub-pixels may include: a light-emitting element 11 and a light-emitting detection circuit 12 for detecting the light-emitting brightness of the light-emitting element 11; the light-emitting detection circuit 12 may include: an optical sensor element 121 and a control transistor 122 connected to the optical sensor element 121; the display substrate may also include: a control signal line G2 (not shown in the figure) extending along a first direction D1 and a detection signal line SL (not shown in the figure) extending along a second direction D2 located on one side of the substrate 10; wherein the control electrodes of the plurality of control transistors 122 are connected to the same control signal line G2, the first electrodes of the plurality of control transistors 122 are connected to the same detection signal line SL, and the first direction D1 intersects with the second direction D2. In this way, in the display substrate, by setting the light-emitting elements in multiple sub-pixels and the optical sensing elements in multiple sub-pixels in a one-to-one correspondence and the optical sensing elements in multiple sub-pixels and the control transistors in multiple sub-pixels in a one-to-one correspondence, the accuracy of detecting the luminous brightness of the light-emitting elements can be guaranteed, and by setting the control transistors in multiple sub-pixels to share the same control signal line and the same detection signal line, wiring space can be saved, the occupied area of ​​the light-emitting detection circuit can be reduced, and the space utilization can be improved, thereby achieving high resolution.

[0063] For example, the “multiple” in which the control transistors in multiple sub-pixels share the same control signal line and the same detection signal line may include but is not limited to two, three, four, five, six, seven or eight, etc. Here, the embodiments of the present disclosure do not limit this.

[0064] In an exemplary embodiment, Figure 2 As shown, the light emitting element 11 may include a backlight side and a light emitting side that are arranged opposite to each other, and the light emitting side is the side of the light emitting element 11 away from the substrate 10, that is, the display substrate in the exemplary embodiment of the present disclosure may be a top-emitting display substrate. In this way, the pixel aperture ratio can be improved, high resolution can be achieved, and better display effects can be achieved. Here, in the exemplary embodiment of the present disclosure, the present disclosure does not limit the light emitting direction of the light emitting element, and it can be set arbitrarily.

[0065] In an exemplary embodiment, Figure 2As shown, each sub-pixel may further include: a pixel driving circuit 13 for driving the light-emitting element 11 to emit light. The pixel driving circuit 13 is connected to the corresponding light-emitting element 11 and is configured to drive the corresponding light-emitting element to emit light according to a driving signal. Here, in the exemplary embodiments of the present disclosure, the present disclosure does not limit whether the light-emitting detection circuit 12 and the pixel driving circuit 13 are located on one side or both sides of the light-emitting element 11, whether the light-emitting detection circuit 12 and the pixel driving circuit 13 are arranged in the same layer, and whether the light-emitting detection circuit 12 and the pixel driving circuit 13 are arranged in a stacked layer, etc., and they can be set arbitrarily.

[0066] In an exemplary embodiment, multiple film layers of at least one transistor in the pixel driving circuit and multiple film layers of the control transistor in the light emitting detection circuit can be manufactured in the same layer. Here, the present disclosure does not limit this.

[0067] In an exemplary embodiment, the display substrate may further include: a driving integrated circuit (IC), wherein a light emitting detection circuit is configured to receive light emitted from a corresponding light emitting element, convert a light signal of the emitted light into an electrical signal, and transmit the electrical signal to a driving chip; and a driving integrated circuit (IC) is configured to control a driving signal provided to a corresponding pixel driving circuit according to the electrical signal transmitted by the light emitting detection circuit to achieve optical compensation.

[0068] In an exemplary embodiment, the pixel driving circuit may include a capacitor unit and a plurality of transistors. For example, the pixel driving circuit may be a 2T1C (ie, including two transistors and a capacitor unit), 3T1C, or 7T1C structure.

[0069] For example, the pixel driving circuit can adopt a 3T1C structure, such as Figure 3 As shown, the pixel driving circuit may include: a driving transistor M1, a first transistor M2, a second transistor M3 and a capacitor unit C1. The control electrode of the first transistor M2 is coupled to the scanning signal line G1, the first electrode of the first transistor M2 is coupled to the data signal line DL, and the second electrode of the first transistor M2 is coupled to the control electrode of the driving transistor M1; the first electrode of the driving transistor M1 is coupled to the first power line VDD, and the second electrode of the driving transistor M1 is coupled to the first anode of the light emitting element L; the first cathode of the light emitting element L is coupled to the second power terminal VSS; the control electrode of the second transistor M3 is coupled to the scanning signal line G1, the first electrode of the second transistor M3 is coupled to the compensation signal line V1, and the second electrode of the second transistor M3 is coupled to the second electrode of the driving transistor M1; the first electrode of the capacitor unit C1 is coupled to the control electrode of the driving transistor M1, and the second electrode of the capacitor unit C1 is coupled to the second electrode of the driving transistor M1.

[0070] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may include but is not limited to one or more of glass and metal foil; the flexible substrate may include but is not limited to one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene and textile fiber.

[0071] In an exemplary embodiment, the display substrate may be an OLED display substrate, a quantum-dot light emitting diode (QLED) display substrate or a WOLED display substrate.

[0072] In an exemplary embodiment, the light-emitting element may be an electronic device having light-emitting properties. For example, the light-emitting element may include any one of an OLED, a quantum dot light-emitting diode (QLED), and an inorganic light-emitting diode (LED). For example, the light-emitting element may be a micron-level light-emitting element, such as a micro light-emitting diode (Micro LED), a sub-millimeter light-emitting diode (Mini LED), or a micro organic light-emitting diode (MicroOLED), etc., and the embodiments of the present disclosure are not limited thereto.

[0073] Figure 4 is a structural schematic diagram of a light emitting detection circuit in an exemplary embodiment of the present disclosure, Figure 5 is a top view of a display substrate in an exemplary embodiment of the present disclosure, Figure 6 for Figure 5 The cross-sectional view of the display substrate along the AA' direction. Figures 4 to 6 As shown, a light emitting detection circuit in a display substrate provided by an exemplary embodiment may include: an optical sensor element DP and a control transistor M0. The optical sensor element DP is electrically connected to the reference signal line V0, and is configured to convert the optical signal of the light emitted from the corresponding light emitting element into an electrical signal; the control transistor M0 is electrically connected to the control signal line G2, the detection signal line SL and the optical sensor element DP, respectively, and is configured to provide the detection signal line SL with the electrical signal converted by the optical sensor element DP under the control of the control signal line G2. Here, in the exemplary embodiments of the present disclosure, the present disclosure does not limit the light emitting direction of the light emitting element, and it can be set arbitrarily.

[0074] In an exemplary embodiment, Figures 4 to 6As shown, the control transistor M0 may include: an active layer 211, a control electrode 212, a first electrode 213, and a second electrode 214, and the optical sensor element DP may include: a first electrode 221 (for example, as a cathode), a photoelectric conversion structure 222, and a second electrode 223 (for example, as an anode) sequentially stacked in a direction away from the substrate 10. The control electrode 212 of the control transistor M0 is connected to the control signal line G2, the first electrode 213 of the control transistor M0 is connected to the detection signal line SL, the second electrode 214 of the control transistor M0 is connected to the first electrode 221 (for example, as a cathode) of the optical sensor element DP, and the second electrode 223 (for example, as an anode) of the optical sensor element DP is connected to the reference signal line V0.

[0075] In an exemplary embodiment, a light emitting detection circuit adopts a 1T1C design (ie, includes: a control transistor M0 and a storage capacitor C0) as an example. Figure 4 As shown, the luminescence detection circuit may further include: a storage capacitor C0, wherein a first electrode of the storage capacitor C0 is connected to a first electrode of the optical sensing element DP (e.g., as a cathode), a second electrode of the storage capacitor C0 is connected to a second electrode of the optical sensing element DP (e.g., as an anode), and the storage capacitor C0 is configured to store an electrical signal converted by the optical sensing element DP.

[0076] In an exemplary embodiment, the control transistor M0 may be a bottom gate structure or a top gate structure, which is not limited in the embodiment of the present disclosure. Figure 5 and Figure 6 The control transistor M0 is taken as an example to be a top-gate structure.

[0077] In an exemplary embodiment, the control transistor M0 may be a P-type transistor, or may be an N-type transistor. The P-type transistor is turned on when the control is a very low level signal, and is turned off when the control is a very high level signal; the N-type transistor is turned on when the control is a very high level signal, and is turned off when the control is a very low level signal. Here, the embodiments of the present disclosure do not limit this.

[0078] In an exemplary embodiment, taking the control transistor M0 as an N-type transistor as an example, combined with Figure 4The light emitting detection circuit shown in the figure may include: in the first stage T1 (i.e., the reset stage), the control transistor M0 is turned on under the control of the high level of the signal g2 of the control signal line G2, and the first electrode (e.g., as a cathode) of the optical sensor element DP is turned on with the detection signal line SL, so that the first electrode (e.g., as a cathode) of the optical sensor element DP is loaded with a positive voltage and reset; a negative voltage (e.g., -5V) is loaded on the reference signal line V0, so that the second electrode (e.g., as an anode) of the optical sensor element DP is loaded with a negative voltage, so that the optical sensor element DP works in a reverse bias state. In the second stage T2 (i.e., the input writing stage), the control transistor M0 is turned off under the control of the low level of the signal g2 of the control signal line G2. In the third stage T3 (i.e., the display stage), the control transistor M0 is turned off under the control of the low level of the signal g2 of the control signal line G2, at which time, the light emitting element can be driven to emit light, so that the optical sensor element DP can receive the light emitted by the light emitting element and convert the received light into an electrical signal, so that the voltage of the first electrode (e.g., as a cathode) of the optical sensor element DP changes. In the fourth stage T4 (i.e., the display off stage), the light emitting element stops emitting light, thereby ensuring that the voltage of the first electrode (e.g., as a cathode) of the optical sensing element DP is stable. In the fifth stage T5 (i.e., the optical detection stage), the control transistor M0 is turned on under the high level control of the signal g2 of the control signal line G2, so as to conduct the optical sensing element DP with the detection signal line SL, thereby transmitting the voltage of the first electrode (e.g., as a cathode) of the optical sensing element DP to the detection signal line SL. For example, the detection signal line SL can be connected to a driver integrated circuit (IC) in a display substrate, and the driver integrated circuit (IC) can obtain an electrical signal on the detection signal line SL for analysis and compensation calculation to achieve electrical compensation, or the detection signal line SL can be connected to a pixel driving circuit in a display substrate, and the pixel driving circuit can obtain an electrical signal on the detection signal line SL to achieve electrical compensation, thereby achieving an improved picture display effect.

[0079] In an exemplary embodiment, the first electrode (for example, serving as a cathode) of the optical sensing element DP may be made of a light-shielding material, and the second electrode (for example, serving as an anode) of the optical sensing element DP may be made of a light-transmitting material.

[0080] In an exemplary embodiment, the optical sensing element DP may be a PIN-type photodiode, or other device that can realize photoelectric conversion, and the embodiments of the present disclosure do not limit this. The PIN-type photodiode is a photosensitive diode, which is composed of a photoelectric conversion structure PIN (also called an intermediate photosensitive layer PIN) and electrodes at both ends. The light emitted by the light-emitting element in the sub-pixel shines on the intermediate photosensitive layer PIN, and the intermediate photosensitive layer PIN can absorb photons and convert them into electric charges. Therefore, according to the electric charge detected by the detection signal line SL, each sub-pixel can be compensated, and the uniformity of the display substrate can be improved.

[0081] In an exemplary embodiment, the material used to make the photoelectric conversion structure PIN may include: amorphous silicon.

[0082] In an exemplary embodiment, the photoelectric conversion structure PIN may include: a first doped layer, an intrinsic layer, and a second doped layer, wherein the first doped layer, the intrinsic layer, and the second doped layer overlap with the orthographic projection of the first electrode.

[0083] In an exemplary embodiment, the first doping layer and the second doping layer have different doping types, for example, the first doping layer may be one of a P-type semiconductor layer and an N-type semiconductor layer, and the second doping layer may be the other of the P-type semiconductor layer and the N-type semiconductor layer. For example, the thickness of the first doping layer may be approximately 200 angstroms to 700 angstroms. For example, the thickness of the second doping layer may be approximately 200 angstroms to 700 angstroms.

[0084] In an exemplary embodiment, the intrinsic layer may be an intrinsic amorphous silicon layer or an intrinsic germanium layer. For example, the thickness of the intrinsic layer may be about 5000 angstroms to 15000 angstroms. The doping concentration of the intrinsic layer is very low, so that the absorption coefficient of the intrinsic layer is very small, and the incident light can easily enter the interior of the material and generate a large number of electron-hole pairs after being fully absorbed, so that the photoelectric conversion efficiency is relatively high.

[0085] In the exemplary embodiment of the present disclosure, the working principle of the photoelectric conversion structure PIN is that the intrinsic layer is used to generate a large number of electron-hole pairs after absorbing incident light. Under the action of a strong electric field, the electrons in the intrinsic layer drift toward the N-type semiconductor layer and the holes drift toward the P-type semiconductor layer, thereby forming a photocurrent and converting the optical signal into an electrical signal.

[0086] In an exemplary embodiment, Figure 5 and Figure 6As shown, the orthographic projection of the first electrode 221 of the optical sensor element DP on the substrate 10 may at least partially overlap with the orthographic projection of the photoelectric conversion structure 222 of the optical sensor element DP on the substrate 10, and the orthographic projection of the second electrode 223 of the optical sensor element DP on the substrate 10 may at least partially overlap with the orthographic projection of the photoelectric conversion structure 222 of the optical sensor element DP on the substrate 10. For example, the orthographic projection of the first electrode 221 of the optical sensor element DP on the substrate 10 may coincide with the orthographic projection of the photoelectric conversion layer 222 of the optical sensor element DP on the substrate 10, and the orthographic projection of the second electrode 223 of the optical sensor element DP on the substrate 10 may coincide with the orthographic projection of the photoelectric conversion structure 222 of the optical sensor element DP on the substrate 10. In this way, the first electrode 221, the photoelectric conversion layer 222, and the second electrode 223 of the optical sensor element DP may be made using the same mask, which can reduce the manufacturing cost of the display substrate. Among them, Figure 5 and Figure 6 The description is made by taking the orthographic projection of the first electrode 221 of the optical sensing element DP on the substrate 10, the orthographic projection of the photoelectric conversion layer 222 of the optical sensing element DP on the substrate 10, and the orthographic projection of the second electrode 223 of the optical sensing element DP on the substrate 10 as an example. Here, in the exemplary embodiment of the present disclosure, the orthographic projection of "A" on the substrate coincides with the orthographic projection of "B" on the substrate, but may not completely coincide, and the existence of misalignment due to tolerance may be allowed.

[0087] In an exemplary embodiment, the light emitting element L is an organic light emitting diode (OLED) as an example. Figure 6 As shown, the light-emitting element 11 may include: an anode 41, an organic light-emitting layer 42, and a cathode 43 which are sequentially stacked in a direction away from the substrate 10. For example, the cathode 43 may be made of a light-transmitting material; the anode 41 may include a reflective layer and a light-transmitting layer, wherein the light-transmitting area is formed by the light-transmitting layer and the reflective layer. The orthographic projection of the light-transmitting layer on the substrate 10 at least partially overlaps with the orthographic projection of the optical sensor element on the substrate 10, and the overlapping area is the photosensitive area of ​​the optical sensor element to the light-emitting element. In this way, by patterning the anode of the light-emitting element, a light-transmitting design is implemented in the area of ​​the anode of the light-emitting element corresponding to the optical sensor element, so that the partial area of ​​the light-emitting element facing the optical sensor element is light-transmitting, so that the optical sensor element can receive the light emitted by the light-emitting element without occupying the opening area of ​​the light-emitting unit.

[0088] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0089] In an exemplary embodiment, the cathodes of the plurality of light emitting elements may be the same electrode. The cathode may be a planar electrode. When the cathodes of all the light emitting elements are the same electrode, the positive projection of the cathode on the substrate may cover the positive projection of the corresponding light emitting detection circuit on the substrate.

[0090] In an exemplary embodiment, the anode may be a transparent electrode, so that it can be ensured that the light emitted from the backlight side of the light emitting structure can enter the optical sensing element to perform optical compensation on the display substrate.

[0091] Fig. 7A is a schematic structural diagram of an active layer of a control transistor in an embodiment of the present disclosure, Figure 7B is another structural schematic diagram of the active layer of the control transistor in the embodiment of the present disclosure, Figure 7C FIG. 1 is another structural diagram of the active layer of the control transistor in the embodiment of the present disclosure. Fig. 7A and Figure 7B In the example, the control transistors in four sub-pixels share the same control signal line and the same detection signal line. Figure 7C In the figure, the control transistors in six sub-pixels share the same control signal line and the same detection signal line as an example for illustration.

[0092] In an exemplary embodiment, Figures 7A to 7CAs shown, the active layers 211 of the multiple control transistors M0 can be arranged radially around the center point pc. The center point pc is the intersection of a first reference line extending along the first direction and a second reference line extending along the second direction. For example, the first reference line can be a central axis of the active layers of the multiple control transistors extending along the first direction, and the second reference line can be a central axis of the active layers of the multiple control transistors extending along the second direction. For example, the first reference line can be a control signal line, and the center point pc can be the intersection of the control signal line and the central axis of the active layer of the control transistor. For example, the second reference line can be a detection signal line, and the center point pc can be the intersection of the central axis of the active layer of the control transistor and the detection signal line. For example, the first reference line can be a control signal line, the second reference line can be a detection signal line, and the center point pc can be the intersection of the control signal line and the detection signal line.

[0093] In an exemplary embodiment, the active layers 211 of the plurality of control transistors M0 may extend along a plurality of different directions. FIG. 7A to FIG. 7C As shown, the extending direction of the active layers of the plurality of control transistors M0 intersects with the first direction D1 and the second direction D2. Fig. 7A As shown, the angle between the extension directions of the active layers 211 of two adjacent control transistors M0 in the active layers 211 of the four control transistors M0 can be about 90 degrees, the angle between the extension direction of the active layer 211 of any one of the four control transistors M0 and the first direction D1 can be about 45 degrees, and the angle between the extension direction of the active layer 211 of any one of the four control transistors M0 and the second direction D2 can be about 45 degrees. Here, in the exemplary embodiments of the present disclosure, the present disclosure does not limit the setting angle of the first region of the control transistor and the setting angle of the active layer of the control transistor, and they can be set arbitrarily.

[0094] In an exemplary embodiment, FIG. 7A to FIG. 7C As shown, the active layer 211 of each control transistor M0 may include: a first region 31 (a region corresponding to the first pole of the control transistor M0), a second region 32 (a region corresponding to the second pole of the control transistor M0), and a channel region 33 (a region corresponding to the control pole of the control transistor M0) located between the first region 31 and the second region 32. Among them, the first regions 31 of multiple control transistors M0 may be interconnected to form a center point pc, or the first regions 31 of multiple control transistors may not be interconnected. Here, the embodiment of the present disclosure does not limit this.

[0095] For example, Fig. 7AAs shown, the first regions 31 of the four control transistors M0 may be connected to each other to form a center point pc, so that the shape of the active layers of the four control transistors M0 may be an "X" type; Figure 7B As shown, the first regions 31 of the four control transistors M0 may not be connected to each other, and the extension lines of the first regions 31 of the four control transistors M0 may intersect at the center point pc; Figure 7C As shown, the first regions 31 of the six control transistors M0 can be connected to each other to form a center point pc, so that the shape of the active layers of the six control transistors M0 can be a "*" type. Here, in the exemplary embodiments of the present disclosure, the present disclosure does not limit the number of control transistors forming the center point, the setting angle of the first region of the control transistor, and the shape of the active layer composition of the control transistor, and can be set arbitrarily.

[0096] Fig. 8A is a structural schematic diagram of a control electrode and a control signal line of a control transistor in an embodiment of the present disclosure, Figure 8B FIG. 1 is another structural diagram of the control electrode and the control signal line of the control transistor in the embodiment of the present disclosure. Fig. 8A In the example, the control transistors in four sub-pixels share the same control signal line. Figure 8B In the figure, the control transistors in six sub-pixels share the same control signal line as an example.

[0097] In an exemplary embodiment, Fig. 8A and Figure 8B As shown, the control electrodes 212 of the plurality of control transistors M0 are disposed in the same layer and made of the same material as the same control signal line G2.

[0098] In an exemplary embodiment, Fig. 8A and Figure 8B As shown, the control electrodes 212 of the plurality of control transistors M0 and the same control signal line G2 may be interconnected as an integral structure. In this way, by setting the control electrodes of the control transistors and the same control signal line as an integral structure, the wiring space can be saved, the space utilization rate can be improved, and a high-resolution design can be achieved. Here, in the exemplary embodiment of the present disclosure, A and B may be interconnected as an integral structure, which may mean that A and B are interconnected and A is a part of B, or A and B may be arranged in the same layer using the same material and A and B may be made by a single patterning process.

[0099] In an exemplary embodiment, Fig. 8A and Figure 8BAs shown, the control electrodes 212 of the multiple control transistors M0 can be connected to form a closed ring structure. Here, in the exemplary embodiment of the present disclosure, the closed ring does not necessarily mean a closed ring, or can be a closed polygon or other closed graphics, which is not limited in the embodiment of the present disclosure.

[0100] In an exemplary embodiment, Fig. 8A As shown, the same control signal line G2 shared by multiple control transistors M0 may include: a first control signal straight line segment L1 and a second control signal straight line segment L2, wherein in the first direction D1, the first control signal straight line segment L1 and the second control signal straight line segment L2 may be symmetrically distributed on both sides of the closed ring structure.

[0101] In an exemplary embodiment, the shape of the closed ring structure may include but is not limited to a polygon or a circle.

[0102] In an exemplary embodiment, taking the example that the control electrodes of the plurality of control transistors M0 can be connected to form a polygon, the number of sides of the polygon is the same as the number of the plurality of control transistors.

[0103] In an exemplary embodiment, taking the example that the control electrodes of multiple control transistors M0 can be spliced ​​together to form a polygon, the polygon can include but is not limited to any one of a triangle, a quadrilateral (such as a rhombus or a rectangle), a pentagon, a hexagon, a heptagon and an octagon. Here, in the exemplary embodiment of the present disclosure, the number of sides of the polygon formed by splicing the control electrodes of multiple control transistors together is not limited and can be set arbitrarily.

[0104] For example, Fig. 8A As shown, taking the example that the control transistors M0 in the four sub-pixels share the same control signal line, the polygon may be a rhombus, which may include: a first straight line segment L01, a second straight line segment L02, a third straight line segment L03 and a fourth straight line segment L04, wherein the first end of the first straight line segment L01 is connected to the first end of the second straight line segment L02, the second end of the first straight line segment L01 is connected to the first end of the fourth straight line segment L04, the second end of the second straight line segment L02 is connected to the first end of the third straight line segment L03, and the second end of the third straight line segment L03 is connected to the second end of the fourth straight line segment L04; one end of the first control signal straight line segment L1 is connected to both the second end of the first straight line segment L01 and the first end of the fourth straight line segment L04, the first control signal straight line segment L1 is connected to both the second end of the first straight line segment L01 and the first end of the fourth straight line segment L04, and one end of the second control signal straight line segment L2 is connected to both the second end of the second straight line segment L02 and the first end of the third straight line segment L03. For example, as Figure 8BAs shown, taking the example that the control transistors in six sub-pixels share the same control signal line, the polygon may be a hexagon.

[0105] In an exemplary embodiment, the geometric center of the closed ring structure formed by splicing the control electrodes of the multiple control transistors M0 coincides with the center point surrounded by the active layers 211 of the multiple control transistors M0 (for example, formed by connecting the first regions of the multiple control transistors M0). Here, in the exemplary embodiment of the present disclosure, the geometric center "coincides" with the center point, and the existence of misalignment caused by tolerance can be allowed.

[0106] In an exemplary embodiment, the orthographic projection of the sides of the polygon formed by splicing the control electrodes of multiple control transistors M0 together on the substrate intersects with the orthographic projections of the active layers of the multiple control transistors on the substrate, and has an overlapping area with the orthographic projections of the channel regions of the multiple control transistors on the substrate.

[0107] In an exemplary embodiment, a plurality of optical sensing elements correspondingly connected to a plurality of control transistors are distributed along the circumference of the closed ring structure. Here, in the exemplary embodiment of the present disclosure, the optical sensing element correspondingly connected to the control transistor may refer to the control transistor and the optical sensing element being located in the same sub-pixel.

[0108] Fig. 9A A schematic diagram of the structure of the first electrode and the second electrode of the control transistor and the detection signal line in the embodiment of the present disclosure, Fig. 9B is another structural schematic diagram of the first electrode and the second electrode of the control transistor and the detection signal line in the embodiment of the present disclosure, Fig. 9C FIG. 1 is another structural diagram of the first electrode and the second electrode of the control transistor and the detection signal line in the embodiment of the present disclosure. Fig. 9A and Fig. 9B In the example, the control transistors in four sub-pixels share the same detection signal line. Fig. 9C In the figure, the control transistors in six sub-pixels share the same detection signal line as an example.

[0109] In an exemplary embodiment, 9A to 9CAs shown, the first electrodes 213 of the plurality of control transistors M0, the second electrodes 214 of the plurality of control transistors M0, the same detection signal line SL shared by the plurality of control transistors M0, and the first electrodes 221 of the plurality of optical sensing elements DP connected to the plurality of control transistors M0 are arranged in the same layer and made of the same material. Here, in the exemplary embodiments of the present disclosure, the present disclosure does not limit whether the detection signal line SL and the first electrode 221 of the optical sensing element DP are arranged in the same layer and whether the same material is used. For example, the detection signal line SL and the first electrode 221 of the optical sensing element DP may be arranged in different layers, or the detection signal line SL and the first electrode 221 of the optical sensing element DP may be made of different materials, which can be arbitrarily set by those skilled in the art according to actual applications.

[0110] In an exemplary embodiment, 9A to 9C As shown, the first electrodes 213 of the plurality of control transistors M0 and the same detection signal line SL shared by the plurality of control transistors M0 are interconnected as an integral structure. In this way, by setting the first electrode of the control transistor and the same detection signal line as an integral structure, the wiring space can be saved, the space utilization rate can be improved, and a high-resolution design can be achieved. Here, in the exemplary embodiment of the present disclosure, A and B can be an interconnected integral structure, which can mean that A and B are interconnected and A is a part of B, or A and B can be set in the same layer using the same material and A and B can be made by a single patterning process.

[0111] In an exemplary embodiment, 9A to 9C As shown, the first electrodes 213 of the plurality of control transistors M0 may be connected to each other to form a polygonal structure. Fig. 9A and Fig. 9C As shown, the first electrodes 213 of the plurality of control transistors M0 may be connected to each other to form a rectangle having a width substantially equal to the width of the detection signal line SL. Fig. 9B As shown, the first electrodes 213 of the plurality of control transistors M0 are interconnected to form a quadrilateral structure whose width is greater than the width of the detection signal line SL. In this way, by setting the first electrodes of the control transistors to be connected to each other, the wiring space can be saved, the space utilization rate can be improved, and a high-resolution design can be achieved. Among them, the width refers to the size feature in the first direction D1. Here, the present disclosure does not limit the relative relationship between the width of the polygonal structure formed by the interconnection of the first electrodes 213 of the control transistors M0 and the width of the detection signal line SL, and can be set arbitrarily.

[0112] In an exemplary embodiment, the first electrodes 213 of the plurality of control transistors M0 may not be interconnected to form a polygonal structure, but may be directly connected to the first regions of the active layers 31 of the plurality of control transistors M0 through vias.

[0113] In an exemplary embodiment, Fig. 9A As shown, the same detection signal line SL shared by multiple control transistors M0 may include: a first detection signal straight line segment L3 and a second detection signal straight line segment L4, wherein, in the second direction D2, the first detection signal straight line segment L3 and the second detection signal straight line segment L4 are symmetrically distributed on both sides of a polygonal structure formed by interconnecting the first electrodes 213 of multiple control transistors M0.

[0114] In an exemplary embodiment, the geometric center of the polygonal structure formed by connecting the first electrodes 213 of the plurality of control transistors M0 coincides with the center point surrounded by the active layers 211 of the plurality of control transistors M0 (for example, formed by connecting the first regions of the plurality of control transistors M0). Here, in the exemplary embodiments of the present disclosure, the geometric center "coincides" with the center point, which means that the boundaries are not strictly defined, and the existence of misalignment caused by process and tolerance can be allowed.

[0115] In an exemplary embodiment, 9A to 9C As shown, the second electrodes 214 of the plurality of control transistors M0 and the first electrodes 221 of the corresponding optical sensing elements DP (for example, as cathodes) are interconnected as an integral structure. Here, in the exemplary embodiment of the present disclosure, A and B can be interconnected as an integral structure, which can mean that A and B are interconnected and A is a part of B, or A and B can be arranged in the same layer using the same material and A and B can be made by a single patterning process. In addition, the present disclosure does not limit whether the second electrode 214 of the control transistor M0 and the first electrode 221 of the corresponding optical sensing element DP are interconnected as an integral structure, whether they are arranged in the same layer, and whether they are made of the same material, and they can be set arbitrarily.

[0116] In an exemplary embodiment, the second electrodes 214 of the plurality of control transistors M0 are arranged in a polygonal structure formed by connecting the first electrodes 213 of the plurality of control transistors M0, and the second electrodes 214 of the plurality of control transistors M0 are connected to the second regions of the plurality of control transistors M0. Here, the present disclosure does not limit the structural parameters such as the arrangement position, spacing, and extension direction of any one of the second electrodes 214 of the control transistors M0, the first electrodes 213 of the control transistors M0, and the first electrodes 221 of the optical sensor element DP, and they can be set arbitrarily.

[0117] The structure of the display substrate in the embodiment of the present disclosure is described below with reference to the accompanying drawings, taking an example in which the display substrate is a top emission structure display substrate, the control transistor M0 is a top gate structure, and the control transistors M0 in four sub-pixels share the same control signal line G2 and the same detection signal line SL.

[0118] In an exemplary embodiment, the four sub-pixels may be arranged in an array in two rows and two columns in a first direction D1 and a second direction D2. For example, the four sub-pixels may include, but are not limited to, one or more of a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. This is not limited in the embodiments of the present disclosure.

[0119] For example, the four sub-pixels may be four sub-pixels in one pixel, or may include any two sub-pixels in two adjacent pixels, or may include any one sub-pixel in four adjacent pixels. Here, the embodiments of the present disclosure do not limit this.

[0120] In an exemplary embodiment, four sub-pixels are arranged in an array in two rows and two columns in the first direction D1 and the second direction D2 as an example, and the four sub-pixels are arranged around the center point. The control signal line G2 extends along the first direction D1, and the detection signal line SL extends along the second direction D2. The four sub-pixels arranged in an array in two rows and two columns are symmetrically distributed on both sides of the control signal line G2 with one control signal line G2 as the symmetry axis, and are symmetrically distributed on both sides of the detection signal line SL with one detection signal line SL as the symmetry axis.

[0121] In an exemplary embodiment, Figure 6 As shown, the display substrate may include: an active layer, a first insulating layer 61, a first metal layer, a second insulating layer 62, a first conductive layer, a photoelectric conversion layer, a second conductive layer, a third insulating layer 63 and a second metal layer sequentially stacked on a substrate 10. Here, the present disclosure does not limit the film parameters of the active layer, the first insulating layer, the first metal layer, the second insulating layer, the first conductive layer, the photoelectric conversion layer, the second conductive layer, the third insulating layer and the second metal layer, and they can be set arbitrarily.

[0122] In an exemplary embodiment, Fig. 7A As shown, the active layer may include: an active layer 211 of four control transistors M0, each active layer 211 of the control transistor M0 may include: a first region 31 (a region corresponding to the first electrode of the control transistor M0), a second region 32 (a region corresponding to the second electrode of the control transistor M0), and a channel region 33 (a region corresponding to the control electrode of the control transistor M0) located between the first region 31 and the second region 32, wherein the first regions 31 of the four control transistors M0 may be connected to each other to form a center point, the second regions 32 of the four control transistors M0 may be arranged around the center point pc, and the channel regions 33 of the four control transistors M0 may be arranged around the center point pc. For example, as Fig. 7AAs shown, the active layer 211 of the four control transistors M0 can be an integrated structure that is interconnected in an "X" shape. In this way, the manufacturing process can be simplified, the production cost can be reduced, and the total area occupied by the light detection circuit in the pixel area can be reduced, which is beneficial to reducing the area of ​​the pixel area, thereby achieving high resolution of the display product.

[0123] For example, the active layer can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the embodiments of the present disclosure are applicable to display substrates of thin film transistors manufactured based on oxide technology, silicon technology, and organic technology. For example, the active layer of the control transistor is made of metal oxide, which can reduce the leakage current of the control transistor and improve the display effect of the display substrate.

[0124] In an exemplary embodiment, Figure 6 As shown, the first insulating layer 61 , which may also be referred to as a gate insulating layer (GI), has an overlapped region between its orthographic projection on the substrate 10 and the orthographic projection on the substrate 10 of the control electrode 212 of the control transistor M0 .

[0125] In an exemplary embodiment, Fig.10 As shown, the first metal layer may include: four control electrodes 212 of control transistors M0 and a control signal line G2, wherein the control electrodes 212 of the four control transistors M0 are spliced ​​together to form a rhombus, and the four sides of the rhombus formed by splicing the control electrodes 212 of the four control transistors M0 are projected on the substrate, intersecting with the projected areas of the active layers of the multiple control transistors on the substrate, and having overlapping areas with the projected areas of the channel regions of the multiple control transistors on the substrate.

[0126] For example, the first metal layer can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd), molybdenum niobium alloy (MoNb), etc., can be a multi-layer metal, such as Mo / Cu / Mo, etc., or can be a stack structure formed by metal and transparent conductive material, such as ITO / Ag / ITO, etc.

[0127] In an exemplary embodiment, Fig.11A and Fig. 11B As shown, the second insulating layer may include: a first via hole K1 exposing a first region in the active layer of the control transistor M0 and a second via hole K2 exposing a second region in the active layer of the control transistor M0. Fig.11AAs shown, taking the example that the first regions 31 of the four control transistors M0 can be connected to form a center point, and the shape of the active layers of the four control transistors M0 can be "X" type, the number of the first via hole K1 is one, and the setting position of the first via hole K1 corresponds to the setting position of the center point. Fig. 11B As shown, taking the example that the first regions 31 of the four control transistors M0 may not be connected to each other, the number of the first vias K1 is four, and the locations of the first vias K1 correspond to the locations of the first regions 31 of the four control transistors M0. Fig.11A and Fig. 11B As shown, the number of the second via holes K2 is four, and the arrangement positions of the second via holes K2 correspond one-to-one to the arrangement positions of the second regions 32 of the four control transistors M0.

[0128] For example, the second insulating layer may be made of insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON), and may be a single layer, multiple layers or a composite layer. Generally, the second insulating layer may be referred to as an interlayer dielectric layer (ILD).

[0129] In an exemplary embodiment, Fig. 12A and Fig. 12B As shown, the first conductive layer may include: first electrodes 213 of four control transistors M0, second electrodes 214 of four control transistors M0, a same detection signal line SL shared by the four control transistors M0, and first electrodes 221 of four optical sensing elements DP connected to the four control transistors M0, wherein the geometric center of the polygonal structure formed by interconnecting the first electrodes 213 of the four control transistors M0 coincides with the center point surrounded by the active layers 211 of the four control transistors M0, the first electrodes 213 of the four control transistors M0 and the same detection signal line SL shared by the four control transistors M0 are an integrated structure interconnected, the second electrodes 214 of the four control transistors M0 and the first electrodes 221 (for example, as cathodes) of four corresponding optical sensing elements DP are an integrated structure interconnected; the first electrode 213 of the control transistor M0 is connected to the first region in the active layer of the control transistor M0 through the corresponding first via K1, and the second electrode 214 of the control transistor M0 is connected to the second region in the active layer of the control transistor M0 through the corresponding second via K2. Here, the present disclosure does not limit whether the second electrode 214 of the control transistor M0 and the first electrode 221 of the optical sensor element DP are arranged in the same layer and whether they use the same material. For example, the second electrode 214 of the control transistor M0 and the first electrode 221 of the optical sensor element DP can be arranged in different layers, or the second electrode 214 of the control transistor M0 and the first electrode 221 of the optical sensor element DP can use different materials and can be arranged arbitrarily.

[0130] For example, the material of the first conductive layer may be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0131] In an exemplary embodiment, Fig.13 As shown, the photoelectric conversion layer may include: photoelectric conversion structures 222 of four optical sensing elements DP, and the setting positions of the photoelectric conversion structures 222 of the four optical sensing elements DP correspond to the setting positions of the first electrodes 221 (for example, as cathodes) of the four optical sensing elements DP, so that the photoelectric conversion structures 222 of the optical sensing elements DP can be connected to the first electrodes 221 (for example, as cathodes) of the optical sensing elements DP. Here, in the exemplary embodiment of the present disclosure, the setting position of the photoelectric conversion structure 222 corresponds to the setting position of the first electrode 221 of the optical sensing element DP, which may mean that the orthographic projection of the photoelectric conversion structure 222 on the substrate and the orthographic projection of the first electrode 221 of the optical sensing element DP on the substrate have an overlapping area, or the orthographic projection of the photoelectric conversion structure 222 on the substrate coincides with the orthographic projection of the first electrode 221 of the optical sensing element DP on the substrate.

[0132] In an exemplary embodiment, Fig.14 As shown, the second conductive layer may include: second electrodes 223 of four optical sensing elements DP (for example, as anodes), wherein the arrangement positions of the second electrodes 223 of the four optical sensing elements DP correspond to the arrangement positions of the photoelectric conversion structures 222 of the four optical sensing elements DP. Here, in the exemplary embodiment of the present disclosure, the arrangement position of the photoelectric conversion structure 222 corresponds to the arrangement position of the second electrode 223 of the optical sensing element DP, which may mean that the orthographic projection of the photoelectric conversion structure 222 on the substrate and the orthographic projection of the second electrode 223 of the optical sensing element DP on the substrate have an overlapping area, or the orthographic projection of the photoelectric conversion structure 222 on the substrate coincides with the orthographic projection of the second electrode 223 of the optical sensing element DP on the substrate.

[0133] For example, the second conductive layer may be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0134] In an exemplary embodiment, Fig.15As shown, the third insulating layer may include: a third via hole K3 exposing the second electrode 223 of the optical sensing element DP, wherein the setting position of the third via hole K3 corresponds to the setting position of the second electrode 223 of the optical sensing element DP. Here, in the exemplary embodiment of the present disclosure, the setting position of the second electrode 223 of the optical sensing element DP corresponds to the setting position of the third via hole K3, which may mean that the orthographic projection of the second electrode 223 of the optical sensing element DP on the substrate and the orthographic projection of the third via hole K3 on the substrate have an overlapping area, and the setting position of the third via hole K3 is located on the side of the second electrode 223 of the optical sensing element DP away from the second via hole K2.

[0135] For example, the third insulating layer can be made of insulating materials such as resin, silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON), and can be a single layer, multiple layers or a composite layer. Usually, the third insulating layer can also be called a passivation (PVX) layer or a planarization layer (PLN).

[0136] In an exemplary embodiment, Figure 5 As shown, the second metal layer may include: a reference signal line V0, wherein the reference signal line V0 is connected to the second electrode 223 of the optical sensing element DP through a third via hole K3.

[0137] For example, the second metal layer can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd), molybdenum niobium alloy (MoNb), etc. It can be a multi-layer metal, such as Mo / Cu / Mo, etc., or it can be a stack structure formed by metal and transparent conductive material, such as ITO / Ag / ITO, etc.

[0138] The structure of the display substrate in the embodiment of the present disclosure is described below with reference to the accompanying drawings, taking an example in which the display substrate is a top emission structure display substrate, the control transistor M0 is a top gate structure, and the control transistors M0 in six sub-pixels share the same control signal line G2 and the same detection signal line SL.

[0139] In an exemplary embodiment, six sub-pixels may be arranged in an array in three rows and two columns in a first direction D1 and a second direction D2, wherein each column of sub-pixels is arranged in a zigzag shape. For example, the six sub-pixels may include, but are not limited to, a plurality of red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. Here, the embodiments of the present disclosure are not limited to this.

[0140] For example, the six sub-pixels may be six sub-pixels in one pixel, or may include any three sub-pixels in two adjacent pixels, or may include any two sub-pixels in three adjacent pixels, or may include any one sub-pixel in six adjacent pixels. This is not limited in the embodiments of the present disclosure.

[0141] In an exemplary embodiment, six sub-pixels are arranged in an array in three rows and two columns in the first direction D1 and the second direction D2, and the six sub-pixels are arranged around the center point. The control signal line G2 extends along the first direction D1, and the detection signal line SL extends along the second direction D2. The six sub-pixels arranged in an array in three rows and two columns are symmetrically distributed on both sides of the control signal line G2 with a control signal line G2 as the symmetry axis, and are symmetrically distributed on both sides of the detection signal line SL with a detection signal line SL as the symmetry axis.

[0142] In an exemplary embodiment, Figure 7C As shown, the active layer may include: six active layers 211 of control transistors M0, each active layer 211 of control transistor M0 may include: a first region 31 (a region corresponding to the first electrode of control transistor M0), a second region 32 (a region corresponding to the second electrode of control transistor M0), and a channel region 33 (a region corresponding to the control electrode of control transistor M0) located between the first region 31 and the second region 32, wherein the first regions 31 of the six control transistors M0 may be connected to each other to form a center point, the second regions 32 of the six control transistors M0 may be arranged around the center point, and the channel regions 33 of the six control transistors M0 may be arranged around the center point. For example, as Fig. 7A As shown, the active layer 211 of the six control transistors M0 can be an integrated structure that is interconnected in an "*" shape. In this way, the manufacturing process can be simplified, the production cost can be reduced, and the total area occupied by the light detection circuit in the pixel area can be reduced, which is beneficial to reducing the area of ​​the pixel area, thereby achieving high resolution of the display product.

[0143] In an exemplary embodiment, Fig.16 As shown, the first metal layer may include: six control electrodes 212 of control transistors M0 and a control signal line G2, wherein the control electrodes 212 of the six control transistors M0 are spliced ​​together to form a hexagon, and the six sides of the hexagon formed by the control electrodes 212 of the six control transistors M0 are projected on the substrate, intersecting with the projected areas of the active layers of the multiple control transistors on the substrate, and having overlapping areas with the projected areas of the channel regions of the multiple control transistors on the substrate.

[0144] In an exemplary embodiment, Fig.17As shown, the second insulating layer may include: a first via hole K1 exposing the first region in the active layer of the control transistor M0 and a second via hole K2 exposing the second region in the active layer of the control transistor M0. Taking the example that the first regions 31 of the six control transistors M0 can be connected to form a center point and the shape of the active layers of the six control transistors M0 can be "*" type, the number of the first via holes K1 can be one or more, and the setting position of the first via holes K1 corresponds to the setting position of the center point.

[0145] In an exemplary embodiment, Fig.18 As shown, the first conductive layer may include: first electrodes 213 of six control transistors M0, second electrodes 214 of six control transistors M0, a same detection signal line SL shared by the six control transistors M0, and first electrodes 221 of six optical sensing elements DP connected to the second electrodes 214 of the six control transistors M0, wherein the geometric center of the polygonal structure formed by interconnecting the first electrodes 213 of the six control transistors M0 coincides with the center point surrounded by the active layers 211 of the six control transistors M0, the first electrodes 213 of the six control transistors M0 and the same detection signal line SL shared by the six control transistors M0 may be an integrated structure connected to each other, the second electrodes 214 of the six control transistors M0 and the first electrodes 221 of the six corresponding optical sensing elements DP (for example, as cathodes) may be an integrated structure connected to each other; the first electrode 213 of the control transistor M0 is connected to the first region in the active layer of the control transistor M0 through the corresponding first via K1, and the second electrode 214 of the control transistor M0 is connected to the second region in the active layer of the control transistor M0 through the corresponding second via K2.

[0146] In an exemplary embodiment, Fig.19 As shown, the photoelectric conversion layer may include: six photoelectric conversion structures 222 of the optical sensing elements DP, and the arrangement positions of the photoelectric conversion structures 222 of the six optical sensing elements DP correspond to the arrangement positions of the first electrodes 221 (for example, as cathodes) of the six optical sensing elements DP, so that the photoelectric conversion structures 222 of the optical sensing elements DP can be connected to the first electrodes 221 (for example, as cathodes) of the optical sensing elements DP. Here, in the exemplary embodiment of the present disclosure, the arrangement position of the photoelectric conversion structure 222 corresponds to the arrangement position of the first electrode 221 of the optical sensing element DP, which may mean that the orthographic projection of the photoelectric conversion structure 222 on the substrate and the orthographic projection of the first electrode 221 of the optical sensing element DP on the substrate have an overlapping area, or the orthographic projection of the photoelectric conversion structure 222 on the substrate coincides with the orthographic projection of the first electrode 221 of the optical sensing element DP on the substrate.

[0147] In an exemplary embodiment, Fig. 20As shown, the second conductive layer may include: six second electrodes 223 of the optical sensing elements DP (for example, as anodes), wherein the arrangement positions of the second electrodes 223 of the six optical sensing elements DP correspond to the arrangement positions of the photoelectric conversion structures 222 of the six optical sensing elements DP. Here, in the exemplary embodiment of the present disclosure, the arrangement position of the photoelectric conversion structure 222 corresponds to the arrangement position of the second electrode 223 of the optical sensing element DP, which may mean that the orthographic projection of the photoelectric conversion structure 222 on the substrate and the orthographic projection of the second electrode 223 of the optical sensing element DP on the substrate have an overlapping area, or the orthographic projection of the photoelectric conversion structure 222 on the substrate coincides with the orthographic projection of the second electrode 223 of the optical sensing element DP on the substrate.

[0148] In an exemplary embodiment, Fig.21 As shown, the third insulating layer may include: a third via hole K3 exposing the second electrode 223 of the optical sensing element DP, wherein the setting position of the third via hole K3 corresponds to the setting position of the second electrode 223 of the optical sensing element DP. Here, in the exemplary embodiment of the present disclosure, the setting position of the second electrode 223 of the optical sensing element DP corresponds to the setting position of the third via hole K3, which may mean that the orthographic projection of the second electrode 223 of the optical sensing element DP on the substrate and the orthographic projection of the third via hole K3 on the substrate have an overlapping area, and the setting position of the third via hole K3 is located on the side of the second electrode 223 of the optical sensing element DP away from the second via hole K2.

[0149] In an exemplary embodiment, Fig. 22 As shown, the second metal layer may include: a reference signal line V0, wherein the reference signal line V0 is connected to the second electrode 223 of the optical sensing element DP through a third via hole K3.

[0150] The present disclosure also provides a display device, which may include: the display substrate in one or more of the above exemplary embodiments.

[0151] In an exemplary embodiment, the display substrate may include but is not limited to an OLED display substrate or a QLED display substrate.

[0152] In an exemplary embodiment, the display device may include but is not limited to an OLED display device or a QLED display device.

[0153] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator. Here, the embodiment of the present disclosure does not limit the type of the display device. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be described in detail here, nor should they be used as limitations on the present disclosure.

[0154] For technical details not disclosed in the embodiment of the display device of the present disclosure, those skilled in the art may refer to the description in the embodiment of the display substrate of the present disclosure for understanding, which will not be repeated here.

[0155] The technical solution of the present disclosure is explained below through the preparation process of the display substrate of the exemplary embodiment of the present disclosure. The "patterning process" mentioned in the embodiment of the present disclosure includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, and a known mature preparation process can be used. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, and etching can adopt known methods, which are not limited here. In the description of the exemplary embodiments of the present disclosure, "thin film" refers to a thin film made of a certain material on a substrate by deposition or other processes.

[0156] The embodiments of the present disclosure also provide a method for preparing a display substrate, and the display substrate may be the display substrate in one or more of the above embodiments.

[0157] In an exemplary embodiment, the preparation method may include:

[0158] Step 131: Provide a substrate.

[0159] Step 132: Form a plurality of light-emitting detection circuits, control signal lines extending along a first direction, and detection signal lines extending along a second direction on a substrate; wherein the light-emitting detection circuits include: an optical sensor element and a control transistor connected to the optical sensor element, wherein control electrodes of a plurality of control transistors are connected to the same control signal line, first electrodes of a plurality of control transistors are connected to the same detection signal line, and the first direction intersects with the second direction.

[0160] Step 133: forming a plurality of light-emitting elements on a substrate having a plurality of light-emitting detection circuits formed thereon; wherein each pixel comprises: a plurality of light-emitting elements, each light-emitting element corresponding one-to-one to a plurality of optical sensing elements in each light-emitting detection circuit unit.

[0161] Thus, the method for preparing a display substrate provided by the embodiment of the present disclosure, in which multiple light-emitting detection circuits corresponding to multiple light-emitting elements are prepared in the display substrate, and the control transistors in multiple sub-pixels share the same control signal line and the same detection signal line, can save wiring space, can reduce the occupied area of ​​the light-emitting detection circuit, can improve space utilization, and thus can achieve high resolution. Moreover, the preparation process of the display substrate can be simplified, saving preparation costs.

[0162] For technical details not disclosed in the embodiment of the method for preparing the display substrate of the present disclosure, those skilled in the art should refer to the description in the embodiment of the display substrate of the present disclosure for understanding, which will not be repeated here.

[0163] Although the embodiments disclosed in the present disclosure are as above, the above contents are only embodiments adopted for facilitating the understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, characterized in that: include: A substrate and a plurality of sub-pixels located on one side of the substrate; The plurality of sub-pixels include: a light emitting element and a light emitting detection circuit for detecting the light emitting brightness of the light emitting element; the light emitting detection circuit includes: an optical sensing element and a control transistor connected to the optical sensing element; It also includes: a control signal line extending along a first direction and a detection signal line extending along a second direction located on one side of the substrate; wherein control electrodes of a plurality of control transistors are connected to the same control signal line, first electrodes of the plurality of control transistors are connected to the same detection signal line, and the first direction intersects the second direction; The first electrodes of the plurality of control transistors, the second electrodes of the plurality of control transistors, the same detection signal line, and the first electrodes of the plurality of optical sensing elements corresponding to the plurality of control transistors are arranged in the same layer and made of the same material; The first electrodes of the plurality of control transistors and the same detection signal line are interconnected as an integrated structure; The first electrodes of the plurality of control transistors are connected to each other to form a polygonal structure; The same detection signal line includes: a first detection signal straight line segment and a second detection signal straight line segment, wherein in the second direction, the first detection signal straight line segment and the second detection signal straight line segment are symmetrically distributed on two sides of the polygonal structure.

2. The display substrate according to claim 1, characterized in that: The active layers of the plurality of control transistors are radially arranged around a center point, wherein the center point is an intersection of a first reference line extending along a first direction and a second reference line extending along a second direction.

3. The display substrate according to claim 2, characterized in that: The active layer of the control transistor includes: a first region, a second region, and a channel region located between the first region and the second region, wherein the first regions of the plurality of control transistors are connected to each other to form the central point.

4. The display substrate according to claim 2, characterized in that: The control electrodes of the plurality of control transistors are connected to the same control signal line in an integrated structure.

5. The display substrate according to claim 4, characterized in that: The control electrodes of the plurality of control transistors are connected to each other to form a closed ring structure; The same control signal line includes: a first control signal straight line segment and a second control signal straight line segment, wherein in a first direction, the first control signal straight line segment and the second control signal straight line segment are symmetrically distributed on both sides of the closed ring structure.

6. The display substrate according to claim 5, characterized in that: The shape of the closed annular structure is polygonal or circular.

7. The display substrate according to claim 6, characterized in that: The orthographic projection of the edge of the polygon on the substrate intersects with the orthographic projection of the active layers of the multiple control transistors on the substrate, and has an overlapping area with the orthographic projection of the channel regions of the multiple control transistors on the substrate.

8. The display substrate according to claim 6, characterized in that: The number of sides of the polygon is the same as the number of the plurality of control transistors.

9. The display substrate according to claim 6, characterized in that: The geometric center of the closed annular structure coincides with the center point.

10. The display substrate according to claim 5, characterized in that: A plurality of optical sensing elements connected to the plurality of control transistors are distributed along the circumference of the closed ring structure.

11. The display substrate according to claim 2, characterized in that: The geometric center of the polygonal structure coincides with the center point.

12. The display substrate according to claim 1, characterized in that: The second electrodes of the plurality of control transistors and the first electrodes of the plurality of optical sensing elements are an integrated structure connected to each other.

13. The display substrate according to claim 1, characterized in that: The number of the multiple control transistors is four, wherein in a first direction, the four optical sensor elements connected to the four control transistors are symmetrically distributed on both sides of the same control signal line with the same control signal line as a symmetry axis, and in a second direction, the four optical sensor elements are symmetrically distributed on both sides of the same detection signal line with the same detection signal line as a symmetry axis.

14. The display substrate according to claim 13, characterized in that: The light-emitting colors of the four sub-pixels where the four control transistors are located include at least one of red, green, blue and white.

15. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 14.

16. A method for preparing a display substrate, characterized in that: The display substrate is a display substrate according to any one of claims 1 to 14, and the preparation method comprises: providing a substrate; forming a plurality of light emitting detection circuits, control signal lines extending along a first direction, and detection signal lines extending along a second direction on the substrate; A plurality of light emitting elements are formed on the substrate on which the plurality of light emitting detection circuits are formed.

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