Package structure and testing method

Abstract

A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device, and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to an interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device via the interconnection portion of the conductive circuit layer.

Description

Technical Field

[0001] This disclosure relates to a packaging structure and a testing method, specifically a packaging structure comprising a wiring structure having at least one test circuit structure, and a method for testing the packaging structure. Background Technology

[0002] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor package structures are being integrated with an increasing number of electronic components or devices to achieve improved electrical performance and additional functionality. Consequently, warping of semiconductor package structures may occur during thermal processing. Because semiconductor package structures have relatively low rigidity or hardness, cracks may form on the top surface of the semiconductor package structure or within the protective material, and these cracks may extend or grow into the interior of the semiconductor package structure. If the crack reaches the semiconductor package structure, the conductive circuit layers within the semiconductor package structure may break or be damaged, potentially leading to an open circuit and rendering the semiconductor package structure inoperable. Therefore, the yield of the semiconductor package structure may be reduced. Summary of the Invention

[0003] In some embodiments, a package structure includes a wiring structure, a first electronic device, and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to an interconnect portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device via an interconnect portion of the conductive circuit layer.

[0004] In some embodiments, a testing method includes: (a) providing a package structure, wherein the package structure includes a first electronic device, a second electronic device electrically connected to the first electronic device via at least one conductive circuit layer, and at least one test circuit structure disposed adjacent to the at least one conductive circuit layer; and (b) testing the at least one test circuit structure. Attached Figure Description

[0005] When read in conjunction with the accompanying drawings, various aspects of some embodiments of this disclosure will be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0006] Figure 1 A top view of a packaging structure according to some embodiments of the present disclosure is shown.

[0007] Figure 2 Show Figure 1An enlarged view of area "A" in the diagram, wherein the first electronic device, the second electronic device, the first protective material, and the first dielectric layer are omitted for clarity.

[0008] Figure 2A A top view showing the interconnect portions and test circuit structure according to some embodiments of the present disclosure is provided.

[0009] Figure 3 Show Figure 2 A three-dimensional image.

[0010] Figure 4 Show Figure 1 The encapsulation structure is a cross-sectional view taken along line 4-4.

[0011] Figure 5 Show Figure 1 The encapsulation structure is shown in a cross-sectional view taken along line 5-5.

[0012] Figure 6 Show Figure 1 The encapsulation structure is shown in a cross-sectional view taken along line 6-6.

[0013] Figure 7 A cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown.

[0014] Figure 8 A cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown.

[0015] Figure 9 A cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown.

[0016] Figure 10 A cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown.

[0017] Figure 11 A perspective view of the test circuit structure and interconnection portions according to some embodiments of the present disclosure is shown.

[0018] Figure 12 A perspective view of the test circuit structure and interconnection portions according to some embodiments of the present disclosure is shown.

[0019] Figure 13 A cross-sectional view of an assembly structure according to some embodiments of the present disclosure is shown.

[0020] Figure 14 This illustrates one or more stages of an example of a test method according to some embodiments of the present disclosure.

[0021] Figure 15 This illustrates one or more stages of an example of a test method according to some embodiments of the present disclosure.

[0022] Figure 16 This illustrates one or more stages of an example of a test method according to some embodiments of the present disclosure.

[0023] Figure 17 This illustrates one or more stages of an example of a test method according to some embodiments of the present disclosure.

[0024] Figure 18 This illustrates one or more stages of an example of a test method according to some embodiments of the present disclosure.

[0025] Figure 19 This illustrates one or more stages of an example of a test method according to some embodiments of the present disclosure.

[0026] Figure 20 This illustrates one or more stages of an example of a test method according to some embodiments of the present disclosure.

[0027] Figure 21 This illustrates one or more stages of an example of a test method according to some embodiments of the present disclosure. Detailed Implementation

[0028] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, embodiments in which a first feature is formed above or on a second feature may include instances where the first and second features are formed or disposed in direct contact, and embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0030] At least some embodiments of this disclosure provide wiring structures including at least one test circuit structure. In some embodiments, a package structure includes this wiring structure such that the test circuit structure can be tested, and the result of this test can simulate the condition of the conductive circuit layers of the wiring structure. At least some embodiments of this disclosure further provide techniques for testing package structures.

[0031] Figure 1 A top view of the packaging structure 3 according to some embodiments of the present disclosure is shown. Figure 2 Show Figure 1 An enlarged view of area "A" in the diagram, wherein the first electronic device 24, the second electronic device 26, the first protective material 32, and the first dielectric layer 141 are omitted for clarity. Figure 2A A top view is shown of the interconnect portion 15a and the test circuit structure 17 according to some embodiments of the present disclosure. Figure 3 Show Figure 2 A three-dimensional image. Figure 4 Show Figure 1 The encapsulation structure 3 is a cross-sectional view taken along line 4-4. Figure 5 Show Figure 1 A cross-sectional view of the encapsulation structure 3 taken along line 5-5. (See attached image.) Figure 4 and Figure 5 As shown, the packaging structure 3 includes a wiring structure 1, a first electronic device 24, a second electronic device 26, a first protective material 32, an encapsulant 34, and multiple solder materials 36. Figure 1 As shown, the packaging structure 3 may include one first electronic device 24 and two second electronic devices 26. However, the number of the first electronic device 24 and the second electronic device 26 is not limited in this disclosure.

[0032] like Figure 4 and Figure 5 As shown, the wiring structure 1 has a first surface 11 (e.g., a top surface), a second surface 12 (e.g., a bottom surface) opposite to the first surface 11, and a side surface 13 extending between the first surface 11 and the second surface 12. The wiring structure 1 may include at least one dielectric layer 14, at least one conductive circuit layer 15 in contact with the dielectric layer 14, at least one test circuit structure 17 in contact with the dielectric layer 14, and a plurality of protruding pads 20. The wiring structure 1 may further include a first chip bonding region 18, a second chip bonding region 19, and a high line density region 16 (or fine line region) disposed between the first chip bonding region 18 and the second chip bonding region 19. A first electronic device 24 may be attached to the first chip bonding region 18, and a second electronic device 26 may be attached to the second chip bonding region 19. Therefore, the high line density region 16 (or fine line region) may be disposed between the first electronic device 24 and the second electronic device 26.

[0033] For example, such as Figure 4 and 5As shown, the wiring structure 1 includes a first dielectric layer 141, a first conductive circuit layer 151, a second dielectric layer 142, a second conductive circuit layer 152, a third dielectric layer 143, a third conductive circuit layer 153, a fourth dielectric layer 144, a fourth conductive circuit layer 154, and a fifth dielectric layer 145. That is, the at least one dielectric layer 14 includes the first dielectric layer 141, the second dielectric layer 142, the third dielectric layer 143, the fourth dielectric layer 144, and the fifth dielectric layer 145. The at least one conductive circuit layer 15 includes the first conductive circuit layer 151, the second conductive circuit layer 152, the third conductive circuit layer 153, and the fourth conductive circuit layer 154.

[0034] The first dielectric layer 141 may be the topmost or outermost dielectric layer of the wiring structure 1. The first conductive circuit layer 151 may be the topmost or outermost conductive circuit layer of the wiring structure 1. The material of the first conductive circuit layer 151 may include, for example, copper, another conductive metal, or an alloy thereof. The material of the first dielectric layer 141 may include an insulating material, a passivating material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB)-based polymer or polyimide (PI). In some embodiments, the first dielectric layer 141 may be made of a photoimageable material. Additionally, the first surface 11 of the wiring structure 1 may be the top surface of the first dielectric layer 141. The first conductive circuit layer 151 is disposed adjacent to the top surface of the first dielectric layer 141. In some embodiments, the first conductive circuit layer 151 is embedded in the first dielectric layer 141 and exposed from the top surface of the first dielectric layer 141. In other words, the first dielectric layer 141 covers the first conductive circuit layer 151 and defines a plurality of openings to expose portions of the first conductive circuit layer 151.

[0035] Furthermore, the first conductive circuit layer 151 may include an interconnect portion 15a and a peripheral portion 15b. The first conductive circuit layer 151 may be the topmost or outermost conductive circuit layer of the wiring structure 1. The interconnect portion 15a is located in the high line density region 16, and the peripheral portion 15b is located in a region outside the high line density region 16 (e.g., a low line density region). For example, a second electronic device 26 may be electrically connected to a first electronic device 24 via the interconnect portion 15a of the first conductive circuit layer 151. The second electronic device 26 and the first electronic device 24 may be electrically connected to the bonding material 36 on the second surface 12 of the wiring structure 1 via the peripheral portion 15b of the first conductive circuit layer 151. In some embodiments, the interconnect portion 15a of the first conductive circuit layer 151 may include a plurality of conductive traces 15' parallel to each other, and the peripheral portion 15b of the first conductive circuit layer 151 may include a plurality of conductive traces 15"". The line width / line space (L / S) of the conductive traces 15' of the interconnect portion 15a may be smaller than the L / S of the conductive traces 15" of the peripheral portion 15b. For example, the L / S of the conductive traces 15' of the interconnect portion 15a may be less than or equal to about 5 μm / about 5 μm, or less than or equal to about 2 μm / about 2 μm, or less than or equal to about 0.8 μm / about 0.8 μm. The L / S of the conductive traces 15" of the peripheral portion 15b may be less than or equal to about 10 μm / about 10 μm, or less than or equal to about 7 μm / about 7 μm, or less than or equal to about 5 μm / about 5 μm.

[0036] A first dielectric layer 141 and a first conductive circuit layer 151 may be disposed on a second dielectric layer 142. Furthermore, the second dielectric layer 142 may cover the second conductive circuit layer 152. A portion of the first conductive circuit layer 151 (i.e., the via portion 15c) extends through the second dielectric layer 142 to electrically connect the second conductive circuit layer 152. The material of the second dielectric layer 142 may be the same as or similar to the material of the first dielectric layer 141. The second conductive circuit layer 152 may also include an interconnect portion 15a located in a high line density region 16 and a peripheral portion 15b located outside the high line density region 16. In some embodiments, the via portion 15c of the first conductive circuit layer 151 may extend from the peripheral portion 15b, and they may be formed simultaneously and integrally.

[0037] Similarly, the second dielectric layer 142 and the second conductive circuit layer 152 may be disposed on the third dielectric layer 143. Furthermore, the third dielectric layer 143 may cover the third conductive circuit layer 153. A portion of the second conductive circuit layer 152 (i.e., the via portion 15c) extends through the third dielectric layer 143 to electrically connect to the third conductive circuit layer 153. The material of the third dielectric layer 143 may be the same as or similar to the material of the second dielectric layer 142. The third conductive circuit layer 153 may also include an interconnect portion 15a located in the high line density region 16 and a peripheral portion 15b located outside the high line density region 16. In some embodiments, the via portion 15c of the second conductive circuit layer 152 may extend from the peripheral portion 15b, and they may be formed simultaneously and integrally.

[0038] Similarly, a third dielectric layer 143 and a third conductive circuit layer 153 may be disposed on a fourth dielectric layer 144. Furthermore, the fourth dielectric layer 144 may cover the fourth conductive circuit layer 154. A portion of the third conductive circuit layer 153 (i.e., the via portion 15c) extends through the fourth dielectric layer 144 to electrically connect to the fourth conductive circuit layer 154. The material of the fourth dielectric layer 144 may be the same as or similar to the material of the third dielectric layer 143. The fourth conductive circuit layer 154 may also include an interconnect portion 15a located in the high line density region 16 and a peripheral portion 15b located outside the high line density region 16.

[0039] A fourth dielectric layer 144 and a fourth conductive circuit layer 154 may be disposed on a fifth dielectric layer 145. A portion of the fourth conductive circuit layer 154 (i.e., the via portion 15c) extends through the fifth dielectric layer 145 to be exposed from the bottom surface of the fifth dielectric layer 145 (e.g., the second surface 12 of the wiring structure 1). The material of the fifth dielectric layer 145 may be the same as or similar to the material of the fourth dielectric layer 144. Figure 4 and Figure 5 As shown, the second electronic device 26 can be electrically connected to the first electronic device 24 via an interconnect portion 15a of the conductive circuit layer 15 (including, for example, the interconnect portion 15a of the first conductive circuit layer 151, the second conductive circuit layer 152, the third conductive circuit layer 153, and the fourth conductive circuit layer 154). The second electronic device 26 and the first electronic device 24 can be electrically connected to the bonding material 36 via a via portion 15c of a peripheral portion 15b of the conductive circuit layer 15 (including, for example, the peripheral portion 15b of the first conductive circuit layer 151, the second conductive circuit layer 152, the third conductive circuit layer 153, and the fourth conductive circuit layer 154).

[0040] The protruding pad 20 may be disposed on and protrude from the first dielectric layer 141 (i.e., the topmost or outermost dielectric layer) of the wiring structure 1. The protruding pad 20 may be disposed on and protrude from the first surface 11 of the wiring structure 1, and extend through the first dielectric layer 141 (i.e., the topmost or outermost dielectric layer) to electrically connect to the first conductive circuit layer 151. The protruding pad 20 may include a plurality of first protruding pads 21 corresponding to the first electronic device 24 and a plurality of second protruding pads 22 corresponding to the second electronic device 26.

[0041] First electronic device 24 and second electronic device 26 are arranged side-by-side adjacent to the first surface 11 of wiring structure 1 and electrically connected to the conductive circuit layer 15 of wiring structure 1. First electronic device 24 may be a semiconductor device, such as an application-specific integrated circuit (ASIC) die. Figure 4 and Figure 5 As shown, the first electronic device 24 may have a first active surface 241, a first back surface 242 opposite to the first active surface 241, and a side surface 243 extending between the first active surface 241 and the first back surface 242. The first electronic device 24 may have a first active region 246 on the first active surface 241. Multiple circuits and multiple electrical components are disposed within the first active region 246. Furthermore, the first electronic device 24 may include a plurality of first electrical contacts 244 disposed adjacent to the first active surface 241. The first electrical contacts 244 may be exposed or protruding from the first active surface 241 for electrical connection. The first electrical contacts 244 may be pads, bumps, studs, pillars, or posts. In some embodiments, the first electrical contacts 244 of the first electronic device 24 may be electrically connected and physically connected to a first protruding pad 21 via a plurality of bonding materials 245. In other words, the first electronic device 24 may be electrically connected to the wiring structure 1 via flip-chip bonding. For example, the first electrical contact 244 may comprise copper, gold, platinum and / or other suitable materials.

[0042] The second electronic device 26 can be a semiconductor device, such as a high bandwidth memory (HBM) die. Figure 4 and Figure 5As shown, the second electronic device 26 may have a second active surface 261, a second back surface 262 opposite to the second active surface 261, and a side surface 263 extending between the second active surface 261 and the second back surface 262. The second electronic device 26 may have a second active region 266 on the second active surface 261. Multiple circuits and multiple electrical components are disposed within the second active region 266. Furthermore, the second electronic device 26 may include a plurality of second electrical contacts 264 disposed adjacent to the second active surface 261. The second electrical contacts 264 may be exposed or protruding from the second active surface 261 for electrical connection. The second electrical contacts 264 may be pads, bumps, posts, pillars, or struts. In some embodiments, the second electrical contacts 264 of the second electronic device 26 may be electrically connected and physically connected to a second protruding pad 22 via a plurality of bonding materials 265. In other words, the second electronic device 26 may be electrically connected to the wiring structure 1 via flip-chip bonding. For example, the second electrical contact 264 may contain copper, gold, platinum and / or other suitable materials.

[0043] like Figures 1 to 3 As shown, the test circuit structure 17 can be positioned adjacent to the interconnect portion 15a of the conductive circuit layer 15. In some embodiments, the wiring structure 1 may include a plurality of interconnect portions 15a, a plurality of test circuit structures 17, and a plurality of shielding walls 155. The interconnect portions 15a, test circuit structures 17, and shielding walls 155 can be positioned on the same layer and can be formed simultaneously. Therefore, the materials of the test circuit structures 17 and the shielding walls 155 can be the same as the materials of the interconnect portions 15a, and the thicknesses of the test circuit structures 17 and the shielding walls 155 can be the same as the thicknesses of the interconnect portions 15a. The outermost dielectric layer (i.e., the first dielectric layer 141) can cover the outermost conductive circuit layer (i.e., the first conductive circuit layer 151) and the test circuit structures 17. In some embodiments, the first conductive circuit layer 151, the test circuit structures 17, and the shielding walls 155 can constitute the first metal layer (i.e., the topmost metal layer) of the wiring structure 1. Furthermore, the wiring structure 1 may further include a second metal layer containing a second conductive circuit layer 152, a third metal layer containing a third conductive circuit layer 153, and a fourth metal layer containing a fourth conductive circuit layer 154. In some embodiments, the first metal layer and the third metal layer may be signal transmission layers, and the second metal layer and the fourth metal layer may be power / ground layers.

[0044] Furthermore, interconnect portions 15a are arranged adjacent to each other. Test circuit structure 17 is arranged on both sides of interconnect portions 15a. Some shielding walls 155 may be arranged between interconnect portions 15a to prevent crosstalk between interconnect portions 15a. Some shielding walls 155 may be arranged between interconnect portions 15a and test circuit structure 17 to prevent crosstalk between interconnect portions 15a and test circuit structure 17. It should be noted that shielding walls 155 may or may not be electrically connected to the ground plane. Test circuit structure 17 and shielding walls 155 may be located in high line density region 16. Therefore, interconnect portions 15a, test circuit structure 17 and shielding walls 155 are arranged below the gap 30 between side 243 of the first electronic device 24 and side 263 of the second electronic device 26. That is, the two ends of interconnect portions 15a extend to the first chip bonding region 18 and the second chip bonding region 19, respectively. A first portion of the interconnect portion 15a is disposed within the vertical projection of the first active region 246 of the first electronic device 24, and a second portion of the interconnect portion 15a is disposed within the vertical projection of the second active region 266 of the second electronic device 26. Furthermore, both ends of the test circuit structure 17 extend to the first chip bonding region 18 and the second chip bonding region 19, respectively. Both ends of the shielding wall 155 extend to the first chip bonding region 18 and the second chip bonding region 19, respectively. The first portion of the test circuit structure 17 is disposed within the vertical projection of the first active region 246 of the first electronic device 24, and the second portion of the test circuit structure 17 is disposed within the vertical projection of the second active region 266 of the second electronic device 26. That is, the first portion of the test circuit structure 17 extends into the space below the first electronic device 24, and the second portion of the test circuit structure 17 extends into the space below the second electronic device 26.

[0045] In some embodiments, the test circuit structure 17 may be dummy and may not be electrically connected to the interconnect portion 15a of the conductive circuit layer 15. That is, the test circuit structure 17 may be electrically isolated from the interconnect portion 15a of the conductive circuit layer 15. Furthermore, the test circuit structure 17 may be electrically isolated from the first electronic device 24 and the second electronic device 26. For example, the interconnect portion 15a of the conductive circuit layer 15 may be used to transmit signals (e.g., digital signals) between the first electronic device 24 and the second electronic device 26, while the test circuit structure 17 does not have the function of transmitting signals (e.g., digital signals). Therefore, the test circuit structure 17 may be electrically isolated from the digital signal transmission path of the package structure 3.

[0046] like Figure 2As shown, the form (or pattern or layout) of the test circuit structure 17 may be similar to or the same as the form (or pattern or layout) of the interconnect portion 15a of the conductive circuit layer 15. For example, the test circuit structure 17 may include multiple segments 171 parallel to each other. The linewidth / spacing (L / S) of the segment 171 of the test circuit structure 17 may be substantially equal to the linewidth / spacing (L / S) of the conductive trace 15' of the interconnect portion 15a. Furthermore, the conductive trace 15' of the interconnect portion 15a and the shielding wall 155 may be substantially parallel to the segment 171 of the test circuit structure 17. In addition, the width of the shielding wall 155 may be, for example, two, three, four, or five times larger than the width of the conductive trace 15' of the interconnect portion 15a, or greater.

[0047] In some embodiments, the gap between the interconnect portion 15a and the shielding wall 155 of the conductive circuit layer 15 may be substantially equal to the line space between the conductive traces 15' of the interconnect portion 15a. The gap between the test circuit structure 17 and the shielding wall 155 may be substantially equal to the line space between the conductive traces 15' of the interconnect portion 15a. If the shielding wall 155 is omitted, the gap between the test circuit structure 17 and the interconnect portion 15a may be substantially equal to the line space between the conductive traces 15' of the interconnect portion 15a.

[0048] like Figure 2A As shown, an angle may be formed between the conductive trace 15' of the interconnect portion 15a and the segment 171 of the test circuit structure 17. This angle may be less than 90 degrees, 60 degrees, 45 degrees, 30 degrees, or 15 degrees. Therefore, the conductive trace 15' of the interconnect portion 15a is not perpendicular to the segment 171 of the test circuit structure 17.

[0049] like Figure 2 and Figure 3 As shown, segments 171 of each of the test circuit structures 17 are connected in series with each other. In some embodiments, each of the test circuit structures 17 may be serpentine in shape. Furthermore, the test circuit structures 17 may be electrically connected to each other via connection portions 175. The connection portions 175 may be located in or outside the high line density region 16. Furthermore, the connection portions 175 and the test circuit structures 17 may be disposed on the same layer or on different layers. In some embodiments, the connection portions 175 may be disposed directly above or directly below the interconnection portion 15a.

[0050] like Figure 3 and Figure 5As shown, one end of the test circuit structure 17 can be electrically connected to the second surface 12 of the wiring structure 1. For example, the outermost segment 171 of one of the test circuit structures 17 may have an electrical connection end 172, which is electrically connected downward to the second surface 12 of the wiring structure 1 via a downward electrical path 174. The downward electrical path 174 may include via portions 15c of a first conductive circuit layer 151, via portions 15c of a second conductive circuit layer 152, via portions 15c of a third conductive circuit layer 153, and via portions 15c of a fourth conductive circuit layer 154. It should be noted that the exposed via portion 15c of the fourth conductive circuit layer 154 may be for probe 91 ( Figure 18 The electrical contacts are connected to the test circuit structure 17. For example, the outermost segment 171 of another part of the test circuit structure 17 may have an electrical connection terminal 173, which is connected via a downward electrical path 176. Figure 6 The downward electrical path 174 is electrically connected to the second surface 12 of the wiring structure 1. The downward electrical path 176 may include via portions 15c of the first conductive circuit layer 151, the second conductive circuit layer 152, the third conductive circuit layer 153, and the fourth conductive circuit layer 154. It should be noted that the exposed via portion 15c of the fourth conductive circuit layer 154 may be an electrical contact for probe contact. The test circuit structure 17 is electrically connected to the electrical contact. Therefore, the test circuit structure 17 is not electrically connected upwards to the first electronic device 24 and the second electronic device 26. There is no protruding pad 20 on the test circuit structure 17. The test circuit structure 17 may not contain upward electrical connections. In some embodiments, the downward electrical paths 174 and 176 are independent electrical paths in the wiring structure 1.

[0051] like Figure 4 and Figure 5 As shown, a first protective material 32 (i.e., underfill) is disposed in a first space 25 between the first electronic device 24 and the wiring structure 1, and in a second space 27 between the second electronic device 26 and the wiring structure 1, to cover and protect the joint structure formed by the first electrical contact 244, the first protruding pad 21, and the bonding material 245, and the joint structure formed by the second electrical contact 264, the second protruding pad 22, and the bonding material 265. Furthermore, the first protective material 32 may extend further into the gap 30 between the side surface 243 of the first electronic device 24 and the side surface 263 of the second electronic device 26.

[0052] The package 34 (i.e., the second protective material) covers at least a portion of the first surface 11 of the wiring structure 1, at least a portion of the first electronic device 24, at least a portion of the second electronic device 26, and the first protective material 32. The material of the package 34 may be a molding compound with or without filler. The package 34 has a first surface 341 (e.g., a top surface) and side surfaces 343. In some embodiments, the first surface 341 of the package 34, the first back surface 242 of the first electronic device 24, the second back surface 262 of the second electronic device 26, and the top surface of the first protective material 32 in the gap 30 may be substantially coplanar with each other. However, in other embodiments, the top surface of the first protective material 32 in the gap 30 may be recessed from the first back surface 242 of the first electronic device 24 and / or the second back surface 262 of the second electronic device 26. Thus, a portion of the package 34 may extend into the gap 30 between the first electronic device 24 and the second electronic device 26. Furthermore, the side surfaces 343 of the package 34 may be substantially coplanar with the side surfaces 13 of the wiring structure 1.

[0053] The bonding material 36 (e.g., solder ball) may be positioned adjacent to the second surface 12 of the wiring structure 1 for external connection. Figure 4 and Figure 5 As shown, bonding material 36 is disposed on the exposed portion (i.e., the bottom portion of via portion 15c) of the fourth conductive circuit layer 154. In some embodiments, bonding material 36 may include test bonding material 361. Test bonding material 361 is electrically connected to the downward electrical path 174. Therefore, test bonding material 361 is electrically connected to the electrical connection terminal 172 of the outermost segment 171 of the test circuit structure 17 via via portions 15c of the first conductive circuit layer 151, via portions 15c of the second conductive circuit layer 152, via portions 15c of the third conductive circuit layer 153, and via portions 15c of the fourth conductive circuit layer 154.

[0054] Figure 6 Show Figure 1 A cross-sectional view of the package structure 3 taken along line 6-6. The outermost segment 171 of one of the test circuit structures 17 may have an electrical connection terminal 173, which is connected via a downward electrical path 176 (…). Figure 3The downward electrical path 176 is electrically connected to the second surface 12 of the wiring structure 1. The downward electrical path 176 may include via portions 15c of the first conductive circuit layer 151, the second conductive circuit layer 152, the third conductive circuit layer 153, and the fourth conductive circuit layer 154. In some embodiments, the bonding material 36 may include a test bonding material 362. The test bonding material 362 is electrically connected to the downward electrical path 176. Therefore, the test bonding material 362 is electrically connected to the electrical connection terminal 173 of the outermost segment 171 of the test circuit structure 17 via the via portions 15c of the first conductive circuit layer 151, the second conductive circuit layer 152, the third conductive circuit layer 153, and the fourth conductive circuit layer 154.

[0055] exist Figures 1 to 6 In the illustrated embodiment, the form (or pattern or layout) of the test circuit structure 17 may be similar to or the same as the form (or pattern or layout) of the interconnect portion 15a of the conductive circuit layer 15. Therefore, the test circuit structure 17 can simulate the condition of the interconnect portion 15a of the conductive circuit layer 15. That is, if a segment 171 of the test circuit structure 17 breaks or is damaged, and an open circuit occurs in the test circuit structure 17, then the interconnect portion 15a of the conductive circuit layer 15 can be considered broken or damaged. In the package structure 3, if a crack forms at the top surface of the first protective material 32 in the gap 30 and the crack extends or grows downwards to cause the interconnect portion 15a of the conductive circuit layer 15 to break or be damaged, this crack may also cause the test circuit structure 17 to break or be damaged simultaneously. Therefore, during the testing phase, the test circuit structure 17 can be tested from the second surface 12 (e.g., the bottom surface) of the wiring structure 1 via downward electrical paths 174, 176 to infer whether the interconnect portion 15a of the conductive circuit layer 15 is broken or damaged. This test loop is only located in the wiring structure 1 and does not pass through the first electronic device 24 and the second electronic device 26. Therefore, the first electronic device 24 and the second electronic device 26 do not need to add any circuitry to test the interconnect portion 15a of the conductive circuit layer 15.

[0056] Figure 7 A cross-sectional view of a packaging structure 3a according to some embodiments of the present disclosure is shown. Figure 7 The packaging structure 3a is similar to Figures 1 to 6 The package structure 3 differs from the test circuit structure 17a in that the outermost segment 171 of the test circuit structure 17a is electrically connected to the power / ground path of the wiring structure 1a. Therefore, it can be omitted. Figure 6The test bonding material 362. In some embodiments, the electrical connection terminal 173 of the outermost segment 171 of one of the test circuit structures 17 may be electrically connected to the conductive circuit layer 15. Therefore, the test circuit structure 17 may receive test signals from the conductive circuit layer 15.

[0057] Figure 8 A cross-sectional view of the packaging structure 3b according to some embodiments of the present disclosure is shown. Figure 8 The 3b packaging structure is similar to Figures 1 to 6 The package structure 3 differs from the wiring structure 1b in the position of the test circuit structure 17. The test circuit structure 17 can be positioned above the interconnect portion 15a of the conductive circuit layer 15. For example... Figure 8 As shown, the test circuit structure 17 can be disposed on the top surface of the first dielectric layer 141 (e.g., the first surface 11 of the wiring structure 1a) and directly above the interconnect portion 15a of the first conductive circuit layer 151. Therefore, the outermost dielectric layer (i.e., the first dielectric layer 141) can cover the outermost conductive circuit layer (i.e., the first conductive circuit layer 151), and the test circuit structure 17 can be disposed on the outermost dielectric layer (i.e., the first dielectric layer 141). In some embodiments, from a top view, the total area of ​​the test circuit structure 17 can be larger than the total area of ​​the interconnect portion 15a of the first conductive circuit layer 151; therefore, the downward electrical paths 174, 176 may not contact the interconnect portion 15a of the first conductive circuit layer 151. In some embodiments, the test circuit structure 17 can be disposed below the interconnect portion 15a of the conductive circuit layer 15.

[0058] Figure 9 A cross-sectional view of a packaging structure 3c according to some embodiments of the present disclosure is shown. Figure 9 The packaging structure of 3C is similar to Figures 1 to 6 The packaging structure 3 differs from the wiring structure 1c in the position of the test circuit structure 17. The interconnect portion 15a of the third conductive circuit layer 153, the test circuit structure 17, and the shielding wall 155 can be placed on the same layer and formed simultaneously. Therefore, the test circuit structure 17 can be placed below the first conductive circuit layer 151. The test circuit structure 17 may not exist in the first metal layer of the wiring structure 1c. The first metal layer of the wiring structure 1c may only contain the first conductive circuit layer 151.

[0059] Figure 10 A 3D cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown. Figure 10 The 3D encapsulation structure is similar to Figures 1 to 6The package structure 3 differs from the wiring structure 1d in the number and location of the test circuit structures 17. Each of the metal layers in the wiring structure 1d may contain a test circuit structure 17. That is, the second metal layer may further contain a test circuit structure 17 disposed adjacent to the interconnect portion 15a of the second conductive circuit layer 152, the third metal layer may further contain a test circuit structure 17 disposed adjacent to the interconnect portion 15a of the third conductive circuit layer 153, and the fourth metal layer may further contain a test circuit structure 17 disposed adjacent to the interconnect portion 15a of the fourth conductive circuit layer 154. In some embodiments, the test circuit structures 17 disposed on different metal layers are connected in series with each other.

[0060] Figure 11 A perspective view of a test circuit structure 17 and an interconnect portion 15a according to some embodiments of the present disclosure is shown. Figure 11 The test circuit structure 17 is similar to Figure 3 The test circuit structure 17 differs from the others in that the test circuit structures 17 are not electrically connected to each other. That is, the connection portion 175 is omitted. In addition, each of the test circuit structures 17 may include an electrical connection terminal 172 electrically connected to the downward electrical path 174, and an electrical connection terminal 173 electrically connected to the downward electrical path 176.

[0061] Figure 12 A perspective view of a test circuit structure 17 and an interconnect portion 15a according to some embodiments of the present disclosure is shown. Figure 12 The test circuit structure 17 is similar to Figure 11 The test circuit structure 17 differs from the previous one in that the number of test circuit structures 17 is increased. For example... Figure 12 As shown, there is only one test circuit structure 17 placed on one side of the interconnect portion 15a.

[0062] Figure 13 A cross-sectional view of an assembly structure 4 according to some embodiments of the present disclosure is shown. The assembly structure 4 may also be a package structure and may include a substrate 40, a package structure 3, a third protective material 44, a heat sink 46, and a plurality of external connectors 49.

[0063] The substrate 40 may comprise a glass-reinforced epoxy resin material (e.g., FR4), bismaleimide triazine (BT), epoxy resin, silicon, printed circuit board (PCB) material, glass, ceramic, or photoimageable dielectric (PID) material. The substrate 40 may have a first surface 401 and a second surface 402 opposite to the first surface 401. Figure 13As shown, the substrate 40 may include a first patterned circuit 41, a second patterned circuit 42, and a plurality of conductive vias 43. The first patterned circuit 41 may be disposed adjacent to a first surface 401 of the substrate 40, and the second patterned circuit 42 may be disposed adjacent to a second surface 402 of the substrate 40. The conductive vias 43 may extend through the substrate 40 and electrically connect the first patterned circuit 41 and the second patterned circuit 42.

[0064] Figure 13 The packaging structure 3 can be used with Figures 1 to 6 The package structure 3 is the same as or similar to the first patterned circuit 41 of the substrate 40 via bonding material 36. A third protective material 44 (i.e., underfill) is disposed in the space between the package structure 3 and the substrate 40 to cover and protect the bonding material 36 and the first patterned circuit 41.

[0065] The heat sink 46 may be a cap or lid structure and may define a cavity 461 for accommodating the package structure 3. The material of the heat sink 46 may include metals, such as copper, aluminum, and / or other suitable materials. A portion of the heat sink 46 may be attached to the top surface of the package structure 3 via a thermal material 48 (e.g., thermal interface material, TIM) to dissipate heat generated by the first electronic device 24 and the second electronic device 26. Another portion of the heat sink 46 (e.g., the bottom portion) may be attached to the substrate 40 via an adhesive material. Furthermore, an external connector 49 (e.g., a solder ball) is formed or disposed on the second patterned circuit 42 for external connectivity. It should be noted that the package structure 3 may be... Figure 7 , 8 The packaging structures 3a, 3b, 3c, and 3d of 9 and 10 are replaced.

[0066] During the testing process, the test circuit structure 17 can be tested from the second surface 402 of the substrate 40.

[0067] Figures 14 to 21 Test methods according to some embodiments of the present disclosure are illustrated. In some embodiments, the methods can also be used to manufacture... Figures 1 to 6 The packaging structure 3 shown in the image, and Figure 13 4. Assembly structure.

[0068] See Figure 14 A carrier 50 is provided. The carrier 50 can be wafer-type or strip-type. The carrier 50 may include a release layer 52 disposed thereon. Then, wiring structure 1' is formed or disposed on the release layer 52 on the carrier 50. Figure 14 The wiring structure 1' can be similar to Figure 5The wiring structure 1 may have a first surface 11, a second surface 12 opposite to the first surface 11, a high line density region 16 (or a fine line region), a first chip bonding region 18, and a second chip bonding region 19. The wiring structure 1' may include at least one dielectric layer 14, at least one conductive circuit layer 15 in contact with the dielectric layer 14, at least one test circuit structure 17 in contact with the dielectric layer 14, and a plurality of protruding pads 20. For example, such as... Figure 14 As shown, the wiring structure 1' includes a first dielectric layer 141, a first conductive circuit layer 151, a second dielectric layer 142, a second conductive circuit layer 152, a third dielectric layer 143, a third conductive circuit layer 153, a fourth dielectric layer 144, a fourth conductive circuit layer 154, and a fifth dielectric layer 145.

[0069] The first conductive circuit layer 151 may include an interconnect portion 15a and a peripheral portion 15b. The interconnect portion 15a is located in a high line density region 16, and the peripheral portion 15b is located outside the high line density region 16 (e.g., a low density region). The linewidth / spacing (L / S) of the conductive trace 15' of the interconnect portion 15a may be smaller than the L / S of the conductive trace 15" of the peripheral portion 15b.

[0070] The test circuit structure 17 can be positioned adjacent to the interconnect portion 15a of the conductive circuit layer 15. In some embodiments, the wiring structure 1' may include a plurality of interconnect portions 15a, a plurality of test circuit structures 17, and a plurality of shielding walls 155. The interconnect portions 15a, test circuit structures 17, and shielding walls 155 may be positioned on the same layer and may be formed simultaneously. The test circuit structures 17 and shielding walls 155 may be located in the high line density region 16.

[0071] In some embodiments, the test circuit structure 17 may be dummy and may not be electrically connected to the interconnect portion 15a of the conductive circuit layer 15. That is, the test circuit structure 17 may be electrically isolated from the interconnect portion 15a of the conductive circuit layer 15. For example, the interconnect portion 15a of the conductive circuit layer 15 may be used to transmit signals (e.g., digital signals), while the test circuit structure 17 does not have the function of transmitting signals (e.g., digital signals).

[0072] like Figure 2 As shown, the form (or pattern or layout) of the test circuit structure 17 may be similar to or the same as the form (or pattern or layout) of the interconnect portion 15a of the conductive circuit layer 15. For example, the test circuit structure 17 may include a plurality of segments 171 parallel to each other. The linewidth / spacing (L / S) of the segments 171 of the test circuit structure 17 may be substantially equal to the linewidth / spacing (L / S) of the conductive traces 15' of the interconnect portion 15a. Furthermore, the conductive traces 15' and the shielding wall 155 of the interconnect portion 15a may be substantially parallel to the segments 171 of the test circuit structure 17. Figure 2and Figure 3 As shown, segments 171 of each of the test circuit structures 17 are connected in series with each other. Furthermore, the test circuit structures 17 can be electrically connected to each other via connection portions 175. Figure 3 and Figure 5 As shown, one end of the test circuit structure 17 can be electrically connected to the second surface 12 of the wiring structure 1'. There is no protruding pad 20 on the test circuit structure 17. The test circuit structure 17 may not contain an upward electrical connection.

[0073] The protruding pad 20 may be disposed on and protrude from the first dielectric layer 141 (i.e., the topmost or outermost dielectric layer) of the wiring structure 1'. The protruding pad 20 may be disposed on and protrude from the first surface 11 of the wiring structure 1', and extend through the first dielectric layer 141 (i.e., the topmost or outermost dielectric layer) to electrically connect to the first conductive circuit layer 151. The protruding pad 20 may include a plurality of first protruding pads 21 and a plurality of second protruding pads 22.

[0074] See Figure 15 The first electronic device 24 and the second electronic device 26 are electrically connected to the conductive circuit layer 15 of the wiring structure 1' via flip-chip bonding. Therefore, the second electronic device 26 can be electrically connected to the first electronic device 24 via the interconnect portion 15a of the conductive circuit layer 15. In some embodiments, the first electrical contact 244 of the first electronic device 24 can be electrically and physically connected to the first protruding pad 21 via a plurality of bonding materials 245. In some embodiments, the second electrical contact 264 of the second electronic device 26 can be electrically and physically connected to the second protruding pad 22 via a plurality of bonding materials 265.

[0075] See Figure 16 A first protective material 32 (i.e., a bottom filler) is formed or disposed in a first space 25 between the first electronic device 24 and the wiring structure 1', and in a second space 27 between the second electronic device 26 and the wiring structure 1', to cover the wiring structure 1', the first electronic device 24, and the second electronic device 26, and to protect the joint structure formed by the first electrical contact 244, the first protruding pad 21, and the bonding material 245, and the joint structure formed by the second electrical contact 264, the second protruding pad 22, and the bonding material 265. Furthermore, the first protective material 32 may extend further into the gap 30 between the side surface 243 of the first electronic device 24 and the side surface 263 of the second electronic device 26.

[0076] See Figure 17An encapsulation 34 (i.e., a second protective material) is formed or disposed to cover at least a portion of the first surface 11 of the wiring structure 1', at least a portion of the first electronic device 24, at least a portion of the second electronic device 26, and the first protective material 32. The encapsulation 34 has a first surface 341 (e.g., a top surface).

[0077] See Figure 18 Remove the carrier 50 and the release layer 52. Thus, the second surface 12 of the wiring structure 1' is exposed, and a portion of the fourth conductive circuit layer 154 (i.e., the bottom portion of the via portion 15c) is exposed from the second surface 12 of the wiring structure 1'.

[0078] Next, the test circuit structure 17 can be tested from the second surface 12 (e.g., the bottom surface) of the wiring structure 1' via downward electrical paths 174, 176. This test can be an electrical test such as an open / short test as described below. The first probe 91 and the second probe of the test equipment are respectively implemented or provided to contact downward electrical paths 174 and 176. Figure 6 In some embodiments, a test signal is applied to one of the electrical paths (e.g., the test signal may be applied to the downward electrical path 174 via the first probe 91), and the other of the electrical paths is grounded (e.g., the downward electrical path 176 may be electrically connected to the ground plane via the second probe). For example, the test signal may be a test current. Therefore, a test current may be applied to the downward electrical path 174 via the first probe 91. Then, the voltage between the two electrical paths 174 and 176 is measured. The measured voltage is used to determine whether an open circuit has occurred between the downward electrical paths 174 and 176. If an open circuit occurs in the test circuit structure 17, it can be inferred that an open circuit has occurred in the interconnect portion 15a of the conductive circuit layer 15. That is, the interconnect portion 15a of the conductive circuit layer 15 can be considered broken or damaged. Therefore, the quality of the interconnect portion 15a of the conductive circuit layer 15 can be determined to be unqualified or abnormal.

[0079] In this disclosure, because the type (or pattern or layout) of the test circuit structure 17 is similar to or the same as the type (or pattern or layout) of the interconnect portion 15a of the conductive circuit layer 15, the test circuit structure 17 can simulate the condition of the interconnect portion 15a of the conductive circuit layer 15. That is, if a segment 171 of the test circuit structure 17 is broken or damaged, and an open circuit occurs in the test circuit structure 17, it can be considered that the conductive trace 15' of the interconnect portion 15a of the conductive circuit layer 15 is broken or damaged.

[0080] It should be noted that, such as Figure 7As shown, if the electrical connection terminal 173 of the outermost segment 171 of one of the test circuit structures 17 is electrically connected to the power / ground path of the wiring structure 1a, the second probe can be omitted.

[0081] See Figure 19 Multiple bonding materials 36 (e.g., solder balls) are formed or disposed on the second surface 12 of the wiring structure 1'. Figure 19 As shown, bonding material 36 is disposed on the exposed portion of the fourth conductive circuit layer 154 (i.e., the bottom portion of the via portion 15c). In some embodiments, bonding material 36 may comprise two test bonding materials 361, 362 ( Figure 6 Test bonding material 361 is electrically connected to the downward electrical path 174, and test bonding material 362 is electrically connected to the downward electrical path 176. In some embodiments, the test bonding materials 361 and 362 may be subjected to the aforementioned tests (electrical tests) to test the test circuit structure 17. For example, a first probe 91 may contact test bonding material 361, and a second probe may contact bonding material 362.

[0082] See Figure 20 The package 34 is thinned from its first surface 341. Therefore, the first surface 341 of the package 34, the first back surface 242 of the first electronic device 24, the second back surface 262 of the second electronic device 26, and the top surface of the first protective material 32 in the gap 30 may be substantially coplanar with each other.

[0083] In some embodiments, the wiring structure 1' may undergo a singulation process to obtain multiple Figures 1 to 6 The packaging structure shown is 3.

[0084] See Figure 21 The package structure 3 can be electrically connected to a first patterned circuit 41 on a substrate 40 via a bonding material 36. The substrate 40 may have a first surface 401 and a second surface 402 opposite to the first surface 401. The substrate 40 may include the first patterned circuit 41, a second patterned circuit 42, and a plurality of conductive vias 43. The first patterned circuit 41 may be disposed adjacent to the first surface 401 of the substrate 40, and the second patterned circuit 42 may be disposed adjacent to the second surface 402 of the substrate 40. The conductive vias 43 may extend through the substrate 40 and electrically connect the first patterned circuit 41 and the second patterned circuit 42. A third protective material 44 (i.e., underfill) is then formed or disposed in the space between the package structure 3 and the substrate 40 to cover and protect the bonding material 36 and the first patterned circuit 41.

[0085] Next, the heat sink 46 may be attached to the first electronic device 24, the second electronic device 26, and the substrate 40. In some embodiments, the heat sink 46 may be a cover or cap structure and may define a cavity 461 for receiving the package structure 3. A portion of the heat sink 46 may be attached to the top surface of the package structure 3 via a thermal material 48 (e.g., a thermal interface material (TIM)). Another portion of the heat sink 46 (e.g., the bottom portion) may be attached to the substrate 40 via an adhesive material. Then, a plurality of external connectors 49 (e.g., solder balls) may be formed or disposed on the second patterned circuit 42 for external connectivity.

[0086] In some embodiments, the external connector 49 (on the second surface 402 of the substrate 40) may be subjected to the aforementioned tests (electrical tests) to test the test circuit structure 17. Next, the wiring structure 1' may undergo a separation process to obtain multiple... Figure 13 The assembly structure shown is 4.

[0087] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper part,” “above,” and “below” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not deviated from by such arrangement.

[0088] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with a numerical value, the term can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two numerical values ​​can be considered “generally” the same or equal.

[0089] If the displacement between two surfaces does not exceed 5 µm, 2 µm, 1 µm, or 0.5 µm, then the two surfaces can be considered to be coplanar or substantially coplanar.

[0090] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural references.

[0091] As used herein, the terms “conductivity” and “electrical conductivity” refer to the ability to carry electric current. Conductive materials are generally those that exhibit very little or no resistance to the flow of electric current. One measure of electrical conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than about 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of a material can sometimes change with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

[0092] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly, including not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0093] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations are not limitations on this disclosure.

Claims

1. A packaging structure comprising: A wiring structure comprising at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer, wherein the at least one test circuit structure is disposed adjacent to at least one interconnect portion of the at least one conductive circuit layer. A first electronic device, which is electrically connected to the wiring structure; A second electronic device, electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device via at least one interconnect portion of the at least one conductive circuit layer, wherein the test circuit structure is not electrically connected to the interconnect portion of the conductive circuit layer, and wherein the test circuit structure is used to simulate the condition of the interconnect portion of the conductive circuit layer; as well as A shielding wall is disposed between at least one interconnect portion and at least one test circuit structure of at least one conductive circuit layer, wherein the width of the shielding wall is greater than the width of the conductive trace of the at least one interconnect portion, wherein an angle is formed between the conductive trace of the at least one interconnect portion and a segment of the test circuit structure, wherein the angle is less than 90 degrees.

2. The packaging structure according to claim 1, wherein the at least one interconnect portion of the at least one conductive circuit layer includes conductive traces, wherein the test circuit structure is used to infer whether the conductive traces of the at least one interconnect portion of the at least one conductive circuit layer are broken or damaged.

3. The packaging structure according to claim 2, wherein the test circuit structure is electrically isolated from the first electronic device and the second electronic device.

4. The packaging structure according to claim 3, wherein the test circuit structure does not have the function of transmitting signals, the test circuit structure comprises multiple segments, wherein the interconnect portion of the at least one conductive circuit layer is used to transmit signals between the first electronic device and the second electronic device, and comprises multiple conductive traces, wherein the line width / spacing of the multiple segments of the test circuit structure is equal to the line width / spacing of the multiple conductive traces of the interconnect portion.

5. The packaging structure of claim 4, wherein the plurality of segments of the test circuit structure are parallel to each other, and the plurality of conductive traces of the interconnect portion are parallel to each other.

6. The packaging structure according to claim 5, wherein each segment of the test circuit structure is connected in series with each other, such that the test circuit structure is in a serpentine shape.

7. The packaging structure of claim 1, wherein the at least one test circuit structure comprises a plurality of test circuit structures disposed on both sides of the at least one interconnect portion of the at least one conductive circuit layer, wherein the plurality of test circuit structures are electrically connected to each other via connection portions, wherein the connection portions and the conductive traces of the at least one interconnect portion are perpendicular.

8. The packaging structure according to claim 7, wherein the connection portion is disposed directly above or directly below the at least one interconnect portion.

9. The packaging structure according to claim 1, wherein the shielding wall and the at least one interconnecting portion are formed simultaneously.

10. The packaging structure according to claim 9, wherein the at least one test circuit structure is disposed above the at least one conductive circuit layer.

11. The packaging structure of claim 10, wherein the at least one conductive circuit layer comprises an outermost conductive circuit layer containing the at least one interconnect portion, the at least one dielectric layer comprises an outermost dielectric layer covering the outermost conductive circuit layer, and the at least one test circuit structure is disposed on the outermost dielectric layer.

12. The packaging structure according to claim 11, wherein the at least one test circuit structure is disposed below the gap between the first electronic device and the second electronic device.

13. The packaging structure of claim 12, wherein a first portion of the test circuit structure extends into the space below the first electronic device, and a second portion of the test circuit structure extends into the space below the second electronic device.

14. The packaging structure according to claim 1, wherein the at least one test circuit structure is electrically connected to the power path of the wiring structure.

15. The packaging structure of claim 14, wherein the first electronic device and the second electronic device are disposed adjacent to a first surface of the wiring structure, and one end of the at least one test circuit structure is electrically connected to an electrical contact on a second surface of the wiring structure.

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