Display substrate and display device including display substrate

Abstract

This invention relates to a display substrate and a display device including the display substrate. The display substrate may include: a substrate; a first lower gate electrode disposed on the substrate; an insulating pattern disposed on the first lower gate electrode and patterned to correspond to the first lower gate electrode, and comprising silicon nitride; a first insulating layer disposed on the insulating pattern and comprising silicon oxide; and a first active pattern disposed on the first insulating layer and formed of oxide semiconductor, and including a first channel region overlapping the first lower gate electrode and a first wiring region disposed on the side of the first channel region.

Description

Technical Field

[0001] This invention relates to display devices. More specifically, this invention relates to display substrates including transistors and display devices including such display substrates. Background Technology

[0002] A display device is a means of displaying images for providing visual information to a user. A display device may include light-emitting elements that generate light for displaying the images. Additionally, a display device may include a display substrate that includes transistors or the like that provide current, voltage, etc., for driving the light-emitting elements. Summary of the Invention

[0003] One object of the present invention is to provide a display substrate with improved transistor characteristics and a display device including such a display substrate.

[0004] However, the purpose of this invention is not limited to the purpose described above, and it can be extended in various ways without departing from the spirit and scope of this invention.

[0005] To achieve an objective of the present invention, a display substrate according to various embodiments may include: a substrate; a first lower gate electrode disposed on the substrate; an insulating pattern disposed on the first lower gate electrode and patterned to correspond to the first lower gate electrode, and comprising silicon nitride; a first insulating layer disposed on the insulating pattern and comprising silicon oxide; and a first active pattern disposed on the first insulating layer and formed of oxide semiconductor, and comprising a first channel region overlapping the first lower gate electrode and a first wiring region disposed on the side of the first channel region.

[0006] In one embodiment, the insulating pattern may be disposed directly above the first lower gate electrode.

[0007] In one embodiment, the width of the first lower gate electrode may be greater than or substantially equal to the width of the first channel region.

[0008] In one embodiment, the value of subtracting the width of the first channel region from the width of the first lower gate electrode may be greater than approximately 1.6 μm.

[0009] In one embodiment, the width of the insulating pattern may be greater than or substantially equal to the width of the first lower gate electrode.

[0010] In one embodiment, the value of subtracting the width of the first lower gate electrode from the width of the insulating pattern may be greater than approximately 1.6 μm.

[0011] In one embodiment, the width of the insulating pattern may be smaller than the width of the first active pattern.

[0012] In one embodiment, the thickness of the insulating pattern may be approximately The above and approximately the following.

[0013] In one embodiment, the fluorine concentration in the first wiring region may be greater than the fluorine concentration in the first channel region.

[0014] In one embodiment, the concentration of fluorine in the first wiring region may be more than twice the concentration of fluorine in the first channel region.

[0015] In one embodiment, the display substrate may further include: a second insulating layer disposed on the first active pattern; and a first upper gate electrode disposed on the second insulating layer and overlapping the first channel region.

[0016] In one embodiment, the display substrate may further include: a second active pattern disposed on the substrate and not overlapping with the first active pattern, and including a second channel region and a second wiring region disposed on the side of the second channel region; a second insulating layer disposed on the second active pattern; and a second gate electrode disposed on the second insulating layer and overlapping with the second channel region.

[0017] In one embodiment, the second active pattern may be formed of polysilicon.

[0018] In one embodiment, the display substrate may further include: a third insulating layer disposed on the second gate electrode; and a capacitor electrode disposed on the third insulating layer and overlapping the second gate electrode.

[0019] In one embodiment, the capacitor electrode may be disposed on the same layer as the first lower gate electrode.

[0020] To achieve an objective of the present invention, a display device according to various embodiments may include: a substrate; a first transistor disposed on the substrate; and a light-emitting element disposed on the first transistor. The first transistor may include: a first lower gate electrode; an insulating pattern disposed on the first lower gate electrode and patterned to correspond to the first lower gate electrode, and comprising silicon nitride; a first insulating layer disposed on the insulating pattern and comprising silicon oxide; and a first active pattern disposed on the first insulating layer and formed of oxide semiconductor, and including a first channel region overlapping the first lower gate electrode and a first wiring region disposed on the side of the first channel region.

[0021] In one embodiment, the display device may further include: a second transistor disposed between the substrate and the light-emitting element, and not overlapping with the first transistor. The second transistor may include: a second active pattern including a second channel region and a second wiring region disposed on the side of the second channel region; a second insulating layer disposed on the second active pattern; and a second gate electrode disposed on the second insulating layer and overlapping with the second channel region.

[0022] In one embodiment, the second active pattern may be formed of polysilicon.

[0023] In one embodiment, the display device may further include a capacitor disposed between the second transistor and the light-emitting element. The capacitor may include: a second gate electrode; a third insulating layer disposed on the second gate electrode; and a capacitor electrode disposed on the third insulating layer and overlapping the second gate electrode.

[0024] In one embodiment, the capacitor electrode may be disposed on the same layer as the first lower gate electrode.

[0025] (Invention Effects)

[0026] In the display substrate and display device including the display substrate according to various embodiments of the present invention, by distributing an insulating pattern patterned to correspond to the first lower gate electrode and including silicon nitride between the first lower gate electrode and the first channel region of the first active pattern, it is possible to block the flow of fluorine from the first lower gate electrode into the first channel region of the first active pattern, and to prevent the first channel region from becoming conductive. Furthermore, fluorine can flow from the first lower gate electrode into the first wiring region of the first active pattern, thereby reducing the resistance of the first wiring region. As a result, the characteristics of the transistor included in the display substrate can be improved.

[0027] However, the effects of the present invention are not limited to those described above, and can be extended in various ways without departing from the spirit and scope of the present invention. Attached Figure Description

[0028] Figure 1 This is a cross-sectional view showing a display substrate according to an embodiment of the present invention.

[0029] Figure 2 It is shown Figure 1 A sectional view of region A.

[0030] Figure 3 This is a plan view illustrating a display device according to an embodiment of the present invention.

[0031] Figure 4 It is shown Figure 3 The circuit diagram of the pixels of the display device.

[0032] Figure 5 It is along Figure 3 A sectional view taken by the B-B' line.

[0033] Symbol explanation:

[0034] 100: Substrate; 120: Second active pattern; 121: Second channel region; 122: Second wiring region; 130: First gate insulating layer; 140: Second gate electrode; 150: Second gate insulating layer; 161: Capacitor electrode; 162: First lower gate electrode; 170: Insulating pattern; 180: First interlayer insulating layer; 190: First active pattern; 191: First channel region; 192: First wiring region; 200: Third gate insulating layer; 210: First upper gate electrode; CAP: Capacitor; EL: Light-emitting element; TO: First transistor; TP: Second transistor. Detailed Implementation

[0035] Hereinafter, a display substrate and a display device according to various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same constituent elements in the drawings.

[0036] The following is for reference Figure 1 and Figure 2 A display substrate according to an embodiment of the present invention will be described.

[0037] Figure 1 This is a cross-sectional view showing a display substrate according to an embodiment of the present invention.

[0038] Reference Figure 1 According to an embodiment of the present invention, a display substrate may include a substrate 100, a buffer layer 110, a second active pattern 120, a first gate insulating layer 130, a second gate electrode 140, a second gate insulating layer 150, a capacitor electrode 161, a first lower gate electrode 162, an insulating pattern 170, a first interlayer insulating layer 180, a first active pattern 190, a third gate insulating layer 200, a first upper gate electrode 210, a second interlayer insulating layer 220, a first source electrode 231, a first drain electrode 232, a second source electrode 233, and a second drain electrode 234.

[0039] The substrate 100 may be an insulating substrate including glass, quartz, plastic, etc. In one embodiment, the substrate 100 may include a first flexible layer, a first barrier layer disposed on the first flexible layer, a second flexible layer disposed on the first barrier layer, and a second barrier layer disposed on the second flexible layer. The first and second flexible layers may include organic insulating materials such as polyimide (PI), and the first and second barrier layers may include inorganic insulating materials such as silicon oxide, silicon nitride, amorphous silicon, etc.

[0040] A buffer layer 110 may be disposed on the substrate 100. The buffer layer 110 can prevent impurities such as oxygen and moisture from diffusing through the substrate 100 to the upper part of the substrate 100. In addition, the buffer layer 110 may provide a flat upper surface on the upper part of the substrate 100. The buffer layer 110 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxide nitride.

[0041] The second active pattern 120 may be disposed on the buffer layer 110. The second active pattern 120 may include a second channel region 121 and a second wiring region 122 disposed on the side of the second channel region 121. For example, the second wiring region 122 may be disposed on both sides of the second channel region 121.

[0042] The second wiring region 122 may be doped with P-type or N-type impurities, and the second channel region 121 may be doped with impurities of the opposite type to those doped in the second wiring region 122. For example, the second wiring region 122 may be doped with P-type impurities, and the second channel region 121 may be doped with N-type impurities.

[0043] In one embodiment, the second active pattern 120 may be formed of polycrystalline silicon. However, the invention is not limited thereto, and in other embodiments, the second active pattern 120 may also be formed of amorphous silicon, oxide semiconductor, etc.

[0044] A first gate insulating layer 130 may be disposed on the second active pattern 120. The first gate insulating layer 130 may cover the second active pattern 120 and be disposed on the buffer layer 110. The first gate insulating layer 130 may insulate the second gate electrode 140 disposed on the second active pattern 120 from the second active pattern 120. The first gate insulating layer 130 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon nitride.

[0045] The second gate electrode 140 may be disposed on the first gate insulating layer 130. The second gate electrode 140 may overlap with the second channel region 121 of the second active pattern 120. The second gate electrode 140 may include a conductive material such as molybdenum (Mo) or copper (Cu). The second active pattern 120, the first gate insulating layer 130, and the second gate electrode 140 may form a second transistor TP.

[0046] A second gate insulating layer 150 may be disposed on the second gate electrode 140. The second gate insulating layer 150 may cover the second gate electrode 140 and be disposed on the first gate insulating layer 130. The second gate insulating layer 150 may insulate the capacitor electrode 161 disposed on the second gate electrode 140 from the second gate electrode 140. The second gate insulating layer 150 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon nitride.

[0047] Capacitor electrode 161 and first lower gate electrode 162 may be disposed on second gate insulating layer 150. Capacitor electrode 161 may overlap with second gate electrode 140. First lower gate electrode 162 may be disposed on the same layer as capacitor electrode 161 and spaced apart from capacitor electrode 161. First lower gate electrode 162 may not overlap with second active pattern 120 and second gate electrode 140. Capacitor electrode 161 and first lower gate electrode 162 may comprise conductive materials such as molybdenum (Mo) and copper (Cu). Second gate electrode 140, second gate insulating layer 150 and capacitor electrode 161 may form capacitor CAP.

[0048] An insulating pattern 170 may be disposed on the first lower gate electrode 162. The insulating pattern 170 may be patterned to correspond to the first lower gate electrode 162. The insulating pattern 170 may include silicon nitride. The insulating pattern 170 may overlap with the first lower gate electrode 162. In other words, the insulating pattern 170 may not be disposed on the capacitor electrode 161 and may not overlap with the capacitor electrode 161.

[0049] In one embodiment, the insulating pattern 170 may be disposed directly above the first lower gate electrode 162. In other words, the lower surface of the insulating pattern 170 may contact the upper surface of the first lower gate electrode 162.

[0050] A first interlayer insulating layer 180 may be disposed on the capacitor electrode 161 and the insulating pattern 170. The first interlayer insulating layer 180 may cover the capacitor electrode 161 and the insulating pattern 170 and be disposed on the second gate insulating layer 150. The first interlayer insulating layer 180 may include silicon oxide. In one embodiment, the thickness of the first interlayer insulating layer 180 may be approximately [missing information - likely a number].

[0051] A first active pattern 190 may be disposed on a first interlayer insulating layer 180. The first active pattern 190 may include a first channel region 191 overlapping with a first lower gate electrode 162 and a first wiring region 192 disposed on the side of the first channel region 191. For example, the first wiring region 192 may be disposed on both sides of the first channel region 191. The first active pattern 190 may not overlap with the capacitor electrode 161. Therefore, the first active pattern 190 may also not overlap with the second gate electrode 140 and the second active pattern 120.

[0052] The first wiring region 192 may be doped with P-type or N-type impurities, and the first channel region 191 may be doped with impurities of the opposite type to those doped in the first wiring region 192. For example, the first wiring region 192 may be doped with N-type impurities, and the first channel region 191 may be doped with P-type impurities.

[0053] In one embodiment, the first active pattern 190 may be formed of an oxide semiconductor. For example, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium tin oxide (ITO), etc.

[0054] A third gate insulating layer 200 may be disposed on the first active pattern 190. The third gate insulating layer 200 may cover the first active pattern 190 and be disposed on the first interlayer insulating layer 180. The third gate insulating layer 200 may insulate the first upper gate electrode 210 disposed on the first active pattern 190 from the first active pattern 190. The third gate insulating layer 200 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon nitride.

[0055] The first upper gate electrode 210 may be disposed on the third gate insulating layer 200. The first upper gate electrode 210 may overlap with the first channel region 191 of the first active pattern 190. The first upper gate electrode 210 may include a conductive material such as molybdenum (Mo) or copper (Cu). The first lower gate electrode 162, the insulating pattern 170, the first interlayer insulating layer 180, the first active pattern 190, the third gate insulating layer 200, and the first upper gate electrode 210 may form a first transistor TO.

[0056] The second interlayer insulating layer 220 may be disposed on the first upper gate electrode 210. The second interlayer insulating layer 220 may cover the first upper gate electrode 210 and be disposed on the third gate insulating layer 200. The second interlayer insulating layer 220 may insulate the first source electrode 231 and the first drain electrode 232 disposed on the first upper gate electrode 210 from the first upper gate electrode 210. The second interlayer insulating layer 220 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon nitride, etc., and / or organic insulating materials such as polyimide (PI).

[0057] A first source electrode 231, a first drain electrode 232, a second source electrode 233, and a second drain electrode 234 may be disposed on a second interlayer insulating layer 220. The first source electrode 231 and the first drain electrode 232 may be electrically connected to a first wiring region 192 of a first active pattern 190. For example, the first source electrode 231 may contact the first wiring region 192 disposed on one side of the first channel region 191 through contact holes formed in the third gate insulating layer 200 and the second interlayer insulating layer 220, and the first drain electrode 232 may contact the first wiring region 192 disposed on the other side of the first channel region 191 through contact holes formed in the third gate insulating layer 200 and the second interlayer insulating layer 220. The second source electrode 233 and the second drain electrode 234 may be electrically connected to a second wiring region 122 of a second active pattern 120. For example, the second source electrode 233 can contact the second wiring region 122 disposed on one side of the second channel region 121 through contact holes formed in the first gate insulating layer 130, the second gate insulating layer 150, the first interlayer insulating layer 180, the third gate insulating layer 200, and the second interlayer insulating layer 220, and the second drain electrode 234 can contact the second wiring region 122 disposed on the other side of the second channel region 121 through contact holes formed in the first gate insulating layer 130, the second gate insulating layer 150, the first interlayer insulating layer 180, the third gate insulating layer 200, and the second interlayer insulating layer 220. The first source electrode 231, the first drain electrode 232, the second source electrode 233, and the second drain electrode 234 may include conductive materials such as aluminum (Al), titanium (Ti), and copper (Cu).

[0058] Figure 2 It is shown Figure 1 A sectional view of region A.

[0059] Reference Figure 1 and Figure 2 The width 162W of the first lower gate electrode 162 may be greater than the width 191W of the first channel region 191 or substantially the same as the width 191W of the first channel region 191. Ideally, the width 162W of the first lower gate electrode 162 is the same as the width 191W of the first channel region 191. However, considering the tolerances generated during the formation of the first active pattern 190 on the first lower gate electrode 162, the width 162W of the first lower gate electrode 162 may be greater than the width 191W of the first channel region 191 or substantially the same as the width 191W of the first channel region 191.

[0060] In one embodiment, the difference between the width 162W of the first lower gate electrode 162 and the width 191W of the first channel region 191 can be approximately 1.6 μm or more. During the formation of the first active pattern 190 on the first lower gate electrode 162, a one-sided tolerance of approximately 0.8 μm may occur. This one-sided tolerance can be the difference between the ideal position of the side portion of the first channel region 191 and the actual position of the side portion of the formed first channel region 191. Taking into account this one-sided tolerance, the width 162W of the first lower gate electrode 162 can be greater than the width 191W of the first channel region 191 by approximately 1.6 μm or more.

[0061] The width 170W of the insulating pattern 170 can be greater than or substantially the same as the width 162W of the first lower gate electrode 162. Ideally, the width 170W of the insulating pattern 170 should be the same as the width 162W of the first lower gate electrode 162. However, considering the tolerances that arise during the formation of the insulating pattern 170 on the first lower gate electrode 162, the width 170W of the insulating pattern 170 can be greater than or substantially the same as the width 162W of the first lower gate electrode 162.

[0062] In one embodiment, the difference between the width 170W of the insulating pattern 170 and the width 162W of the first lower gate electrode 162 can be approximately 1.6 μm or more. During the formation of the insulating pattern 170 on the first lower gate electrode 162, a one-sided tolerance of approximately 0.8 μm may occur. This one-sided tolerance can be the difference between the ideal position of the side portion of the insulating pattern 170 and the actual position of the side portion of the formed insulating pattern 170. Taking into account this one-sided tolerance, the width 170W of the insulating pattern 170 can be approximately 1.6 μm or more greater than the width 162W of the first lower gate electrode 162.

[0063] The concentration of fluorine (F) in the first wiring region 192 can be greater than the concentration of fluorine (F) in the first channel region 191. In one embodiment, the concentration of fluorine (F) in the first wiring region 192 can be more than twice the concentration of fluorine (F) in the first channel region 191. Since an insulating pattern 170 comprising silicon nitride with a relatively high hydrogen content is disposed on the first lower gate electrode 162 and patterned to correspond to the first lower gate electrode 162, the insulating pattern 170 can block the flow of fluorine (F) from the first lower gate electrode 162 into the first channel region 191. This prevents the first channel region 191 from becoming conductive due to the inflow of fluorine (F).

[0064] Because a first interlayer insulating layer 180, comprising silicon oxide with a relatively low hydrogen content, is disposed on the side of the first lower gate electrode 162, and because no insulating pattern 170 is disposed between the side of the first lower gate electrode 162 and the first interlayer insulating layer 180, or the width of the insulating pattern 170 disposed between the side of the first lower gate electrode 162 and the first interlayer insulating layer 180 is relatively small, fluorine (F) can flow from the first lower gate electrode 162 through the first interlayer insulating layer 180 into the first wiring region 192. With fluorine (F) flowing into the first wiring region 192, the resistance of the first wiring region 192 can be reduced, thereby increasing the on-state current of the first transistor TO.

[0065] The thickness of the insulation pattern 170 is 170T, which can be approximately The above and approximately Below. The thickness of the insulating pattern 170 is less than approximately... In some cases, the insulating pattern 170 may not be able to block the flow of fluorine F from the first lower gate electrode 162 into the first channel region 191. Furthermore, when the thickness 170T of the insulating pattern 170 is greater than approximately... In such cases, the first interlayer insulating layer 180 disposed on the insulating pattern 170 may generate a relatively large height difference, and thus, the characteristics of the first active pattern 190 disposed on the first interlayer insulating layer 180 may decrease.

[0066] The width 170W of the insulating pattern 170 can be smaller than the width 190W of the first active pattern 190. When the width 170W of the insulating pattern 170 is greater than the width 190W of the first active pattern 190, since the width 170W of the insulating pattern 170 disposed between the side of the first lower gate electrode 162 and the first interlayer insulating layer 180 is relatively large, fluorine (F) may not flow from the first lower gate electrode 162 through the first interlayer insulating layer 180 into the first wiring region 192. Therefore, in order for fluorine (F) to flow from the first lower gate electrode 162 through the first interlayer insulating layer 180 into the first wiring region 192, the width 170W of the insulating pattern 170 can be smaller than the width 190W of the first active pattern 190.

[0067] The following is for reference Figure 3 , Figure 4 and Figure 5 A display device according to an embodiment of the present invention will be described.

[0068] Figure 3 This is a plan view illustrating a display device according to an embodiment of the present invention.

[0069] Reference Figure 3A display device according to an embodiment of the present invention may include a plurality of pixels PX. Each pixel PX may emit light, and the display device may display an image formed by the light emitted from each pixel PX. The pixels PX may be arranged in a substantially matrix configuration along the row and column directions.

[0070] Figure 4 It is shown Figure 3 The circuit diagram of the pixel PX of the display device.

[0071] Reference Figure 4 A pixel PX may include pixel circuitry and a light-emitting element EL connected to the pixel circuitry. The pixel circuitry may provide a drive current to the light-emitting element EL. The light-emitting element EL may emit light based on the drive current provided by the pixel circuitry. The pixel circuitry may include at least one transistor and at least one capacitor to generate the drive current.

[0072] In one embodiment, the pixel circuit may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second initialization transistor T7, and a capacitor CAP. However, the present invention is not limited thereto; in other embodiments, the pixel circuit may also include two to six or more transistors and / or two or more capacitors.

[0073] The gate electrode of the driving transistor T1 can be connected to the first node N1. The source electrode of the driving transistor T1 can be connected to the second node N2, and the drain electrode of the driving transistor T1 can be connected to the third node N3. The driving transistor T1 can generate a driving current based on the voltage between the gate electrode and the source electrode.

[0074] A first scan signal SS1 can be applied to the gate electrode of switching transistor T2. A data signal DS can be applied to the source electrode of switching transistor T2, and the drain electrode of switching transistor T2 can be connected to the second node N2. Switching transistor T2 can transmit the data signal DS to the second node N2 based on the first scan signal SS1.

[0075] A first scan signal SS1 can be applied to the gate electrode of the compensation transistor T3. The source electrode of the compensation transistor T3 can be connected to the first node N1, and the drain electrode of the compensation transistor T3 can be connected to the third node N3. The compensation transistor T3 can connect the gate electrode and drain electrode of the driving transistor T1 based on the first scan signal SS1, thereby compensating the threshold voltage of the driving transistor T1.

[0076] A second scan signal SS2 may be applied to the gate electrode of the first initialization transistor T4. In one embodiment, if pixel PX is included in the Nth pixel row, the second scan signal SS2 may be a first scan signal applied to the (N-1)th pixel row. An initialization voltage VINT may be applied to the source electrode of the first initialization transistor T4, and the drain electrode of the first initialization transistor T4 may be connected to the first node N1. The first initialization transistor T4 may transmit the initialization voltage VINT to the first node N1 based on the second scan signal SS2, thereby initializing the gate electrode of the driving transistor T1.

[0077] A light-emitting control signal EM can be applied to the gate electrode of the first light-emitting control transistor T5. A first power supply voltage VDD can be applied to the source electrode of the first light-emitting control transistor T5, and the drain electrode of the first light-emitting control transistor T5 can be connected to the second node N2.

[0078] A light-emitting control signal EM can be applied to the gate electrode of the second light-emitting control transistor T6. The source electrode of the second light-emitting control transistor T6 can be connected to the third node N3, and the drain electrode of the second light-emitting control transistor T6 can be connected to the light-emitting element EL. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 can transmit the drive current generated by the drive transistor T1 to the light-emitting element EL based on the light-emitting control signal EM.

[0079] A third scan signal SS3 may be applied to the gate electrode of the second initialization transistor T7. In one embodiment, if pixel PX is included in the Nth pixel row, the third scan signal SS3 may be a first scan signal applied to the (N+1)th pixel row. An initialization voltage VINT may be applied to the source electrode of the second initialization transistor T7, and the drain electrode of the second initialization transistor T7 may be connected to the light-emitting element EL. The second initialization transistor T7 may initialize the light-emitting element EL by transmitting the initialization voltage VINT to the light-emitting element EL based on the third scan signal SS3.

[0080] In one embodiment, the driving transistor T1, the switching transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second initialization transistor T7 can each be a single-gate transistor, and the compensation transistor T3 and the first initialization transistor T4 can each be a dual-gate transistor. In this case, the gate electrodes of the compensation transistor T3 and the first initialization transistor T4 can each include a lower gate electrode and an upper gate electrode, and the lower gate electrode and the upper gate electrode can be electrically connected.

[0081] In one embodiment, the active patterns of the driving transistor T1, the switching transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second initialization transistor T7 can each be formed of polysilicon, and the active patterns of the compensation transistor T3 and the first initialization transistor T4 can each be formed of oxide semiconductor.

[0082] In one embodiment, the driving transistor T1, the switching transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second initialization transistor T7 can all be PMOS, and the compensation transistor T3 and the first initialization transistor T4 can all be NMOS. However, the present invention is not limited thereto. In other embodiments, the driving transistor T1, the switching transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second initialization transistor T7 can also be NMOS or CMOS, and the compensation transistor T3 and the first initialization transistor T4 can also be PMOS or CMOS.

[0083] A first power supply voltage VDD can be applied to the first electrode of capacitor CAP, and the second electrode of capacitor CAP can be connected to the first node N1. Even when switching transistor T2 is turned off, capacitor CAP can maintain the voltage between the gate electrode and the source electrode of driving transistor T1, thereby enabling light-emitting element EL to emit light.

[0084] The first electrode of the light-emitting element EL can be connected to the aforementioned pixel circuit, and a second power supply voltage VSS can be applied to the second electrode of the light-emitting element EL. In one embodiment, the second power supply voltage VSS can be less than the first power supply voltage VDD. The light-emitting element EL can emit light based on the driving current transmitted from the aforementioned pixel circuit.

[0085] Figure 5 It is along Figure 3 A sectional view taken by the B-B' line.

[0086] Reference Figure 5 A display device according to an embodiment of the present invention may include a first transistor TO, a second transistor TP, a capacitor CAP, a light-emitting element EL, and an encapsulation layer 290 disposed on a substrate 100. (See also...) Figure 5 The display device described may include reference Figure 1 and Figure 2 The display substrate described. Therefore, in reference... Figure 5 In the described display device, for reference Figure 1 and Figure 2 Descriptions of components that are substantially the same as or similar to those of the display substrate will be omitted.

[0087] In one embodiment, the first transistor TO may be Figure 4The compensation transistor T3 and the first initialization transistor T4 are either selected, and the second transistor TP can be either selected or initialized. Figure 4 The driving transistor T1, the switching transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second initialization transistor T7 are all selected from these transistors.

[0088] A via insulating layer 240 may be disposed on the first source electrode 231, the first drain electrode 232, the second source electrode 233, and the second drain electrode 234. The via insulating layer 240 may cover the first source electrode 231, the first drain electrode 232, the second source electrode 233, and the second drain electrode 234 and be disposed on the second interlayer insulating layer 220. The via insulating layer 240 may provide a flat surface on the upper part of the first transistor TO, the second transistor TP, and the capacitor CAP. The via insulating layer 240 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon nitride oxide, and / or organic insulating materials such as polyimide (PI).

[0089] A first electrode 250 may be disposed on the through-hole insulating layer 240. The first electrode 250 may include a conductive material such as a metal, alloy, or transparent conductive oxide. For example, the first electrode 250 may include silver (Ag), indium tin oxide (ITO), etc.

[0090] A pixel defining film 260 may be disposed on the first electrode 250. The pixel defining film 260 may cover the first electrode 250 and is disposed on the via insulating layer 240. The pixel defining film 260 may have a pixel opening that exposes at least a portion of the first electrode 250. In one embodiment, the pixel opening may expose the central portion of the first electrode 250, and the pixel defining film 260 may cover the peripheral portion of the first electrode 250. The pixel defining film 260 may include an organic insulating material such as polyimide (PI).

[0091] A light-emitting layer 270 may be disposed on the first electrode 250. The light-emitting layer 270 may be disposed on the first electrode 250 exposed by the aforementioned pixel opening. The light-emitting layer 270 may include at least one of organic light-emitting materials and quantum dots.

[0092] In one embodiment, the organic light-emitting material may include low-molecular-weight organic compounds or high-molecular-weight organic compounds. For example, low-molecular-weight organic compounds may include copper phthalocyanine, N,N'-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, etc., and high-molecular-weight organic compounds may include poly(3,4-ethylenedioxythiophene), polyaniline, poly-phenylenevinylene, polyfluorene, etc.

[0093] In one embodiment, the quantum dot may include a core containing group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof. In another embodiment, the quantum dot may have a core-shell structure including a core and a shell surrounding the core. The shell may function as a protective layer to prevent chemical degradation of the core to maintain semiconductor properties and as a charging layer to impart electrophoretic properties to the quantum dot.

[0094] A second electrode 280 may be disposed on the light-emitting layer 270. In one embodiment, the second electrode 280 may also be disposed on the pixel defining film 260. The second electrode 280 may include a conductive material such as a metal, alloy, or transparent conductive oxide. For example, the second electrode 280 may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), etc. The first electrode 250, the light-emitting layer 270, and the second electrode 280 may form a light-emitting element EL.

[0095] An encapsulation layer 290 may be disposed on the second electrode 280. The encapsulation layer 290 may cover the light-emitting element EL to protect it from impurities such as oxygen and moisture. The encapsulation layer 290 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In one embodiment, the encapsulation layer 290 may include a first inorganic encapsulation layer disposed on the second electrode 280, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer. The inorganic encapsulation layer may include silicon nitride, silicon oxide nitride, etc., and the organic encapsulation layer may include epoxy resin, acrylic resin, polyimide resin, etc.

[0096] (Industry availability)

[0097] The display substrates according to various exemplary embodiments of the present invention can be applied to display devices including computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs, MP3 players, etc.

[0098] The display substrate and display device according to various exemplary embodiments of the present invention have been described above with reference to the accompanying drawings. However, the provided embodiments are illustrative, and those skilled in the art can make modifications and alterations without departing from the technical concept of the present invention as described in the claims.

Claims

1. A display substrate, comprising: substrate; A first lower gate electrode is disposed on the substrate; An insulating pattern is disposed on the first lower gate electrode and patterned to correspond to the first lower gate electrode, and includes silicon nitride; A first insulating layer, disposed on the insulating pattern and comprising silicon oxide; and A first active pattern is disposed on the first insulating layer and formed of an oxide semiconductor, and includes a first channel region overlapping the first lower gate electrode and a first wiring region disposed on the side of the first channel region. The width of the insulating pattern disposed between the side of the first lower gate electrode and the first insulating layer is smaller than the thickness of the insulating pattern disposed between the upper part of the first lower gate electrode and the first insulating layer.

2. The display substrate according to claim 1, wherein, The insulating pattern is disposed directly above the first lower gate electrode.

3. The display substrate according to claim 1, wherein, The width of the first lower gate electrode is greater than or equal to the width of the first channel region.

4. The display substrate according to claim 1, wherein, The width of the insulating pattern is greater than or equal to the width of the first lower gate electrode.

5. The display substrate according to claim 1, wherein, The width of the insulating pattern is smaller than the width of the first active pattern.

6. The display substrate according to claim 1, wherein, The fluorine concentration in the first wiring region is greater than the fluorine concentration in the first channel region.

7. The display substrate according to claim 1, further comprising: A second insulating layer is disposed on the first active pattern; as well as The first upper gate electrode is disposed on the second insulating layer and overlaps with the first channel region.

8. The display substrate according to claim 1, further comprising: The second active pattern is disposed on the substrate and does not overlap with the first active pattern, and includes a second channel region and a second wiring region disposed on the side of the second channel region. A second insulating layer is disposed on the second active pattern; as well as The second gate electrode is disposed on the second insulating layer and overlaps with the second channel region. The second active pattern is formed from polycrystalline silicon.

9. The display substrate according to claim 8, further comprising: A third insulating layer is disposed on the second gate electrode; as well as The capacitor electrode is disposed on the third insulating layer and overlaps with the second gate electrode. The capacitor electrodes are disposed on the same layer as the first lower gate electrode.

10. A display device, comprising: substrate; A first transistor is disposed on the substrate; as well as A light-emitting element is disposed on the first transistor. The first transistor includes: First lower gate electrode; An insulating pattern is disposed on the first lower gate electrode and patterned to correspond to the first lower gate electrode, and includes silicon nitride; A first insulating layer, disposed on the insulating pattern and comprising silicon oxide; and A first active pattern is disposed on the first insulating layer and formed of an oxide semiconductor, and includes a first channel region overlapping the first lower gate electrode and a first wiring region disposed on the side of the first channel region. The width of the insulating pattern disposed between the side of the first lower gate electrode and the first insulating layer is smaller than the thickness of the insulating pattern disposed between the upper part of the first lower gate electrode and the first insulating layer.

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