Display device

Abstract

A display device includes a substrate, a first active pattern, a first gate electrode, a second active pattern, a second gate electrode, a first connection pattern, and a second connection pattern. The first connection pattern is disposed on the second active pattern and electrically connected to the first gate electrode, and the second connection pattern is disposed on the first connection pattern and electrically connected to the first connection pattern and the second active pattern.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to display devices, and more specifically, to display devices resistant to loads and shocks. Background Technology

[0002] Typically, a display device includes multiple pixel structures. A pixel structure may include transistors, at least one storage capacitor, and a light-emitting diode (LED). A transistor may include a first transistor that generates a drive current and provides the drive current to the LED, a second transistor that transmits a data voltage to the first transistor in response to a gate signal, and a third transistor that compensates for a threshold voltage of the first transistor. The display device may further include a data line for transmitting the data voltage to the second transistor. The first transistor and the third transistor may be electrically connected to each other via a connection pattern disposed between the first transistor and the third transistor. Summary of the Invention

[0003] In display devices, crosstalk can occur between data lines and connection patterns. The area occupied by connection patterns in display devices limits the reduction of the pixel structure's area on the plane.

[0004] Embodiments of the display device provide a display device with improved display quality.

[0005] An embodiment of the display device includes: a substrate; a first active pattern disposed on the substrate; a first gate electrode disposed on the first active pattern and forming a first transistor together with the first active pattern; a second active pattern disposed on the first gate electrode; a second gate electrode disposed on the second active pattern and forming a second transistor together with the second active pattern; a first connection pattern disposed on the second active pattern and electrically connected to the first gate electrode; and a second connection pattern disposed on the first connection pattern and electrically connected to the first connection pattern and the second active pattern.

[0006] According to an embodiment, the first connection pattern and the second gate electrode can be disposed in the same layer.

[0007] According to an embodiment, the display device may further include a shielding pattern disposed on a first connection pattern and a data line disposed on the shielding pattern, the shielding pattern being able to receive a constant voltage, and the data line being able to overlap with the shielding pattern and provide a data voltage.

[0008] According to an embodiment, the shielding pattern may overlap with the first connection pattern.

[0009] According to an embodiment, a shielding pattern can be disposed between the data cable and the first connection pattern.

[0010] According to an embodiment, the data line can be positioned on the second connection pattern.

[0011] According to an embodiment, the constant voltage can be the power supply voltage.

[0012] According to an embodiment, the display device may further include power voltage lines disposed on a shielding pattern, and the power voltage lines may provide power voltage to the shielding pattern.

[0013] According to an embodiment, the second connecting pattern may partially overlap with the first connecting pattern.

[0014] According to an embodiment, the display device may further include a storage capacitor electrode disposed on a first gate electrode, wherein an aperture may be defined to pass through the storage capacitor electrode, and a second connection pattern may not overlap with the aperture.

[0015] According to an embodiment, the first connection pattern can contact the first gate electrode through a first contact hole that overlaps with the first connection pattern and the first gate electrode, and the second connection pattern may not overlap with the first contact hole.

[0016] According to an embodiment, the second connecting pattern can contact the first connecting pattern through a second contact hole that overlaps with the first connecting pattern and the second connecting pattern.

[0017] According to an embodiment, the second connection pattern can contact the second active pattern through a third contact hole that overlaps with the second connection pattern and the second active pattern.

[0018] According to an embodiment, the first contact hole, the second contact hole, and the third contact hole may be spaced apart from each other.

[0019] According to an embodiment, the display device may further include a first bottom gate electrode, which is disposed below the second active pattern and electrically connected to the second gate electrode, and the second gate electrode may be arranged in an island shape.

[0020] According to an embodiment, the first bottom gate electrode may overlap with the second gate electrode.

[0021] According to an embodiment, the display device may further include: a third gate electrode disposed on a second active pattern and forming a third transistor together with the second active pattern; and a second bottom gate electrode disposed below the second active pattern, overlapping the third gate electrode, and electrically connected to the third gate electrode.

[0022] According to an embodiment, the first active pattern may include polysilicon, and the second active pattern may include oxide semiconductor.

[0023] According to an embodiment, the display device may further include a light-blocking pattern disposed on the second connecting pattern and overlapping the second active pattern.

[0024] According to an embodiment, the display device may further include a first gate line between a first active pattern and a second active pattern, and together with the first active pattern, form a fourth transistor.

[0025] As described herein, in embodiments of the display device, the gate terminal of the first transistor and the second terminal of the third transistor are connected to each other via a first connection pattern and a second connection pattern. In such embodiments, the display device includes a shielding pattern that shields the first connection pattern, thereby effectively preventing crosstalk between the first connection pattern and the data lines. In such embodiments, the area of ​​the pixel structure on the plane can be reduced by partially overlapping the second connection pattern and the first connection pattern, thereby increasing the resolution of the display device. Attached Figure Description

[0026] The above and other features of the invention will become more apparent from the embodiments described in further detail with reference to the accompanying drawings, in which:

[0027] Figure 1 This is a plan view showing a display device according to an embodiment;

[0028] Figure 2 It is shown that it includes Figure 1 An enlarged view of the connecting lines in the display device;

[0029] Figure 3 It is shown that it includes Figure 1 A circuit diagram of an embodiment of pixel circuits and organic light-emitting diodes in a display device;

[0030] Figures 4 to 16 It is shown that it includes Figure 1 A plan view of the pixel structure in a display device;

[0031] Figure 17 It is along Figure 16 A cross-sectional view taken from line I-I';

[0032] Figure 18 It is shown that it includes Figure 1 A plan view of the third and fourth conductive patterns in the display device;

[0033] Figure 19 It is along Figure 18 A cross-sectional view taken from line II-II';

[0034] Figure 20 It is shown that it includes Figure 1 A plan view of the fourth and fifth conductive patterns in the display device;

[0035] Figure 21 It is along Figure 20A cross-sectional view taken from line III-III';

[0036] Figure 22 It is along Figure 16 A cross-sectional view taken from line IV-IV';

[0037] Figure 23 It is along Figure 16 A cross-sectional view taken from line V-V';

[0038] Figure 24 This is a plan view showing a display device according to an alternative embodiment;

[0039] Figure 25 It is shown that it includes Figure 24 An enlarged view of the connecting lines in the display device;

[0040] Figure 26 It is shown that it includes Figure 24 A circuit diagram of an embodiment of pixel circuits and organic light-emitting diodes in a display device;

[0041] Figures 27 to 39 It is shown that it includes Figure 24 A plan view of the pixel structure in a display device;

[0042] Figure 40 It is along Figure 39 A cross-sectional view taken from line VI-VI';

[0043] Figure 41 It is along Figure 39 A cross-sectional view taken from line VII-VII';

[0044] Figure 42 It is along Figure 35 A cross-sectional view taken from line VIII-VIII';

[0045] Figure 43 It is along Figure 35 A cross-sectional view taken from line IX-IX';

[0046] Figure 44 It is along Figure 39 A cross-sectional view taken by line X-X'; and

[0047] Figure 45 It is along Figure 39 The cross-sectional view taken from line XI-XI'. Detailed Implementation

[0048] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more inventive concepts disclosed herein. However, it will be apparent, however, that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are illustrated in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but are not necessarily exclusive. For example, particular shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0049] Unless otherwise specified, the illustrated embodiments are to be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of the various embodiments may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0050] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Thus, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between the elements shown, and / or any other characteristics, properties, etc., of the elements, unless specifically stated. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be enlarged for clarity and / or descriptive purposes. When embodiments can be implemented differently, specific processes may be performed in a different order than those described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Similarly, the same reference numerals refer to the same elements.

[0051] When a component or layer is referred to as being "on" another component or layer, "connected to," or "coupled to" another component or layer, it may be directly on, directly connected to, or coupled to that other component or layer, or there may be intermediate components or layers present. However, when a component or layer is referred to as being "directly on" another component or layer, "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without intermediate components. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system such as the x, y, and z axes, and can be interpreted in a broader sense. For example, the D1, D2, and D3 axes may be perpendicular to each other, or they may be different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of more than two of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] While the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure.

[0053] Spatial relative terms such as “below,” “under,” “lower,” “above,” “on,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes and thereby to describe the relationship of one element to another (other elements) as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture other than those depicted in the figures. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features would then be oriented “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or otherwise), and in such cases, the spatial relative descriptors used herein are interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a” and “the” and variations thereof are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms “comprising,” “including,” and variations thereof, when used in this specification, indicate the presence of the stated feature, integral, step, operation, element, component, and / or combination thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. It should also be noted that, as used herein, the terms “substantially,” “approximately,” and other similar terms are used as approximate terms rather than terms of degree, and thus are used to account for inherent deviations in the measured, calculated, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0055] Various embodiments are described herein with reference to cross-sectional and / or exploded views as schematic representations of idealized embodiments and / or intermediate structures. Thus, variations in the shapes of the figures are expected due to factors such as manufacturing techniques and / or limitations. Therefore, the embodiments disclosed herein are not necessarily to be interpreted as limited to a specific illustrated shape of the region, but will include deviations in shape due to factors such as manufacturing. In this way, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and this is not necessarily intended to be limiting.

[0056] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense, unless expressly so specified herein.

[0057] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0058] Figure 1 This is a plan view showing a display device according to an embodiment. Figure 2 It is shown that it includes Figure 1 An enlarged view of the connecting lines in the display device. Figure 3 It is shown that it includes Figure 1 A circuit diagram of an embodiment of pixel circuitry and organic light-emitting diodes in a display device.

[0059] refer to Figure 1 , Figure 2 and Figure 3An embodiment of the display device 10 may include a display area DA and a non-display area NDA surrounding the display area DA. The non-display area NDA may include a flexible curved area BA, a peripheral area SA between the display area DA and the curved area BA, and a pad area PA.

[0060] In one embodiment, for example, a pixel structure PX may be disposed in a display area DA, and a driver for driving the pixel structure PX may be disposed in a non-display area NDA. In another embodiment, for example, a pad portion PD and a data driver DDV may be disposed in a pad area PA, and a curved area BA may be curved based on a virtual bending axis. In such an embodiment, the pixel structure PX is not disposed in a peripheral area SA, such that the width of the peripheral area SA extending in the second direction D2 may be defined as the dead space of the display device 10.

[0061] In such an embodiment, the pixel structure PX, the data line DL connected to the pixel structure PX, the gate line GL connected to the pixel structure PX, the emission management (or emission control) line EML connected to the pixel structure PX, the drive voltage line PL connected to the pixel structure PX, and the connection line FL connected to the pixel structure PX can be set in the display area DA.

[0062] The data line DL can be electrically connected to the data driver DDV and can extend along the second direction D2. The data line DL can receive data voltage DATA from the data driver DDV and can transmit the data voltage DATA to the pixel structure PX.

[0063] The gate line GL can be electrically connected to the gate driver GDV and can extend along a first direction D1 that intersects the second direction D2. The gate line GL can receive gate signals from the gate driver GDV and transmit the gate signals to the pixel structure PX.

[0064] The transmit management line EML can be electrically connected to the transmit driver EDV and can extend along the first direction D1. The transmit management line EML can receive the transmit management (or transmit control) signal EM from the transmit driver EDV and transmit the transmit management signal EM to the pixel structure PX. In one embodiment, for example, the active period of the transmit management signal EM can be the transmit period of the display device 10, and the inactive period of the transmit management signal EM can be the non-transmit period of the display device 10.

[0065] The driving voltage line PL can be electrically connected to the pad portion PD and can extend along the second direction D2. In an embodiment, the driving voltage line PL can receive a high power supply voltage ELVDD from the pad portion PD and can transmit the high power supply voltage ELVDD to the pixel structure PX. In such an embodiment, a low power supply voltage ELVSS can be provided together to the counter electrode (e.g., the cathode electrode) of the organic light-emitting diode OLED.

[0066] The driver may include a gate driver (GDV), a data driver (DDV), a transmit driver (EDV), and a pad section (PD). In such an embodiment, the driver may further include a timing controller, which can control the gate driver (GDV), the data driver (DDV), the transmit driver (EDV), and the pad section (PD).

[0067] The gate driver GDV can receive voltage from the pad portion PD to generate a gate signal. In one embodiment, for example, the gate signal may include a first gate signal GW, a second gate signal GC, a third gate signal GI, and a fourth gate signal GB.

[0068] The data driver DDV generates data voltages DATA corresponding to both transmit and non-transmit periods. The transmit driver EDV receives voltage from the pad section PD to generate the transmit management signal EM. The pad section PD can be electrically connected to external devices and can supply voltages to the gate driver GDV, the transmit driver EDV, and the drive voltage line PL, respectively.

[0069] In an embodiment, such as Figure 1 As shown, the gate driver GDV and the transmitter driver EDV are respectively disposed on the left and right sides of the display device 10, but the present invention is not limited thereto.

[0070] In an embodiment, such as Figure 1 As shown, the data driver DDV is mounted in the non-display area NDA of the display device 10, but the invention is not limited thereto. In an alternative embodiment, for example, the data driver DDV may be disposed on a separate flexible printed circuit board (“FPCB”), and the pad portion PD may be electrically connected to the FPCB.

[0071] In an embodiment, such as Figure 2 As shown, data lines DL and FL can be positioned within the display area DA. In one embodiment, for example, first to fourth data lines DL1, DL2, DL3, and DL4, first FL1, and second FL2 can be positioned within the display area DA. In another embodiment, for example, FL can be a fan-out line electrically connecting the data driver DDV and the data lines DL.

[0072] In one embodiment, for example, the pixel structure PX may include first to fourth pixel structures disposed along a first direction D1. A first data line DL1 may be connected to the first pixel structure, a second data line DL2 may be connected to the second pixel structure, a third data line DL3 may be connected to the third pixel structure, and a fourth data line DL4 may be connected to the fourth pixel structure.

[0073] In one embodiment, the first connecting line FL1 may include a first vertical connecting line VFL1 and a first horizontal connecting line HFL1, and the second connecting line FL2 may include a second vertical connecting line VFL2 and a second horizontal connecting line HFL2. In one embodiment, for example, the first vertical connecting line VFL1 and the second vertical connecting line VFL2 may extend in a second direction D2, and the first horizontal connecting line HFL1 and the second horizontal connecting line HFL2 may extend in a first direction D1.

[0074] The first connection line FL1 can electrically connect the data driver DDV and the first data line DL1. In one embodiment, for example, a first data voltage can be provided to the first pixel structure through the first connection line FL1 and the first data line DL1.

[0075] In such an embodiment, the first vertical connection line VFL1 can be connected to the first transmission line SCL1, the first transmission line SCL1 can be connected to the first curved transmission line BCL1, and the first curved transmission line BCL1 can be connected to the first data transmission line DCL1.

[0076] In a first embodiment, for example, a first vertical connecting line VFL1 can extend from the peripheral region SA to the display region DA, and can be disposed in the first layer (e.g., where...). Figure 38 The fifth conductive pattern 2700 is disposed in the first layer. The first transmission line SCL1 can be disposed in the peripheral area SA, and can be disposed in the second layer disposed below the first layer (e.g., where...). Figure 29 The first conductive pattern 2200 is set in the second layer. The first curved transmission line BCL1 can be set in the curved area BA and can also be set in the first layer. The first data transmission line DCL1 can be set in the pad area PA and can receive the first data voltage from the data driver DDV.

[0077] The second connection line FL2 can electrically connect the data driver DDV and the second data line DL2. In one embodiment, for example, a second data voltage can be provided to the second pixel structure via the second connection line FL2 and the second data line DL2.

[0078] In this embodiment, the second vertical connection line VFL2 can be connected to the second transmission line SCL2, the second transmission line SCL2 can be connected to the second curved transmission line BCL2, and the second curved transmission line BCL2 can be connected to the second data transmission line DCL2. In such an embodiment, the structures of the second vertical connection line VFL2, the second transmission line SCL2, the second curved transmission line BCL2, and the second data transmission line DCL2 can be substantially the same as the structures of the first vertical connection line VFL1, the first transmission line SCL1, the first curved transmission line BCL1, and the first data transmission line DCL1, and therefore, any repeated detailed descriptions thereof will be omitted.

[0079] The third data line DL3 can be connected to the data driver DDV. In one embodiment, for example, a third data voltage can be provided to the third pixel structure via the third data line DL3.

[0080] In such an embodiment, the third data line DL3 can be connected to the third transmission line SCL3, the third transmission line SCL3 can be connected to the third curved transmission line BCL3, and the third curved transmission line BCL3 can be connected to the third data transmission line DCL3.

[0081] In one embodiment, for example, a third data line DL3 can extend from the peripheral area SA to the display area DA, and can be disposed in the first layer. A third transmission line SCL3 can be disposed in the peripheral area SA, and can be disposed in a third layer located below the first layer (e.g., where...). Figure 30 The second conductive pattern 2300 is set in the third layer. The third curved transmission line BCL3 can be set in the curved area BA and can also be set in the first layer. The third data transmission line DCL3 can be set in the pad area PA and can receive the third data voltage from the data driver DDV.

[0082] The fourth data line DL4 can be connected to the data driver DDV. In one embodiment, for example, a fourth data voltage can be provided to the fourth pixel structure via the fourth data line DL4.

[0083] In this embodiment, the fourth data line DL4 can be connected to the fourth transmission line SCL4, the fourth transmission line SCL4 can be connected to the fourth curved transmission line BCL4, and the fourth curved transmission line BCL4 can be connected to the fourth data transmission line DCL4. In such an embodiment, the structures of the fourth data line DL4, the fourth transmission line SCL4, the fourth curved transmission line BCL4, and the fourth data transmission line DCL4 can be substantially the same as the structures of the third data line DL3, the third transmission line SCL3, the third curved transmission line BCL3, and the third data transmission line DCL3, and therefore, any repeated detailed descriptions thereof will be omitted.

[0084] In one embodiment, the second layer may be positioned below the third layer. In one embodiment, for example, the first transmission line SCL1 and the second transmission line SCL2 may be positioned below the third transmission line SCL3 and the fourth transmission line SCL4.

[0085] Therefore, in such an embodiment, the space allowance can be ensured in the second (or third) layer of the peripheral region SA, and additional lines can be further arranged within the space allowance. However, the invention is not limited thereto, and various modifications can be made to the connection structure and arrangement of the aforementioned lines.

[0086] In this embodiment, the connecting line FL is disposed in the display area DA, such that the width of the peripheral area SA of the display device 20 extending in the second direction D2 can be reduced compared to the width of the peripheral area of ​​a conventional display device extending in the second direction D2. Therefore, in such an embodiment, the dead space of the display device 20 can be reduced.

[0087] In an embodiment, such as Figure 3 As shown, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, and a boost capacitor CBS. The pixel circuit PC can be electrically connected to the organic light-emitting diode (OLED) and can provide driving current to the OLED.

[0088] An organic light-emitting diode (OLED) may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal). The first terminal of the OLED can be electrically connected to a first transistor T1 via a sixth transistor T6 and can receive a drive current. The second terminal can receive a low supply voltage ELVSS. The OLED can produce light with a brightness corresponding to the drive current.

[0089] The storage capacitor CST may include a first terminal and a second terminal. The first terminal of the storage capacitor CST may be connected to a first transistor T1, and the second terminal of the storage capacitor CST may receive a high supply voltage ELVDD. During the inactive period of the first gate signal GW, the storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor T1.

[0090] The boost capacitor CBS may include a first terminal and a second terminal. The first terminal of the boost capacitor CBS may be connected to the first terminal of the storage capacitor CST, and the second terminal of the boost capacitor CBS may receive a first gate signal GW. When the application of the first gate signal GW is stopped, the boost capacitor CBS can compensate for the voltage drop at the gate terminal by increasing the voltage level at the gate terminal of the first transistor T1.

[0091] The first transistor T1 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the first transistor T1 may be connected to the first terminal of the storage capacitor CST. The first terminal of the first transistor T1 may be connected to a second transistor T2 to receive a data voltage DATA. The second terminal of the first transistor T1 may be connected to an organic light-emitting diode (OLED) via a sixth transistor T6 to provide a drive current. The first transistor T1 may generate the drive current based on the voltage difference between the gate terminal and the first terminal. In such an embodiment, the first transistor T1 may be referred to as a drive transistor.

[0092] The second transistor T2 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the second transistor T2 can receive a first gate signal GW through the gate line GL.

[0093] The second transistor T2 can be turned on or off in response to the first gate signal GW. In one embodiment, for example, when the second transistor T2 is a P-type metal-oxide-semiconductor (“PMOS”) transistor, the second transistor T2 can be turned off when the first gate signal GW has a positive voltage level and can be turned on when the first gate signal GW has a negative voltage level. The first terminal of the second transistor T2 can receive the data voltage DATA through the data line DL. When the second transistor T2 is turned on, the second terminal of the second transistor T2 can provide the data voltage DATA to the first terminal of the first transistor T1. In such an embodiment, the second transistor T2 can be referred to as a switching transistor.

[0094] The third transistor T3 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the third transistor T3 may receive a second gate signal GC. The first terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1. The second terminal of the third transistor T3 may be connected to the gate terminal of the first transistor T1.

[0095] The third transistor T3 can be turned on or off in response to the second gate signal GC. In one embodiment, for example, when the third transistor T3 is an N-type metal-oxide-semiconductor (“NMOS”) transistor, the third transistor T3 can be turned on when the second gate signal GC has a positive voltage level and can be turned off when the second gate signal GC has a negative voltage level.

[0096] During the period when the third transistor T3 is turned on in response to the second gate signal GC, the third transistor T3 can be diode-connected to the first transistor T1. When the first transistor T1 is diode-connected, a voltage difference equal to the threshold voltage of the first transistor T1 can appear between the gate terminal and the first terminal of the first transistor T1. Therefore, during the period when the third transistor T3 is turned on, the voltage obtained by adding the data voltage DATA and the voltage difference can be provided to the gate terminal of the first transistor T1. Thus, the third transistor T3 can compensate for the threshold voltage of the first transistor T1. In such an embodiment, the third transistor T3 can be referred to as a compensation transistor.

[0097] The fourth transistor T4 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fourth transistor T4 may receive a third gate signal GI. The first terminal of the fourth transistor T4 may be connected to the gate terminal of the first transistor T1. The second terminal of the fourth transistor T4 may receive a gate initialization voltage VINT.

[0098] The fourth transistor T4 can be turned on or off in response to the third gate signal GI. In one embodiment, for example, when the fourth transistor T4 is an NMOS transistor, the fourth transistor T4 can be turned on when the third gate signal GI has a positive voltage level and can be turned off when the third gate signal GI has a negative voltage level.

[0099] During the period when the fourth transistor T4 is turned on in response to the third gate signal GI, the gate initialization voltage VINT can be provided to the gate terminal of the first transistor T1. Therefore, the fourth transistor T4 can initialize the gate terminal of the first transistor T1 to the gate initialization voltage VINT. In such an embodiment, the fourth transistor T4 can be referred to as the gate initialization transistor.

[0100] The fifth transistor T5 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fifth transistor T5 may receive a transmit management signal EM. The first terminal of the fifth transistor T5 may receive a high supply voltage ELVDD. The second terminal of the fifth transistor T5 may be connected to the first terminal of the first transistor T1. When the fifth transistor T5 is turned on in response to the transmit management signal EM, the fifth transistor T5 may supply the high supply voltage ELVDD to the first transistor T1.

[0101] The sixth transistor T6 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the sixth transistor T6 may receive an emission management signal EM. The first terminal of the sixth transistor T6 may be connected to the second terminal of the first transistor T1. The second terminal of the sixth transistor T6 may be connected to the first terminal of the organic light-emitting diode (OLED). When the sixth transistor T6 is turned on in response to the emission management signal EM, the sixth transistor T6 may transmit the drive current generated by the first transistor T1 to the organic light-emitting diode (OLED).

[0102] The seventh transistor T7 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the seventh transistor T7 may receive a fourth gate signal GB. The first terminal of the seventh transistor T7 may receive an anode initialization voltage AINT. The second terminal of the seventh transistor T7 may be connected to the first terminal of an organic light-emitting diode (OLED). When the seventh transistor T7 is turned on in response to the fourth gate signal GB, the seventh transistor T7 can provide the anode initialization voltage AINT to the OLED. Therefore, the seventh transistor T7 can initialize the first terminal of the OLED to the anode initialization voltage AINT.

[0103] Figure 3 The connection structure of the pixel circuit PC shown is merely exemplary and can be modified in various ways.

[0104] Figures 4 to 16 It is shown that it includes Figure 1 A plan view of the pixel structure in a display device.

[0105] refer to Figure 4 An embodiment of the pixel structure PX may include a substrate SUB and a first active pattern 1100 disposed on the substrate SUB.

[0106] The substrate SUB may include a glass substrate, a quartz substrate, or a plastic substrate, etc. In an embodiment, the substrate SUB may include a plastic substrate, and therefore the display device 10 may be a flexible display device. In such an embodiment, the substrate SUB may have a structure in which at least one organic film layer and at least one barrier layer are alternately stacked. In one embodiment, for example, the organic film layer may include or be formed of an organic material such as polyimide, and the barrier layer may include or be formed of an inorganic material such as silicon oxide or silicon nitride.

[0107] A buffer layer can be disposed on the substrate SUB. The buffer layer can effectively prevent metal atoms or impurities from diffusing from the substrate SUB into the first active pattern 1100. In such an embodiment, the buffer layer can allow the first active pattern 1100 to be uniformly formed by controlling the heat transfer rate during the crystallization process for forming the first active pattern 1100.

[0108] The first active pattern 1100 may be disposed on a buffer layer. In an embodiment, the first active pattern 1100 may include a silicon semiconductor. In one embodiment, for example, the first active pattern 1100 may include amorphous silicon or polycrystalline silicon, etc.

[0109] In one embodiment, ions may be selectively implanted into the first active pattern 1100. In one embodiment, for example, when the first transistor T1 and the second transistor T2 are PMOS transistors, the first active pattern 1100 may include a source region where cations are implanted, a drain region where cations are implanted, and a channel region where cations are not implanted.

[0110] First gate insulating layer (e.g., Figure 17 The first gate insulating layer (GI1) may cover the first active pattern 1100 and may be disposed on the substrate SUB. The first gate insulating layer may include an insulating material. In one embodiment, for example, the first gate insulating layer may include silicon oxide, silicon nitride, titanium oxide, or tantalum oxide, etc.

[0111] refer to Figure 5 and Figure 6 The first conductive pattern 1200 may be disposed on the first gate insulating layer. The first conductive pattern 1200 may include a fourth gate line 1210, a first gate line 1220, a first gate electrode 1230, and an emission management line 1240.

[0112] The fourth gate line 1210 may form a seventh transistor T7 together with a portion of the first active pattern 1100. In one embodiment, for example, a fourth gate signal GB may be provided to the fourth gate line 1210.

[0113] The first gate line 1220 may form a second transistor T2 together with a portion of the first active pattern 1100. In one embodiment, for example, a first gate signal GW may be provided to the first gate line 1220.

[0114] The first gate electrode 1230 can form a first transistor T1 together with a portion of the first active pattern 1100. The emitter management line 1240 can form a fifth transistor T5 and a sixth transistor T6 together with a portion of the first active pattern 1100.

[0115] In one embodiment, for example, the first conductive pattern 1200 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. In one embodiment, for example, the first conductive pattern 1200 may include at least one material selected from silver (“Ag”), silver-containing alloys, molybdenum (“Mo”), molybdenum-containing alloys, aluminum (“Al”), aluminum-containing alloys, aluminum nitride (“AlN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), and indium zinc oxide (“IZO”).

[0116] First interlayer insulation layer (e.g., Figure 17 The first interlayer insulating layer (ILD1) may cover the first conductive pattern 1200 and may be disposed on the first gate insulating layer. The first interlayer insulating layer may include an insulating material.

[0117] In such an embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be referenced above. Figure 3 The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are described. In one embodiment, for example, the first gate electrode 1230 may be associated with a reference. Figure 3 The gate terminal of the first transistor T1 is described.

[0118] In such an embodiment, the above reference Figure 3 The described gate terminal, first terminal, and second terminal can substantially correspond to the conductive pattern described later. However, this correspondence will not be described in detail, and it will be obvious to those skilled in the art.

[0119] refer to Figure 7 and Figure 8The second conductive pattern 1300 can be disposed on the first interlayer insulating layer. The second conductive pattern 1300 may include an anode initialization voltage line 1310, a first bottom gate electrode 1320, a second bottom gate electrode 1330, and a storage capacitor electrode 1340.

[0120] The anode initialization voltage line 1310 can provide the anode initialization voltage AINT to the seventh transistor T7.

[0121] The third gate signal GI can be provided to the first bottom gate electrode 1320. In an embodiment, the first bottom gate electrode 1320 can be arranged in an island shape along the first direction D1.

[0122] A second gate signal GC can be provided to a second bottom gate electrode 1330. In an embodiment, the second bottom gate electrode 1330 may extend in a first direction D1. In such an embodiment, the second bottom gate electrode 1330 may include a protrusion.

[0123] Storage capacitor electrode 1340 may form a storage capacitor CST together with the first gate electrode 1230. In one embodiment, for example, storage capacitor electrode 1340 may overlap with the first gate electrode 1230, and a high supply voltage ELVDD may be provided to storage capacitor electrode 1340. In an embodiment, opening H may be defined to pass through storage capacitor electrode 1340. The gate terminal of the first transistor T1 and the second terminal of the third transistor T3 may be connected to each other through opening H.

[0124] In one embodiment, for example, the second conductive pattern 1300 may include metal, alloy, conductive metal oxide, or transparent conductive material, etc.

[0125] Second interlayer insulation layer (e.g., Figure 17 The second interlayer insulating layer (ILD2) can cover the second conductive pattern 1300 and can be disposed on the first interlayer insulating layer. The second interlayer insulating layer may include an insulating material.

[0126] refer to Figure 9 and Figure 10 The second active pattern 1400 can be disposed on the second interlayer insulating layer. In one embodiment, for example, the second active pattern 1400 can overlap with the first bottom gate electrode 1320 and the second bottom gate electrode 1330.

[0127] In one embodiment, the second active pattern 1400 and the first active pattern 1100 may be disposed in different layers and may not overlap with the first active pattern 1100. In one embodiment, for example, the second active pattern 1400 may be formed separately from the first active pattern 1100. In one embodiment, for example, the first active pattern 1100 may include a silicon semiconductor, and the second active pattern 1400 may include an oxide semiconductor.

[0128] In an embodiment, the pixel structure PX may include a first transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 as silicon-based semiconductor elements, and a third transistor T3 and a fourth transistor T4 as oxide-based semiconductor elements. In one embodiment, for example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be PMOS transistors, while the third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0129] Second gate insulating layer (e.g., Figure 17 The second gate insulating layer (GI2) can cover the second active pattern 1400 and can be disposed on the second interlayer insulating layer. The second gate insulating layer may include an insulating material.

[0130] refer to Figure 11 and Figure 12 The third conductive pattern 1500 can be disposed on the second gate insulating layer. The third conductive pattern 1500 may include a gate initialization voltage line 1510, a third gate electrode 1520, a second gate electrode 1530, a first connection pattern 1540, and a shielding pattern 1550.

[0131] The gate initialization voltage line 1510 can transmit the gate initialization voltage VINT to the fourth transistor T4.

[0132] The third gate electrode 1520 may form a fourth transistor T4 together with a portion of the second active pattern 1400. In one embodiment, for example, a third gate signal GI may be provided to the third gate electrode 1520.

[0133] In this embodiment, the third gate electrode 1520 may overlap with the third contact hole CNT3. The third gate electrode 1520 may contact the first bottom gate electrode 1320 through the third contact hole CNT3.

[0134] The second gate electrode 1530 may form a third transistor T3 together with a portion of the second active pattern 1400. In one embodiment, for example, a second gate signal GC may be provided to the second gate electrode 1530.

[0135] In one embodiment, the second gate electrode 1530 may overlap with the second contact hole CNT2. The second gate electrode 1530 may contact the second bottom gate electrode 1330 through the second contact hole CNT2. In one embodiment, for example, the second contact hole CNT2 may overlap with a protrusion of the second bottom gate electrode 1330.

[0136] The first connection pattern 1540 can be configured to connect the gate terminal of the first transistor T1 and the second terminal of the third transistor T3.

[0137] In one embodiment, the first connection pattern 1540 may contact the first gate electrode 1230. In another embodiment, for example, the first connection pattern 1540 may overlap with a first contact hole CNT1. The first contact hole CNT1 may overlap with the opening H of the storage capacitor electrode 1340. The first connection pattern 1540 may contact the first gate electrode 1230 through the first contact hole CNT1.

[0138] In one embodiment, the shielding pattern 1550 may be configured to surround the first connection pattern 1540 on a plane or when viewed in a plan view in the thickness direction of the display device (perpendicular to the first direction D1 and the second direction D2). In one embodiment, for example, the second gate electrode 1530 may be arranged in an island shape along the first direction D1 to ensure space for the shielding pattern 1550 to be disposed therein.

[0139] The third interlayer insulation layer (e.g., Figure 17 The third interlayer insulating layer (ILD3) may cover the third conductive pattern 1500 and may be disposed on the second gate insulating layer. The third interlayer insulating layer may include insulating material.

[0140] refer to Figure 13 and Figure 14 The fourth conductive pattern 1600 can be disposed on the third interlayer insulating layer. The fourth conductive pattern 1600 may include a data line 1610, a high power supply voltage line 1620, a second connection pattern 1630, a first pad 1640, an anode initialization voltage connection pattern 1650, a gate initialization voltage connection pattern 1660, and a compensation connection pattern 1670.

[0141] Data voltage DATA can be provided to data line 1610. Data line 1610 can transmit the data voltage DATA to the second transistor T2. In one embodiment, for example, data line 1610 can be connected to the referenced above. Figure 2 The description corresponds to one of the first to fourth data lines DL1, DL2, DL3 and DL4.

[0142] In one embodiment, the data line 1610 may overlap with the shielding pattern 1550. In such an embodiment, the shielding pattern 1550 and the first connection pattern 1540 may be disposed in the same layer, and may be disposed between the first connection pattern 1540 and the data line 1610.

[0143] A high supply voltage ELVDD can be provided to a high supply voltage line 1620. The high supply voltage line 1620 can transmit the high supply voltage ELVDD to the fifth transistor T5. In one embodiment, the high supply voltage line 1620 can transmit the high supply voltage ELVDD to a shielding pattern 1550. In one embodiment, for example, the high supply voltage line 1620 can be connected to a reference... Figure 1 The described driving voltage line PL corresponds to this.

[0144] The first connection pattern 1540 and the second connection pattern 1630 can be configured to connect the gate terminal of the first transistor T1 and the second terminal of the third transistor T3.

[0145] A second connection pattern 1630 may be disposed on the first connection pattern 1540. In an embodiment, the second connection pattern 1630 may partially overlap with the first connection pattern 1540. In one embodiment, for example, the second connection pattern 1630 may not overlap with the first contact hole CNT1. In such an embodiment, the second connection pattern 1630 may not overlap with the opening H of the storage capacitor electrode 1340.

[0146] In one embodiment, the second connection pattern 1630 may overlap with the fourth contact hole CNT4 and the fifth contact hole CNT5. In one embodiment, for example, the fourth contact hole CNT4 may expose the upper surface of the first connection pattern 1540, and the second connection pattern 1630 may contact the first connection pattern 1540. In another embodiment, for example, the fifth contact hole CNT5 may expose the upper surface of the second connection pattern 1400, and the second connection pattern 1630 may contact the second active pattern 1400.

[0147] In one embodiment, the first contact hole CNT1, the fourth contact hole CNT4, and the fifth contact hole CNT5 may be spaced apart from each other. In one embodiment, for example, the first contact hole CNT1 and the fourth contact hole CNT4 may be spaced apart from each other, such that the second connection pattern 1630 can be formed with a minimum planar area.

[0148] The first pad 1640 can be configured to connect the second terminal of the sixth transistor T6 to the first terminal of the organic light-emitting diode (OLED). In an embodiment, the first pad 1640 can be spaced apart from the second connection pattern 1630 by a predetermined distance DTC. In one embodiment, for example, as the planar area of ​​the second connection pattern 1630 decreases, the planar area of ​​the pixel structure PX can decrease. Therefore, the resolution of the display device 10 can be increased.

[0149] The anode initialization voltage connection pattern 1650 can electrically connect the anode initialization voltage line 1310 and the first active pattern 1100. In one embodiment, for example, the anode initialization voltage AINT transmitted through the anode initialization voltage line 1310 can be provided to the seventh transistor T7 through the anode initialization voltage connection pattern 1650.

[0150] The gate initialization voltage connection pattern 1660 can electrically connect the gate initialization voltage line 1510 and the second active pattern 1400. In one embodiment, for example, the gate initialization voltage VINT transmitted via the gate initialization voltage line 1510 can be provided to the fourth transistor T4 through the gate initialization voltage connection pattern 1660. In another embodiment, the gate initialization voltage connection pattern 1660 can provide the gate initialization voltage VINT to a light blocking pattern (e.g., as described later) Figure 15 (Light blocking pattern 1730 in the text).

[0151] The compensation connection pattern 1670 can electrically connect the second active pattern 1400 and the first active pattern 1100. In one embodiment, for example, the first terminal of the third transistor T3 (e.g., the source terminal of the third transistor T3) can be connected to the second terminal of the first transistor T1 (e.g., the drain terminal of the first transistor T1) via the compensation connection pattern 1670.

[0152] First through-hole insulating layer (e.g., Figure 17 The first through-hole insulating layer (VIA1) can cover the fourth conductive pattern 1600 and can be disposed on the third interlayer insulating layer. The first through-hole insulating layer can include an organic insulating material. In one embodiment, for example, the first through-hole insulating layer can include a photoresist, polyacrylic resin, polyimide resin, or acrylic resin, etc.

[0153] refer to Figure 15 and Figure 16 The fifth conductive pattern 1700 can be disposed on the first via insulating layer. The fifth conductive pattern 1700 may include a first connecting line 1710 extending in the second direction D2, a second connecting line 1720 extending in the first direction D1, a light blocking pattern 1730, and a second pad 1740.

[0154] Data voltage DATA can be provided to the first connection line 1710 and the second connection line 1720. In an embodiment, the first connection line 1710 and the second connection line 1720 can be positioned within the display area DA. In one embodiment, for example, the first connection line 1710 and the second connection line 1720 can overlap with the first active pattern 1100.

[0155] In one embodiment, the first connection line 1710 and the second connection line 1720 can provide the data voltage DATA to the data line 1610. In one embodiment, for example, the first connection line 1710 and the second connection line 1720 can be referenced above. Figure 2 The description corresponds to one of the first connecting line FL1 and the second connecting line FL2.

[0156] In one embodiment, the light-blocking pattern 1730 may overlap with the second active pattern 1400. In one embodiment, for example, the second active pattern 1400 may include an oxide semiconductor. When the oxide semiconductor is exposed to light, leakage current can be generated by a third transistor T3 and a fourth transistor T4, both including the oxide semiconductor. In this case, the light may be external light or light generated by an organic light-emitting diode (OLED). In one embodiment, the light-blocking pattern 1730 may overlap with the second active pattern 1400 to effectively prevent the second active pattern 1400 from being exposed to light.

[0157] In one embodiment, the gate initialization voltage VINT can be provided to the light-blocking pattern 1730. In one embodiment, for example, the light-blocking pattern 1730 contacts the gate initialization voltage connection pattern 1660, such that the light-blocking pattern 1730 can receive the gate initialization voltage VINT.

[0158] The first pad 1640 and the second pad 1740 can be configured to connect the second terminal of the sixth transistor T6 and the first terminal of the organic light-emitting diode (OLED). In one embodiment, for example, the second pad 1740 may partially overlap with the first pad 1640.

[0159] Second through-hole insulating layer (e.g., Figure 21 The second through-hole insulating layer (VIA2) can cover the fifth conductive pattern 1700 and can be disposed on the first through-hole insulating layer. The second through-hole insulating layer can include an organic insulating material.

[0160] In an embodiment, the first electrode (e.g., Figure 21 The first electrode 1810 in the middle), the pixel defining layer (e.g., Figure 21 Pixel confinement layer (PDL) and emissive layer (e.g., Figure 21 The light-emitting layer 1820 in the middle) and the second electrode (e.g., Figure 21The second electrode 1830 can be sequentially disposed on the second through-hole insulating layer. In an embodiment, the first electrode can correspond to the first terminal of the organic light-emitting diode (OLED), and the second electrode can correspond to the second terminal of the OLED. In one embodiment, for example, the first electrode can contact the second pad 1740.

[0161] Figure 17 It is along Figure 16 The cross-sectional view taken by line I-I'. Specifically, Figure 17 It could be a cross-sectional view showing a portion of the first transistor and a portion of the third transistor.

[0162] refer to Figure 16 and Figure 17 The first active pattern 1100, the first gate electrode 1230, the storage capacitor electrode 1340, the second active pattern 1400, the first connection pattern 1540, the second connection pattern 1630, and the light blocking pattern 1730 can be sequentially disposed on the substrate SUB.

[0163] In an embodiment, the first contact hole CNT1 may be defined or formed in the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the second gate insulating layer GI2. The first contact hole CNT1 may overlap with the opening H of the storage capacitor electrode 1340 and the first connection pattern 1540. The first contact hole CNT1 may expose the upper surface of the first gate electrode 1230.

[0164] In an embodiment, the first connection pattern 1540 can contact the first gate electrode 1230 through the first contact hole CNT1.

[0165] In one embodiment, the fourth contact hole CNT4 may be defined or formed in the third interlayer insulating layer ILD3. The fourth contact hole CNT4 may overlap with the first connection pattern 1540. The fourth contact hole CNT4 may expose the upper surface of the first connection pattern 1540. In such an embodiment, the fourth contact hole CNT4 may not overlap with the first contact hole CNT1 and the opening H.

[0166] In one embodiment, the second connecting pattern 1630 can contact the first connecting pattern 1540 through the fourth contact hole CNT4. In one embodiment, for example, the second connecting pattern 1630 may partially overlap with the first connecting pattern 1540. In such an embodiment, the second connecting pattern 1630 may not overlap with the first contact hole CNT1. Therefore, in such an embodiment, the area of ​​the second connecting pattern 1630 on the plane can be reduced. Therefore, as referenced above... Figure 13 The area of ​​the pixel structure PX on the plane can be reduced, and the resolution of the display device 10 can be increased.

[0167] In an embodiment, the fifth contact hole CNT5 may be defined or formed within the second gate insulating layer GI2 and the third interlayer insulating layer ILD3. The fifth contact hole CNT5 may overlap with the second active pattern 1400. The fifth contact hole CNT5 may expose the upper surface of the second active pattern 1400.

[0168] In one embodiment, the second connection pattern 1630 can contact the second active pattern 1400 through the fifth contact hole CNT5. In one embodiment, for example, the portion of the second active pattern 1400 exposed by the fifth contact hole CNT5 can correspond to the second terminal of the third transistor T3. Therefore, in such an embodiment, the gate terminal of the first transistor T1 and the second terminal of the third transistor T3 can be electrically connected to each other through the first connection pattern 1540 and the second connection pattern 1630.

[0169] In an embodiment, the light blocking pattern 1730 may overlap with the first connecting pattern 1540 and the second connecting pattern 1630.

[0170] Figure 18 It is shown that it includes Figure 1 A plan view of the third and fourth conductive patterns in the display device. Figure 19 It is along Figure 18 The cross-sectional view taken from line II-II'.

[0171] refer to Figure 18 and Figure 19 The shielding pattern 1550 and the first connection pattern 1540 can be arranged in the same layer and can be arranged below the data line 1610. The high power supply voltage line 1620 to which the high power supply voltage ELVDD is supplied can be arranged in the same layer as the data line 1610.

[0172] In one embodiment, shielding pattern 1550 may shield the first connection pattern 1540. In one embodiment, for example, a constant voltage may be provided to shielding pattern 1550. In one embodiment, for example, the constant voltage may be a high supply voltage ELVDD. In such an embodiment, by providing the high supply voltage ELVDD to shielding pattern 1550, shielding pattern 1550 may prevent crosstalk between the first connection pattern 1540 and the data line 1610. In one embodiment, for example, shielding pattern 1550 may be configured to surround the first connection pattern 1540 in a plane. Therefore, shielding pattern 1550 may overlap with the data line 1610 and may extend toward the first connection pattern 1540.

[0173] Figure 20 It is shown that it includes Figure 1 A plan view of the fourth and fifth conductive patterns in the display device. Figure 21 It is along Figure 20 The cross-sectional view taken from line III-III'.

[0174] refer to Figure 20 and Figure 21 The first pad 1640 can be set to be spaced apart from the second connection pattern 1630 by a predetermined distance DTC'. The predetermined distance DTC' can be substantially the same as the one referenced above. Figure 13 The predetermined distance DTC described corresponds to this. In such an embodiment, as described above, the second connection pattern 1630 may not overlap with the opening H, and therefore, the planar area of ​​the second connection pattern 1630 can be reduced. Consequently, the area of ​​the pixel structure PX on the plane can be reduced, and the resolution of the display device 10 can be increased.

[0175] Figure 22 It is along Figure 16 The cross-sectional view taken by line IV-IV'. Specifically, Figure 22 This could be a cross-sectional view showing the third transistor T3.

[0176] refer to Figure 16 and Figure 22 The second bottom gate electrode 1330 can be disposed below the second active pattern 1400, and the second gate electrode 1530 can be disposed on the second active pattern 1400. The second bottom gate electrode 1330 and the second gate electrode 1530 can be connected to each other through the second contact hole CNT2. The light blocking pattern 1730 can overlap with the second active pattern 1400.

[0177] The second gate signal GC can be provided to the second bottom gate electrode 1330 and the second gate electrode 1530. In such an embodiment, when the display device 10 includes the second bottom gate electrode 1330, the conduction and / or cutoff characteristics of the third transistor T3 can be improved. In such an embodiment, as... Figure 11 As shown, as the second bottom gate electrode 1330 extends in the first direction D1, the second gate electrode 1530 can be arranged in an island shape. Therefore, space can be ensured where the shielding pattern 1550 is arranged.

[0178] Figure 23 It is along Figure 16 A cross-sectional view taken from line V-V'. Specifically, Figure 23 This could be a cross-sectional view showing the fourth transistor T4.

[0179] refer to Figure 16 and Figure 23A first bottom gate electrode 1320 may be disposed below the second active pattern 1400, and a third gate electrode 1520 may be disposed on the second active pattern 1400. The first bottom gate electrode 1320 and the third gate electrode 1520 may be connected to each other through a third contact hole CNT3. A light-blocking pattern 1730 may overlap with the second active pattern 1400. In one embodiment, for example, the light-blocking pattern 1730 may contact the gate initialization voltage connection pattern 1660, and the gate initialization voltage VINT may be provided through the gate initialization voltage connection pattern 1660.

[0180] The third gate signal GI can be provided to the first bottom gate electrode 1320 and the third gate electrode 1520. In such an embodiment, when the display device 10 includes the first bottom gate electrode 1320, the conduction and / or cutoff characteristics of the fourth transistor T4 can be improved.

[0181] The display device 10 can electrically connect the gate terminal of the first transistor T1 and the second terminal of the third transistor T3 via a first connection pattern 1540 and a second connection pattern 1630. In such an embodiment, the display device 10 includes a shielding pattern 1550 that shields the first connection pattern 1540, thereby effectively preventing crosstalk between the first connection pattern 1540 and the data line 1610. In such an embodiment, the second connection pattern 1630 partially overlaps with the first connection pattern 1540, thereby reducing the area of ​​the second connection pattern 1630 on the plane and increasing the resolution of the display device 10.

[0182] Figure 24 This is a plan view showing a display device according to an alternative embodiment. Figure 25 It is shown that it includes Figure 24 An enlarged view of the connecting lines in the display device. Figure 26 It is shown that it includes Figure 24 A circuit diagram of an embodiment of the pixel circuit and organic light-emitting diode in a display device. Specifically, Figure 25 It can be Figure 24 A magnified view of region A.

[0183] refer to Figure 24 , Figure 25 and Figure 26 An embodiment of the display device 20 may include a display area DA and a non-display area NDA surrounding the display area DA. The non-display area NDA may include a flexible curved area BA, a peripheral area SA between the display area DA and the curved area BA, and a pad area PA.

[0184] In one embodiment, for example, a pixel structure PX can be disposed in a display area DA, and a driver for driving the pixel structure PX can be disposed in a non-display area NDA. In another embodiment, for example, a pad portion PD and a data driver DDV can be disposed in a pad area PA, and a curved area BA can be curved based on a virtual bending axis. Since the pixel structure PX is not disposed in the peripheral area SA, the width of the peripheral area SA extending in the second direction D2 can be defined as the dead space of the display device 20.

[0185] In such an embodiment, the pixel structure PX, the data line DL connected to the pixel structure PX, the gate line GL connected to the pixel structure PX, the emission management line EML connected to the pixel structure PX, the drive voltage line PL connected to the pixel structure PX, and the connection line FL connected to the pixel structure PX can be disposed in the display area DA. In such an embodiment, the data line DL, the gate line GL, the emission management line EML, and the drive voltage line PL can be the same as those referenced above. Figure 1 The data lines DL, gate lines GL, emit management lines EML, and drive voltage lines PL are described in a basically the same way.

[0186] The connector FL can be electrically connected to the data drive DDV and the data line DL. The connector FL can receive the data voltage DATA from the data drive DDV and supply the data voltage DATA to the data line DL.

[0187] The driver may include a gate driver (GDV), a data driver (DDV), a transmit driver (EDV), and a pad section (PD). In such an embodiment, the driver may further include a timing controller, which can control the gate driver (GDV), the data driver (DDV), the transmit driver (EDV), and the pad section (PD). In such an embodiment, the gate driver (GDV), the data driver (DDV), the transmit driver (EDV), the pad section (PD), and the timing controller can be referenced above. Figure 1 The gate driver (GDV), data driver (DDV), transmitter driver (EDV), pad section (PD), and timing controller described are basically the same.

[0188] In an embodiment, such as Figure 25 As shown, data lines DL and FL can be positioned within the display area DA. In one embodiment, for example, first to fourth data lines DL1, DL2, DL3, and DL4, first FL1, and second FL2 can be positioned within the display area DA. In another embodiment, for example, FL can be a fan-out line electrically connecting the data driver DDV and the data lines DL.

[0189] In one embodiment, for example, the pixel structure PX may include first to fourth pixel structures disposed along a first direction D1. A first data line DL1 may be connected to the first pixel structure, a second data line DL2 may be connected to the second pixel structure, a third data line DL3 may be connected to the third pixel structure, and a fourth data line DL4 may be connected to the fourth pixel structure.

[0190] In one embodiment, the first connecting line FL1 may include a first vertical connecting line VFL1 and a first horizontal connecting line HFL1, and the second connecting line FL2 may include a second vertical connecting line VFL2 and a second horizontal connecting line HFL2. In one embodiment, for example, the first vertical connecting line VFL1 and the second vertical connecting line VFL2 may extend in a second direction D2, and the first horizontal connecting line HFL1 and the second horizontal connecting line HFL2 may extend in a first direction D1.

[0191] The first connection line FL1 can electrically connect the data driver DDV and the first data line DL1. In one embodiment, for example, a first data voltage can be provided to the first pixel structure through the first connection line FL1 and the first data line DL1.

[0192] In such an embodiment, the first vertical connection line VFL1 can be connected to the first transmission line SCL1, the first transmission line SCL1 can be connected to the first curved transmission line BCL1, and the first curved transmission line BCL1 can be connected to the first data transmission line DCL1.

[0193] In one embodiment, for example, the first vertical connecting line VFL1 can extend from the peripheral area SA to the display area DA, and can be set in the first layer (e.g., where...). Figure 38 The fifth conductive pattern 2700 is disposed in the first layer. The first transmission line SCL1 can be disposed in the peripheral area SA, and can be disposed in the second layer disposed below the first layer (e.g., where...). Figure 29 The first conductive pattern 2200 is set in the second layer. The first curved transmission line BCL1 can be set in the curved area BA and can also be set in the first layer. The first data transmission line DCL1 can be set in the pad area PA and can receive the first data voltage from the data driver DDV.

[0194] The second connection line FL2 can electrically connect the data driver DDV and the second data line DL2. In one embodiment, for example, a second data voltage can be provided to the second pixel structure via the second connection line FL2 and the second data line DL2.

[0195] In this embodiment, the second vertical connection line VFL2 can be connected to the second transmission line SCL2, the second transmission line SCL2 can be connected to the second curved transmission line BCL2, and the second curved transmission line BCL2 can be connected to the second data transmission line DCL2. In such an embodiment, the structures of the second vertical connection line VFL2, the second transmission line SCL2, the second curved transmission line BCL2, and the second data transmission line DCL2 can be substantially the same as the structures of the first vertical connection line VFL1, the first transmission line SCL1, the first curved transmission line BCL1, and the first data transmission line DCL1, and therefore, any repeated detailed descriptions thereof will be omitted.

[0196] The third data line DL3 can be connected to the data driver DDV. In one embodiment, for example, a third data voltage can be provided to the third pixel structure via the third data line DL3.

[0197] In such an embodiment, the third data line DL3 can be connected to the third transmission line SCL3, the third transmission line SCL3 can be connected to the third curved transmission line BCL3, and the third curved transmission line BCL3 can be connected to the third data transmission line DCL3.

[0198] In one embodiment, for example, a third data line DL3 can extend from the peripheral area SA to the display area DA, and can be disposed in the first layer. A third transmission line SCL3 can be disposed in the peripheral area SA, and can be disposed in a third layer located below the first layer (e.g., where...). Figure 30 The second conductive pattern 2300 is set in the third layer. The third curved transmission line BCL3 can be set in the curved area BA and can also be set in the first layer. The third data transmission line DCL3 can be set in the pad area PA and can receive the third data voltage from the data driver DDV.

[0199] The fourth data line DL4 can be connected to the data driver DDV. In one embodiment, for example, a fourth data voltage can be provided to the fourth pixel structure via the fourth data line DL4.

[0200] In this embodiment, the fourth data line DL4 can be connected to the fourth transmission line SCL4, the fourth transmission line SCL4 can be connected to the fourth curved transmission line BCL4, and the fourth curved transmission line BCL4 can be connected to the fourth data transmission line DCL4. In such an embodiment, the structures of the fourth data line DL4, the fourth transmission line SCL4, the fourth curved transmission line BCL4, and the fourth data transmission line DCL4 can be substantially the same as the structures of the third data line DL3, the third transmission line SCL3, the third curved transmission line BCL3, and the third data transmission line DCL3, and therefore, any repeated detailed descriptions thereof will be omitted.

[0201] In one embodiment, the second layer may be positioned below the third layer. In one embodiment, for example, the first transmission line SCL1 and the second transmission line SCL2 may be positioned below the third transmission line SCL3 and the fourth transmission line SCL4.

[0202] Therefore, in such an embodiment, the space allowance can be ensured in the second (or third) layer of the peripheral region SA, and additional lines can be further arranged within the space allowance. However, the invention is not limited thereto, and various modifications can be made to the connection structure and arrangement of the aforementioned lines.

[0203] In this embodiment, the connecting line FL is disposed in the display area DA, such that the width of the peripheral area SA of the display device 20 extending in the second direction D2 can be reduced compared to the width of the peripheral area of ​​a conventional display device extending in the second direction D2. Therefore, in such an embodiment, the dead space of the display device 20 can be reduced.

[0204] In such an embodiment, such as Figure 26 As shown, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, and a boost capacitor CBS. The pixel circuit PC may be electrically connected to the organic light-emitting diode (OLED) and may provide driving current to the OLED. In such an embodiment, the pixel circuit PC and the OLED may be connected to the above-referenced... Figure 3 The pixel circuits described are basically the same for PCs and OLEDs.

[0205] Figures 27 to 39 It is shown that it includes Figure 24 A plan view of the pixel structure in a display device.

[0206] refer to Figure 27 The display device 20 may include a pixel structure PX and a symmetrical pixel structure PX1 adjacent to the pixel structure PX. In one embodiment, for example, the structure of the symmetrical pixel structure PX1 may be substantially the same as the structure in which the structure of the pixel structure PX is symmetrical with respect to an imaginary line of symmetry SL. The pixel structure PX will be described in detail below.

[0207] refer to Figure 28 The pixel structure PX may include a substrate SUB and a first active pattern 2100 disposed on the substrate SUB.

[0208] The substrate SUB may include a glass substrate, a quartz substrate, or a plastic substrate, etc. In an embodiment, the substrate SUB may include a plastic substrate, and therefore the display device 20 may be a flexible display device. In such an embodiment, the substrate SUB may have a structure in which at least one organic film layer and at least one barrier layer are alternately stacked. In one embodiment, for example, the organic film layer may include or be formed of an organic material such as polyimide, and the barrier layer may include or be formed of an inorganic material such as silicon oxide or silicon nitride.

[0209] A buffer layer can be disposed on the substrate SUB. The buffer layer can effectively prevent metal atoms or impurities from diffusing from the substrate SUB into the first active pattern 2100. In such an embodiment, the buffer layer can allow the first active pattern 2100 to be uniformly formed by controlling the heat transfer rate during the crystallization process for forming the first active pattern 2100.

[0210] The first active pattern 2100 may be disposed on the buffer layer. In an embodiment, the first active pattern 2100 may include a silicon semiconductor. In one embodiment, for example, the first active pattern 2100 may include amorphous silicon or polycrystalline silicon, etc.

[0211] In one embodiment, ions may be selectively implanted into the first active pattern 2100. In one embodiment, for example, when the first transistor T1 and the second transistor T2 are PMOS transistors, the first active pattern 2100 may include a source region where cations are implanted, a drain region where cations are implanted, and a channel region where cations are not implanted.

[0212] First gate insulating layer (e.g., Figure 40 The first gate insulating layer (GI1) may cover the first active pattern 2100 and may be disposed on the substrate SUB. The first gate insulating layer may include an insulating material. In one embodiment, for example, the first gate insulating layer may include silicon oxide, silicon nitride, titanium oxide, or tantalum oxide, etc.

[0213] refer to Figure 29 The first conductive pattern 2200 can be disposed on the first gate insulating layer. The first conductive pattern 2200 may include a first gate line 2210, a gate electrode 2220, and a second gate line 2230.

[0214] The first gate line 2210 may be disposed on the first active pattern 2100 and may extend in the first direction D1. In an embodiment, the first gate line 2210 may form a second transistor T2 together with a portion of the first active pattern 2100. In one embodiment, for example, a first gate signal GW may be provided to the first gate line 2210.

[0215] In one embodiment, for example, the first gate line 2210 may together with another portion of the first active pattern 2100 form a seventh transistor T7. In one embodiment, for example, a fourth gate signal GB may be provided to the first gate line 2210. In one embodiment, for example, the first gate signal GW and the fourth gate signal GB may have substantially the same waveform, but with a phase difference or time difference.

[0216] The gate electrode 2220 can be used together with a portion of the first active pattern 2100 to form the first transistor T1.

[0217] The second gate line 2230 may be disposed on the first active pattern 2100 and may extend in the first direction D1. In one embodiment, for example, the second gate line 2230 may together with a portion of the first active pattern 2100 form a fifth transistor T5 and a sixth transistor T6. In such an embodiment, the second gate line 2230 may correspond to an emitter management line.

[0218] In one embodiment, for example, the first conductive pattern 2200 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. In one embodiment, for example, the first conductive pattern 2200 may include at least one material selected from silver (“Ag”), silver-containing alloys, molybdenum (“Mo”), molybdenum-containing alloys, aluminum (“Al”), aluminum-containing alloys, aluminum nitride (“AlN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), and indium zinc oxide (“IZO”).

[0219] First interlayer insulation layer (e.g., Figure 40 The first interlayer insulating layer (ILD1) may cover the first conductive pattern 2200 and may be disposed on the first gate insulating layer. The first interlayer insulating layer may include an insulating material.

[0220] In such an embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be referenced above. Figure 26 The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 described correspond to each other. In one embodiment, for example, the gate electrode 2220 may be as described above. Figure 26 The gate terminal of the first transistor T1 is described.

[0221] Additionally, refer to Figure 26The described gate terminal, first terminal, and second terminal can substantially correspond to the conductive pattern described later. However, this correspondence will not be described in detail, and it will be obvious to those skilled in the art.

[0222] refer to Figure 30 and Figure 31 The second conductive pattern 2300 can be disposed on the first interlayer insulating layer. The second conductive pattern 2300 may include a gate initialization voltage line 2310, a third gate line 2320, a fourth gate line 2330, and a storage capacitor electrode 2340.

[0223] The gate initialization voltage line 2310 may extend in the first direction D1. In an embodiment, the gate initialization voltage line 2310 may transmit the gate initialization voltage VINT to the fourth transistor T4. In one embodiment, for example, the gate initialization voltage line 2310 may transmit the gate initialization voltage VINT to the second active pattern (e.g., Figure 32 The second active pattern 2400).

[0224] The third gate line 2320 may extend in the first direction D1. In an embodiment, the third gate line 2320 may transmit the second gate signal GC to the third transistor T3. In one embodiment, for example, the third gate line 2320 may contact the first top electrode (e.g., Figure 42 The first top electrode 2530).

[0225] The fourth gate line 2330 may extend in the first direction D1. In an embodiment, the fourth gate line 2330 may transmit the third gate signal GI to the fourth transistor T4. In one embodiment, for example, the fourth gate line 2330 may contact the second top electrode (e.g., Figure 43 The second top electrode 2540 in the middle.

[0226] The storage capacitor electrode 2340 may extend in the first direction D1. In an embodiment, the storage capacitor electrode 2340 may form a storage capacitor CST together with the gate electrode 2220. In one embodiment, for example, the storage capacitor electrode 2340 may overlap with the gate electrode 2220, and a high supply voltage ELVDD may be provided to the storage capacitor electrode 2340.

[0227] In an embodiment, the opening H may be defined to extend through the storage capacitor electrode 2340 to expose the upper surface of the gate electrode 2220. The gate electrode 2220 may contact the first connection pattern (e.g., ...) through the opening H. Figure 40 (First connection pattern 2520). In one embodiment, for example, the gate terminal of the first transistor T1 and the second terminal of the third transistor T3 can be electrically connected to each other through an opening H.

[0228] In one embodiment, for example, the second conductive pattern 2300 may include metal, alloy, conductive metal oxide, or transparent conductive material, etc.

[0229] Second interlayer insulation layer (e.g., Figure 40 The second interlayer insulating layer (ILD2) can cover the second conductive pattern 2300 and can be disposed on the first interlayer insulating layer. The second interlayer insulating layer can include an insulating material.

[0230] refer to Figure 32 and Figure 33 The second active pattern 2400 can be disposed on the second interlayer insulating layer. In one embodiment, for example, the second active pattern 2400 can overlap with the third gate line 2320 and the fourth gate line 2330.

[0231] In one embodiment, the second active pattern 2400 and the first active pattern 2100 may be disposed in different layers and may not overlap with the first active pattern 2100. In one embodiment, for example, the second active pattern 2400 may be formed separately from the first active pattern 2100. In one embodiment, for example, the first active pattern 2100 may include a silicon semiconductor, and the second active pattern 2400 may include an oxide semiconductor.

[0232] In an embodiment, the pixel structure PX may include a first transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 as silicon-based semiconductor elements, and a third transistor T3 and a fourth transistor T4 as oxide-based semiconductor elements. In one embodiment, for example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be PMOS transistors, while the third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0233] Second gate insulating layer (e.g., Figure 40 The second gate insulating layer (GI2) can cover the second active pattern 2400 and can be disposed on the second interlayer insulating layer. The second gate insulating layer may include an insulating material.

[0234] refer to Figure 34 and Figure 35 The third conductive pattern 2500 can be disposed on the second gate insulating layer. The third conductive pattern 2500 may include a third connection pattern 2510, a first connection pattern 2520, a first top electrode 2530, and a second top electrode 2540.

[0235] In an embodiment, the third connection pattern 2510 can provide the anode initialization voltage AINT to the seventh transistor T7. The third connection pattern 2510 can also provide the anode initialization voltage AINT to the fourth connection pattern (e.g., Figure 41 (The fourth connection pattern 2630). In one embodiment, for example, the third connection pattern 2510 may contact the fourth connection pattern.

[0236] In an embodiment, the third connection pattern 2510 may be connected to the first gate line 2210, the fourth gate line 2330, and the vertical connection line (e.g., Figure 41 The vertical connector (2720) overlaps. This will be referenced later. Figure 41 To describe in more detail.

[0237] In an embodiment, the first connection pattern 2520 can electrically connect the gate terminal of the first transistor T1 and the second terminal of the third transistor T3. The first connection pattern 2520 can contact the gate electrode 2220 and the second connection pattern (e.g., Figure 40 (Second connection pattern 2660 in the diagram). In one embodiment, for example, the gate electrode 2220, the opening H of the storage capacitor electrode 2340, and the first connection pattern 2520 may overlap each other. In such an embodiment, the first connection pattern 2520 may overlap with the first contact hole CNT1-1. The first contact hole CNT1-1 may overlap with the opening H of the storage capacitor electrode 2340. The first connection pattern 2520 can contact the gate electrode 2220 through the first contact hole CNT1-1. This will be referred to later. Figure 40 To describe in more detail.

[0238] In one embodiment, the first top electrode 2530 can provide the second gate signal GC to the third transistor T3. The first top electrode 2530 can contact the third gate line 2320. In one embodiment, for example, the first top electrode 2530 can overlap with the third gate line 2320 and the second active pattern 2400. This will be referred to later. Figure 42 To describe in more detail.

[0239] In one embodiment, the second top electrode 2540 can provide the third gate signal GI to the fourth transistor T4. The second top electrode 2540 can contact the fourth gate line 2330. In one embodiment, for example, the second top electrode 2540 can overlap with the fourth gate line 2330 and the second active pattern 2400.

[0240] The third interlayer insulation layer (e.g., Figure 40 The third interlayer insulating layer (ILD3) may cover the third conductive pattern 2500 and may be disposed on the second gate insulating layer. The third interlayer insulating layer may include insulating material.

[0241] refer to Figure 36 and Figure 37 The fourth conductive pattern 2600 can be disposed on the third interlayer insulating layer. The fourth conductive pattern 2600 may include a horizontal connecting line 2610, a data voltage pad 2620, a fourth connection pattern 2630, a gate initialization voltage connection pattern 2640, a shielding pattern 2650, a second connection pattern 2660, a first pad 2670, and a compensation connection pattern 2680.

[0242] The horizontal connection line 2610 may extend in the first direction D1. In an embodiment, the horizontal connection line 2610 may transmit the data voltage DATA to the second transistor T2. The horizontal connection line 2610 may contact the vertical connection line (e.g., Figure 38 Vertical connector 2720) and data cable (e.g., Figure 38 Data cable 2710). In one embodiment, for example, horizontal connector 2610 can be connected to... Figure 25 The first horizontal connector HFL1 or the second horizontal connector HFL2 corresponds to it.

[0243] In this embodiment, the horizontal connection line 2610 may overlap with the third connection pattern 2510. Therefore, the area of ​​the pixel structure PX on the plane can be reduced. Furthermore, the third connection pattern 2510 may overlap with the fourth gate line 2330 and the horizontal connection line 2610. Therefore, the third connection pattern 2510 can effectively prevent crosstalk between the fourth gate line 2330 and the horizontal connection line 2610.

[0244] The data voltage pad 2620 can provide a data voltage DATA to the first active pattern 2100. The data voltage pad 2620 can contact the first active pattern 2100 and the data line. In one embodiment, for example, the data voltage pad 2620 can overlap with the first active pattern 2100 and the data line.

[0245] In one embodiment, the fourth connection pattern 2630 can provide the anode initialization voltage AINT to the seventh transistor T7. In one embodiment, for example, the fourth connection pattern 2630 can provide the anode initialization voltage AINT to the first active pattern 2100. The fourth connection pattern 2630 can contact the first active pattern 2100.

[0246] In an embodiment, the fourth connection pattern 2630 may be connected to the first gate line 2210, the third gate line 2320, and the vertical connection line (e.g., Figure 41 The vertical connector (2720) overlaps. This will be referenced later. Figure 41 To describe in more detail.

[0247] Gate initialization voltage connection pattern 2640 can provide the gate initialization voltage VINT to the fourth transistor T4. In one embodiment, for example, gate initialization voltage connection pattern 2640 can provide the gate initialization voltage VINT to the second active pattern 2400. Gate initialization voltage connection pattern 2640 can contact gate initialization voltage line 2310 and the second active pattern 2400.

[0248] The shielding pattern 2650 can provide a high supply voltage EGLDD to the first active pattern 2100. In an embodiment, the shielding pattern 2650 can provide a high supply voltage line (e.g., Figure 45 The high power supply voltage line 2740 and the first active pattern 2100 are electrically connected. In one embodiment, for example, a shielding pattern 2650 may extend in a first direction D1 and may contact the high power supply voltage line and the first active pattern 2100. The shielding pattern 2650 may overlap with the high power supply voltage line and the first active pattern 2100. This will be referred to later. Figure 45 To describe in more detail.

[0249] In an embodiment, the shielding pattern 2650 may overlap with the vertical connecting line and the second gate line 2230. Therefore, the shielding pattern 2650 can effectively prevent crosstalk between the vertical connecting line and the second gate line 2230. This will be referred to later. Figure 44 To describe in more detail.

[0250] In one embodiment, a shielding pattern 2650 may be disposed between the vertical connecting line and the first connecting pattern 2520. Therefore, the shielding pattern 2650 can prevent crosstalk between the vertical connecting line and the first connecting pattern 2520. This will be referred to later. Figure 44 To describe in more detail.

[0251] In one embodiment, the second connection pattern 2660 can electrically connect the gate terminal of the first transistor T1 and the second terminal of the third transistor T3. The second connection pattern 2660 can contact the second active pattern 2400 and the first connection pattern 2520. In one embodiment, for example, the second connection pattern 2660 can overlap with the second active pattern 2400 and the first connection pattern 2520. In such an embodiment, the second connection pattern 2660 may not overlap with the first contact hole CNT1-1. Therefore, the second connection pattern 2660 can be formed with a minimal planar area. In such an embodiment, the second connection pattern 2660 can overlap with the fourth contact hole CNT4-1 and the fifth contact hole CNT5-1. Therefore, the second connection pattern 2660 can contact the first connection pattern 2520 and the second active pattern 2400. This will be referred to later. Figure 40 To describe in more detail.

[0252] The first pad 2670 can provide the anode initialization voltage AINT to the first electrode (e.g., ...). Figure 40 The first electrode 2810).

[0253] The compensation connection pattern 2680 can electrically connect the second active pattern 2400 and the first active pattern 2100. In one embodiment, for example, the first terminal of the third transistor T3 (e.g., the source terminal of the third transistor T3) can be connected to the second terminal of the first transistor T1 (e.g., the drain terminal of the first transistor T1) via the compensation connection pattern 2680.

[0254] First through-hole insulating layer (e.g., Figure 40 The first through-hole insulating layer (VIA1) can cover the fourth conductive pattern 2600 and can be disposed on the third interlayer insulating layer. The first through-hole insulating layer can include an organic insulating material. In one embodiment, for example, the first through-hole insulating layer can include a photoresist, polyacrylic resin, polyimide resin, or acrylic resin, etc.

[0255] refer to Figure 38 and Figure 39 The fifth conductive pattern 2700 can be disposed on the insulating layer of the first via. The fifth conductive pattern 2700 may include a data line 2710, a vertical connection line 2720, a second pad 2730, and a high power supply voltage line 2740.

[0256] Data line 2710 may extend in the second direction D2. In one embodiment, data line 2710 may transmit data voltage DATA to the second transistor T2. In one embodiment, for example, data line 2710 may contact data voltage pad 2620.

[0257] In one embodiment, data line 2710 can transmit data voltage DATA from data driver DDV to data voltage pad 2620. In such an embodiment, data line 2710 can be connected to... Figure 25 The third data line DL3 or the fourth data line DL4 corresponds to this. In an alternative embodiment, data line 2710 can transmit the data voltage DATA from the horizontal connection line to the data voltage pad 2620. In such an embodiment, data line 2710 can be connected to... Figure 25 The first data line DL1 or the second data line DL2 corresponds to it.

[0258] The vertical connection line 2720 may extend in the second direction D2. In an embodiment, the vertical connection line 2720 may transmit the data voltage DATA to the second transistor T2. The vertical connection line 2720 may contact the horizontal connection line 2610. In one embodiment, for example, the vertical connection line 2720 may be connected to... Figure 25The first vertical connection line VFL1 or the second vertical connection line VFL2 corresponds.

[0259] In one embodiment, the fourth gate line 2330, the third connecting pattern 2510, and the vertical connecting line 2720 may overlap each other. In another embodiment, the first gate line 2210, the third connecting pattern 2510, the fourth connecting pattern 2630, and the vertical connecting line 2720 may overlap each other. In yet another embodiment, the third gate line 2320, the fourth connecting pattern 2630, and the vertical connecting line 2720 may overlap each other. This will be referred to later. Figure 41 To describe in more detail.

[0260] In one embodiment, the second gate line 2230, the shielding pattern 2650, and the vertical connecting line 2720 may overlap each other. This will be referred to later. Figure 44 To describe in more detail.

[0261] The high power supply voltage line 2740 may extend in the second direction D2. In an embodiment, the high power supply voltage line 2740 may transmit the high power supply voltage ELVDD through a shielding pattern 2650. In one embodiment, for example, the high power supply voltage line 2740 may contact the shielding pattern 2650.

[0262] In one embodiment, the high power supply voltage line 2740 may overlap with the second active pattern 2400. In one embodiment, for example, the second active pattern 2400 may include an oxide semiconductor. When the oxide semiconductor is exposed to light, leakage current may be generated by a third transistor T3 and a fourth transistor T4, both including the oxide semiconductor. In this case, the light may be external light or light generated by an organic light-emitting diode (OLED). In an embodiment of the display device 20, the high power supply voltage line 2740 overlaps with the second active pattern 2400 such that the second active pattern 2400 may not be exposed to light.

[0263] Figure 40 It is along Figure 39 The cross-sectional view taken from line VI-VI'.

[0264] refer to Figure 26 , Figure 39 and Figure 40The pixel structure PX can have a structure in which the substrate SUB, buffer layer BFR, first active pattern 2100, first gate insulating layer GI1, gate electrode 2220, first interlayer insulating layer ILD1, third gate line 2320, storage capacitor electrode 2340, second interlayer insulating layer ILD2, second active pattern 2400, second gate insulating layer GI2, first connection pattern 2520, third interlayer insulating layer ILD3, second connection pattern 2660, first via insulating layer VIA1, high power supply voltage line 2740, second via insulating layer VIA2, first electrode 2810, emitter layer 2820, and second electrode 2830 are sequentially arranged. The third gate line 2320 and storage capacitor electrode 2340 can be disposed in the same layer as each other. The first electrode 2810, emitter layer 2820, and second electrode 2830 can constitute an organic light-emitting structure 2800. In one embodiment, for example, the organic light-emitting structure 2800 can correspond to the organic light-emitting diode (OLED) described above.

[0265] In an embodiment, the first connection pattern 2520 and the second connection pattern 2660 may be configured to connect the gate terminal of the first transistor T1 and the second terminal of the third transistor T3. In one embodiment, for example, the first connection pattern 2520 may contact the gate electrode 2220, and the second connection pattern 2660 may contact the first connection pattern 2520 and the second active pattern 2400.

[0266] In one embodiment, the gate electrode 2220, the opening H of the storage capacitor electrode 2340, and the first connection pattern 2520 may overlap each other. In another embodiment, the second active pattern 2400 and the second connection pattern 2660 may overlap each other.

[0267] In such an embodiment, the first connection pattern 2520 can contact the gate electrode 2220 through a first contact hole CNT1-1 that overlaps with the opening H. In such an embodiment, the second connection pattern 2660 can contact the first connection pattern 2520 through a fourth contact hole CNT4-1 spaced apart from the first contact hole CNT1-1, and can contact the second active pattern 2400 through a fifth contact hole CNT5-1 spaced apart from the first contact hole CNT1-1 and the fourth contact hole CNT4-1. Therefore, the second connection pattern 2660 can partially overlap with the first connection pattern 2520.

[0268] In one embodiment, the display device 20 includes a first connection pattern 2520 and a second connection pattern 2660, which allows the area of ​​the pixel structure PX on the plane to be reduced. Therefore, the resolution of the display device 20 can be increased.

[0269] In an embodiment, a predetermined distance (e.g., Figure 36The DTC (Device Traceability Control) can be provided between the second connection pattern 2660 and the first pad 2670. In embodiments where the first connection pattern 2520 is disposed below the second connection pattern 2660, the second connection pattern 2660 may not be disposed in the area where the first connection pattern 2520 is disposed (e.g., Figure 40 In region G). Therefore, the first pad 2670 can be positioned at a predetermined distance DTC from the second connection pattern 2660 in the second direction D2. Therefore, the area of ​​the pixel structure PX on the plane can be reduced.

[0270] Figure 41 It is along Figure 39 The cross-sectional view taken from line VII-VII'.

[0271] refer to Figure 26 , Figure 39 and Figure 41 The pixel structure PX can have a structure in which the substrate SUB, buffer layer BFR, first active pattern 2100, first gate insulating layer GI1, first gate line 2210, first interlayer insulating layer ILD1, third gate line 2320, fourth gate line 2330, second interlayer insulating layer ILD2, second gate insulating layer GI2, third connecting pattern 2510, third interlayer insulating layer ILD3, horizontal connecting line 2610, fourth connecting pattern 2630, first via insulating layer VIA1, vertical connecting line 2720, second via insulating layer VIA2, first electrode 2810, emitter layer 2820, and second electrode 2830 are arranged sequentially. The third gate line 2320 and the fourth gate line 2330 can be disposed in the same layer as each other, and the horizontal connecting line 2610 and the fourth connecting pattern 2630 can be disposed in the same layer as each other.

[0272] In an embodiment, a first gate signal GW may be provided to a first gate line 2210, a second gate signal GC may be provided to a third gate line 2320, and a third gate signal GI may be provided to a fourth gate line 2330. Each of the first to third gate signals GW, GC, and GI may include a clock signal for turning on or off a transistor.

[0273] In one embodiment, the third connection pattern 2510 and the fourth connection pattern 2630 may provide the anode initialization voltage AINT to the first active pattern 2100. In one embodiment, for example, the fourth connection pattern 2630 may contact the third connection pattern 2510 and the first active pattern 2100. The third connection pattern 2510 may provide the anode initialization voltage AINT to the fourth connection pattern 2630, and the fourth connection pattern 2630 may provide the anode initialization voltage AINT to the first active pattern 2100. In one embodiment, for example, the anode initialization voltage AINT may be a constant voltage having a constant voltage level.

[0274] In one embodiment, horizontal connection line 2610 and vertical connection line 2720 can provide a data voltage DATA to data line 2710. In one embodiment, for example, horizontal connection line 2610 and vertical connection line 2720 can be in contact with each other. Vertical connection line 2720 can provide a data voltage DATA to horizontal connection line 2610, and horizontal connection line 2610 can provide a data voltage DATA to data line 2710. In one embodiment, for example, the data voltage DATA can have a variable voltage level to emit light from an organic light-emitting diode (OLED) with a desired brightness.

[0275] Crosstalk can occur between the vertical connection line 2720, which provides the data voltage DATA, and the first gate line 2210, which provides the first gate signal GW. Therefore, the voltage level of the data voltage DATA can be changed by the first gate signal GW.

[0276] Crosstalk can occur between the vertical connection line 2720, which provides the data voltage DATA, and the third gate line 2320, which provides the second gate signal GC. Therefore, the voltage level of the data voltage DATA can be changed by the second gate signal GC.

[0277] Crosstalk can occur between the vertical connection line 2720 (or horizontal connection line 2610) that provides the data voltage DATA and the fourth gate line 2330 that provides the third gate signal GI. Therefore, the voltage level of the data voltage DATA can be changed by the third gate signal GI.

[0278] If the voltage level of the data voltage DATA changes, the organic light-emitting diode (OLED) can emit light with an undesirable brightness. Therefore, users can visually identify stains.

[0279] In an embodiment, the display device 20 may include a third connection pattern 2510 and a fourth connection pattern 2630 to prevent crosstalk as described above.

[0280] In this embodiment, the first gate line 2210, the third connecting pattern 2510, the fourth connecting pattern 2630, and the vertical connecting line 2720 can be Figure 41 The regions C overlap with each other. In one embodiment, for example, the third connection pattern 2510 and the fourth connection pattern 2630 can prevent crosstalk between the first gate line 2210 and the vertical connection line 2720.

[0281] In this embodiment, the third gate line 2320, the fourth connecting pattern 2630, and the vertical connecting line 2720 can be... Figure 41 The regions D overlap with each other. In one embodiment, for example, the fourth connection pattern 2630 can prevent crosstalk between the third gate line 2320 and the vertical connection line 2720.

[0282] In this embodiment, the fourth gate line 2330, the third connecting pattern 2510, the horizontal connecting line 2610, and the vertical connecting line 2720 can be... Figure 41 The regions B overlap with each other. In one embodiment, for example, the third connection pattern 2510 can prevent crosstalk between the fourth gate line 2330 and the horizontal connection line 2610, and can prevent crosstalk between the fourth gate line 2330 and the vertical connection line 2720.

[0283] Figure 42 It is along Figure 35 The cross-sectional view taken from line VIII-VIII'.

[0284] refer to Figure 26 , Figure 35 and Figure 42 The pixel structure PX can have a structure in which the substrate SUB, buffer layer BFR, first gate insulating layer GI1, first interlayer insulating layer ILD1, third gate line 2320, second interlayer insulating layer ILD2, second active pattern 2400, second gate insulating layer GI2, first top electrode 2530 and third interlayer insulating layer ILD3 are arranged sequentially to each other.

[0285] In one embodiment, the third gate line 2320 may be disposed below the second active pattern 2400, and the first top electrode 2530 may be disposed on the second active pattern 2400. In such an embodiment, the third gate line 2320, the second active pattern 2400, and the first top electrode 2530 may overlap each other.

[0286] In one embodiment, the second gate signal GC can be provided to the third gate line 2320. In such an embodiment, the first top electrode 2530 can contact the third gate line 2320. Specifically, the first top electrode 2530 can contact the third gate line 2320 through the second contact hole CNT2-1. Therefore, the second gate signal GC can also be provided to the first top electrode 2530. Thus, the conduction and / or cutoff characteristics of the third transistor T3 can be improved.

[0287] Figure 43 It is along Figure 35 The cross-sectional view taken from line IX-IX'.

[0288] refer to Figure 26 , Figure 35 and Figure 43 The pixel structure PX may have a structure in which the substrate SUB, buffer layer BFR, first gate insulating layer GI1, first interlayer insulating layer ILD1, fourth gate line 2330, second interlayer insulating layer ILD2, second active pattern 2400, second gate insulating layer GI2, second top electrode 2540 and third interlayer insulating layer ILD3 are arranged sequentially to each other.

[0289] In one embodiment, the fourth gate line 2330 may be disposed below the second active pattern 2400, and the second top electrode 2540 may be disposed on the second active pattern 2400. In such an embodiment, the fourth gate line 2330, the second active pattern 2400, and the second top electrode 2540 may overlap each other.

[0290] In one embodiment, the third gate signal GI can be provided to the fourth gate line 2330. In such an embodiment, the second top electrode 2540 can contact the fourth gate line 2330. Specifically, the second top electrode 2540 can contact the fourth gate line 2330 through the third contact hole CNT3-1. Therefore, the second gate signal GC can also be provided to the second top electrode 2540. Thus, the conduction and / or cutoff characteristics of the fourth transistor T4 can be improved.

[0291] Figure 44 It is along Figure 39 A cross-sectional view taken by line X-X'.

[0292] refer to Figure 26 , Figure 39 and Figure 44The pixel structure PX can have a structure in which the substrate SUB, buffer layer BFR, first active pattern 2100, first gate insulating layer GI1, gate electrode 2220, second gate line 2230, first interlayer insulating layer ILD1, storage capacitor electrode 2340, second interlayer insulating layer ILD2, second gate insulating layer GI2, first connection pattern 2520, third interlayer insulating layer ILD3, shielding pattern 2650, first via insulating layer VIA1, vertical connection line 2720, second via insulating layer VIA2, first electrode 2810, emitter layer 2820, and second electrode 2830 are arranged sequentially. The gate electrode 2220 and the second gate line 2230 can be disposed in the same layer.

[0293] In one embodiment, for example, the first connection pattern 2520 can electrically connect the gate terminal of the first transistor T1 and the second terminal of the third transistor T3. A high supply voltage ELVDD can be provided to the shield pattern 2650. A vertical connection line 2720 can provide the data voltage DATA to the data line 2710. An emit management signal EM can be provided to the second gate line 2230. The emit management signal EM may include a clock signal for turning the transistor on or off.

[0294] Crosstalk can occur between the vertical connection line 2720 to which the data voltage DATA is supplied and the first connection pattern 2520. Therefore, the voltage level of the data voltage DATA can be changed.

[0295] Crosstalk can occur between the vertical connection line 2720, which provides the data voltage DATA, and the second gate line 2230, which provides the transmit management signal EM. Therefore, the voltage level of the data voltage DATA can be changed by the transmit management signal GC.

[0296] If the voltage level of the data voltage DATA changes, the organic light-emitting diode (OLED) can emit light with an undesirable brightness. Therefore, users can visually identify stains.

[0297] In an embodiment, the display device 20 may include a shielding pattern 2650 to prevent crosstalk as described above.

[0298] In this embodiment, the first connecting pattern 2520, the shielding pattern 2650, and the vertical connecting line 2720 can be... Figure 44 The regions E overlap with each other. In one embodiment, for example, the shielding pattern 2650 can prevent crosstalk between the first connecting pattern 2520 and the vertical connecting line 2720.

[0299] In this embodiment, the second gate line 2230, the shielding pattern 2650, and the vertical connecting line 2720 can be Figure 44The regions F overlap with each other. In one embodiment, for example, the shielding pattern 2650 can prevent crosstalk between the second gate line 2230 and the vertical connecting line 2720.

[0300] Figure 45 It is along Figure 39 The cross-sectional view taken from line XI-XI'.

[0301] refer to Figure 26 , Figure 39 and Figure 45 The pixel structure PX may have a structure in which the substrate SUB, buffer layer BFR, first active pattern 2100, first gate insulating layer GI1, first gate line 2210, gate electrode 2220, first interlayer insulating layer ILD1, third gate line 2320, fourth gate line 2330, storage capacitor electrode 2340, second interlayer insulating layer ILD2, second active pattern 2400, second gate insulating layer GI2, first top electrode 2530, second top electrode 2540, third interlayer insulating layer ILD3, fourth connection pattern 2630, shielding pattern 2650, second connection pattern 2660, first via insulating layer VIA1, second pad 2730, high power supply voltage line 2740, second via insulating layer VIA2, first electrode 2810, emitter layer 2820 and second electrode 2830 are arranged sequentially. The first gate line 2210 and gate electrode 2220 can be disposed in the same layer as each other, and the third gate line 2320, the fourth gate line 2330 and the storage capacitor electrode 2340 can be disposed in the same layer as each other. The first top electrode 2530 and the second top electrode 2540 can be disposed in the same layer as each other, the fourth connection pattern 2630, the shielding pattern 2650 and the second connection pattern 2660 can be disposed in the same layer as each other, and the second pad 2730 and the high power supply voltage line 2740 can be disposed in the same layer as each other.

[0302] In one embodiment, the high power supply voltage line 2740 can provide a high power supply voltage ELVDD to the first active pattern 2100. In one embodiment, for example, the high power supply voltage line 2740 can contact the shielding pattern 2650, and the shielding pattern 2650 can contact the first active pattern 2100. The high power supply voltage ELVDD can be provided to the high power supply voltage line 2740, the shielding pattern 2650, and the first active pattern 2100.

[0303] In one embodiment, the high power supply voltage line 2740 may overlap with the second active pattern 2400. In one embodiment, for example, the second active pattern 2400 may include an oxide semiconductor. When the oxide semiconductor is exposed to light, leakage current can be generated by a third transistor T3 and a fourth transistor T4, both including the oxide semiconductor. In this case, the light may be external light or light generated by an organic light-emitting diode (OLED). In another embodiment, the high power supply voltage line 2740 overlaps with the second active pattern 2400 such that the second active pattern 2400 may not be exposed to light.

[0304] The display device 20 can electrically connect the gate terminal of the first transistor T1 and the second terminal of the third transistor T3 via a first connection pattern 2520 and a second connection pattern 2660. In such an embodiment, when the display device 20 includes a shielding pattern 2650 that shields the first connection pattern 2520, the shielding pattern 2650 can prevent crosstalk between the first connection pattern 2520 and the data line 2710. In such an embodiment, the area of ​​the second connection pattern 2660 on the plane can be reduced by partially overlapping the second connection pattern 2660 and the first connection pattern 2520, and the resolution can be increased.

[0305] In such an embodiment, when the display device 20 includes the shielding pattern 2650, crosstalk between the second gate line 2230 and the connecting line can be effectively prevented, and crosstalk between the first connecting pattern 2520 and the connecting line can also be effectively prevented. Therefore, the display quality of the display device 20 can be improved.

[0306] In such an embodiment, the display device 20 includes a third connection pattern 2510 and a fourth connection pattern 2630, and crosstalk between the gate lines (e.g., the first gate line 2210, the third gate line 2320, and the fourth gate line 2330) and the connecting lines (e.g., the horizontal connecting line 2610 and the vertical connecting line 2720) can be effectively prevented. Therefore, the display quality of the display device 20 can be improved.

[0307] In such an embodiment, the display device 20 includes a first top electrode 2530 and a second top electrode 2540 to improve the conduction and / or cutoff characteristics of the transistor.

[0308] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0309] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made herein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: substrate; A first active pattern is disposed on the substrate; The first gate electrode is disposed on the first active pattern and together with the first active pattern forms the first transistor; A second active pattern is disposed on the first gate electrode; The second gate electrode is disposed on the second active pattern and together with the second active pattern forms the second transistor; A first connection pattern is disposed on the second active pattern and electrically connected to the first gate electrode; as well as The second connection pattern is disposed on the first connection pattern and electrically connected to the first connection pattern and the second active pattern.

2. The display device according to claim 1, wherein the first connection pattern and the second gate electrode are disposed in the same layer.

3. The display device according to claim 1, further comprising: A shielding pattern is disposed on the first connection pattern, wherein the shielding pattern receives a constant voltage; as well as A data line is disposed on the shielding pattern, wherein the data line overlaps with the shielding pattern and provides data voltage.

4. The display device according to claim 3, wherein the shielding pattern overlaps with the first connection pattern.

5. The display device according to claim 3, wherein the shielding pattern is disposed between the data line and the first connection pattern.

6. The display device according to claim 3, wherein the data line is disposed on the second connection pattern.

7. The display device according to claim 3, wherein the constant voltage is a power supply voltage.

8. The display device according to claim 7, further comprising: A power supply voltage line is disposed on the shielding pattern, wherein the power supply voltage line provides the power supply voltage to the shielding pattern.

9. The display device according to claim 1, wherein the second connection pattern partially overlaps with the first connection pattern.

10. The display device according to claim 9, further comprising: The storage capacitor electrode is disposed on the first gate electrode. The hole is defined to pass through the electrodes of the storage capacitor, and The second connection pattern does not overlap with the hole.

11. The display device according to claim 9, wherein: The first connection pattern contacts the first gate electrode through a first contact hole that overlaps with the first connection pattern and the first gate electrode, and The second connection pattern does not overlap with the first contact hole.

12. The display device of claim 11, wherein the second connection pattern contacts the first connection pattern through a second contact hole that overlaps with the first connection pattern and the second connection pattern.

13. The display device of claim 12, wherein the second connection pattern contacts the second active pattern through a third contact hole that overlaps with the second connection pattern and the second active pattern.

14. The display device according to claim 13, wherein the first contact hole, the second contact hole and the third contact hole are spaced apart from each other.

15. The display device according to claim 1, further comprising: The first bottom gate electrode is disposed below the second active pattern and electrically connected to the second gate electrode, and The second gate electrode is arranged in an island shape.

16. The display device of claim 15, wherein the first bottom gate electrode overlaps with the second gate electrode.

17. The display device according to claim 16, further comprising: The third gate electrode is disposed on the second active pattern and together with the second active pattern forms the third transistor; as well as The second bottom gate electrode is disposed below the second active pattern, overlaps with the third gate electrode, and is electrically connected to the third gate electrode.

18. The display device according to claim 1, wherein: The first active pattern comprises polysilicon, and The second active pattern includes an oxide semiconductor.

19. The display device according to claim 18, further comprising: A light-blocking pattern is disposed on the second connecting pattern and overlaps with the second active pattern.

20. The display device according to claim 1, further comprising: A first gate line is disposed between the first active pattern and the second active pattern, and together with the first active pattern, forms a fourth transistor.

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