Processing input / output store instructions

Abstract

A data processing system (210) and method for processing an input / output store instruction (30) includes a system nest (18) communicatively coupled to at least one input / output bus (22) by an input / output bus controller (20). The data processing system (210) further includes at least a data processing unit (216) including a core (12), system firmware (10), and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load data from and / or store data to at least one external device (214) communicatively coupled to the input / output bus (22). The data processing unit (216) is configured to complete the input / output store instruction (30) prior to completion of execution of the input / output store instruction (30) in the system nest (18). The asynchronous core-nest interface (14) includes an input / output status array (44) having a plurality of input / output status buffers (24).

Description

Technical Field

[0001] This invention relates generally to data processing systems, and more specifically to methods for processing input / output stored instructions to multiple external devices, as well as computer program products and data processing systems. Background Technology

[0002] A computing environment may include one or more types of input / output devices, including different types of adapters. One type of adapter is a Peripheral Component Interconnect (PCI) or Fast Peripheral Component Interconnect (PCIe) adapter. This adapter includes one or more address spaces for transferring data between the adapter and the system attached to the adapter.

[0003] In some systems, a portion of the address space of the central processing unit (CPU) coupled to the adapter is mapped into the adapter's address space, allowing CPU instructions that access memory to directly manipulate data in the adapter's address space.

[0004] Communication with an adapter (such as a PCI or PCIe adapter) can be facilitated by control commands specifically designed to send and receive data to and from the adapter and to facilitate communication.

[0005] In the prior art, storage instructions for storing data in an adapter include, for example, obtaining machine instructions for execution, defined according to a computer architecture for computer execution, including, for example, an opcode field identifying the store-to-adapter instruction. A first field identifies a first location including the data to be stored in the adapter. A second field identifies a second location, the contents of which include a function handle identifying the adapter, the name of the address space within the adapter where the data will be stored, and an offset within that address space. The machine instructions are executed, the execution including using the function handle to obtain a function table entry associated with the adapter. At least one of the information in the function table entry and the offset is used to obtain the adapter's data address. Data is stored from the first location in a specific location within the address space identified by the name of the address space, the specific location being identified by the adapter's data address.

[0006] A common feature of large multiprocessor systems is the ability to quiesce all processors within a target region. The purpose of quiescing is to temporarily halt or alter the state of a processor or group of processors to perform, for example, system updates or backups. In some instances, quiescing interrupts apply only to a subset of system resources. In such cases, the system can be partitioned into different regions. For a quiescing operation applicable to one region (the target region), processors outside the target region are allowed to continue running, although new transitions may be blocked. Typically, at least one system controller or other mechanism broadcasts quiescing to all physical processors in the system, collects quiescing status information, and either instructs the requesting processor when all processors have been started, or ignores (filters out) the quiescing request.

[0007] A silence controller can be communicatively coupled to a processor in a multiprocessor system and a silence state machine configured to receive silence requests. The computer system is configured to perform a method comprising: receiving a silence request from a requesting processor, which is one of a plurality of processors in the multiprocessor system, at the silence controller; and determining, based on the state of the silence state machine, that the silence request is not accepted. The method further comprises, based on the unaccepted request, generating a rejection message configured to indicate that the silence request has been rejected; retaining the rejection message until a silence command is broadcast to the multiprocessor system, the silence command being based on a different silence request; and, based on the silence controller detecting the broadcast of the silence command, sending a rejection message to the requesting processor. Summary of the Invention

[0008] A data processing system for processing input / output store instructions is proposed, comprising a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system further includes at least a data processing unit comprising a kernel, system firmware, and an asynchronous kernel-nested interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load data from and / or store data to at least one external device communicatively coupled to the input / output bus. The asynchronous kernel-nested interface includes an input / output state array with multiple input / output state buffers, and array management and access logic.

[0009] The data processing system is configured to execute: (i) an operating system running on the data processing system issues an input / output store instruction that specifies at least an input / output function having an offset address, data to be transferred, and / or a pointer to the data to be transferred, and the length of said data; (ii) a data processing unit is configured to identify the input / output function by the address specified in the input / output store instruction; (iii) a data processing unit is configured to verify whether access to the input / output function is permitted in the address space and at the client instance level, the client running on the data processing system; (iv) a data processing unit is configured to complete the input / output store instruction before the execution of the input / output store instruction in the system nesting is completed; (v) the system firmware is configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during the asynchronous execution of the input / output store instruction; and (vi) a barrier instruction delays the processing of the store instruction until all previous store instructions have been completed.

[0010] Advantageously, a barrier instruction can be introduced to order asynchronous memory instructions. Advantageously, the barrier instruction can be a PCI SMT thread barrier instruction, which is completed when all previous PCI memory instructions have been sent to the PCIe bus for that SMT thread.

[0011] A data processing system according to a first embodiment of the present invention includes instructions loaded from at least one external device of the data processing system and stored in at least one external device of the data processing system via an input / output bus. Asynchronous instructions are completed before the data is stored in the external device, while synchronous instructions are completed after the data is stored in the external device. Within the embodiments described herein, PCI will be interchangeably used with any other input / output technology, and therefore the embodiments of the invention are not limited to PCI.

[0012] Embodiments of the present invention describe the execution of input / output stored instructions in a strictly ordered manner observable from the architectural boundaries, while the actual execution within the hardware of the data processing unit (CPU) may be unordered.

[0013] According to embodiments of the present invention, PCI storage instructions can be executed asynchronously through asynchronous execution and asynchronous state processing of PCIe storage effects. Asynchronous reliable execution is based on the reliable forwarding mechanism in the microarchitecture of the data processing system of the present invention.

[0014] Existing PCI storage and block instructions are typically synchronous until the PCI storage data has been transferred to the PCIe interface and completed and returned to the processing unit.

[0015] The PCI standard only requires asynchronous transmission commands for PCI information, which is typically achieved by aggregating asynchronously transmitted data through a storage queue in the processor.

[0016] Advantageously, according to embodiments of the invention, improvements in the number of cycles per instruction can be achieved by replacing synchronous PCI instructions with reliable asynchronous transmission processing of input / output storage instructions.

[0017] As a replacement or supplement to the data to be transmitted, the storage instructions according to embodiments of the present invention may also specify a pointer to the main memory, which should be used to retrieve data from it rather than directly containing the data.

[0018] The client instance level can also mean that a single client or host can run on the data processing system.

[0019] The address of the offset of the input / output function itself can be a virtual, physical, or logical address. Virtual and logical addresses are usually translated into physical addresses by the memory management unit (MMU), and then the physical address can be used to identify which function and offset are being referred to.

[0020] In this article, the physical address refers to "the lowest address in the address translation hierarchy that can be accessed from within the client / operating system".

[0021] Advantageously, input / output status buffers can collect return status from system nesting and / or from the input / output bus controller, particularly completion messages from system nesting. These input / output status buffers, by collecting return status, act as asynchronous system message buffers supporting asynchronous delivery processes. Advantageously, for fast response, the input / output status buffers can be directly integrated into the asynchronous kernel-nested interface.

[0022] According to an advantageous embodiment of the data processing system of the present invention, a barrier instruction can restrict the serial processing of storage instructions for a single input / output bus controller. Therefore, it is possible to effectively order storage instructions for that input / output bus controller to ensure that messages reach specific external devices.

[0023] According to an advantageous embodiment of the data processing system of the present invention, a barrier instruction can restrict the serial processing of stored instructions for a single input / output function, particularly a single external input / output device. Therefore, it is possible to effectively order stored instructions for the input / output bus controller to ensure that messages reach the designated external device.

[0024] According to an advantageous embodiment of the data processing system of the present invention, the array management and access logic can provide the ability to summarize and query all input / output state buffers of the input / output state array, returning aggregated information about the states of the input / output state buffers. In this way, information can be efficiently collected from the input / output state buffers.

[0025] According to an advantageous embodiment of the data processing system of the present invention, the system firmware may include array management logic that allocates / releases input / output state buffers in the input / output state array and / or initiates the start of new memory instructions. Therefore, idle state buffers can be attributed to further memory instructions. The orderly processing of memory instructions can be handled in an efficient and time-saving manner.

[0026] According to an advantageous embodiment of the data processing system of the present invention, the data processing unit can delay the execution of asynchronous and / or synchronous store instructions until the input / output status buffer is available to store information about the completion of pending store instructions. Thus, the sequencing process of multiple store instructions to multiple input / output devices can be handled in an efficient manner, providing the ability to save processing time.

[0027] According to an advantageous embodiment of the data processing system of the present invention, the input / output status buffer can collect message status from system nesting and / or from the input / output bus controller, particularly completion status from system nesting. In this way, information regarding the completion status of different stored instructions can be processed in an orderly and efficient manner.

[0028] According to an advantageous embodiment of the data processing system of the present invention, message states and / or completion states can be numbered using input / output state buffer indices. Numbering enables the processing of messages, particularly completion states, in an orderly and efficient manner for further processing of other stored instructions.

[0029] According to an advantageous embodiment of the data processing system of the present invention, the aggregation buffer can be communicatively coupled to an asynchronous kernel-nested interface via an asynchronous bus. Thus, the aggregation buffer can continuously process data directly sent by the asynchronous kernel-nested interface until all data to be transmitted to external devices has been stored in the aggregation buffer. In this way, asynchronous transmission mechanisms for transferring data from the asynchronous kernel-nested interface can be advantageously supported.

[0030] According to an advantageous embodiment of the data processing system of the present invention, if the length of the source data exceeds 8 bytes, the data can be transmitted to the aggregation buffer in multiple data packets via an asynchronous transmission mechanism with early completion messages, using input / output storage instructions; otherwise, the data can be transmitted in a single data packet. This asynchronous transmission mechanism is advantageous because the transmitting device is free for reuse in earlier states.

[0031] According to an advantageous embodiment of the data processing system of the present invention, the system firmware may include asynchronous input / output driver code for processing input / output storage instructions. Thus, an asynchronous transfer mechanism can be used to transfer data from the data processing unit to an external device. Further, advantageously, the kernel may include asynchronous setup code for processing memory requests for status information of the asynchronous input / output driver code. This asynchronous setup code can further facilitate asynchronous transfer mechanisms via aggregate buffers to system nesting and input / output bus controllers.

[0032] According to an advantageous embodiment of the data processing system of the present invention, the asynchronous kernel-nested interface may include an asynchronous kernel-nested interface forwarding component for forwarding locally completed data. This component may be implemented in the hardware of the asynchronous kernel-nested interface. Therefore, advantageous asynchronous transmission modes for sending data in packets to an aggregation buffer can be supported.

[0033] According to an advantageous embodiment of the data processing system of the present invention, the aggregation buffer may include early completion logic for transmitting an idle-for-reuse message after a request has been sent. This enables processing to continue earlier, via the aggregation buffer, to the system nesting and input / output bus controllers.

[0034] Advantageously, the system firmware may include array management logic that allocates / releases input / output state buffers in the input / output state array and / or initiates new store instructions. Therefore, idle state buffers can be attributed to further store instructions. The ordered processing of store instructions can be handled in an efficient and time-saving manner.

[0035] According to an advantageous embodiment of the data processing system of the present invention, system messages may include one of the following: a hierarchical physical target address; an identifier for an SMT (Simultaneous Multithreading) thread or aggregation buffer; a data length; an input / output bus address; or an input / output status buffer index. This ensures the advantageous transmission of relevant information through the data processing system.

[0036] Furthermore, a method is proposed for processing input / output memory instructions for at least one external device in a data processing system, the data processing system including a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system also includes at least one data processing unit comprising a kernel, system firmware, and an asynchronous kernel-nested interface. The data processing unit is communicatively coupled to the system nest via an aggregate buffer. The external device is communicatively coupled to the input / output bus. The asynchronous kernel-nested interface includes an input / output state array with multiple input / output state buffers, and array management and access logic.

[0037] The method includes: (i) an operating system running on a data processing system issuing an input / output store instruction that specifies at least an input / output function having an offset address, data to be transferred, and / or a pointer to the data to be transferred, and the length of said data; (ii) a data processing unit being configured to identify the input / output function by the address specified in the input / output store instruction; (iii) a data processing unit being configured to verify whether access to the input / output function is permitted at the address space and at the client instance level, the client running on the data processing system; (iv) a data processing unit being configured to complete the input / output store instruction before the execution of the input / output store instruction in the system nesting is completed; (v) system firmware being configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during the asynchronous execution of the input / output store instruction; and (vi) a barrier instruction delaying the processing of the store instruction until all previous store instructions have been completed.

[0038] Advantageously, barrier instructions can be introduced to order asynchronous memory instructions. Advantageously, the barrier instruction can be a PCI SMT thread barrier instruction, which is completed when all previous PCI memory instructions have been sent to the PCIe bus for that SMT thread.

[0039] A method according to another embodiment of the invention includes loading and storing instructions from an external device of the data processing system to at least one external device of the data processing system via an input / output bus. Asynchronous instructions are completed before the data is stored on the external device, while synchronous instructions are completed after the data is stored on the external device. Within the embodiments described herein, PCI will be interchangeably used with any other input / output technology, and therefore the embodiments of the invention are not limited to PCI.

[0040] Embodiments of the present invention describe the execution of input / output stored instructions in a strictly ordered manner observable from above the architectural boundary, while the actual execution within the hardware of the data processing unit (CPU) may be unordered.

[0041] According to embodiments of the method of the present invention, PCI storage instructions can be executed asynchronously through asynchronous execution of PCIe storage effects and asynchronous state processing. Asynchronous reliable execution is based on the reliable forwarding mechanism in the microarchitecture of the data processing system of the present invention.

[0042] Existing PCI storage and block instructions are typically synchronous until the PCI storage data has been transferred to the PCIe interface and completed and returned to the processing unit.

[0043] The PCI standard only requires asynchronous sending commands for PCI information, which is typically achieved by aggregating asynchronously sent data through a storage queue in the processor.

[0044] Advantageously, according to embodiments of the method of the invention, improvements in the cycle time for each instruction can be achieved by replacing synchronous PCI instructions with reliable asynchronous transmission processing of input / output storage instructions.

[0045] As a replacement or supplement to the data to be transmitted, the storage instruction according to an embodiment of the present invention may also specify a pointer to the main memory, which should be used to retrieve data from it rather than directly containing the data.

[0046] The client instance level can also mean that a single client or host can run on the data processing system.

[0047] The address of the offset of the input / output function itself can be a virtual, physical, or logical address. Virtual and logical addresses are usually translated into physical addresses by the memory management unit (MMU), and then the physical address can be used to identify which function and offset are being referred to.

[0048] In this article, the physical address refers to "the lowest address in the address translation hierarchy that can be accessed from within the client / operating system".

[0049] According to an advantageous embodiment of the data processing system of the present invention, a barrier instruction can restrict the serial processing of storage instructions for a single input / output bus controller. Therefore, it is possible to effectively order storage instructions for that input / output bus controller to ensure that messages reach specific external devices.

[0050] According to an advantageous embodiment of the data processing system of the present invention, a barrier instruction can restrict the serial processing of stored instructions for a single input / output function, particularly a single external input / output device. Therefore, it is possible to effectively order stored instructions for the input / output bus controller to ensure that messages reach the designated external device.

[0051] According to an advantageous embodiment of the data processing system of the present invention, the array management and access logic can provide the ability to summarize and query all input / output state buffers of the input / output state array, returning aggregated information about the states of the input / output state buffers. In this way, information can be efficiently collected from the input / output state buffers.

[0052] According to an advantageous embodiment of the data processing system of the present invention, the system firmware may include array management logic that allocates / releases input / output state buffers in the input / output state array and / or initiates the start of new memory instructions. Therefore, idle state buffers can be attributed to further memory instructions. The orderly processing of memory instructions can be handled in an efficient and time-saving manner.

[0053] Advantageously, the input / output status buffer can collect message states from system nesting and / or from the input / output bus controller, particularly completion states from system nesting, where message states and / or completion states are numbered using the input / output status buffer index. In this way, information about the completion status of different stored instructions can be processed in an orderly and efficient manner. Numbering enables the possibility of processing messages, and especially completion states, in an orderly and efficient manner to further process other stored instructions.

[0054] According to an advantageous embodiment, the method may further include: (i) the operating system issuing an input / output store instruction; (ii) the system firmware (10) allocating an index for a free input / output state buffer; if no available free input / output state buffer index exists, waiting for the free input / output state buffer index; (iii) the system firmware injecting the store instruction into the asynchronous transmission engine; if blocked by another store instruction, waiting until the store instruction completes; (iv) depending on the length of the data: if the length of the data exceeds 8 bytes, the system firmware software repeatedly issues system messages to send data packets to the aggregation buffer until all data in the store block has been forwarded to the aggregation buffer, the system firmware software waiting until the system message has sent the data; otherwise, the system firmware issues a system message to send the data to the aggregation buffer; further independent of the length of the data, (v) the system firmware issues a system message to the aggregation buffer to asynchronously forward the data as a single nested message to the input / output bus controller, while waiting for the aggregation buffer to send a completion message; vi) The aggregation buffer injects the nested message into the system nest, wherein the aggregation buffer is idle for immediate reuse after the send operation, thereby signaling back to the system firmware; then the aggregation buffer sends an idle-for-reuse message; (vii) the system nest forwards the message to the target location; (viii) the input / output bus controller receives the message and forwards the data in the data frame to the input / output bus; (ix) the input / output bus controller sends a completion message to the system nest; (x) the system nest forwards the completion message to the initiating aggregation buffer; (xi) the aggregation buffer forwards the completion to the asynchronous kernel-nested interface; (xii) the asynchronous kernel-nested interface stores the completion status in the input / output status buffer for input / output status buffer indexing and signals the completion of the operation to the system firmware; (xiii) the system firmware updates the input / output status buffer track via the input / output status buffer index; and (xiv) the system firmware asynchronously signals the defect to the operating system in case of an error.

[0055] Only step (ii) is related to the length of the data, and it is different for data lengths exceeding 8 bytes compared to data lengths not exceeding 8 bytes.

[0056] According to an embodiment of the method of the present invention, data is transmitted to an aggregation buffer in the form of slices until all data of the storage block is forwarded to the aggregation buffer, wherein the system firmware waits until the data has been sent by the asynchronous kernel-nested interface.

[0057] Therefore, if the data is less than eight bytes, the process of filling the aggregation buffer with data packets in fragmented form can be skipped, and the data transfer to the external device can be completed in a single step. According to an advantageous embodiment of the method, if the source data is longer than eight bytes, the data can be transferred to the aggregation buffer in multiple data packets via an asynchronous transmission mechanism with early completion messages, using input / output storage instructions. This asynchronous transmission mechanism is advantageous because the sending device is free for reuse in earlier states.

[0058] According to an advantageous embodiment of the method of the present invention, the system firmware can use asynchronous input / output driver code to process input / output storage instructions. Thus, data can be transferred from the data processing unit to external devices using an asynchronous transfer mechanism.

[0059] According to an advantageous embodiment of the method of the present invention, the kernel can use asynchronous setup code to handle memory requests for state information of asynchronous input / output driver code. This asynchronous setup code can further facilitate asynchronous transfer mechanisms to system nesting and input / output bus controllers via aggregate buffers.

[0060] According to an advantageous embodiment of the method of the present invention, the asynchronous kernel-nested interface can use an asynchronous kernel-nested interface forwarding component to forward locally completed data. Therefore, advantageous asynchronous transmission modes for sending data in packets to an aggregation buffer can be supported.

[0061] According to an advantageous embodiment of the method of the present invention, the aggregation buffer can use early completion logic to deliver an idle-for-reuse message after a send request. This enables processing of data transfer to the system nesting and I / O bus controllers via the aggregation buffer to continue earlier.

[0062] Advantageously, input / output status buffers can collect return status from system nesting and / or from the input / output bus controller, particularly completion messages from system nesting. These input / output status buffers, by collecting return status, act as asynchronous system message buffers supporting asynchronous transmission processes.

[0063] According to an advantageous embodiment of the method of the present invention, the system message may include one of the following: a hierarchical physical target address; an identifier for sourcing an SMT thread or aggregation buffer; the length of the data; an input / output bus address; or an input / output status buffer index. This ensures the advantageous transmission of relevant information through the data processing system.

[0064] Furthermore, an advantageous computer program product is proposed for processing input / output storage instructions to at least one external device of a data processing system comprising a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system also includes at least one data processing unit comprising a kernel, system firmware, and an asynchronous kernel-nested interface. The data processing unit is communicatively coupled to the system nest via an aggregate buffer. The external device is communicatively coupled to the input / output bus. The asynchronous kernel-nested interface includes an input / output state array with multiple input / output state buffers, and array management and access logic.

[0065] The computer program product includes a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by the computer system to cause the computer system to perform a method comprising: (i) an operating system running on the data processing system issuing the input / output storage instruction, which specifies at least an input / output function having an offset of an address, data to be transferred and / or a pointer to the data to be transferred, and a length of the data; (ii) the data processing unit being configured to identify the input / output function by means of the address specified in the input / output storage instruction; (iii) (iv) The data processing unit is configured to verify whether access to the input / output function is permitted at the address space and at the client instance level, the client running on the data processing system; (v) The data processing unit is configured to complete the input / output storage instruction before the system completes the execution of the nested input / output storage instruction; (vi) The system firmware is configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during the asynchronous execution of the input / output storage instruction; (vi) A barrier instruction delays the processing of the storage instruction until all previous storage instructions have been completed.

[0066] Furthermore, a data processing system for executing data processing procedures is proposed, the data processing system including computer-readable program instructions for executing the above methods. Attached Figure Description

[0067] The invention, as well as the above and other objects and advantages, can be best understood from the following detailed description of the embodiments, but the invention is not limited to these embodiments.

[0068] Figure 1 A block diagram of a data processing system for processing input / output storage instructions for an external device, according to an embodiment of the present invention, is shown.

[0069] Figure 2 A message sequence diagram illustrating a method for processing input / output storage instructions for an external device according to an embodiment of the present invention is shown.

[0070] Figure 3 The first part of a flowchart illustrating a process for processing input / output storage instructions for an external device according to an embodiment of the present invention is shown.

[0071] Figure 4 The second part of a flowchart illustrating a process for processing input / output storage instructions for an external device according to an embodiment of the present invention is shown.

[0072] Figure 5 An exemplary embodiment of a data processing system for performing the method according to the invention is shown. Detailed Implementation

[0073] In the accompanying drawings, the same elements are denoted by the same reference numerals. The drawings are merely schematic and are not intended to describe specific parameters of the invention. Furthermore, the drawings are intended to illustrate only typical embodiments of the invention and should not be considered as limiting the scope of the invention.

[0074] The illustrative embodiments described herein provide a data processing system and method for disposing of input / output storage instructions. The data processing system includes a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system also includes at least one data processing unit, which includes a kernel, system firmware, and an asynchronous kernel-nested interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load data from and / or store data to external devices communicatively coupled to the input / output bus. The asynchronous kernel-nested interface includes an input / output state array having multiple input / output state buffers, and array management and access logic.

[0075] An illustrative embodiment may be used in a method comprising: (i) an operating system running on a data processing system specifying at least an input / output function having an offset address, data to be transferred, and / or a pointer to the data to be transferred, and the length of said data; (ii) a data processing unit configured to identify the input / output function by means of an address specified in an input / output store instruction; (iii) a data processing unit configured to verify whether access to the input / output function is permitted at the address space and at the client instance level, the client running on the data processing system; (iv) a data processing unit configured to complete the input / output store instruction before execution of the input / output store instruction is completed within the system nesting; (v) system firmware configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during the asynchronous execution of the input / output store instruction; and (vi) a barrier instruction delaying the processing of the store instruction until all previous store instructions have been completed.

[0076] Alternatively or additionally, for the data to be transmitted, the storage instruction according to an embodiment of the present invention may also specify a pointer that should be used to retrieve the data from the main memory, rather than directly containing the data.

[0077] The client instance level can also mean that a single client or host can run on the data processing system.

[0078] The address of the offset of the input / output function itself can be a virtual, physical, or logical address. Virtual and logical addresses are usually translated into physical addresses by the memory management unit (MMU), and then the physical address can be used to identify which function and offset are being referred to.

[0079] In the context of this specification, a physical address refers to "the lowest address in the address translation hierarchy accessible from within the client / operating system".

[0080] Figure 1 A block diagram of a data processing system 210 for processing input / output stored instructions 30 to at least one external device 214 according to an embodiment of the present invention is shown. The data processing system 210 includes a system nest 18 communicatively coupled to an input / output bus 22 via an input / output bus controller 20, and a data processing unit 216 including a kernel 12, system firmware 10, and an asynchronous kernel-nested interface 14. The input / output bus controller 20 may also be coupled to multiple external devices 214 via multiple input / output buses 22.

[0081] Data processing unit 216 is communicatively coupled to system nest 18 via aggregation buffer 16. System nest 18 is configured to asynchronously load data from and / or store data to external device 214, which is communicatively coupled to input / output bus 22, via buffer input / output bus controller interface 28 and input / output bus controller 20, which are part of system nest 18.

[0082] Aggregate buffer 16 is communicatively coupled to asynchronous kernel-nested interface 14. System firmware 10 includes asynchronous input / output driver code 32 for processing input / output store instructions 30. Kernel 12 includes asynchronous setup code 34 for handling memory requests for status information of asynchronous input / output driver code 32. Asynchronous kernel-nested interface 14 includes asynchronous kernel-nested interface forwarding component 36 for forwarding locally completed data. Aggregate buffer 16 includes early completion logic 26 for delivering idle-for-reuse messages after a request is sent. Aggregate buffer 16 is coupled to asynchronous kernel-nested interface 14 via asynchronous bus 38. Asynchronous kernel-nested interface 14 includes input / output status array 44 with multiple input / output status buffers 24, and array management and access logic 46. Input / output status buffers 24 collect return status from system nest 18 and / or from input / output bus controller 20, particularly completion messages from system nest 18. Input / output status buffers 24 are directly integrated into asynchronous kernel-nested interface 14. Message 48 with an array entry identifier (e.g., a completion message sent to one of the input / output status buffers 24) can be received by system nesting 18.

[0083] System firmware 10 includes array management logic 42, which allocates / releases input / output state buffers 24 in input / output state array 44 and / or initiates the start of new storage instructions 30.

[0084] According to an embodiment of the method of the present invention, an operating system running on a data processing system 210 issues an input / output store instruction 30, which specifies at least an input / output function having an offset address, data to be transferred, and / or a pointer to the data to be transferred, and the length of said data. A data processing unit 216 is thus configured to identify the input / output function by the address specified in the input / output store instruction 30. The data processing unit 216 is configured to verify whether access to the input / output function is permitted at the address space and at the client instance level, on which the client runs on the data processing system 210. The data processing unit 216 is configured to complete the input / output store instruction 30 before the completion of its execution within system nesting 18. The system firmware 10 is configured to notify the operating system by interrupting and sending data indicating failed asynchronous execution if an error is detected by the data processing unit 216 during the asynchronous execution of the input / output store instruction 30. A barrier instruction delays the processing of the store instruction until all previous store instructions have been completed.

[0085] Barrier instructions can restrict the serial processing of stored instructions 30 for a single input / output bus controller 20. Barrier instructions can further restrict the serial processing of stored instructions 30 for a single input / output function, particularly a single external input / output device 214. The array management and access logic 46 provides the ability to query a summary of all input / output state buffers 24 of the input / output state array 44, returning aggregated information about the state of the input / output state buffers.

[0086] Array management and access logic 46 collects the completion of storage instruction 30 and updates input / output status buffer 24 based on the received completion message. Data processing unit 216 delays the execution of storage instruction 30 until input / output status buffer 24 is available to store information about the completion of pending storage instruction 30. Specifically, data processing unit 216 delays the execution of asynchronous and / or synchronous storage instructions 30 until input / output status buffer 24 is available to store information about the completion of pending storage instruction 30.

[0087] The input / output status buffer 24 collects message status from system nest 18 and / or from input / output bus controller 20, particularly completion status from system nest 18. Ideally, the message status and / or completion status can be numbered using an input / output status buffer index.

[0088] The input / output storage instruction 30 is located in the data processing system 210 on the side of the user interface 40, which separates the system hardware / firmware 50 from the user side 40 at the architectural boundary.

[0089] Therefore, if the length of the source data exceeds 8 bytes, the data can be transmitted to the aggregation buffer 16 in multiple data packets by the input / output storage instruction 30 through an asynchronous transmission mechanism with an early completion message; otherwise, the data can be transmitted in a single data packet.

[0090] The system messages of an embodiment of the data processing system according to the present invention include one of the following: a hierarchical physical target address; an identifier for an SMT thread or aggregate buffer; the length of the data; an input / output bus address; or an input / output status buffer index.

[0091] The queuing and ordering semantics for processing memory instructions 30 to multiple external devices 214 can advantageously be performed as described below. For individual SMT threads and I / O function relationships, all conventional I / O load / store operations can be ordered relative to a single thread of processor unit 216. New I / O store instructions are completely unordered from each other. New I / O store instructions are ordered relative to conventional I / O instructions. All I / O instructions for different I / O functions are not ordered relative to each other.

[0092] Two additional types of ordering instructions are added to the rule set of system firmware 10. The first is a functional barrier that separates all previous input / output store instructions from all subsequent input / output store instructions from the perspective of a single SMT thread. When the barrier instruction completes, all previous input / output store instructions are sent to the input / output bus 22 where that function resides. The second is an input / output SMT thread barrier instruction, which completes when all previous input / output store instructions are sent to the input / output bus 22 of that SMT thread. For example, lightweight exit / entry of the z Systems Start interpretativeExecution (SIE) instruction has no effect on ordering; full SIE exit / entry with changes to the virtual data processing unit is handled by the input / output SMT thread barrier.

[0093] Figure 2 A message sequence diagram illustrating a method for processing input / output storage instructions 30 for an external device 214 according to an embodiment of the present invention is shown.

[0094] like Figure 2As shown, the method begins with the operating system issuing an input / output store instruction 30. In step S101, system firmware 10 allocates an index for a free input / output status buffer. If no free input / output status buffer index is available, system firmware 10 waits. In step S103, system firmware 10 checks whether the store instruction can be injected into the asynchronous send engine. If this is possible, the process continues. If this is not possible, the store instruction is delayed until the store instruction causing the delay is completed.

[0095] Next, as shown in steps S100 and S104, if the data length exceeds 8 bytes, system firmware 10 repeatedly publishes system messages to send data packets to aggregation buffer 16 until all data in the store block has been forwarded to aggregation buffer 16. Meanwhile, system firmware 10 waits until the data has been sent via system messages. In steps S102 and S106, a local completion message is sent back to system firmware 10.

[0096] Then in step S108, the system firmware 10 sends a system message to the aggregation buffer 16 to asynchronously forward data to the input / output bus controller 20 in the form of a single nested message, while waiting for the aggregation buffer 16 to send a completion message.

[0097] Next, in step S110, the aggregation buffer 16 injects the nested message into the system nest 18, wherein the aggregation buffer 16 immediately becomes idle for reuse after the sending operation and sends a signal back to the system firmware 10. Then, the aggregation buffer 16 sends an idle for reuse message.

[0098] In step S112, system nest 18 forwards the message to the target location. Then, in step S114, input / output bus controller 20 receives the message and forwards the data in the data frame to the input / output bus. Then, in step S116, input / output bus controller 20 sends a completion message to system nest 18.

[0099] Next, in step S118, system nesting 18 forwards the completion message to the originating aggregation buffer 16. Then, in step S120, aggregation buffer 16 forwards the completion message to the asynchronous kernel-nested interface 14. Then, in step S122, asynchronous kernel-nested interface 14 stores the state of the corresponding input / output state buffer index in input / output buffer 24 and sends a signal to system firmware 10 notifying of operation completion. Finally, in step S123, system firmware 10 updates the input / output state buffer 24 tracking using the input / output state buffer index. Input / output state buffer 24 is now idle again.

[0100] In the event of an error during data transmission, system firmware 10 asynchronously sends a signal to the operating system notifying it of the defect.

[0101] If the data to be transmitted is less than 8 bytes, skip the repeated padding of the aggregation buffer 16.

[0102] Figure 3 The first portion of a flowchart illustrating the processing of input / output storage instructions 30 for an external device 214 according to an embodiment of the present invention is shown, while Figure 4 The second part of the flowchart is shown.

[0103] In step S200, the system firmware of the data processing unit begins. In step S202, the system firmware receives legacy input / output block instructions via messages. In step S208, it is checked whether there are any incomplete new memory instructions 30 with or without asynchronous responses. If so, it waits until the kernel-nested interface 14 no longer has any incomplete asynchronous responses. If not, the process immediately continues to step S212, where the kernel-nested interface 14 sends the legacy input / output memory instruction 30 as a message. Then, in step S214, the system waits until it receives a legacy response message in step S216. Then, in step S218, the legacy memory instruction 30 is completed with a message, and then in step S220, the system firmware 10 ends the process.

[0104] In step S204, system firmware 10 receives new input / output storage instructions 30 in parallel via messages. In step S222, it checks whether a free status slot—i.e., the input / output status buffer 24—is available. If so, the slot is marked as used in step S224, and the stored procedure continues. Figure 4 Connection point A is shown in the second part of the flowchart. If this is not the case, then wait in step S226 until the kernel-nested interface 14 has an available free slot.

[0105] In step S206, an asynchronous execution completion message may be received. Subsequently, in step S228, the slot trace is updated with the corresponding input / output status buffer index. Then, in step S230, system firmware 10 terminates the process.

[0106] In step S232, system firmware 10 receives a message with a barrier instruction for each storage function in the parallel path. Next, in step S234, it checks if the kernel-nested interface state buffer 24 is idle. If so, in step S236, the barrier instruction is completed, and then in step S238, system firmware 10 terminates the process. If not, in step S240, system firmware 10 waits for a trace update of the state buffer 24. If any state buffer 24 in step S242 is still not idle for that function, the loop continues by waiting in step S240. If any of the state buffers 24 is idle, the process continues by completing the barrier instruction in step S236.

[0107] In step S244, a barrier instruction is received. Then, in step S246, the digest query capability provided by the array management and access logic 46 in the kernel-nested interface 14 is utilized to wait until there are no more pending asynchronous responses from the kernel-nested interface 14. The barrier instruction is then completed in step S248, and the process is terminated by the system firmware 10 in step S250.

[0108] Figure 4 The second part of the flowchart, starting from connection point A, is shown. First, in step S304, it is checked whether more than 8 bytes need to be transferred. If so, in step S306, the process proceeds. In step S308, the system firmware waits until a local completion message is sent in step S310, returning to step S304. If less than 8 bytes remain in the check in step S304, the process continues in step S312, the kernel-nested interface sends an asynchronous I / O message, and then waits for the buffer response in step S316 in step S314. Then, in step S318, a finish store block instruction is executed, and then in step S320, the process ends with the end of the system firmware.

[0109] In step S328, the asynchronous kernel-nested interface logic starts the outbound processing loop. Subsequently, in step S322, a completion message is received from the aggregation buffer, and in step S324, the data message is forwarded to the aggregation buffer. Then, in step S326, the completion message is sent back to the system firmware. In step S330, an asynchronous input / output send message is received, and then the input / output send message is forwarded to the aggregation buffer.

[0110] In step S338, the aggregation buffer logic begins the outbound processing loop, followed by receiving data in step S334 and aggregating the data in the aggregation buffer in step S336. In step S340, the aggregation buffer also receives input / output send messages, and then forwards the data in the aggregation buffer with input / output send messages in step S242. Next, in step S344, a response message from the aggregation buffer is sent to the system firmware via the kernel-nested interface.

[0111] Now refer to Figure 5 The diagram illustrates an example of a data processing system 210. Data processing system 210 is merely one example of a suitable data processing system and is not intended to impose any limitation on the scope of use or functionality of the embodiments of the invention described herein. In any case, data processing system 210 can be implemented and / or perform any of the functions described above.

[0112] Data processing system 210 includes computer system / server 212, which can operate with many other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations suitable for use with computer system / server 212 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the aforementioned systems or devices, etc.

[0113] Computer system / server 212 can be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer system / server 212 can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules may reside on both local and remote computer system storage media, including memory storage devices.

[0114] like Figure 5 As shown, the computer system / server 212 in the data processing system 210 is illustrated in the form of a general-purpose computing device. The components of the computer system / server 212 may include, but are not limited to, one or more processors or processing units 216, system memory 228, and a bus 218 that couples the various system components, including the system memory 228, to the processor 216.

[0115] Bus 218 represents one or more of several types of bus architectures, including memory buses or memory controllers, peripheral buses, accelerated graphics ports, and processor or local buses using any of the various bus architectures. By way of example and not limitation, such architectures include Industry Standard Architecture (ISA) buses, Micro Channel Architecture (MCA) buses, Enhanced ISA (EISA) buses, Video Electronics Standards Association (VESA) local buses, and Peripheral Component Interconnect (PCI) buses.

[0116] Computer system / server 212 typically includes various computer system readable media. Such media can be any available media that can be accessed by computer system / server 212, and includes volatile and non-volatile media, removable and non-removable media.

[0117] System memory 228 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 230 and / or cache memory 232. Computer system / server 212 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 234 may be provided for reading from and writing to non-removable, non-volatile magnetic media (not shown, commonly referred to as "hard disk drives"). Although not shown, disk drives for reading and writing to removable non-volatile disks (e.g., "floppy disks") and optical disc drives for reading and writing to removable non-volatile optical discs such as CD-ROMs, DVD-ROMs, or other optical media may be provided. In such instances, each may be connected to bus 218 via one or more data media interfaces. As will be further described and illustrated below, memory 228 may include at least one program product having a set (e.g., at least one) of program modules configured to perform embodiments of the invention.

[0118] A program / utility 240 having a set (at least one) of program modules 242, along with an operating system, one or more applications, other program modules, and program data, may be stored in memory 228 in an exemplary, rather than limiting, manner. Each of the operating system, one or more applications, other program modules, and program data, or a combination thereof, may comprise an embodiment of a networked environment. Program modules 242 typically perform the functions and / or methods of embodiments of the invention described herein.

[0119] Computer system / server 212 can also communicate with: one or more external devices 214 such as a keyboard, pointing device, or display 224; one or more devices that enable a user to interact with computer system / server 212; and / or any device that enables computer system / server 212 to communicate with one or more other computing devices (e.g., network interface card, modem, etc.). Such communication can be performed via input / output (I / O) interface 222. Furthermore, computer system / server 212 can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet) via network adapter 220. As shown, network adapter 220 communicates with other components of computer system / server 212 via bus 218. It should be understood that, although not shown, other hardware and / or software components can be used in conjunction with computer system / server 212. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archiving storage systems.

[0120] The present invention can be a system, method, and / or computer program product. The computer program product may comprise a computer-readable storage medium (or medium) having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

[0121] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital universal disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or raised structures in grooves with instructions recorded thereon), and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0122] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0123] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet provided by an Internet service provider). In some embodiments, electronic circuitry (including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs)) may execute the computer-readable program instructions by utilizing state information from the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of the invention.

[0124] This document describes aspects of the invention with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0125] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that, upon execution by the processor of the computer or other programmable data processing apparatus, the instructions create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that instructs a computer, programmable data processing apparatus, and / or other means to function in a particular manner, such that the computer-readable storage medium having the instructions stored therein includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0126] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other apparatus to cause a series of operational steps to be performed on the computer, other programmable apparatus or other apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other apparatus, perform the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0127] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or performs a combination of dedicated hardware and computer instructions.

[0128] Various embodiments of the invention have been described for illustrative purposes, but the above description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to the technology on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0129] Figure Labels

[0130] 10 System FW

[0131] 12 kernels

[0132] 14 Asynchronous Kernel - Nested IF

[0133] 16 Aggregation Buffer

[0134] 18 System Nesting

[0135] 20 I / O bus controller

[0136] 22 I / O bus

[0137] 24 I / O status buffer

[0138] 26. Early Completion Logic

[0139] 28 Buffer-IO Bus Controller IF

[0140] 30 I / O storage instructions

[0141] 32 Asynchronous I / O driver code

[0142] 34 I / O setup codes

[0143] 36 Asynchronous forwarding

[0144] 38 Asynchronous Bus

[0145] 40 User IF

[0146] 42 Array Management Logic

[0147] 44 I / O State Array

[0148] 46 Array Management and Access Logic

[0149] 48 Messages with array item identifiers

[0150] 50 System HW / FW

[0151] 210 Data Processing System

[0152] 212 Computer Systems / Servers

[0153] 214 External Devices

[0154] 216 CPU / Data Processing Unit

[0155] 218 Input / Output Bus

[0156] 220 Network Adapter

[0157] 222 Input / Output Interface

[0158] 224 monitor

[0159] 228 memory

[0160] 230 RAM

[0161] 232 Cache Memory

[0162] 234 Storage System

[0163] 240 Programs / Utilities

[0164] 242 Program Module

Claims

1. A data processing system (210) for processing input / output storage instructions (30), comprising: System nesting (18) is communicatively coupled to at least one input / output bus (22) via an input / output bus controller (20). It also includes at least The data processing unit (216) includes a kernel (12), system firmware (10), and an asynchronous kernel-nested interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The asynchronous kernel-nested interface (14) includes an input / output state array (44) with multiple input / output state buffers (24), array management and access logic (46). And among them (i) The operating system running on the data processing system (210) issues the input / output storage instruction (30), which specifies at least an input / output function having an offset of the address, the data to be transferred and / or a pointer to the data to be transferred and the length of the data; (ii) The data processing unit (216) is configured to identify the input / output function by means of the address specified in the input / output storage instruction (30); (iii) The data processing unit (216) is configured to verify whether access to the input / output function is permitted in the address space and at the client instance level, the client running on the data processing system (210); (iv) The data processing unit (216) is configured to complete the input / output storage instruction (30) before the execution of the input / output storage instruction (30) in the system nest (18) is completed, the system nest (18) being configured to asynchronously load data from and / or store data to at least one external device (214) communicatively coupled to the input / output bus (22), wherein the external device (214) is communicatively coupled to the input / output bus (22) and is located outside the system nest (18), the aggregation buffer (16), and the data processing unit (216); (v) The system firmware (10) is configured to send a system message to the aggregation buffer (16) to asynchronously forward data to the input / output bus controller (20) in the form of a single nested message; (vi) The data processing unit (216) is configured to receive an idle reusable message from the aggregation buffer (16) after sending a request to the system nest (18) so as to continue transmitting data to the system nest (18) and the input / output bus controller (20) through the aggregation buffer (16) as soon as possible; (vii) The system firmware (10) is configured to asynchronously notify the operating system via an interrupt if an error is detected by the data processing unit (216) during the asynchronous execution of the input / output storage instruction (30), including during data transmission; (viii) The barrier instruction delays the processing of the storage instruction (30) until all previous storage instructions (30) have been completed.

2. The data processing system according to claim 1, wherein, The barrier instruction restricts the serial processing of stored instructions (30) for a single input / output bus controller (20).

3. The data processing system according to claim 1, wherein, The barrier instruction restricts the serial processing of input / output storage instructions (30) for a single input / output function, particularly for a single external device (214).

4. The data processing system according to any one of claims 1-3, wherein, The array management and access logic (46) provides the ability to query the summary of all input / output state buffers (24) of the input / output state array (44) and returns aggregated information of the state of the input / output state buffers (24).

5. The data processing system according to claim 1, wherein, The system firmware (10) includes array management logic (42) that allocates / releases input / output state buffers (24) in the input / output state array (44) and / or initiates the start of a new storage instruction (30).

6. The data processing system according to any one of claims 1-3, wherein the aggregation buffer (16) is communicatively coupled to the asynchronous kernel-nested interface (14) via an asynchronous bus (38).

7. The data processing system according to any one of claims 1-3, wherein, If the length of the data exceeds 8 bytes, the data can be transmitted to the aggregation buffer (16) in multiple packets by the input / output storage instruction (30) through an asynchronous transmission mechanism with an early completion message; otherwise, the data is transmitted in one packet.

8. The data processing system according to any one of claims 1-3, wherein the system firmware (10) includes asynchronous input / output driver code (32) for processing the input / output storage instruction (30), and / or the kernel (12) includes asynchronous setup code (34) for processing memory requests for status information of the asynchronous input / output driver code (32).

9. The data processing system according to any one of claims 1-3, wherein the asynchronous kernel-nested interface (14) includes an asynchronous kernel-nested interface forwarding component (36) for forwarding locally completed data.

10. The data processing system according to any one of claims 1-3, wherein the aggregation buffer (16) includes early completion logic (26) for transmitting an idle-for-reuse message after a request is sent.

11. The data processing system according to any one of claims 1-3, wherein the system message includes one of the following: - Hierarchical physical target address, - Provide an SMT thread or aggregate buffer identifier. - Data length, - Input / output bus address, -Index to the input / output status buffer.

12. A method for processing input / output stored instructions (30) for at least one external device (214) of a data processing system (210), the data processing system (210) comprising: The system is nested (18) and communicatively coupled to at least one input / output bus (22) via an input / output bus controller (20). It further includes at least a data processing unit (216), which includes a kernel (12), system firmware (10), and an asynchronous kernel-nested interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The external device (214) is communicatively coupled to the input / output bus (22). The asynchronous kernel-nested interface (14) includes an input / output state array (44) with multiple input / output state buffers (24), array management and access logic (46). The method includes (i) The operating system running on the data processing system (210) issues the input / output storage instruction (30), which specifies at least an input / output function having an offset of the address, the data to be transferred and / or a pointer to the data to be transferred and the length of the data; (ii) The data processing unit (216) identifies the input / output function by the address specified in the input / output storage instruction (30); (iii) The data processing unit (216) verifies whether access to the input / output function is permitted at the address space and at the client instance level, the client running on the data processing system (210); (iv) The data processing unit (216) completes the input / output storage instruction (30) in the system nest (18) before the execution of the input / output storage instruction (30) is completed, the system nest (18) asynchronously loading data from at least one external device (214) communicatively coupled to the input / output bus (22) and / or storing data to the at least one external device (214), wherein the external device (214) is communicatively coupled to the input / output bus (22) and is located outside the system nest (18), the aggregation buffer (16) and the data processing unit (216); (v) The system firmware (10) sends a system message to the aggregation buffer (16) to asynchronously forward data to the input / output bus controller (20) in the form of a single nested message; (vi) After sending a request to the system nest (18), the data processing unit (216) receives an idle for reuse message from the aggregation buffer (16) so that it can continue to transmit data to the system nest (18) and the input / output bus controller (20) through the aggregation buffer (16) as soon as possible; (vii) If an error is detected by the data processing unit (216) during the asynchronous execution of the input / output storage instruction (30), including during data transmission, the system firmware (10) asynchronously notifies the operating system via an interrupt; (viii) The barrier instruction delays the processing of the storage instruction (30) until all previous storage instructions (30) have been completed.

13. The method of claim 12, wherein the barrier instruction restricts the serial processing of stored instructions (30) for a single input / output bus controller (20).

14. The method of claim 12, wherein the barrier instruction restricts serial processing of input / output storage instructions (30) for a single input / output function, particularly for a single external device (214).

15. The method according to any one of claims 12 to 14, wherein the array management and access logic (46) provides the ability to query the summary of all input / output state buffers (24) of the input / output state array (44) and returns aggregate information of the state of the input / output state buffers (24).

16. The method according to any one of claims 12 to 14, wherein the system firmware (10) includes array management logic (42) that allocates / releases input / output state buffers (24) in the input / output state array (44) and / or initiates the start of a new storage instruction (30).

17. The method according to any one of claims 13 to 14, further comprising: (i) The operating system issues the input / output storage instruction (30); (ii) The system firmware (10) allocates an index for an idle input / output status buffer. If no index for an idle input / output status buffer is available, it waits for an index for an idle input / output status buffer. (iii) The system firmware (10) injects the storage instruction (30) into the asynchronous transmission engine; If blocked by another store instruction, wait until that store instruction completes; (iv) Depending on the data length: if the data length exceeds eight bytes, the system firmware (10) repeatedly publishes system messages to send data packets to the aggregation buffer (16) until all data in the storage block has been forwarded to the aggregation buffer (16), while the system firmware (10) waits until the data has been sent by system messages; otherwise The system firmware (10) publishes a system message to send the data to the aggregation buffer (16). (v) The system firmware (10) publishes a system message to the aggregation buffer (16) to asynchronously forward the data as a single nested message to the input / output bus controller (20), while waiting for the aggregation buffer (16) to send a completion message; (vi) The aggregation buffer (16) injects the nested message into the system nest (18), wherein the aggregation buffer (16) is idle for reuse just after sending the completion message, and signals back to the system firmware (10); then the aggregation buffer (16) sends an idle for reuse message; (vii) The system nesting (18) forwards the message to the target location; (viii) The input / output bus controller (20) receives the message and forwards the data in the data frame to the input / output bus; (ix) The input / output bus controller (20) sends a completion message to the system nest (18); (x) The system nest (18) forwards the completion message to the aggregation buffer (16); (xi) The aggregate buffer (16) will complete the forwarding to the asynchronous kernel-nested interface (14). (xii) The asynchronous kernel-nested interface (14) stores the completion status in the input / output status buffer (24) for the input / output status buffer index, and signals the completion of the operation to the system firmware (10). (xiii) The system firmware (10) updates the input / output state buffer tracking through the input / output state buffer index; (xiv) In case of an error, the system firmware (10) asynchronously notifies the operating system of the defect signal.

18. The method according to any one of claims 12 to 14, further, if the length of the data exceeds 8 bytes, the data is transmitted to the aggregation buffer (16) in multiple data packets by an input / output storage instruction (30) through an asynchronous transmission mechanism with an early completion message.

19. The method according to any one of claims 12 to 14, further wherein the system firmware (10) uses asynchronous input / output driver code (32) for processing the input / output storage instructions (30).

20. The method according to claim 19, further wherein the kernel (12) uses asynchronous setup code (34) for processing memory requests for state information of the asynchronous input / output driver code (32).

21. The method according to any one of claims 12 to 14, further wherein the asynchronous kernel-nested interface (14) uses the asynchronous kernel-nested interface forwarding component (36) to forward locally completed data.

22. The method according to any one of claims 12 to 14, further wherein the aggregation buffer (16) uses early completion logic (26) to transmit an idle-for-reuse message after the sending request.

23. The method according to any one of claims 12 to 14, wherein, System messages include one of the following: - Hierarchical physical target address, - Provide an SMT thread or aggregate buffer identifier. - Data length, - Input / output bus address, -Index to the input / output status buffer.

24. A computer program product for processing input / output stored instructions (30) for at least one external device (214) of a data processing system (210), said data processing system (210) comprising: The system is nested (18) and communicatively coupled to at least one input / output bus (22) via an input / output bus controller (20). Furthermore, it also includes at least a data processing unit (216), which includes a kernel (12), system firmware (10), and an asynchronous kernel-nested interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The external device (214) is communicatively coupled to the input / output bus (22). The asynchronous kernel-nested interface (14) includes an input / output state array (44) with multiple input / output state buffers (24), array management and access logic (46). The computer program product includes program instructions that can be executed by a computer system to cause the computer system to perform the method as described in any one of claims 12-23.

25. A computer-readable storage medium storing program instructions that can be executed by a computer system to cause the computer system to perform the method according to any one of claims 12 to 23.

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