Semiconductor devices and methods

Abstract

The present disclosure relates to semiconductor devices and methods. Methods for adjusting an effective work function of a gate electrode in a semiconductor device and semiconductor devices formed by the methods are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate, a gate dielectric layer over the channel region, and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al), a first work function adjustment layer over the first work function metal layer, the first work function adjustment layer including aluminum tungsten (AlW), and a fill material over the first work function adjustment layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor layers of material over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, allowing more components to be integrated into a given area. SUMMARY

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode comprising: a first work function metal layer over the gate dielectric layer, the first work function metal layer comprising aluminum (Al); a first work function adjustment layer over the first work function metal layer, the first work function adjustment layer comprising aluminum tungsten (AlW); and a fill material over the first work function adjustment layer.

[0005] According to another embodiment of the present disclosure, a method of fabricating a semiconductor device is provided, comprising: forming a channel region over a semiconductor substrate; depositing a gate dielectric layer over the channel region; depositing an n-type work function metal layer over the gate dielectric layer; and exposing the n-type work function metal layer to a work function adjustment gas, the work function adjustment gas comprising a transition metal chloride, wherein a first work function adjustment layer is deposited over the n-type work function metal layer.

[0006] According to yet another embodiment of the present disclosure, a semiconductor device is provided, comprising: a fin extending from a semiconductor substrate; an interface layer over the fin; a first dielectric layer over the interface layer; a p-type work function metal layer over the first dielectric layer, the p-type work function metal layer comprising a doped transition metal nitride material; and a fill material over the p-type work function metal layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] FIG. 1 Examples of semiconductor devices including FinFETs are shown in a three-dimensional view according to some embodiments.

[0009] FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A , FIG. 10B , FIG. 10C , FIG. 11A , FIG. 11B , FIG. 12A , FIG. 12B , FIG. 13A , FIG. 13B , FIG. 14A , FIG. 14B , FIG. 15A , FIG. 15B , FIG. 16A , FIG. 16B , FIG. 17A , FIG. 17B , FIG. 18A , FIG. 18B , FIG. 19A , FIG. 19B , FIG. 20A , FIG. 20B , FIG. 21A and FIG. 21B This is a cross-sectional view of an intermediate stage in the manufacture of a semiconductor device according to some embodiments.

[0010] FIG. 15C and FIG. 17C Energy dispersive spectroscopy (EDS) plots of the dielectric layer and work function layer in an example gate stack according to some embodiments are shown.

[0011] FIG. 17D An X-ray photoelectron spectroscopy (XPS) pattern of an n-type work function metal layer according to some embodiments is shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature is formed directly in contact with the second feature, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not be directly in contact. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0013] Also, spatially relative terms (e.g., "beneath," "below," "lower," "above," "upper," and the like) can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Such spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] Various embodiments provide methods of adjusting a work function value of a gate electrode in a semiconductor device and semiconductor devices formed by the methods. The work function value can be adjusted by performing various processes on a work function metal layer included in the gate electrode of the semiconductor device. For example, in some embodiments, the work function value can be adjusted by implanting dopants in a p-type work function metal layer. The dopants can include lanthanum, aluminum, magnesium, and the like. In some embodiments, the work function value can be adjusted by exposing an n-type work function metal layer to an adjustment gas. The adjustment gas can be a transition metal chloride, such as tungsten chloride, tantalum chloride, hafnium chloride, titanium chloride, and the like. Exposing the n-type work function metal layer to the adjustment gas can deposit an adjustment layer on the n-type work function metal layer, can change the composition of the n-type work function metal layer, and can deposit a thin layer on the n-type work function metal layer, thereby forming a work function layer that can be more suitable for a p-type transistor. Thinning the n-type work function metal layer can increase the process window for filling the gate electrode, which provides greater flexibility for subsequently deposited layers. By adjusting the work function value of the semiconductor device, semiconductor devices with lower threshold voltage (V t ), higher speed, and better performance can be manufactured.

[0015] FIG. 1An example of a FinFET is shown in accordance with some embodiments. The FinFET includes a fin 55 on a substrate 50 (e.g., a semiconductor substrate). Shallow trench isolation (STI) regions 58 are disposed in the substrate 50, and the fin 55 protrudes above and between adjacent STI regions 58. Although the STI regions 58 are depicted / illustrated as being separate from the substrate 50, as used herein, the term "substrate" can be used to refer to either a semiconductor substrate alone or a semiconductor substrate that includes STI regions. Additionally, although the fin 55 is shown as a single continuous material with the substrate 50, the fin 55 and / or the substrate 50 can include a single material or multiple materials. In this context, the fin 55 refers to the portion that extends between adjacent STI regions 58.

[0016] A gate dielectric layer 100 is along sidewalls of the fin 55 and over a top surface of the fin 55, and a gate electrode 102 is over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed opposite sides of the fin 55, gate dielectric layer 100, and gate electrode 102. FIG. 1 Further shown are reference cross-sections used in later figures. Cross-section A-A' is along a longitudinal axis of the gate electrode 102, and in a direction perpendicular to, for example, a direction of current flow between epitaxial source / drain regions 92 of the FinFET. Cross-section B-B' is perpendicular to cross-section A-A', and along a longitudinal axis of the fin 55 and in a direction of current flow between, for example, epitaxial source / drain regions 92 of the FinFET. Cross-section C-C' is parallel to cross-section A-A', and extends through epitaxial source / drain regions 92 of the FinFET. For clarity, subsequent figures refer to these reference cross-sections.

[0017] Some embodiments discussed herein are discussed in the context of a fin field effect transistor (FinFET) formed using a gate-last process. In some embodiments, a gate-first process can be used. Further, some embodiments contemplate aspects used in planar devices (e.g., planar field effect transistors), nanostructure (e.g., nanosheet, nanowire, wrap-around gate, etc.) field effect transistors (NSFETs), and the like.

[0018] FIG. 2 to FIG. 21B is a cross-sectional view of an intermediate stage of manufacturing a FinFET in accordance with some embodiments. FIG. 2 to FIG. 5 is shown FIG. 1 The reference cross-section A-A' is shown. FIG. 6A , FIG. 11A , FIG. 12A , FIG. 13A , FIG. 14A , FIG. 14B , FIG. 15A ,FIG. 15B , FIG. 16A , FIG. 16B , FIG. 17A , FIG. 17B , FIG. 18A , FIG. 18B , FIG. 19A , FIG. 20A and FIG. 21A Along FIG. 1 The reference cross section A-A' is shown. FIG. 6B , FIG. 7B , FIG. 8B , FIG. 9B , FIG. 10B , FIG. 11B , FIG. 12B , FIG. 13B , FIG. 19B , FIG. 20B and FIG. 21B Along FIG. 1 A similar cross-section B-B' is shown. FIG. 7A , FIG. 8A , FIG. 9A , FIG. 10A and FIG. 10C Along FIG. 1 The reference cross section C-C' is shown.

[0019] exist FIG. 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0020] Substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type FinFET. Region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type FinFET. Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between region 50N and region 50P.

[0021] In FIG. 3 In

[0022] The fins 55 can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fins 55, including a double patterning process or a multiple patterning process. Generally, a double patterning process or a multiple patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns having smaller pitch, for example, than is obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 55. In some embodiments, a mask (or other layer) can remain on the fins 55.

[0023] In FIG. 4 In

[0024] A removal process is then applied to the insulating material to remove excess insulating material over the fins 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like, can be employed. The planarization process can planarize the insulating material and the fins 55. The planarization process exposes the fins 55 such that the top surfaces of the fins 55 and the insulating material are flush after the planarization process is completed.

[0025] The insulating material is then recessed to form STI regions 58 as shown. FIG. 4 The insulating material is recessed such that the fins 55 and upper portions of the substrate 50 protrude from between adjacent STI regions 58. In addition, the top surfaces of the STI regions 58 can have planar surfaces (as shown), convex surfaces, concave surfaces (e.g., dished), or combinations thereof. The top surfaces of the STI regions 58 can be made planar, convex, and / or concave by appropriate etching. The STI regions 58 can be recessed using an acceptable etching process, e.g., an etching process that is selective to the material of the insulating material (e.g., etches the material of the insulating material at a faster rate than the material of the fins 55 and substrate 50). For example, oxide removal using, e.g., diluted hydrofluoric acid (dHF) acid can be employed.

[0026] Referring to FIG. 2 to FIG. 4 The process described is merely one example of how the fins 55 can be formed. In some embodiments, the fins 55 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and a trench can be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form the fins. Additionally, in some embodiments, a heteroepitaxial structure can be used for the fins 55. For example, FIG. 4 The fins 55 in FIG. 1 can be recessed, and a material different from the fins 55 can be epitaxially grown over the recessed fins 55. In such embodiments, the fins 55 include the recessed material and the epitaxially grown material disposed over the recessed material. In some embodiments, a dielectric layer can be formed over the top surface of the substrate 50, and a trench can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 55. In some embodiments in which a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material can be doped in situ during growth, which can eliminate pre- and post-implants, but in situ doping and implant doping can be used together.

[0027] In addition, it can be advantageous to epitaxially grow a material in the regions 50N (e.g., NMOS regions) that is different from the material in the regions 50P (e.g., PMOS regions). In some embodiments, the upper portions of the fins 55 can be formed of silicon germanium (SiGe) in the regions 50N and of silicon (Si) in the regions 50P. In some embodiments, the upper portions of the fins 55 can be formed of silicon carbon (SiC) in the regions 50N and of silicon (Si) in the regions 50P. In some embodiments, the upper portions of the fins 55 can be formed of silicon germanium carbon (SiGeC) in the regions 50N and of silicon (Si) in the regions 50P. x Ge 1-xformed of silicon, silicon-germanium, silicon-carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0028] Further in FIG. 4 , appropriate wells (not shown separately) can be formed in the fins 55 and / or the substrate 50. In some embodiments, a P-well can be formed in the region 50N, and an N-well can be formed in the region 50P. In some embodiments, a P-well or an N-well is formed in both the region 50N and the region 50P.

[0029] In embodiments having different well types, a photoresist or other mask (not shown separately) can be used to implement different implant steps for the region 50N and the region 50P. For example, a photoresist can be formed over the fins 55 and the STI region 58 in the region 50N. The photoresist is patterned to expose the region 50P of the substrate 50, e.g., the PMOS region. The photoresist can be formed by using a spin-on technique, and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implant is performed in the region 50P, and the photoresist can be used as a mask to substantially prevent the n-type impurity from being implanted into the region 50N, e.g., the NMOS region. The n-type impurity can be phosphorous, arsenic, antimony, etc. implanted into the region at a concentration equal to or less than 1 x 1012atoms / cm2, e.g., between about 1 x 1011atoms / cm2and about 1 x 1012atoms / cm2. After implantation, the photoresist is removed, e.g., by an acceptable ashing process. 18 atoms / cm2 3 , e.g., between about 1 x 1011atoms / cm2and about 1 x 1012atoms / cm2. After implantation, the photoresist is removed, e.g., by an acceptable ashing process. 16 atoms / cm2 3 and about 1 x 1012atoms / cm2. After implantation, the photoresist is removed, e.g., by an acceptable ashing process. 18 atoms / cm2 3 . After implantation, the photoresist is removed, e.g., by an acceptable ashing process.

[0030] After implantation of the region 50P, a photoresist is formed over the fins 55 and the STI region 58 in the region 50P. The photoresist is patterned to expose the region 50N of the substrate 50, e.g., the NMOS region. The photoresist can be formed by using a spin-on technique, and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implant can be performed in the region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the region 50P, e.g., the PMOS region. The p-type impurity can be boron, boron fluoride, indium, etc. implanted into the region at a concentration equal to or less than 1 x 1012atoms / cm2, e.g., between about 1 x 1011atoms / cm2and about 1 x 1012atoms / cm2. After implantation, the photoresist is removed, e.g., by an acceptable ashing process. 18 atoms / cm2 3for example, about 1 x 1011 16 atoms / cm 3 and about 1 x 1011 18 atoms / cm 3 Between implantation and annealing, the photoresist can be removed, for example, by an acceptable ashing process.

[0031] After implantation of regions 50N and 50P, annealing can be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the epitaxial fin growth material can be doped in-situ during growth, which can eliminate implantation, but in-situ doping and implantation doping can be used together.

[0032] In FIG. 5 , a dummy dielectric layer 60 is formed over the fins 55 and the substrate 50. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 can be deposited over the dummy dielectric layer 60 and then planarized by a process such as CMP. The mask layer 64 can be deposited over the dummy gate layer 62. The dummy gate layer 62 can be a conductive material or a non-conductive material, and can be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 62 can be made of other materials that have a high etch selectivity with respect to the material of the STI region 58. The mask layer 64 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the regions 50N and 50P. It is noted that the dummy dielectric layer 60 is shown as covering only the fins 55 and the substrate 50 for illustration purposes only. In some embodiments, the dummy dielectric layer 60 can be deposited such that the dummy dielectric layer 60 covers the STI region 58, extending between the dummy gate layer 62 and the STI region 58.

[0033] FIG. 6A to FIG. 21B Various additional steps in the manufacture of an embodiment device are shown. FIG. 6B to FIG. 13B and FIG. 19A to FIG. 21B Features in either of the regions 50N or 50P are shown. For example, FIG. 6B to FIG. 13B and FIG. 19A to FIG. 21B The structures shown can be applicable to both of the regions 50N and 50P. Differences, if any, in the structures of the regions 50N and 50P are described in the text accompanying each figure.

[0034] In FIG. 6A and FIG. 6B , the mask layer 64 (see FIG. 5 ) can be patterned using acceptable photolithography and etching techniques to form a mask 74. The pattern of the mask 74 can be transferred to the dummy gate layer 62 using acceptable etching techniques to form the dummy gates 72. In some embodiments, the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60. The dummy gates 72 cover the respective channel regions 68 of the fins 55. The pattern of the mask 74 can be used to separate each dummy gate 72 from an adjacent dummy gate physically. The dummy gates 72 can also have a length direction substantially perpendicular to the length direction of the respective fins 55. The dummy dielectric layer 60, the dummy gates 72, and the mask 74 can be collectively referred to as a “dummy gate stack”.

[0035] In FIG. 7A and FIG. 7B , a first spacer layer 80 and a second spacer layer 82 are formed on top of the structures shown in FIG. 6A and FIG. 6B . In FIG. 7A and FIG. 7B , the first spacer layer 80 is formed on the top surface of the STI regions 58, the top surface and sidewalls of the fins 55 and the mask 74, and the sidewalls of the dummy gates 72 and the dummy dielectric layer 60. The second spacer layer 82 is deposited on top of the first spacer layer 80. The first spacer layer 80 can be formed by thermal oxidation, or deposited by CVD, ALD, etc. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The second spacer layer 82 can be deposited by CVD, ALD, etc. The second spacer layer 82 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0036] In FIG. 8A and FIG. 8B , the first spacer layer 80 and the second spacer layer 82 are etched to form first spacers 81 and second spacers 83. The first spacer layer 80 and the second spacer layer 82 can be etched using appropriate etching processes, such as anisotropic etching processes (e.g., dry etching processes), etc. The first spacers 81 and the second spacers 83 can be disposed on the sidewalls of the fins 55, the dummy dielectric layer 60, the dummy gates 72, and the mask 74. Due to the etching processes used to etch the first spacer layer 80 and the second spacer layer 82, and the different heights between the fins 55 and the dummy gate stack, the first spacers 81 and the second spacers 83 can have different heights adjacent to the fins 55 and the dummy gate stack. Specifically, as shown in FIG. 8A and FIG. 8BAs shown, in some embodiments, the first spacer 81 and the second spacer 83 can partially extend upward to sidewalls of the fin 55 and the dummy gate stack. In some embodiments, the first spacer 81 and the second spacer 83 can extend to a top surface of the dummy gate stack.

[0037] After the first spacer 81 and the second spacer 83 are formed, an implantation for lightly doped source / drain (LDD) regions (not shown separately) can be performed. In embodiments with different device types, similar to the implantation discussed above in FIG. 4 , a mask (e.g., photoresist) can be formed over the regions 50N, while exposing the regions 50P, and impurities of an appropriate type (e.g., p-type) can be implanted into the exposed fin 55 and substrate 50 in the regions 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the regions 50P, while exposing the regions 50N, and impurities of an appropriate type (e.g., n-type) can be implanted into the exposed fin 55 and substrate 50 in the regions 50N. The mask can then be removed. The n-type impurities can be any of the n-type impurities discussed previously, and the p-type impurities can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have an impurity concentration of about 1 x 1010atoms / cm3to about 1 x 1011atoms / cm3. Annealing can be used to repair implant damage and activate the implanted impurities. 15 3 19 3 atoms / cm3. Annealing can be used to repair implant damage and activate the implanted impurities.

[0038] Note that the above disclosure generally describes processes of forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be employed, different step sequences can be employed (e.g., the first spacer 81 can be formed before the second spacer 83, additional spacers can be formed and removed, etc.). Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0039] In FIG. 9A and FIG. 9B , a first recess 86 is formed in the fin 55 and the substrate 50. As FIG. 9A ​​​As shown, the top surface of the STI region 58 can be flush with the top surface of the substrate 50. The substrate 50 can be etched such that the bottom surface of the first groove 86 is positioned above or below the top surface of the STI region 58. The first groove 86 can be formed by etching the fin 55 and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first groove 86, the first spacer 81, the second spacer 83, and the mask 74 mask portions of the fin 55 and the substrate 50. The first groove 86 can be formed using a single etching process or multiple etching processes. A timed etching process can be used to stop etching the first groove 86 after it reaches a desired depth.

[0040] exist FIG. 10A to FIG. 10C In the first groove 86, an epitaxial source / drain region 92 is formed to apply stress to the channel region 68 of the fin 55, thereby improving performance. FIG. 10B As shown, an epitaxial source / drain region 92 is formed in the first recess 86 such that each dummy gate 72 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 92 do not short-circuit the gate of the subsequently formed FinFET.

[0041] The epitaxial source / drain region 92 in region 50N (e.g., an NMOS region) can be formed by masking region 50P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 86. The epitaxial source / drain region 92 can include any acceptable material, such as materials suitable for n-type FinFETs. For example, if fin 55 is silicon, the epitaxial source / drain region 92 can include a material on which tensile strain is applied, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon-phosphorus, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding surface of fin 55 and can have facets.

[0042] The epitaxial source / drain region 92 in region 50P (e.g., a PMOS region) can be formed by masking region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 86. The epitaxial source / drain region 92 can include any acceptable material, such as materials suitable for p-type NSFETs. For example, if fin 55 is silicon, the epitaxial source / drain region 92 can include a material on which compressive strain is applied, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can also have a surface protruding from the corresponding surface of fin 55 and can have a facet.

[0043] The epitaxial source / drain regions 92, the fins 55, and / or the substrate 50 can be implanted with dopants to form source / drain regions, similar to the processes discussed previously for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions can be between about 1 x 1018atoms / cm3 19 and about 1 x 1019atoms / cm3 3 and about 1 x 1019atoms / cm3 21 and about 1 x 1019atoms / cm3 3 The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0044] As a result of the epitaxial process used to form the epitaxial source / drain regions 92 in the regions 50N and the regions 50P, the upper surface of the epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of the fins 55. In some embodiments, the facets cause adjacent epitaxial source / drain regions 92 of the same FinFET to merge, as shown in FIG. 10A In some embodiments, adjacent epitaxial source / drain regions 92 remain separate after the epitaxial process is complete, as shown in FIG. 10C In embodiments shown in FIG. 10A and FIG. 10C The first spacers 81 can be formed to cover the portions of the sidewalls of the fins 55 that extend above the STI regions 58, thereby preventing epitaxial growth. In some embodiments, the spacer etch used to form the first spacers 81 can be adjusted to remove spacer material to allow the region of epitaxial growth to extend to the surface of the STI regions 58.

[0045] The epitaxial source / drain regions 92 can include one or more layers of semiconductor material. For example, the epitaxial source / drain regions 92 can include a first layer of semiconductor material 92A, a second layer of semiconductor material 92B, and a third layer of semiconductor material 92C. Any number of layers of semiconductor material can be used for the epitaxial source / drain regions 92. Each of the first layer of semiconductor material 92A, the second layer of semiconductor material 92B, and the third layer of semiconductor material 92C can be formed of a different semiconductor material and / or can be doped to a different dopant concentration. In some embodiments, the dopant concentration of the first layer of semiconductor material 92A can be less than the second layer of semiconductor material 92B but greater than the third layer of semiconductor material 92C. In embodiments in which the epitaxial source / drain regions 92 include three layers of semiconductor material, the first layer of semiconductor material 92A can be deposited, the second layer of semiconductor material 92B can be deposited over the first layer of semiconductor material 92A, and the third layer of semiconductor material 92C can be deposited over the second layer of semiconductor material 92B.

[0046] In FIG. 11A and FIG. 11B , a first interlayer dielectric (ILD) 96 is deposited over the structures shown in FIG. 6A and FIG. 10B , respectively FIG. 7A-FIG. 10C The process of depositing the first ILD 96 does not change the cross-section shown in FIG. 6A , which shows dummy gate 72 and the multi-layer stack protected by dummy gate 72. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 74, and the first spacers 81. The CESL 94 can include a dielectric material having a different etch rate than the material of the overlying first ILD 96, e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.

[0047] In FIG. 12A and FIG. 12B , a planarization process such as CMP can be performed to level the top surface of the first ILD 96 with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 over the dummy gate 72, and the portions of the first spacers 81 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the first spacers 81, and the first ILD 96 are level. Thus, the top surface of the dummy gate 72 is exposed through the first ILD 96. In some embodiments, the mask 74 can remain, in which case the planarization process levels the top surface of the first ILD 96 with the top surfaces of the mask 74 and the first spacers 81.

[0048] In FIG. 13A and FIG. 13BIn one or more etching steps, the dummy gate 72 and mask 74 (if present) are removed to form a second recess 98. A portion of the dummy dielectric layer 60 in the second recess 98 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed by the second recess 98. In some embodiments, the dummy dielectric layer 60 is removed from the second recess 98 in a first region of the die (e.g., a core logic region) and remains in the second recess 98 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 72 at a rate faster than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or covers the channel region 68 of the corresponding fin 55. Each channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 can be used as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 can then be optionally removed after the dummy gate 72 is removed.

[0049] FIG. 14A to FIG. 18B Various steps are shown for forming the gate dielectric layer 100 and gate electrode 102 for replacing the gate. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as the "gate stack". FIG. 14A to FIG. 18B It shows FIG. 13A Detailed view of area 101. FIG. 14A , FIG. 15A , FIG. 16A , FIG. 17A and FIG. 18A Features in region 50N are shown, while FIG. 14B , FIG. 15B , FIG. 16B , FIG. 17B and FIG. 18B Features in region 50P are shown. The gate dielectric layer 100 may include one or more sublayers, such as interface layer 100A and first dielectric layer 100B. The gate electrode 102 may also include one or more sublayers, such as cap layer 102A, p-type work function metal layer 102B, first adjustment layer 102C, n-type work function metal layer 102D, second adjustment layer 102E, barrier layer 102F, and filler material 102G.

[0050] exist FIG. 14A and FIG. 14BIn some embodiments, an interface layer 100A, a first dielectric layer 100B, a cap layer 102A, and a p-type work function metal layer 102B are formed. The interface layer 100A can be formed or deposited conformally in the second recess 98, for example, on the top surface of the STI region 58 and on the top surface and sidewalls of the fin 55. The interface layer 100A can include a dielectric material, for example, silicon oxide (SiO2), silicon oxynitride (SiON), etc. The interface layer 100A can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, etc. The thickness of the interface layer 100A can be about 1 A to about 10 A, for example, about 2 A to about 5 A. to about 10 A, for example, about 2 A to about 5 A.

[0051] The first dielectric layer 100B can be deposited over the interface layer 100A using a conformal process. The first dielectric layer 100B can be a high dielectric constant (high-k) material, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (LaO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO2), tantalum oxide (Ta2O3), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), combinations thereof, or multilayers thereof, etc. The first dielectric layer 100B can be formed by ALD, CVD, etc. In some embodiments, the interface layer 100A can be omitted, and the first dielectric layer 100B can be deposited directly on the fin 55. The thickness of the first dielectric layer 100B can be about 5 A to about 50 A, for example, about 10 A to about 30 A. to about 10 A, for example, about 2 A to about 5 A. or about 10 A, for example, about 2 A to about 5 A. to about 10 A, for example, about 2 A to about 5 A.

[0052] The formation of the interface layer 100A and the first dielectric layer 100B in the region 50N and the region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be different materials. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0053] After the first dielectric layer 100B is formed, a cap layer 102A is formed on the first dielectric layer 100B. The cap layer 102A can be used as a barrier layer to prevent the diffusion of subsequently deposited metal-containing materials into the gate dielectric layer 100. Suitable examples of materials that can be used for the cap layer 102A include TiN, TiSiN, combinations thereof, or multilayers thereof, etc. The cap layer 102A can be formed by ALD, CVD, etc. The thickness of the cap layer 102A can be about 5 A to about 50 A, for example, about 10 A to about 30 A. to about 10 A, for example, about 2 A to about 5 A. or about 10 A, for example, about 2 A to about 5 A. to about 10 A, for example, about 2 A to about 5 A. The cap layer 102A can be optional and can be omitted in some embodiments.

[0054] A p-type work function metal layer 102B is then formed on the cap layer 102A. The p-type work function metal layer 102B is formed to adjust the work function of the device. The p-type work function metal layer 102B can be a p-type work function material for a p-type NSFET device. Suitable examples of p-type work function materials include transition metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN), other suitable p-type work function metal materials, multilayers thereof, or combinations thereof, etc. The p-type work function metal layer 102B can be formed by ALD, CVD, etc. The thickness of the p-type work function metal layer 102B can be about 1 nm to about 10 nm, or about 2 nm to about 5 nm. to about 1 x 1012atoms / cm2, or about 1 x 1011atoms / cm2. or about 1 x 1012atoms / cm2, or about 1 x 1011atoms / cm2. to about 1 x 1012atoms / cm2, or about 1 x 1011atoms / cm2.

[0055] In FIG. 15A and FIG. 15B , the p-type work function metal layer 102B in the region 50P is doped to form a first adjustment layer 102C, and the p-type work function metal layer 102B is etched from the region 50N. In some embodiments, the p-type work function metal layer 102B in both the region 50N and the region 50P can be doped prior to etching the p-type work function metal layer 102B from the region 50N. In some embodiments, the p-type work function metal layer 102B in the region 50P can be doped after the p-type work function metal layer 102B is removed from the region 50N. In embodiments where the p-type work function metal layer 102B in the region 50P is doped after the p-type work function metal layer 102B is removed from the region 50N, the cap layer 102A and / or the first dielectric layer 100B in the region 50N can be doped by the process used to dope the p-type work function metal layer 102B in the region 50P. The dopant can be doped throughout the entire thickness of the first adjustment layer 102C. The atomic percentage of the dopant in the first adjustment layer 102C can be in the range of about 0.5% to about 30%, or about 10% to about 20%. In some embodiments, the first adjustment layer 102C in the region 50P can be doped to a dopant concentration of about 1 x 1012atoms / cm2, or about 1 x 1011atoms / cm2. 17 atoms / cm2, or about 1 x 1011atoms / cm2. 3 atoms / cm2, or about 1 x 1011atoms / cm2. 19 atoms / cm2, or about 1 x 1011atoms / cm2. 3 atoms / cm2, or about 1 x 1011atoms / cm2. 18 atoms / cm2, or about 1 x 1011atoms / cm2. 3 atoms / cm2, or about 1 x 1011atoms / cm2. 19 atoms / cm2, or about 1 x 1011atoms / cm2. 3

[0056] ​Dopants for the p-type work function metal layer 102B can include lanthanum (La), aluminum (Al), magnesium (Mg), combinations thereof, or the like. Implanting any of lanthanum, aluminum, and magnesium into the p-type work function metal layer 102B increases the effective work function in the region 50P, shifts the flatband voltage (V FB ) to the p-side, and decreases the threshold voltage (V t ) in the completed device. The p-type work function metal layer 102B can be doped by forming a dopant-containing layer (not shown separately) over the p-type work function metal layer 102B, and then performing a drive-in anneal process to drive the dopants from the dopant-containing layer into the p-type work function metal layer 102B. The dopant-containing layer can be formed by ALD, CVD, or the like. The thickness of the dopant-containing layer can be formed to be about to about or about to about The dopant-containing layer can be formed of lanthanum oxide (La2O3), aluminum oxide (Al2O3), magnesium oxide (MgO), or the like. The dopant-containing layer can be deposited over the p-type work function metal layer 102B in a deposition chamber maintained at a pressure of about 1 Torr to about 40 Torr, or about 15 Torr to about 25 Torr, and a temperature of about 200 °C to about 400 °C, or about 275 °C to 325 °C.

[0057] One or more precursor gases can be flowed over the p-type work function metal layer 102B to form a dopant-containing layer. The precursor gases can include a carrier gas, such as argon (Ar), and the like, and a process gas, such as a lanthanum-containing gas (e.g., lanthanum bis(trimethylsilyl)amide (La(N(Si(CH3)3)2)3), tris(cyclopentadienyl)lanthanum(III) (La(C5H5)3), and the like), an aluminum-containing gas (e.g., triethylaluminum ((Al2(C2H5)3), and the like), a magnesium-containing gas (e.g., bis(ethylcyclopentadienyl)magnesium (Mg(C5H4C2H5)2), and the like), an oxygen-containing gas (e.g., water (H2O), oxygen (O2), ozone (O3), and the like), combinations thereof, and the like. For example, in embodiments where the dopant-containing layer includes La2O3, the precursor gases can include lanthanum bis(trimethylsilyl)amide and ozone, which react to form the dopant-containing layer over the p-type work function metal layer 102B. The precursor gases can be flowed at a flow rate of about 500 seem to about 4000 seem, or about 2000 seem to about 2500 seem. The dopant-containing layer can be deposited by one or more pulses, each of which can be followed by a purge. The deposition time for one pulse can be about 1 millisecond to about 10 seconds, or about 3 seconds to about 7 seconds. The thickness of the dopant-containing layer can be about 1.5 nm to about 4 nm, or about 1.5 nm to about 2.5 nm. The ratio of the thickness of the dopant-containing layer to the thickness of the p-type work function metal layer 102B can be about 0.3 to about 1.

[0058] Then, a drive-in anneal process is performed to drive the dopants from the dopant-containing layer into the p-type work function metal layer 102B. The anneal process can use a spike anneal, a rapid thermal anneal (RTA), a flash anneal, and the like. The anneal process can be performed for a duration in a range of about 0.2 seconds to about 600 seconds, or about 25 seconds to about 35 seconds. The anneal process can be performed at a temperature of about 350 °C to about 800 °C, or about 400 °C to about 500 °C. The anneal process can be performed for a minimum time to avoid driving the dopants into the first dielectric layer 100B or the interface layer 100A. Driving the dopants into the interface between the first dielectric layer 100B and the interface layer 100A can decrease the effective work function in the region 50P, increasing the flatband voltage and the threshold voltage. As such, the process time is used to drive the dopants into the p-type work function metal layer 102B, avoiding driving the dopants into the first dielectric layer 100B and the interface layer 100A.

[0059] Then, the first adjustment layer 102C is etched from region 50N. A patterned mask, such as a patterned photoresist, can be formed over the first adjustment layer 102C in region 50P. The patterned photoresist can be formed by depositing a photoresist layer over the first adjustment layer 102C in regions 50P and 50N using spin coating or the like. The photoresist layer can then be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions of the photoresist layer, thereby forming the patterned photoresist. The first adjustment layer 102C is then etched from region 50N using a suitable etching process (e.g., isotropic etching (e.g., wet etching), anisotropic etching (e.g., dry etching), etc.). The patterned photoresist can then be removed. The first adjustment layer 102C may be optional and may be omitted in some embodiments. In embodiments where the first adjustment layer 102C is omitted, the p-type work function metal layer 102B can be etched using the same or similar process as that used to etch the first adjustment layer 102C.

[0060] Doping a p-type work function metal layer 102B in region 50P to form a first adjustment layer 102C can increase the effective work function in region 50P, which reduces the flat-band voltage (V) in the complete device with the first adjustment layer 102C. FB ) and threshold voltage (V t This can increase device speed and improve device performance in the complete device.

[0061] FIG. 15C Energy dispersive spectroscopy (EDS) plots of the first dielectric layer 100B and the first adjustment layer 102C in region 50P according to some embodiments are shown. The y-axis provides the relative abundance of the elements detected by EDS, while the x-axis provides the relative positions of the elements within the first dielectric layer 100B and the first adjustment layer 102C. FIG. 15C In the illustrated embodiment, the cap layer 102A can be omitted, allowing the first adjustment layer 102C to be formed directly on the first dielectric layer 100B. FIG. 15C In the illustrated embodiment, the first dielectric layer 100B comprises hafnium oxide, and the first conditioning layer 102C comprises lanthanum-doped titanium nitride. The EDS diagram shows the corresponding concentrations of oxygen (O), aluminum (Al), titanium (Ti), hafnium (Hf), tantalum (Ta), and lanthanum (La). As shown in the EDS diagram, lanthanum is successfully doped throughout the entire first conditioning layer 102C.

[0062] like FIG. 15CFurther shown, the concentration of hafnium in the first dielectric layer 100B can increase from the bottom surface of the first dielectric layer 100B to reach a maximum at about half the thickness of the first dielectric layer and then begin to decrease until the interface with the first adjustment layer 102C. The concentration of oxygen in the first dielectric layer 100B can reach a maximum near the bottom surface of the first dielectric layer 100B. The concentration of oxygen in the first dielectric layer 100B can decrease from the bottom surface of the first dielectric layer 100B to reach a local minimum at about half the thickness of the dielectric layer 100B, then begin to increase to reach a local maximum at about three-quarters of the thickness of the dielectric layer 100B, and then begin to decrease until the interface with the first adjustment layer 102C. The concentration of aluminum in the first dielectric layer 100B can increase from the bottom surface of the first dielectric layer 100B to reach a maximum at about three-quarters of the thickness of the dielectric layer 100B, and then begin to decrease until the interface with the first adjustment layer 102C. Aluminum can diffuse from the n-type work function metal layer 102D into the first dielectric layer 100B. The first dielectric layer 100B can include relatively low concentrations of titanium and lanthanum, the concentrations of titanium and lanthanum increasing from the bottom surface of the first dielectric layer 100B until the interface with the first adjustment layer 102C. The energy peaks of tantalum, hafnium, and tungsten can overlap, such that the relative concentrations of tungsten and hafnium can be mis-represented as the relative concentration of tantalum. As such, while FIG. 15C A relatively high concentration of tantalum in the first dielectric layer 100B is shown, but the concentration of tantalum can actually represent the concentration of hafnium and tungsten in the first dielectric layer 100B, which can be relatively high.

[0063] FIG. 15C Further shown, the concentration of titanium and lanthanum in the first adjustment layer 102C can increase from the interface with the first dielectric layer 100B to reach a maximum at about half the thickness of the first adjustment layer 102C, then begin to decrease until the top surface of the first adjustment layer 102C. While FIG. 15C The concentration of nitrogen in the first adjustment layer 102C is not shown, but the first adjustment layer includes a relatively high concentration of nitrogen. The concentration of oxygen and aluminum in the first adjustment layer 102C can increase from a local minimum near the interface with the first dielectric layer 100B to reach a local maximum at about half the thickness of the first adjustment layer 102C, and then begin to decrease until the top surface of the first adjustment layer 102C. The first adjustment layer 102C can include a relatively low concentration of hafnium, the concentration of hafnium decreasing from the interface with the first dielectric layer 100B until approaching zero. While FIG. 16A A relatively high concentration of tantalum in the first adjustment layer 102C is shown, but the concentration of tantalum shown can represent a relatively high concentration of hafnium and tungsten in the first adjustment layer 102C.

[0064] In FIG. 16Band FIG. 17A In this process, an n-type work function metal layer 102D is formed on the cap layer 102A of region 50N and the first adjustment layer 102C of region 50P. The n-type work function metal layer 102D is formed to adjust the work function of the device. The n-type work function metal layer 102D can be an n-type work function material for n-type FinFET devices. Suitable examples of n-type work function materials include TaAl, TaAlC, HfAl, TiAl, TiAlN, TiAlC, other suitable n-type work function metal materials, multilayers thereof, or combinations thereof. Including aluminum in the n-type work function material can reduce the effective work function of the n-type work function metal layer 102D, which reduces the threshold voltage, increases device speed, and improves device performance for devices formed in region 50N. The n-type work function metal layer 102D can be formed by ALD, CVD, etc. The thickness of the n-type work function metal layer 102D can be approximately... To date or about To date

[0065] exist FIG. 17B and FIG. 17C In this process, an n-type work function metal layer 102D is exposed to a work function adjusting gas to thin the n-type work function metal layer 102D and form a second adjusting layer 102E on the n-type work function metal layer 102D. The work function adjusting gas may include a first adjusting gas and a second adjusting gas. The first adjusting gas may be a transition metal chloride, etc. For example, the first adjusting gas may include tungsten chloride (e.g., WCl5), tantalum chloride (e.g., TaCl5), hafnium chloride (e.g., HfCl4), titanium chloride (e.g., TiCl4), and combinations thereof. The second adjusting gas may be a carrier gas, such as argon (Ar), hydrogen (H2), etc. The first adjusting gas may be supplied at a flow rate of about 100 sccm to about 1000 sccm, or about 450 sccm to about 550 sccm. The second adjusting gas may be supplied at a flow rate of about 1000 sccm to about 7000 sccm, or about 2500 sccm to about 3500 sccm. The ratio of the flow rates of the first conditioning gas to the second conditioning gas can be from about 2 to about 20, or from about 4 to about 8. The work function conditioning gas can be supplied in a deposition chamber maintained at a temperature of about 300°C to about 500°C, or about 350°C to about 450°C, and a pressure of about 0.5 Torr to about 50 Torr, or about 15 Torr to about 25 Torr, for a duration ranging from about 5 seconds to about 600 seconds, or from about 25 seconds to about 35 seconds.

[0066] Exposing the n-type work function metal layer 102D can thin the n-type work function metal layer 102D, reduce the concentration of elements (e.g., aluminum (Al)) in the n-type work function metal layer 102D, and cause the second adjustment layer 102E to be deposited on top of the n-type work function metal layer 102D. When the n-type work function metal layer 102D is exposed to the work function adjustment gas, the work function adjustment gas reacts with the n-type work function metal layer 102D to form the second adjustment layer 102E, which can include an alloy of metals from the n-type work function metal layer 102D and metals from the work function adjustment gas. In some embodiments, the second adjustment layer 102E can be an alloy of a transition metal from the work function adjustment gas and a metal from the n-type work function metal layer 102D. For example, in embodiments where the n-type work function metal layer 102D includes TiAl and the work function adjustment gas includes WC15, the WC15 gas can react with the aluminum of the n-type work function metal layer 102D, thereby forming AlW. Example materials of the second adjustment layer 102E include aluminum tungsten (AlW), aluminum tantalum (AlTa), aluminum hafnium (AlHf), aluminum titanium (AlTi), etc.

[0067] In some embodiments, an element such as chlorine can be included in the first adjustment gas to etch an oxide layer, which can be present in the n-type work function metal layer 102D. For example, an oxide layer including titanium oxide, tantalum oxide, hafnium oxide, etc. can be formed at a top surface of the n-type work function metal layer 102D, and chlorine from the first adjustment gas can etch the oxide layer. The first adjustment gas also includes a transition metal (e.g., tungsten, tantalum, hafnium, titanium, etc.) that bonds to an element such as aluminum included in the first work function metal layer 102D and forms the second adjustment layer 102E. Thus, the amount of aluminum in the first work function metal layer 102D is reduced, and the aluminum in the second adjustment layer 102E that is bonded to the transition metal is prevented from diffusing to the interface between the cap layer 102A and the first dielectric layer 100B. This allows for adjustment of the effective work function.

[0068] The n-type work function metal layer 102D can have an atomic weight percentage of aluminum of about 15% to about 30%, or about 20% to about 25% prior to exposure to the work function adjustment gas. The n-type work function metal layer 102D can have an atomic weight percentage of aluminum of about 5% to about 20%, or about 10% to about 15% after exposure to the work function adjustment gas. The thickness of the n-type work function metal layer 102D can be reduced to a range of about to about , a range of about to about , or a range of about to about The range. The thickness of the second adjustment layer 102E can be approximately to approximately The atomic weight percentage of aluminum in the second adjustment layer 102E can be from about 5% to about 35%, or from about 15% to about 25%. The second adjustment layer 102E can be optional and can be omitted in some embodiments.

[0069] Reducing the aluminum content of the n-type work function metal layer 102D, making it thinner, and forming a second adjustment layer 102E on top of the n-type work function metal layer 102D can increase the effective work function in region 50P. Thus, a thinner p-type work function metal layer 102B and / or the first adjustment layer 102C can be used in region 50P to achieve the same threshold voltage (V) as a device not exposed to the work function adjustment gas. t This adds a gap-fill window and flexibility to the subsequent layers of the gate electrode 102, while providing a device with a lower threshold voltage, increased device speed, and improved device performance.

[0070] The embodiments discussed above include a doping process for forming a first adjustment layer 102C and a work function adjustment process for thinning the n-type work function metal layer 102D and forming a second adjustment layer 102E. In some embodiments, either a doping-only process or a work function adjustment-only process may be performed.

[0071] FIG. 17C Energy dispersive spectroscopy (EDS) plots of the cap layer 102A, the n-type work function metal layer 102D, and the second adjustment layer 102E in region 50N according to some embodiments are shown. The y-axis provides the relative abundance of the elements detected by EDS, while the x-axis provides the relative positions of the elements within the cap layer 102A, the n-type work function metal layer 102D, and the second adjustment layer 102E. FIG. 17C The EDS diagram shown can be obtained in region 50N, allowing the n-type work function metal layer 102D to be formed directly on the cap layer 102A. FIG. 17C In the illustrated embodiment, capping layer 102A comprises titanium nitride, n-type work function metal layer 102D comprises titanium aluminum, and second conditioning layer 102E comprises aluminum tungsten. The EDS diagram shows the corresponding concentrations of tungsten (W), aluminum (Al), titanium (Ti), nitrogen (N), oxygen (O), and silicon (Si). As shown in the EDS diagram, the second conditioning layer 102E comprising aluminum tungsten was successfully formed over the titanium aluminum n-type work function metal layer 102D. The second conditioning layer 102E can have the highest concentrations of aluminum and tungsten. Tungsten from the work function conditioning gas can penetrate both the n-type work function metal layer 102D and capping layer 102A.

[0072] like FIG. 17CAs shown, the concentration of titanium in the capping layer 102A can increase from the interface with the first dielectric layer 100B to reach a maximum at about half the thickness of the capping layer 102A, and then begin to decrease until the interface with the n-type work function metal layer 102D. The concentration of aluminum in the capping layer 102A can increase from the interface with the first dielectric layer 100B to reach a local maximum at about half the thickness of the capping layer 102A, and then begin to decrease until the interface with the n-type work function metal layer 102D. The concentration of oxygen in the capping layer 102A can increase from the interface with the first dielectric layer 100B to reach a maximum at about half the thickness of the capping layer 102A, and then begin to decrease until the interface with the n-type work function metal layer 102D. The concentration of tungsten in the capping layer 102A can increase from the interface with the first dielectric layer 100B to reach a local maximum at about half the thickness of the capping layer 102A, and then begin to decrease until the interface with the n-type work function metal layer 102D. The concentration of silicon in the capping layer 102A can increase from the interface with the first dielectric layer 100B to reach a local maximum at about half the thickness of the capping layer 102A, and then begin to decrease until approaching zero. The presence of tungsten in the capping layer 102A can reduce the detection of nitrogen by EDS. As such, while the capping layer 102A is shown to include a relatively low concentration of nitrogen, the actual concentration of nitrogen included in the capping layer 102A can be higher. FIG. 17D As shown, the concentration of titanium in the capping layer 102A can increase from the interface with the first dielectric layer 100B to reach a maximum at about half the thickness of the capping layer 102A, and then begin to decrease until the interface with the n-type work function metal layer 102D. The concentration of aluminum in the capping layer 102A can increase from the interface with the first dielectric layer 100B to reach a local maximum at about half the thickness of the capping layer 102A, and then begin to decrease until the interface with the n-type work function metal layer 102D. The concentration of oxygen in the capping layer 102A can increase from the interface with the first dielectric layer 100B to reach a maximum at about half the thickness of the capping layer 102A, and then begin to decrease until the interface with the n-type work function metal layer 102D. The concentration of tungsten in the capping layer 102A can increase from the interface with the first dielectric layer 100B to reach a local maximum at about half the thickness of the capping layer 102A, and then begin to decrease until the interface with the n-type work function metal layer 102D. The concentration of silicon in the capping layer 102A can increase from the interface with the first dielectric layer 100B to reach a local maximum at about half the thickness of the capping layer 102A, and then begin to decrease until approaching zero. The presence of tungsten in the capping layer 102A can reduce the detection of nitrogen by EDS. As such, while the capping layer 102A is shown to include a relatively low concentration of nitrogen, the actual concentration of nitrogen included in the capping layer 102A can be higher.

[0073] In the n-type work function metal layer 102D, the concentration of aluminum can decrease from the interface with the capping layer 102A to reach a local minimum at about half the thickness of the n-type work function metal layer 102D, and then begin to increase until the interface with the second adjustment layer 102E. The concentration of titanium in the n-type work function metal layer 102D can decrease from the interface with the capping layer 102A until the interface with the second adjustment layer 102E. The concentration of tungsten in the n-type work function metal layer 102D can decrease from the interface with the capping layer 102A to reach a local minimum at about half the thickness of the n-type work function metal layer 102D, and then begin to increase until the interface with the second adjustment layer 102E. The concentration of oxygen in the n-type work function metal layer 102D can decrease from the interface with the capping layer 102A until the interface with the second adjustment layer 102E. The n-type work function metal layer 102D can include a relatively low concentration of nitrogen and silicon.

[0074] In the second adjustment layer 102E, the concentration of tungsten and aluminum can increase from the interface with the n-type work function metal layer 102D to reach a maximum at about half the thickness of the second adjustment layer 102E, and then decrease until the top surface of the second adjustment layer 102E. The concentration of oxygen in the second adjustment layer 102E can remain relatively constant throughout the entire thickness of the second adjustment layer 102E. The concentration of titanium in the second adjustment layer 102E can decrease from the interface with the n-type work function metal layer 102D until the top surface of the second adjustment layer 102E. The second adjustment layer 102E can include relatively low concentrations of nitrogen and silicon.

[0075] FIG. 17D X-ray photoelectron spectroscopy (XPS) plots of the n-type work function metal layer 102D in an Al2p spectrum for different work function adjustment gas exposure times are shown in accordance with some embodiments. The y-axis provides the relative abundance of electrons detected by XPS, while the x-axis provides the binding energy of the detected electrons. In embodiment 201, the n-type work function metal layer 102D is not exposed to a work function adjustment gas. In embodiment 203, the n-type work function metal layer 102D is exposed to a work function adjustment gas for a time ti. In embodiment 205, the n-type work function metal layer 102D is exposed to a work function adjustment gas for a time t2. The time ti can be from about 15 seconds to about 45 seconds, or from about 20 seconds to about 40 seconds. The time t2 can be about twice the time ti. For example, the time t2 can be from about 45 seconds to about 75 seconds, or from about 50 seconds to about 70 seconds.

[0076] In FIG. 18A embodiment 203, and less than embodiment 203 in embodiment 205. As such, the percentage of metal-aluminum bonds present in the n-type work function metal layer 102D decreases as the exposure time to the work function adjustment gas increases. Reducing the number of metal-aluminum bonds present in the n-type work function metal layer 102D can increase the effective work function in the region 50P. As such, a thinner p-type work function metal layer 102B and / or first adjustment layer 102C can be used in the region 50P to achieve the same threshold voltage (V t). This adds a gap fill window and flexibility for subsequent layers of the gate electrode 102, while providing devices with lower threshold voltage, improved device speed, and improved device performance.

[0077] In FIG. 18B and FIG. 19A , a barrier layer 102F is formed on the second adjustment layer 102E, and a fill material 102G is formed on the barrier layer 102F. Suitable examples of materials that can be used for the barrier layer 102F include TiN, TiSiN, combinations thereof, or multilayers thereof, etc. The barrier layer 102F can be formed by ALD, CVD, etc. The thickness of the barrier layer 102F can be about to about or about to about The barrier layer 102F can be optional, and can be omitted in some embodiments.

[0078] The fill material 102G can include a metal, such as tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), combinations thereof, etc. The fill material 302G can be deposited by ALD, CVD, etc. The fill material 302G fills at least the remaining portion of the second recess 98, e.g., the portion of the second recess 98 that is not filled by the gate dielectric layer 100 and the cap layer 102A, the first adjustment layer 102C, the n-type work function metal layer 102D, the second adjustment layer 102E, and the barrier layer 102F. Although the gate electrode 102 is described as including the cap layer 102A, the first adjustment layer 102C, the n-type work function metal layer 102D, the second adjustment layer 102E, the barrier layer 102F, and the fill material 102G, any of the layers can be omitted, or additional layers can be provided.

[0079] In FIG. 19B and FIG. 20A , the gate electrode 102 and the gate dielectric layer 100 are planarized. For example, after the fill material 102G is formed, a planarization process such as CMP can be performed to remove excess portions of the gate electrode 102 and the gate dielectric layer 100 that are above the top surface of the first ILD 96.

[0080] In FIG. 20B and FIG. 21AIn this process, a second ILD 106 is deposited over the first ILD 96. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc. In some embodiments, prior to forming the second ILD 106, the gate stack (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed to form a groove directly above the gate stack and between opposing portions of the first spacer 81. The groove is filled with a gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96. The gate contacts subsequently formed (e.g., below regarding...) FIG. 21B and FIG. 21A The gate contact 112 discussed passes through the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0081] exist FIG. 21B and ​ In the first ILD 106, gate contacts 112 and source / drain contacts 114 are formed through the second ILD 106 and the first ILD 96. Openings for the source / drain contacts 114 are formed through the first ILD 96 and the second ILD 106, and openings for the gate contacts 112 are formed through the second ILD 106 and the gate mask 104. Acceptable photolithography and etching techniques can be used to form the openings. A liner, such as a diffusion barrier layer or an adhesion layer, and a conductive material are formed within the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the surface of the second ILD 106. The remaining liner and conductive material form the source / drain contacts 114 and the gate contacts 112 within the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 92 and the source / drain contact 114. The source / drain contact 114 is physically and electrically coupled to the epitaxial source / drain region 92, and the gate contact 112 is physically and electrically coupled to the gate electrode 102. The source / drain contact 114 and the gate contact 112 can be formed using different processes, or they can be formed using the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 114 and the gate contact 112 can be formed in different cross-sections, which can prevent short circuits at the contacts.

[0082] As previously described, the semiconductor device formed according to the above-described methods (including the first adjustment layer 102C, the n-type work function metal layer 102D, and / or the second adjustment layer 102E) can have a reduced threshold voltage (V t ), improved device performance, etc. In particular, including the above-described first adjustment layer 102C can increase the effective work function and reduce the threshold voltage in the region 50P. Including the above-described n-type work function metal layer 102D and second adjustment layer 102E can allow for the use of a thinner p-type work function metal layer 102B and / or first adjustment layer 102C, increasing the gap fill window for subsequent layers of the gate electrode 102, while also increasing the effective work function and reducing the threshold voltage in the region 50P.

[0083] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructure (e.g., nanosheet, nanowire, wrap-around gate, etc.) field effect transistors (NSFETs). In NSFET embodiments, the fin is replaced by a nanostructure formed by patterning an alternating stack of channel layers and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a similar manner as the above-described embodiments. After removal of the dummy gate stacks, the sacrificial layers can be partially or fully removed in the channel regions. Replacement gate structures are formed in a similar manner as the above-described embodiments, can partially or fully fill the openings left by removal of the sacrificial layers, and can partially or fully surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and source / drain regions can be formed in a similar manner as the above-described embodiments. Nanostructure devices can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated by reference herein in its entirety.

[0084] According to embodiments, a semiconductor device includes: a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including: a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function adjustment layer over the first work function metal layer, the first work function adjustment layer including aluminum tungsten (AlW); a fill material over the first work function adjustment layer. In embodiments, the first work function metal layer includes titanium aluminum (TiAl). In embodiments, the first work function metal layer has a thickness of to In embodiments, the first work function adjustment layer has a thickness of to In an embodiment, the gate electrode further includes a second work function metal layer between the gate dielectric layer and the first work function metal layer, and the second work function metal layer includes titanium nitride (TiN). In an embodiment, the second work function metal layer has a thickness of to In an embodiment, the second work function metal layer further includes lanthanum (La).

[0085] According to another embodiment, a method includes forming a channel region over a semiconductor substrate; depositing a gate dielectric layer over the channel region; depositing an n-type work function metal layer over the gate dielectric layer; exposing the n-type work function metal layer to a work function adjustment gas, the work function adjustment gas including a transition metal chloride, a first work function adjustment layer is deposited over the n-type work function metal layer. In an embodiment, the transition metal chloride includes tungsten chloride (WCl5). In an embodiment, the transition metal chloride includes hafnium chloride (HfCl4). In an embodiment, after exposing the n-type work function metal layer to the work function adjustment gas, an atomic percentage of aluminum in the n-type work function metal layer is 5% to 20%. In an embodiment, a ratio of a flow rate of the transition metal chloride to a flow rate of a carrier gas in the work function adjustment gas is 2 to 20. In an embodiment, the method further includes depositing a p-type work function metal layer over the gate dielectric layer; and doping the p-type work function metal layer, after doping the p-type work function metal layer, the n-type work function metal layer is deposited over the p-type work function metal layer. In an embodiment, the p-type work function metal layer is doped with lanthanum (La).

[0086] According to another embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; an interface layer over the fin; a first dielectric layer over the interface layer; a p-type work function metal layer over the first dielectric layer, the p-type work function metal layer including a doped transition metal nitride material; and a fill material over the p-type work function metal layer. In an embodiment, the p-type work function metal layer includes titanium nitride doped with lanthanum. In an embodiment, an atomic concentration of a dopant in the p-type work function metal layer is 0.5% to 30%. In an embodiment, the dopant includes aluminum (Al). In an embodiment, the dopant includes magnesium (Mg). In an embodiment, the p-type work function metal layer has a thickness of to and the dopant extends through an entire thickness of the p-type work function metal layer.

[0087] The foregoing summary of features of the several embodiments has been presented for the purposes of better enabling those skilled in the art to make and use the disclosure. The skilled person will appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. The skilled person will also appreciate that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations thereto without departing from the spirit and scope of the disclosure.

[0088] Example 1. A semiconductor device comprising: a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode comprising: a first work function metal layer over the gate dielectric layer, the first work function metal layer comprising aluminum (Al); a first work function adjustment layer over the first work function metal layer, the first work function adjustment layer comprising aluminum tungsten (AlW); and a fill material over the first work function adjustment layer.

[0089] Example 2. The semiconductor device of Example 1, wherein the first work function metal layer comprises titanium aluminum (TiAl).

[0090] Example 3. The semiconductor device of Example 1, wherein a thickness of the first work function metal layer is to

[0091] Example 4. The semiconductor device of Example 3, wherein a thickness of the first work function adjustment layer is to

[0092] Example 5. The semiconductor device of Example 4, wherein the gate electrode further comprises a second work function metal layer between the gate dielectric layer and the first work function metal layer, and wherein the second work function metal layer comprises titanium nitride (TiN).

[0093] Example 6. The semiconductor device of Example 5, wherein a thickness of the second work function metal layer is to

[0094] Example 7. The semiconductor device of Example 5, wherein the second work function metal layer further comprises lanthanum (La).

[0095] Example 8. A method of fabricating a semiconductor device, comprising: forming a channel region over a semiconductor substrate; depositing a gate dielectric layer over the channel region; depositing an n-type work function metal layer over the gate dielectric layer; and exposing the n-type work function metal layer to a work function adjustment gas, the work function adjustment gas comprising a transition metal chloride, wherein a first work function adjustment layer is deposited over the n-type work function metal layer.

[0096] Example 9. The method of example 8, wherein the transition metal chloride comprises tungsten chloride, WCl5.

[0097] Example 10. The method of example 8, wherein the transition metal chloride comprises hafnium chloride, HfCl4.

[0098] Example 11. The method of example 8, wherein an atomic percent of aluminum in the n-type work function metal layer is 5% to 20% after exposing the n-type work function metal layer to the work function adjustment gas.

[0099] Example 12. The method of example 8, wherein a ratio of a flow rate of the transition metal chloride to a flow rate of a carrier gas in the work function adjustment gas is 2 to 20.

[0100] Example 13. The method of example 8, further comprising: depositing a p-type work function metal layer over the gate dielectric layer; and doping the p-type work function metal layer, wherein the n-type work function metal layer is deposited over the p-type work function metal layer after doping the p-type work function metal layer.

[0101] Example 14. The method of example 13, wherein the p-type work function metal layer is doped with lanthanum, La.

[0102] Example 15. A semiconductor device, comprising: a fin extending from a semiconductor substrate; an interface layer over the fin; a first dielectric layer over the interface layer; a p-type work function metal layer over the first dielectric layer, the p-type work function metal layer comprising a doped transition metal nitride material; and a fill material over the p-type work function metal layer.

[0103] Example 16. The semiconductor device of example 15, wherein the p-type work function metal layer comprises titanium nitride doped with lanthanum.

[0104] Example 17. The semiconductor device of example 15, wherein an atomic concentration of a dopant in the p-type work function metal layer is 0.5% to 30%.

[0105] Example 18. The semiconductor device of example 17, wherein the dopant comprises aluminum, Al.

[0106] Example 19. The semiconductor device of example 17, wherein the dopant comprises magnesium, Mg.

[0107] Example 20. The semiconductor device of example 15, wherein the p-type work function metal layer has a thickness of to and wherein a dopant extends through an entire thickness of the p-type work function metal layer.

Claims

1. A semiconductor device, comprising: The channel region is located on the semiconductor substrate; A gate dielectric layer is disposed above the channel region; as well as A gate electrode, situated above the gate dielectric layer, comprising: Cap layer; A first work function metal layer is disposed on the cap layer, the first work function metal layer comprising aluminum (Al); A first work function adjustment layer, situated above the first work function metal layer, comprising aluminum tungsten (AlW). The aluminum concentration in the first work function metal layer decreases from the interface between the first work function metal layer and the capping layer to half the thickness of the first work function metal layer, and then begins to increase until it reaches the interface between the first work function metal layer and the first work function adjustment layer; and Filling material is placed on top of the first work function adjustment layer.

2. The semiconductor device according to claim 1, wherein, The first work function metal layer comprises titanium aluminum (TiAl).

3. The semiconductor device according to claim 1, wherein, The thickness of the first work function metal layer is to 4. The semiconductor device according to claim 3, wherein, The thickness of the first work function adjustment layer is to 5. The semiconductor device according to claim 4, wherein, The gate electrode further includes a second work function metal layer between the gate dielectric layer and the first work function metal layer, wherein the second work function metal layer comprises titanium nitride (TiN).

6. The semiconductor device according to claim 5, wherein, The thickness of the second work function metal layer is to 7. The semiconductor device according to claim 5, wherein, The second work function metal layer also includes lanthanum (La).

8. A method for manufacturing a semiconductor device, comprising: A channel region is formed on a semiconductor substrate; A gate dielectric layer is deposited over the channel region; An n-type work function metal layer is deposited on the gate dielectric layer; as well as The n-type work function metal layer is exposed to a work function adjusting gas comprising a transition metal chloride, wherein a first work function adjusting layer is deposited on the n-type work function metal layer. Specifically, the n-type work function metal layer is exposed to the work function adjusting gas to reduce the concentration of elements in the n-type work function metal layer.

9. The method according to claim 8, wherein, The transition metal chloride includes tungsten chloride (WCl5).

10. The method according to claim 8, wherein, The transition metal chlorides include hafnium chloride (HfCl4).

11. The method according to claim 8, wherein, After the n-type work function metal layer is exposed to the work function adjusting gas, the atomic percentage of aluminum in the n-type work function metal layer is 5% to 20%.

12. The method according to claim 8, wherein, The work function adjusts the ratio of the flow rate of the transition metal chloride in the gas to the flow rate of the carrier gas to be 2 to 20.

13. The method of claim 8, further comprising: A p-type work function metal layer is deposited on the gate dielectric layer; as well as The p-type work function metal layer is doped, wherein, after the p-type work function metal layer is doped, the n-type work function metal layer is deposited on the p-type work function metal layer.

14. The method according to claim 13, wherein, The p-type work function metal layer is doped with lanthanum (La).

15. A semiconductor device, comprising: Fins extend from the semiconductor substrate; An interface layer is placed on top of the fins. A first dielectric layer is disposed above the interface layer; A p-type work function metal layer is placed above the first dielectric layer. The p-type work function metal layer comprises a doped transition metal nitride material. The dopant in the p-type work function metal layer includes lanthanum. The concentration of lanthanum increases from the interface with the first dielectric layer to reach a maximum at half the thickness of the p-type work function metal layer, and then begins to decrease until the top surface of the p-type work function metal layer. as well as Filler material is placed on top of the p-type work function metal layer.

16. The semiconductor device according to claim 15, wherein, The p-type work function metal layer includes titanium nitride doped with lanthanum.

17. The semiconductor device according to claim 15, wherein, The atomic concentration of the dopant in the p-type work function metal layer is between 0.5% and 30%.

18. The semiconductor device according to claim 15, wherein, The thickness of the p-type work function metal layer is to Furthermore, the dopant extends throughout the entire thickness of the p-type work function metal layer.

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