Semiconductor device

Abstract

The present application provides a semiconductor device capable of stably ensuring symmetry of electromagnetic conversion characteristics using a two-direction driving rotary current method. The semiconductor device includes a magnetic switch provided on a semiconductor substrate. The magnetic switch includes a horizontal Hall element including a first electrode pair and a second electrode pair disposed at a position orthogonal to the first electrode pair; a switching circuit having a plurality of switches, capable of selecting a driving current direction of the Hall element from four directions; an SH comparator alternately performing a first action of sampling a signal transmitted from the Hall element and a second action of outputting a signal based on a comparison result of a reference value and a sampled signal value; a latch circuit holding the output signal and outputting the same as a latch output signal; and a control circuit selecting the driving current direction in a period of the first action and a period of the second action based on the latch output signal.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Hall elements, as magnetic sensors, can detect position or angle in a non-contact manner, and are therefore used in a wide variety of applications. One example of a Hall element's application is a magnetic switch. A magnetic switch has, for example, a Hall element and peripheral circuitry including an amplifier or comparator, integrated on a semiconductor chip. Regarding magnetic switches, as a classification focusing on magnetic detection methods, it is known that there are bipolar magnetic field detection types capable of detecting magnetic fields at both the S and N poles, or alternating magnetic field detection types capable of detecting alternating magnetic fields where the S and N poles change alternately over time.

[0003] In alternating-detection magnetic switches or bipolar-detection magnetic switches, the symmetry between the S-side threshold and the N-side threshold is crucial. On the other hand, asymmetry arises due to the offset voltage of the Hall element itself, as well as the amplifiers and comparators arranged after the Hall element.

[0004] To prevent output signal jitter caused by inherent noise and interference noise when a zero magnetic field is applied, a hysteresis amplitude is sometimes set in the magnetic switch. The hysteresis amplitude is defined by the difference between the operating point (which serves as the threshold on the S-pole side) and the reset point (which serves as the threshold on the N-pole side). The magnetic offset is defined by the average of the operating point and the reset point. The magnetic offset is used as a measure of the symmetry of the sensitivity between the magnetic poles and is ideally zero.

[0005] When deviations occur at the operating point or reset point, the duty cycle or phase deviation of the output pulse signal increases in applications requiring alternating magnetic field testing. In BL (brushless) DC motors, which primarily use alternating test magnetic switches, deviations in the duty cycle or phase of the output pulse signal become a cause of speed fluctuations and vibrations, and are therefore undesirable.

[0006] Furthermore, in two-pole test type magnetic switches, without proper polarity management of the magnets used in combination, deviations in the testing distance of the magnetic material testing mechanism may occur, potentially generating offset voltage. As one method for removing offset voltage, the rotating current method is known. A technique has been proposed that uses the rotating current method to remove offset voltage from the Hall element and the subsequent amplifier stage, and further removes the asymmetry caused by the comparator's offset voltage (see, for example, Patent Document 1).

[0007] The technology described in Patent Document 1 is a technique using a so-called bidirectional driven rotating current method. Regarding rotating current methods, in addition to the aforementioned bidirectional driven rotating current method, there is also a four-directional driven rotating current method. Both the bidirectional and four-directional driven rotating current methods have their advantages and disadvantages. From the viewpoint of maximizing processing speed (shorter processing time), the bidirectional driven rotating current method is superior to the four-directional driven rotating current method.

[0008] Prior technology literature

[0009] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2009-2851. Summary of the Invention

[0011] [The problem the invention aims to solve]

[0012] However, from the viewpoint of the symmetry of the electromagnetic conversion characteristics in a magnetic switch, the technique using the existing bidirectional driven rotating current method, as described in Patent Document 1, is inferior to the technique using the four-directional driven rotating current method. Specifically, in the technique using the existing bidirectional driven rotating current method, there is a situation where the electromagnetic conversion characteristics in the magnetic switch may not be linearly symmetrical on the S-pole side and the N-pole side.

[0013] Regarding existing bidirectional rotating current methods, a residual offset voltage may remain if the absolute value of the Hall element's offset voltage differs between the current driving directions. If this residual offset voltage exists, the electromagnetic switching characteristics of the magnetic switch become asymmetrical. Therefore, in existing bidirectional rotating current methods, it may be impossible to obtain electromagnetic switching characteristics with good symmetry.

[0014] In view of the above circumstances, the present invention aims to provide a semiconductor device capable of stably ensuring the symmetry of electromagnetic conversion characteristics using a bidirectional driven rotating current method.

[0015] [Solution to the problem]

[0016] The semiconductor device according to the present invention is characterized in that it is a semiconductor device having a magnetic switch disposed on a semiconductor substrate, wherein the magnetic switch has a Hall element comprising a first electrode and a second electrode disposed on a first straight line, and a third electrode and a fourth electrode disposed on a second straight line orthogonal to the first straight line.

[0017] A first switching circuit having multiple switches configured to select one of four directions from which the direction of the drive current of the Hall element can be chosen: a first direction from the first electrode toward the second electrode, a second direction from the second electrode toward the first electrode, a third direction from the third electrode toward the fourth electrode, and a fourth direction from the fourth electrode toward the third electrode; a comparison circuit alternately performing a first action of sampling the signal transmitted from the Hall element and a second action of outputting a result signal, the result signal being a result signal based on a comparison of a reference value and the value of a differential signal between the signal transmitted from the Hall element and the signal sampled by the first action; a latching circuit. The circuit includes a path that holds the result signal output from the comparison circuit and outputs the held signal as a latched output signal; and a control circuit configured to select one of a first mode and a second mode based on the latched output signal, wherein the first mode controls the opening and closing state of the switch by causing the drive current to flow in the third direction during a first period of performing the first action and by causing the drive current to flow in the first direction during a second period of performing the second action, and the second mode controls the opening and closing state of the switch by causing the drive current to flow in the second direction during the first period and by causing the drive current to flow in the fourth direction during the second period.

[0018] [The effects of the invention]

[0019] According to the present invention, a semiconductor device is provided that can stably ensure the symmetry of electromagnetic conversion characteristics using a bidirectional driven rotating current method. Attached Figure Description

[0020]

【 Figure 1 [Illustration] is a schematic diagram of the semiconductor device according to the first embodiment.

[0021]

【 Figure 2 This is a circuit diagram illustrating an example of a sample-and-hold comparator in a semiconductor device according to this embodiment.

[0022]

【 Figure 3 [Illustration 1] is a circuit diagram illustrating an example of a control circuit in a semiconductor device according to an embodiment.

[0023]

【 Figure 4 This is an explanatory diagram illustrating an example of the control logic pattern of a logic circuit in a control circuit.

[0024]

【 Figure 5 (a) to (d) are explanatory diagrams illustrating the direction of the drive current of the horizontal Hall element in the semiconductor device according to this embodiment.

[0025]

【 Figure 6 (a) is a schematic diagram illustrating the relationship between the amplifier's input voltage and the magnetic flux density Bin. (b) is a schematic diagram illustrating the relationship between the amplifier's input voltage and the magnetic flux density Bin when the direction of the drive current flowing through the aforementioned horizontal Hall element is the second direction pair.

[0026]

【 Figure 7 [Image] is a schematic diagram illustrating the relationship between the amplifier's output voltage and the magnetic flux density Bin when the direction of the drive current flowing through the horizontal Hall element of the semiconductor device according to this embodiment is a first direction pair.

[0027]

【 Figure 8 [Image] is a schematic diagram illustrating the relationship between the output voltage of the latch circuit and the magnetic flux density Bin when the direction of the drive current flowing through the horizontal Hall element of the semiconductor device according to this embodiment is a first direction pair.

[0028]

【 Figure 9 [Image] is a schematic diagram illustrating the relationship between the amplifier's output voltage and the magnetic flux density Bin when the direction of the drive current flowing through the horizontal Hall element of the semiconductor device according to this embodiment is a second direction pair.

[0029]

【 Figure 10 This is a schematic diagram illustrating the relationship between the output voltage of the latch circuit and the magnetic flux density Bin when the direction of the drive current flowing through the horizontal Hall element of the semiconductor device involved in this embodiment is a second direction pair.

[0030]

【 Figure 11 This is a schematic diagram illustrating the relationship between the output voltage of the amplifier and the output voltage of the latch circuit relative to the magnetic flux density Bin when the magnetic deflection of the horizontal Hall element of the semiconductor device involved in this embodiment is positive.

[0031]

【 Figure 12 This is a schematic diagram illustrating the relationship between the output voltage of the amplifier and the output voltage of the latch circuit relative to the magnetic flux density Bin when the magnetic deflection of the horizontal Hall element of the semiconductor device involved in this embodiment is negative.

[0032]

【 Figure 13 The diagram above is a schematic representation of the relationship between the reference clock signal input to the control circuit, the magnetic flux density Bin, and the magnetic detection state.

[0033]

【 Figure 14 The diagram shows the timing of the reference clock signal input to the control circuit, the latched output signal, and the drive control signal and transmission control signal output from the control circuit.

[0034]

【 Figure 15 [Illustration] is a schematic diagram of the semiconductor device according to the second embodiment.

[0035]

【 Figure 16 (a) to (d) are explanatory diagrams illustrating the direction of the drive current of the vertical Hall element in the semiconductor device according to this embodiment.

[0036]

【 Figure 17 [Illustration] is a schematic diagram of the semiconductor device according to the third embodiment.

[0037]

【 Figure 18 This is a circuit diagram illustrating an example of a sample-and-hold comparator in a semiconductor device according to this embodiment.

[0038]

【 Figure 19 This is a schematic diagram illustrating the relationship between the output voltage of the amplifier and the output voltage of the latch circuit relative to the magnetic flux density Bin when the magnetic deflection of the horizontal Hall element of the semiconductor device involved in this embodiment is positive.

[0039]

【 Figure 20 This is a schematic diagram illustrating the relationship between the output voltage of the amplifier and the output voltage of the latch circuit relative to the magnetic flux density Bin when the magnetic deflection of the horizontal Hall element of the semiconductor device involved in this embodiment is negative.

[0040]

Figure 21

[0041] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings. The semiconductor device according to the embodiment includes a magnetic switch provided on a semiconductor substrate. Furthermore, in the description, the conversion characteristic from magnetic flux density acting on the semiconductor substrate to an analog signal is referred to as "electromagnetic conversion characteristic", and the conversion characteristic from the magnetic flux density to a logic signal is referred to as "electromagnetic switching characteristic".

[0042] [First Implementation Method]

[0043] Figure 1 This is a schematic diagram showing the configuration of the semiconductor device 1A according to the first embodiment.

[0044] Semiconductor device 1A includes a magnetic switch 10A disposed on semiconductor substrate 2. Magnetic switch 10A includes drive terminals 11P and 11N, output terminal 12, horizontal Hall element 20, switches SP1-SP4, SN1-SN4, and SS1-SS4 as a first switching circuit, amplifier 30, a sample-and-hold comparator (hereinafter referred to as "SH comparator") 40A as a comparison circuit, control circuit 50, and latch circuit 80A.

[0045] The horizontal Hall element 20 is a magnetic verification element having electrodes 21-24 and receiving an output corresponding to a magnetic flux density Bin perpendicular to the semiconductor substrate 2. Electrodes 21-24 are disposed on a resistor formed from an impurity diffusion layer or a well layer of the semiconductor substrate 2. As described later, electrodes 21-24 are arranged on a first straight line L1 passing through electrodes 21 and 22 (refer to...). Figure 5 (a) and the second straight line L2 passing through electrodes 23 and 24 (refer to) Figure 5 (a) Orthogonal positions. In other words, electrode 21, which serves as the first electrode, and electrode 22, which serves as the second electrode, are arranged on the first straight line L1. Electrode 23, which serves as the third electrode, and electrode 24, which serves as the fourth electrode, are arranged on the second straight line L2.

[0046] Each switch SP1-SP4, SN1-SN4, and SS1-SS4 has a first terminal and a second terminal located at both ends of a freely openable / closeable circuit, as well as an opening / closing control terminal. Each switch SP1-SP4, SN1-SN4, and SS1-SS4 is configured to switch between an open state (disconnected circuit) and a closed state (short circuit) based on the level of the control signal input from the opening / closing control terminal. Switches SP1-SP4, SN1-SN4, and SS1-SS4 are controlled to be in a closed state when the level of the control signal input from the opening / closing control terminal is high (hereinafter referred to as "H"), and in an open state when the level is low (hereinafter referred to as "L").

[0047] Amplifier 30 is composed of a differential amplifier circuit having: a non-inverting input terminal INP and an inverting input terminal INN, which are input with signals transmitted from the horizontal Hall element 20; and an output terminal OT, which amplifies and outputs the difference between the two signals input from the non-inverting input terminal INP and the inverting input terminal INN.

[0048] Specifically, as described below, the SH comparator 40A has: an input terminal 41, which receives a signal S1 output from the amplifier 30; an input terminal 42, which receives a signal S3 fed back from the latch circuit 80A; an input terminal 44, which receives a reference clock signal CLK; and an output terminal 43, which outputs a signal.

[0049] Specifically, as described below, the control circuit 50 has: an input terminal 51a, which receives a reference clock signal CLK; an input terminal 51b, which receives a signal S3; output terminals 56a to 56d, which output drive control signals Sd1 to Sd4 as control signals; and output terminals 56e and 56f, which output control signals St1 and St2.

[0050] The latch circuit 80A includes: a signal input terminal on which a signal S2 is input; an inverting clock input terminal on which a signal opposite in phase to the reference clock signal CLK, i.e., an inverted reference clock signal CLKX, is input; an output terminal on which a signal S3, serving as a latch output signal, is output; and a latch output signal generation unit (not shown) that generates signal S3 based on signal S2 and the inverted reference clock signal CLKX. The latch circuit 80A is configured to perform so-called data latching.

[0051] The drive terminal 11P, which serves as the first drive terminal, is connected to a first power supply (not shown) that provides the power supply voltage VDD. Additionally, the drive terminal 11P is connected to the first terminals of switches SP1 to SP4.

[0052] The second terminal of switch SP1, which acts as the first switch, is connected to the first terminal of switch SN2, which acts as the sixth switch, electrode 21, and the first terminal of switch SS1. These connection points form node P1.

[0053] The second terminal of switch SP2, which is the fifth switch, is connected to the first terminal of switch SN1, which is the second switch, electrode 22, and the first terminal of switch SS4. These connection points form node P2.

[0054] The second terminal of switch SP3, which acts as the third switch, is connected to the first terminal of switch SN4, which acts as the eighth switch, electrode 23, and the first terminal of switch SS3. These connection points form node P3.

[0055] The second terminal of switch SP4, which is the seventh switch, is connected to the first terminal of switch SN3, which is the fourth switch, electrode 24, and the first terminal of switch SS2. These connection points form node P4.

[0056] The second terminals of switches SN1 to SN4 are connected to drive terminal 11N, which serves as the second drive terminal. Drive terminal 11N is connected to a second power supply (not shown) that supplies power voltage VSS.

[0057] The second terminals of switches SS1 and SS2 are connected to the non-inverting input terminal INP of amplifier 30. The second terminals of switches SS3 and SS4 are connected to the inverting input terminal INN of amplifier 30.

[0058] The output terminal OT of amplifier 30 is connected to the input terminal 41 of SH comparator 40A. The output terminal 43 of SH comparator 40A is connected to the signal input terminal of latch circuit 80A. The output terminal of latch circuit 80A is connected to the output terminal 12 of magnetic switch 10A, the input terminal 51b of control circuit 50, and the input terminal 42 of SH comparator 40A.

[0059] The configuration of the SH comparator 40A and the control circuit 50 will be further explained.

[0060] Figure 2 This is a circuit diagram showing the SH comparator 40A.

[0061] The SH comparator 40A has input terminals 41, 42, 44, a sample-and-hold amplifier (hereinafter referred to as "SHA") 45, a reference voltage circuit 46, a comparator 47, and an output terminal 43.

[0062] SHA45 has: a first input terminal connected to input terminal 41; a second input terminal connected to input terminal 44; a third input terminal connected to input terminal 42; and an output terminal. Reference voltage circuit 46 has: an input terminal 46a connected to input terminal 42; an output terminal 46b; and a variable voltage source 46c. Variable voltage source 46c has: a first terminal connected to output terminal 46b; and a second terminal connected to GND (ground). Comparator 47 has: a non-inverting input terminal connected to the output terminal of SHA45; ​​an inverting input terminal connected to output terminal 46b; and an output terminal connected to output terminal 43.

[0063] Figure 3 This is a circuit diagram showing an example of control circuit 50. Figure 4 This is an explanatory diagram showing an example of the control logic pattern of logic circuit 57 in control circuit 50.

[0064] The control circuit 50 includes input terminals 51a and 51b, a logic circuit 57 and a switch circuit 58 serving as a control signal generation circuit, output terminals 56a to 56d serving as a first control signal output terminal to a fourth control signal output terminal, and output terminals 56e and 56f.

[0065] The control circuit 50 is configured to generate six control signals: drive control signals Sd1 to Sd4 (four control signals) and transmission control signals St1 and St2 (two control signals), based on the reference clock signal CLK input from input terminal 51a and the signal S3 input from input terminal 51b. The reference clock signal CLK is a period T consisting of a first period Φ1 that is at high level and a second period Φ2 that is at low level. CA periodic signal that acts as a cycle.

[0066] Drive control signals Sd1 to Sd4 are output from output terminals 56a to 56d, respectively. Transmission control signals St1 and St2 are output from output terminals 56e and 56f, respectively.

[0067] The logic circuit 57 has: two input terminals connected to input terminals 51a and 51b respectively; six output terminals connected to output terminals 56a to 56f respectively; and multiple logic operation elements connecting the two input terminals to the six output terminals. The logic circuit 57 can be configured to... Figure 4 The control signals outputting L-level or H-level signals, as shown, are configured in a manner that includes at least one of the first and second control logic patterns, namely, driving control signals Sd1 to Sd4 and transmitting control signals St1 and St2.

[0068] Multiple logic operation elements include, for example, inverters 52a, 52b, 54a-54e, NAND elements 53a-53d, and EXOR element 55. These multiple logic operation elements, together with the switching circuit 58, form a path for transmitting signals between input terminals 51a, 51b and output terminals 56a-56f.

[0069] Regarding inverter 52a, NAND elements 53b and 53c, and EXOR element 55, their input terminals are connected to input terminal 51a. Additionally, regarding inverter 52b, its input terminal is connected to input terminal 51b. Regarding NAND elements 53a-53d and EXOR element 55, the second input terminal of the first and second input terminals is connected to input terminal 51b via switching circuit 58 or by inverter 52b and switching circuit 58.

[0070] The second switching circuit 58 has pairs of switches SL1a and SL2a, SL1b and SL2b, and SL1c and SL2c, each with different on / off states. If one switch SL1a, SL1b, or SL1c of a pair is closed, the other switch SL2a, SL2b, or SL2c of the pair is open. Conversely, if one switch SL1a, SL1b, or SL1c of a pair is open, the other switch SL2a, SL2b, or SL2c of the pair is closed.

[0071] If switches SL1a, SL1b, and SL1c are closed and switches SL2a, SL2b, and SL2c are open, the second input terminals of NAND elements 53a-53d and EXOR element 55 are connected to input terminal 51b via a first path. If switches SL1a, SL1b, and SL1c are open and switches SL2a, SL2b, and SL2c are closed, the second input terminals of NAND elements 53a-53d and EXOR element 55 are connected to input terminal 51b via a second path different from the first path.

[0072] When the second input terminals of NAND elements 53a-53d and EXOR element 55 are connected to input terminal 51b via a first path, the output control logic pattern corresponds to the first control logic pattern. Conversely, when the second input terminals of NAND elements 53a-53d and EXOR element 55 are connected to input terminal 51b via a second path, the output control logic pattern corresponds to the second control logic pattern.

[0073] Next, the function of magnetic switch 10A will be explained.

[0074] Figure 5 (a) ~ Figure 5 (d) is an illustration of the direction of the drive current defined in the horizontal Hall element 20.

[0075] In the magnetic switch 10A, it is configured such that the direction of the drive current of the horizontal Hall element 20 can be selected from four directions via switches SP1-SP4 and SN1-SN4. The opening and closing states of switches SP1-SP4 and SN1-SN4 are controlled by the control circuit 50, thereby allowing appropriate switching of the direction of the drive current of the horizontal Hall element 20. Hereinafter, for ease of explanation, the direction from electrode 21 to electrode 22 will be referred to as the "first direction," and the direction from electrode 22 to electrode 21 will be referred to as the "second direction." Furthermore, the direction of the drive current from electrode 23 to electrode 24 will be referred to as the "third direction," and the direction from electrode 24 to electrode 23 will be referred to as the "fourth direction."

[0076] Furthermore, the pair of the first direction and the third direction is called the "first direction pair," and the pair of the second direction and the fourth direction is called the "second direction pair." Since lines L1 and L2 are orthogonal, the first and second directions, as well as the third and fourth directions, are also orthogonal. Therefore, the "first direction pair" and the "second direction pair" are two orthogonal direction pairs.

[0077] The horizontal Hall element 20 is formed parallel to the XY plane in the XYZ three-dimensional orthogonal coordinate system. When a magnetic flux density Bin is applied to the horizontal Hall element 20 in a direction perpendicular to the paper (Z-axis direction) from the surface to the back, a positive Hall electromotive force (EMF) is generated between electrodes 24 and 23 when the driving current direction is a first direction, and a negative Hall EMF is generated between electrodes 24 and 23 when the driving current direction is a second direction. Furthermore, a positive Hall EMF is generated between electrodes 21 and 22 when the driving current direction is a third direction, and a negative Hall EMF is generated between electrodes 21 and 22 when the driving current direction is a fourth direction. The horizontal Hall element 20 generally exhibits a certain regularity for each driving current direction, generating an offset voltage with a larger absolute value than the Hall EMF that serves as the output signal of the horizontal Hall element 20.

[0078] The output signal of the horizontal Hall element 20 is transmitted from electrodes 21 to 24 to amplifier 30 via switches SS1 to SS4. Switches SS1 to SS4 are controlled to open and close in a manner that differs from the open and closed states of switches SS2 and SS3 based on the transmission control signals St1 and St2.

[0079] When the direction of the driving current is in the first direction, since switches SS2 and SS3 are closed and switches SS1 and SS4 are open, electrode 23 is connected to the inverting input terminal INN via switch SS3. When the direction of the driving current is in the second direction, the opening and closing states of switches SS1 to SS4 are the same as when the direction of the driving current is in the first direction. Therefore, electrode 23 is connected to the inverting input terminal INN via switch SS3, and electrode 24 is connected to the non-inverting input terminal INP via switch SS2.

[0080] When the direction of the driving current is in the third direction, since switches SS1 and SS4 are closed and switches SS2 and SS3 are open, electrode 23 is connected to the inverting input terminal INN via switch SS3. When the direction of the driving current is in the fourth direction, the opening and closing states of switches SS1 to SS4 are the same as when the direction of the driving current is in the third direction. Therefore, electrode 23 is connected to the inverting input terminal INN via switch SS3, and electrode 24 is connected to the non-inverting input terminal INP via switch SS2.

[0081] Amplifier 30 amplifies the differential input voltage ΔV between the non-inverting input terminal INP and the inverting input terminal INN with a predetermined amplification factor G, and outputs the amplified signal from the output terminal OT to the SH comparator 40A. Within amplifier 30, there exists an input offset voltage V.OSA The signal S1 output from the output terminal OT is subject to the input offset voltage V. OSA The influence of the differential input voltage ΔV and the input offset voltage V. OSA The sum of the products of the magnification and the amplification factor G, i.e. (ΔV + V) OSA G represents the input offset voltage V included in signal S1. OSA The two processes are offset by performing the aforementioned rotating current method.

[0082] The SH comparator 40A performs the following actions: sampling the signal S1; and comparison and determination, comparing a predetermined reference voltage with a differential voltage signal that is a differential signal of the signal S1 from the previous period, and outputting a result signal based on the comparison result. The SHA45 performs the sampling of the signal S1 as the first action. The comparator 47 performs the comparison and determination as the second action. The sampling and comparison and determination of the signal S1 are performed alternately.

[0083] The SH comparator 40A samples the signal S1 within the first period Φ1 and compares it with a predetermined reference voltage, and then compares the sampled differential voltage signal of the signal S1 within the first period Φ1 with the signal S1 within the second period Φ2. The SH comparator 40A outputs the comparison result of the differential voltage signal with the predetermined reference voltage and a corresponding signal S2. The level of signal S2 switches, for example, according to the comparison result, as follows: it is at level L when the differential voltage signal is lower than the predetermined reference voltage, and at level H when the differential voltage signal is the same as or higher than the predetermined reference voltage.

[0084] A predetermined reference voltage is generated by a variable voltage source 46c as a reference value. The generated voltage is switched to either a first voltage or a second voltage different from the first voltage according to the signal S3 output from the latch circuit 80A.

[0085] The offset voltage of the horizontal Hall element 20 and the amplifier 30 is offset by using differential processing of the first period Φ1 and the second period Φ2. In the SH comparator 40A, a so-called automatic zeroing process that runs through the first period Φ1 and the second period Φ2 can also be performed to offset the offset voltage of the SH comparator 40A itself.

[0086] Signal S2 is input from SH comparator 40A to latch circuit 80A. At the last moment of the second period Φ2, i.e., the falling edge of the inverting reference clock signal CLKX, latch circuit 80A maintains a level opposite to that of the input signal S2, and outputs the held signal as signal S3. Therefore, according to each period T corresponding to one cycle of the reference clock signal CLK... CThe signal S3 is updated based on its level.

[0087] Figure 6 (a) is a schematic diagram illustrating the relationship between the input voltage of amplifier 30 and magnetic flux density Bin when the direction of the drive current flowing through horizontal Hall element 20 is a first direction pair (a first direction and a third direction pair). Figure 6 (b) is a schematic diagram illustrating the relationship between the input voltage of amplifier 30 and magnetic flux density Bin when the direction of the drive current flowing through the horizontal Hall element 20 is a second direction pair (a pair of second and fourth directions).

[0088] exist Figure 6 (a) and Figure 6 In the figures of (b), the horizontal axis represents the magnetic flux density Bin acting on the semiconductor substrate 2, and the vertical axis represents the voltage V. The solid line L... ID1 ~L ID4 These represent the differential input voltage ΔV of amplifier 30 relative to the magnetic flux density Bin corresponding to the first through fourth directions. The differential input voltage ΔV is equivalent to the sum of two voltages output from the horizontal Hall element 20: one positive voltage and one anti-phase voltage. The differential input voltage ΔV (hereinafter referred to as the "vertical intercept") when the magnetic flux density Bin is 0 (zero) represents the offset voltage in zero magnetic field. The slope of the straight line represents the electromagnetic conversion coefficient. Solid line L ID1 L ID4 The slope is equal to the electromagnetic conversion coefficient K. H (∂ΔV / ∂Bin=K) H Solid line L ID2 L ID3 The slope is equal to the electromagnetic conversion coefficient -K H (∂ΔV / ∂Bin=-K) H ).

[0089] The dashed line BL1 represents the electromagnetic conversion characteristic of the difference between the offset voltage ΔV1 when the driving current flows in the first direction and the offset voltage ΔV3 when the driving current flows in the third direction. The dashed line BL2 represents the electromagnetic conversion characteristic of the difference between the offset voltage ΔV2 when the driving current flows in the second direction and the offset voltage ΔV4 when the driving current flows in the fourth direction.

[0090] The differential operations between offset voltages ΔV1 and ΔV3, and between offset voltages ΔV2 and ΔV4, are performed by the SH comparator 40A. The slopes of the dashed lines BL1 and BL2 represent the electromagnetic conversion coefficient K. H With electromagnetic conversion coefficient -K H The difference becomes the solid line L. ID1 LID4 Twice the slope (=2K) H ).

[0091] Here, if the offset voltage is taken as the offset voltage V when the direction of the drive current flowing through the horizontal Hall element 20 is the first direction and the second direction. OS2 The offset voltage V is taken as the offset voltage in the third and fourth directions. OS1 Then the offset voltages ΔV1~ΔV4 are represented by the following equations (1)~(4).

[0092]

[0093] Next, the differences between the directions constituting the first direction pair are represented by the following equations (5) and (6). The differences between the directions constituting the second direction pair are represented by the following equations (7) and (8).

[0094]

[0095] Since the offset voltage differs in each direction, its influence is not eliminated during differential processing. The differences between the directions constituting the first direction pair and the differences between the directions constituting the second direction pair are called the ordinate intercepts, which are (V... OS2 -V OS1 ) or (V OS1 -V OS2 (The non-ideal characteristics of)

[0096] Here, if we consider the slope value "2K" H "Calculate the magnetic flux density Bin (horizontal intercept) when the differential input voltage ΔV becomes zero (ΔV=0), then the magnetic deflection B of the horizontal Hall element 20 corresponding to the first and second direction pairs..." OSDP1 B OSDP2 It can be represented by the following equations (9) and (10) respectively.

[0097]

[0098] Figure 7 and Figure 8 These are explanations of what is happening in each case. Figure 6 In the case shown in (a) (i.e., in magnetic offset B) OSDP1 positive (B) OSDP1 =(V OS2 -V OS1 ) / 2K H A schematic diagram of the relationship between signals S1 and S3 and magnetic flux density Bin (when >0).

[0099] Figure 9 and Figure 10These are explanations of what is happening in each case. Figure 6 In the case shown in (b) (i.e., in magnetic offset B) OSDP2 negative (B) OSDP2 =(V OS1 -V OS2 ) / 2K H A schematic diagram of the relationship between signals S1 and S3 and magnetic flux density Bin (when <0). Figure 7 and Figure 9 The dashed line BL shown OD1 ~BL OD4 The signals S1 represent the magnetic flux densities Bin corresponding to the first to fourth directions, respectively.

[0100] in accordance with Figure 7 and Figure 9 Dashed line BL OD1 ~BL OD4 Relative to the solid line L ID1 ~L ID4 And along the vertical axis, the voltage GV OSA Change. Here, voltage GV OSA It is the amplification factor G and the input offset voltage V OSA The product of . If the magnetic offset B OSDP1 If positive, then regarding the characteristics of the electromagnetic switch, such as Figure 8 As shown, action point B OP and reset point B RP All change along the positive direction of magnetic flux density (to the right of the diagram). If the magnetic deflection B OSDP2 If it is negative, then regarding the characteristics of the electromagnetic switching switch, such as... Figure 10 As shown, action point B OP and reset point B RP They all change along the negative direction of magnetic flux density (left side of the figure).

[0101] In equations (9) and (10) above, if |V OS2 -V OS1 | is 0 or | V OS2 -V OS1 |Small enough to be negligible magnetic offset B OSDP1 B OSDP2 The degree of this state (referred to as "approximately 0"), i.e., the offset voltage V. OS2 With offset voltage V OS1 Equal or with differences so small as to be negligible magnetic offset B OSDP1 B OSDP2 If the degree of similarity (this state is referred to as "equal degree") is such that magnetic offset B can be ignored. OSDP1 B OSDP2 .

[0102] However, in semiconductor device 1A, it is not limited to being able to use |V at all times OS2 -V OS1 | Becomes a Hall element with approximately 0. Therefore, in this embodiment, a new technique is proposed to eliminate the differential offset voltage (V) without using so-called four-way drive signal processing. OS2 -V OS1 The impact of ).

[0103] The right sides of the above equations (9) and (10) are such that the absolute values ​​are equal and the signs are opposite. With this in mind, in this embodiment, the direction of the drive current is switched as a first direction pair or as a second direction pair according to the polarity of the magnetic field being tested (i.e., the level of signal S3, which is the output signal of the latch circuit 80A).

[0104] In magnetic switch 10A, if the direction of the drive current is not switched according to the level of signal S3, the operating point B... OP and reset point B RP It is asymmetrical relative to the magnetic flux density Bin=0. That is, regarding the magnetic switch 10A, without switching the direction of the drive current according to the level of signal S3, for example, as Figure 8 and Figure 10 As shown, it has asymmetrical electromagnetic switching characteristics.

[0105] The magnetic switch 10A switches the direction of the drive current according to the level of signal S3, thereby obtaining the operating point B on the S pole side. OP The reset point B on the N-side, which is reversed relative to the straight line where Bin=0. RP That is, the magnetic switch 10A switches the direction of the drive current according to the level of the signal S3, thereby obtaining an electromagnetic switching characteristic that is linearly symmetrical with respect to the straight line with Bin=0.

[0106] Figure 11 This describes the magnetic deflection B of the horizontal Hall element 20 itself. OSDP A schematic diagram showing the relationship between signals S1 and S3 and magnetic flux density Bin when the value is positive.

[0107] exist Figure 11 In the middle, the solid line L DP1 The magnetic deflection B is shown when the direction pair of the driving current is the first direction pair. OSDP It becomes a positive electromagnetic conversion characteristic. Solid line L DP2 This shows the magnetic deflection B when the direction pair of the driving current is the second direction pair. OSDP It becomes a negative electromagnetic conversion characteristic. (Dashed line BL) id It is shown that it becomes magnetic offset B OS=0 is the ideal electromagnetic conversion characteristic. Blank arrows (1), (1a), (2), (3), (3a) and (4) represent the hysteresis trajectory of the electromagnetic conversion characteristic.

[0108] in addition, Figure 11 The electromagnetic conversion characteristics shown are an example under the following conditions: signal S3 is at level H and selects a third direction during the first period Φ1; signal S3 is at level H and selects a first direction during the second period Φ2; signal S3 is at level L and selects a second direction during the first period Φ1; signal S3 is at level L and selects a fourth direction during the second period Φ2. This example corresponds to the first control logic pattern.

[0109] In the first control logic mode, the drive control signal Sd1, which serves as the first control signal, is output from output terminal 56a. Similarly, the drive control signals Sd2, Sd3, and Sd4, which serve as the second, third, and fourth control signals, are output from output terminals 56b, 56c, and 56d, respectively. In addition, the transmission control signals St1 and St2 are output from output terminals 56e and 56f, respectively.

[0110] Through the opening and closing actions of switches SP1-SP4, SN1-SN4 and SS1-SS4 based on drive control signals Sd1-Sd4 and transmission control signals St1 and St2, signal S3 is at level H and selects a third direction during the first period Φ1, and signal S3 is at level H and selects a first direction during the second period Φ2.

[0111] During the phase when signal S3 is at level H and magnetic flux density Bin increases towards the S pole side, along the solid line L... DP1 The trajectory of the corresponding electromagnetic conversion characteristic advances (blank arrow (1)). If the voltage input to the SH comparator 40A, i.e., the voltage of signal S1, exceeds the reference voltage V, which is the first voltage. BOP (ΔV･G>V) BOP If the signal S3 then transitions to the L level, the reference voltage V... BOP In the electromagnetic conversion characteristics, the magnetic flux density Bin at the operating point B OP The voltage at that point.

[0112] As the level of signal S3 changes, the reference voltage of comparator 40A changes from the reference voltage V. BOP Switching to the reference voltage V as the second voltage BRP Reference voltage V BRP In the electromagnetic conversion characteristics, the magnetic flux density Bin at the reset point B RP The voltage at that point. Reference voltage V BRP It is relative to the reference voltage V BOP In contrast, voltages are positive and negative.

[0113] When signal S3 is at level L, since the direction of the drive current is selected as either the second or fourth direction, it flows towards the solid line L. DP2 The corresponding electromagnetic conversion characteristics change (blank arrow (2)). Subsequently, as the magnetic flux density Bin further increases towards the S pole side, the voltage V changes along the solid line L. DP2 Further increase towards the positive side (blank arrow (3a)). On the other hand, the trajectory of the magnetic flux density Bin changing to decrease at the S pole, Bin=0, and then increase at the N pole is blank arrow (3). Moreover, if the magnetic flux density Bin increases towards the N pole side, the voltage input to the SH comparator 40A, i.e., the voltage of signal S1, exceeds the reference voltage V on the negative side. BRP (ΔV･G) <V BRP If the signal S3 changes level, then signal S3 transitions to the H level. Along with the level change of signal S3, the reference voltage of the SH comparator 40A changes from the reference voltage V. BRP Switch to reference voltage V BOP .

[0114] When signal S3 is at level H, the direction of the drive current is selected as either the third direction or the first direction, and thus the direction is perpendicular to the solid line L. DP1 The corresponding electromagnetic conversion characteristics change (blank arrow (4)). Subsequently, as the magnetic flux density Bin further increases towards the N-pole side, the voltage V changes along the solid line L. DP1 Further increasing towards the negative side (blank arrow (1a)). On the other hand, the trajectory of the magnetic flux density Bin when it decreases at the N pole, Bin=0, and then increases at the S pole is the aforementioned blank arrow (1). In this embodiment, the shape of the hysteresis trajectory in the electromagnetic conversion characteristic becomes a parallelogram shape.

[0115] In magnetic switch 10A, when connected to solid line L... DP1 The corresponding electromagnetic conversion characteristics and the solid line L DP2 The corresponding electromagnetic conversion characteristics change. The magnetic deflection B of the aforementioned horizontal Hall element 20 itself... OSDP When the magnetic flux density Bin changes in the direction increasing towards the S pole, a third and first driving current are used. Additionally, when the magnetic flux density Bin changes in the direction increasing towards the N pole, a second and fourth driving current are used. Therefore, the operating point B... OP From its design value (hereinafter referred to as "action point design value") B OPid With magnetic offset B OSDP Accordingly, it shifts towards the low-sensitivity side (the direction away from Bin=0). Additionally, the reset point B... RP From its design value (hereinafter referred to as "reset point design value") B RPid With magnetic offset B OSDP Accordingly, the sensitivity is shifted towards the lower sensitivity side.

[0116] The magnetic deflection B of the horizontal Hall element 20 itself OSDP When it becomes positive, the following equations (11) to (16) hold true. Here, B HYS B HYSid and B OS These are the lag amplitude and the lag amplitude B, respectively. HYS The design values ​​and the magnetic offset in the electromagnetic switching characteristics of the 10A magnetic switch.

[0117]

[0118] Based on equations (11) and (12) above, action point B OP and reset point B RP From the action point design value B, which is its design value. OPid and reset point design value B RPid The absolute value of the deviation and B OSDP They are equal but opposite in sign. Therefore, in the magnetic switch 10A, while maintaining the symmetry of the electromagnetic switching characteristics as is, the sensitivity changes between the S and N poles. The magnetic deflection B of the aforementioned horizontal Hall element 20 itself... OSDP When the signal is positive, the magnetic switch 10A operates by deviating towards lower sensitivity between the S and N poles.

[0119] Figure 12 This describes the magnetic deflection B of the horizontal Hall element 20 itself. OSDP A schematic diagram showing the relationship between signals S1 and S3 and magnetic flux density Bin when the values ​​are negative.

[0120] exist Figure 12 In the middle, the solid line L DP1 solid line L DP2 The dashed BLid and blank arrows (1), (1a), (2), (3), (3a) and (4) are related to Figure 11 Similarly, Additionally, Figure 12 The electromagnetic conversion characteristics shown are an example under the following conditions: signal S3 is at level H and selects the second direction during the first period Φ1; signal S3 is at level H and selects the fourth direction during the second period Φ2; signal S3 is at level L and selects the third direction during the first period Φ1; signal S3 is at level L and selects the first direction during the second period Φ2. This example corresponds to the second control logic pattern.

[0121] In the second control logic mode, the drive control signal Sd1, which is the fifth control signal, is output from output terminal 56a. Similarly, the drive control signals Sd2, Sd3, and Sd4, which are the sixth, seventh, and eighth control signals, are output from output terminals 56b, 56c, and 56d, respectively. In addition, the transmission control signals St1 and St2 are output from output terminals 56e and 56f, respectively.

[0122] Through the opening and closing actions of switches SP1-SP4, SN1-SN4 and SS1-SS4 based on drive control signals Sd1-Sd4 and transmission control signals St1 and St2, signal S3 is at H level and selects the second direction within the first period Φ1, signal S3 is at H level and selects the fourth direction within the second period Φ2, signal S3 is at L level and selects the first direction within the first period Φ1, and signal S3 is at L level and selects the third direction within the second period Φ2.

[0123] During the phase when signal S3 is at level H and magnetic flux density Bin increases towards the S pole side, along the solid line L... DP2 The trajectory of the corresponding electromagnetic conversion characteristic advances (blank arrow (1)). If the voltage input to the SH comparator 40A, i.e., the voltage of signal S1, exceeds the reference voltage V on the positive side. BOP (ΔV･G>V) BOP If the signal S3 changes level, then signal S3 transitions to the L level. Along with the level change of signal S3, the reference voltage of the SH comparator 40A changes from the reference voltage V. BOP Switch to reference voltage V BRP .

[0124] When signal S3 is at level L, since the direction of the drive current is selected as either the third direction or the first direction, it is perpendicular to the solid line L. DP1 The corresponding electromagnetic conversion characteristics change (blank arrow (2)). Subsequently, as the magnetic flux density Bin further increases towards the S pole side, the voltage V changes along the solid line L. DP1 Further increase towards the positive side (blank arrow (3a)).

[0125] On the other hand, the trajectory of the magnetic flux density Bin when it decreases at the S pole, Bin=0, and then increases at the N pole is a blank arrow (3). Moreover, if the magnetic flux density Bin increases towards the N pole side, the voltage input to the SH comparator 40A, i.e., the voltage of signal S1, exceeds the reference voltage V on the negative side. BRP (ΔV･G) <V BRP If the signal S3 changes level, then signal S3 transitions to the H level. Along with the level change of signal S3, the reference voltage of the SH comparator 40A changes from the reference voltage V. BRP Switch to reference voltage V BOP .

[0126] When signal S3 is at level H, since the direction of the drive current is selected as either the second or fourth direction, it flows towards the solid line L. DP2 The corresponding electromagnetic conversion characteristics change (blank arrow (4)). Subsequently, as the magnetic flux density Bin further increases towards the N-pole side, the voltage V changes along the solid line L. DP2 Further increase towards the negative side (blank arrow (1a)). On the other hand, the trajectory of the magnetic flux density Bin when it decreases at the N pole, Bin=0, and then increases at the S pole is the blank arrow (1) mentioned above.

[0127] In magnetic switch 10A, when connected to solid line L... DP1 The corresponding electromagnetic conversion characteristics and the solid line L DP2 The corresponding electromagnetic conversion characteristics change. The magnetic deflection B of the aforementioned horizontal Hall element 20 itself... OSDP When the magnetic flux density Bin changes in the direction of increasing towards the S pole, the driving current in the second and fourth directions is used.

[0128] Furthermore, when the magnetic flux density Bin changes in the direction increasing towards the N pole, a driving current in the third direction and the first direction is used. Therefore, the operating point B... OP From the action point design value B OPid With magnetic offset B OSDP Accordingly, it shifts towards the high-sensitivity side (closer to the direction of Bin=0). Additionally, the reset point B... RP Design value B from the reset point RPid With magnetic offset B OSDP Accordingly, the sensitivity is shifted towards the higher sensitivity side.

[0129] The magnetic deflection B of the aforementioned horizontal Hall element 20 itself OSDP When the value becomes negative, the following equations (17) to (19) hold. Furthermore, the magnetic deflection B on the electromagnetic switching characteristics... OS The value is the same as in equation (14) above, which is 0.

[0130]

[0131] Based on equations (17) and (18) above, action point B OP and reset point B RP From the action point design value B, which is its design value. OPid and reset point design value B RPid The absolute value of the deviation and B OSDP They are equal but opposite in sign. Therefore, in the magnetic switch 10A, while maintaining the symmetry of the electromagnetic switching characteristics as is, the sensitivity changes between the S and N poles. The magnetic deflection B of the aforementioned horizontal Hall element 20 itself... OSDPWhen the signal becomes negative, the magnetic switch 10A operates by deviating towards higher sensitivity between the S and N poles.

[0132] Next, the relationship between magnetic flux density Bin and the magnetic detection state shown by signal S3 will be explained.

[0133] Figure 13 This is a schematic diagram illustrating the relationship between the reference clock signal CLK, magnetic flux density Bin, and the magnetic detection state. Furthermore, during the illustration, the latch circuit 80A is reset at time t=0. Additionally, the initial values ​​of magnetic flux density Bin and signal S3 at time t=0 are taken as magnetic flux density Bin=0 and signal S3=H, respectively.

[0134] The reference clock signal CLK is a periodic signal that is at level H during the first period Φ1 and at level L during the second period Φ2. The latch circuit 80A updates the determination of the magnetic flux density Bin based on the electromagnetic conversion characteristics of the signal S3 offset being canceled at the last moment of the second period Φ2.

[0135] If the magnetic flux density Bin exceeds the action point B on the positive side (in the diagram, from bottom to top) from time t=0 onwards. OP The transition to S-pole detection begins at time t1, starting from the initial arrival of Φ1 in the first period. At time t1, the N-pole detection remains in the previous state. Subsequently, if the original state is maintained and the magnetic flux density Bin exceeds the action point B... OP The state that is maintained in the original state of the S-pole detection has been maintained for a period of time T. C At time t2, the latch circuit 80A outputs a signal S3 indicating the L level of the S-pole detection. That is, at time t2, the determination of the magnetic flux density Bin is updated from N-pole detection to S-pole detection.

[0136] Furthermore, if time passes, the magnetic flux density Bin changes from the S pole to the N pole and then shifts to the negative side (from top to bottom in the diagram) beyond the reset point B. RP If the magnetic flux density Bin remains unchanged, the N-pole detection determination will begin at time t3, starting from the initial time t1. At time t3, the S-pole detection will continue as in the previous detection state. Thereafter, if the magnetic flux density Bin remains unchanged, the N-pole detection state will continue for a period T. C At time t4, the latch circuit 80A outputs a signal S3 indicating the H level of the N-pole detection. That is, at time t4, the determination of the magnetic flux density Bin changes from S-pole detection to N-pole detection. This process repeats as the magnetic flux density Bin changes periodically.

[0137] In this way, the signal S3 that transitions between the L level and the H level is transmitted from the latch circuit 80A to the output terminal 12, the control circuit 50, and the SH comparator 40A. The reference clock signal CLK is input to the control circuit 50 together with the signal S3. In the control circuit 50, drive control signals Sd1 to Sd4 and transfer control signals St1 and St2 are generated based on the input signal S3 and the reference clock signal CLK.

[0138] Figure 14 is a timing chart of the reference clock signal CLK and the signal S3 input to the control circuit 50, and the drive control signals Sd1 to Sd4 and the transfer control signals St1 and St2 output from the control circuit 50. In addition, the timing chart shown in this figure is the case where the above-mentioned first control logic pattern is applied. Also, similar to Figure 13 the latch circuit 80A is reset at time t = 0, and the initial values of the magnetic flux density Bin and the signal S3 at time t = 0 are the magnetic flux density Bin = 0 and the signal S3 = H level, respectively.

[0139] The control circuit 50 switches between the first mode according to the table for N - pole detection ( Figure 4 ) and the second mode according to the table for S - pole detection ( Figure 4 ). In the timing chart shown in Figure 14 , N - pole detection is performed at times 0 < t < t2 and t ≥ t4, and S - pole detection is performed at times t2 ≤ t < t4.

[0140] In N - pole detection, the drive control signals Sd1, Sd2 and the transfer control signals St2, St1 operate in synchronization with the reference clock signal CLK. The drive control signal Sd1 and the drive control signal Sd2 are output in an inverted state where the levels of the L level and the H level are different from each other. The transfer control signal St2 and the transfer control signal St1 are also output in an inverted state similar to the drive control signal Sd1 and the drive control signal Sd2.

[0141] Therefore, at times 0 < t < t2 and t ≥ t4 when N - pole detection is performed, the drive control signal Sd1 and the transfer control signal St2 become H level in the first period Φ1 and become L level in the second period Φ2. The drive control signal Sd2 and the transfer control signal St1 become L level in the first period Φ1 and become H level in the second period Φ2.

[0142] On the other hand, in S - pole detection, the drive control signals Sd3, Sd4 and the transfer control signals St1, St2 operate in synchronization with the reference clock signal CLK. The drive control signal Sd3 and the drive control signal Sd4 are output in an inverted state. The transfer control signal St1 and the transfer control signal St2 are output in an inverted state.

[0143] Therefore, at the time t2 < t < t4 for S-pole detection, the drive control signal Sd3 and the transfer control signal St1 become H level within the first period Φ1 and become L level within the second period Φ2. The drive control signal Sd4 and the transfer control signal St2 become L level within the first period Φ1 and become H level within the second period Φ2.

[0144] Accordingly, the magnetic switch 10A includes the SH comparator 40A configured to be able to switch and output a predetermined reference voltage from multiple candidates. According to the semiconductor device 1A having the magnetic switch 10A and the magnetic switch 10A, by switching the direction of the drive current according to the level of the signal S3, the operation point B on the S-pole side OP with respect to the straight line of Bin = 0 can be reversed to obtain the reset point B on the N-pole side RP or the reset point B on the N-pole side RP with respect to the straight line of Bin = 0 can be reversed to obtain the operation point B on the S-pole side OP . By switching the open / closed states of the switches SL1a, SL1b, SL1c and the switches SL2a, SL2b, SL2c, such a change can be made: whether to obtain the operation point B on the S-pole side OP with respect to the straight line of Bin = 0 can be reversed to obtain the reset point B on the N-pole side RP , or whether to obtain the reset point B on the N-pole side RP with respect to the straight line of Bin = 0 can be reversed to obtain the operation point B on the S-pole side OP .

[0145] According to this embodiment, the two-direction drive rotating current method that switches the direction of the drive current according to the level of the signal S3 can be used to cause the influence of the residual offset voltage to be generated symmetrically on the S-pole side and the N-pole side lines, so that a hysteresis characteristic with high symmetry can be obtained. Therefore, according to this embodiment, the operation point B OP and the reset point B RP with equal absolute values can be obtained, that is, an electromagnetic conversion switch characteristic with line symmetry between the S-pole and the N-pole can be obtained.

[0146] As described above, the electromagnetic conversion switch characteristic of the entire magnetic switch 10A becomes an electromagnetic conversion switch characteristic with line symmetry between the S-pole and the N-pole. Therefore, according to this embodiment, the two-direction drive rotating current method that switches the direction of the drive current according to the level of the signal S3 can be used to obtain an electromagnetic conversion switch characteristic that can suppress the influence of the residual offset voltage to the same extent as the four-direction drive rotating current method.

[0147] Furthermore, since a two-directional driven rotating current method is used, even if the processing time for each direction is the same, the processing time required for detecting and determining the magnetic pole can be halved compared to a four-directional driven rotating current method. Therefore, for the semiconductor device 1A equipped with the magnetic switch 10A, compared to a magnetic switch using a four-directional driven rotating current method and a semiconductor device equipped with that magnetic switch, signal processing can be performed in a short time even if the processing time for each direction is the same.

[0148] Furthermore, in magnetic switches using a four-way driven rotating current method and semiconductor devices equipped with such magnetic switches, increasing the reference clock frequency might make the processing time for each cycle the same. However, increasing the reference clock frequency necessitates increasing the bandwidth of the amplifier or comparator, leading to increased power consumption. Therefore, regarding magnetic switch 10A and semiconductor device 1A equipped with magnetic switch 10A, compared to magnetic switches using a four-way driven rotating current method and semiconductor devices equipped with such magnetic switches, signal processing can be performed with low power consumption even if the processing time for each full driving direction (one cycle) is the same.

[0149] According to this embodiment, based on the level of signal S3, the magnetic deflection B of the horizontal Hall element 20 itself is adjusted. OSDP By distributing the drive current in a positive or negative manner, two different patterns of linearly symmetrical electromagnetic switching characteristics can be obtained. The magnetic deflection B of the horizontal Hall element 20 itself... OSDP When it becomes positive, the apparent sensitivity deviation can be taken as a deviation towards the lower sensitivity side. The magnetic deflection B of the horizontal Hall element 20 itself... OSDP When the sensitivity becomes negative, the apparent deviation in sensitivity can be considered as a deviation towards the higher sensitivity side. Furthermore, according to this embodiment, it is possible to select a desired single-mode linear symmetrical electromagnetic switching characteristic by switching between two different modes of linear symmetrical electromagnetic switching characteristics.

[0150] According to this embodiment, the action point B can be adjusted in advance. OP and reset point B RP Optimization. For example, the magnetic offset B for each combination of the directions of the driving current. OSDP The deviation is normal and the magnetic offset B is known. OSDP In the case of polarity, the pre-planned magnetic offset B was adjusted in advance. OSDP The deviation of the reference voltage V BRP V BRP The absolute value is sufficient.

[0151] On the other hand, the magnetic deflection B in each combination of the directions of the driving current OSDP When the random deviation is large and the polarity is not known, the magnetic offset B in the electromagnetic switching characteristics of the magnetic switch 10A of the semiconductor device 1A is first measured. OS Then, the magnetic offset B in the characteristics of the electromagnetic switching device is additionally considered. OS The adjustment process can be completed by fine-tuning the fuse or writing to the EEPROM based on the test results.

[0152] According to this embodiment, regardless of the magnetic deflection B of the horizontal Hall element 20 itself OSDP Regardless of its magnitude, it can cause a symmetrical residual offset voltage to be generated on the S-side and N-side lines. Therefore, in order to suppress the magnetic offset B of the horizontal Hall element 20 itself... OSDP Alternatively, a horizontal Hall element 20, which connects multiple Hall element units in parallel, may not necessarily be applicable. According to this embodiment, electromagnetic switching characteristics with symmetrical S and N poles can be obtained without increasing the chip's footprint or current consumption.

[0153] [Second Implementation]

[0154] Figure 15 This is a schematic diagram showing the configuration of the semiconductor device 1B according to the second embodiment.

[0155] Figure 16 (a) to (d) are schematic diagrams showing the configuration and connection state of the vertical Hall element 60 provided in the semiconductor device 1B.

[0156] Regarding semiconductor device 1B, it differs from semiconductor device 1A in that it has a vertical Hall element 60 instead of the horizontal Hall element 20 connected to nodes P1 to P4, but the other points are the same. Therefore, in this embodiment, the description will focus on the vertical Hall element 60, and descriptions that are repeated with those of semiconductor device 1A will be omitted.

[0157] Semiconductor device 1B includes a magnetic switch 10B disposed on semiconductor substrate 2. The magnetic switch 10B includes drive terminals 11P and 11N, output terminal 12, vertical Hall element 60, switches SP1 to SP4, SN1 to SN4 and switches SS1 to SS4, amplifier 30, SH comparator 40A, control circuit 50 and latch circuit 80A.

[0158] The vertical Hall element 60 has electrodes 61 to 65, which are arranged, for example, at a predetermined distance along the Y-axis. The two electrodes 61 and 65 located closest to each other along the Y-axis are connected (short-circuited) by wiring 66. Electrodes 61 and 65 are connected to node P3 via wiring 66. Electrode 62 is connected to node P2. Electrode 63 is connected to node P1. Electrode 64 is connected to node P4.

[0159] In the magnetic switch 10B constructed as described above, the first to fourth current driving directions can be defined in the same way as in the magnetic switch 10A. For example, the direction in which the driving current flows from the central third electrode 63 of electrodes 61-65 to the closest end electrodes 61 and 65 can be defined as the first current driving direction (see reference). Figure 16 (a)). The direction in which the driving current flows from electrode 61 and electrode 65 to electrode 63 (i.e., the direction opposite to the first current driving direction) is taken as the second current driving direction (refer to). Figure 16 (b)). The direction in which the driving current flows from electrode 62 (number 2) to electrode 64 (number 4) among electrodes 61-65 is taken as the third current driving direction (see reference). Figure 16 (c)). The direction in which the driving current flows from electrode 64 to electrode 62 (i.e., the direction opposite to the third current driving direction) is taken as the fourth current driving direction (refer to...). Figure 16 (d)).

[0160] According to the example above, the vertical Hall element 60 generates a positive Hall electromotive force between electrodes 64 and 62 in the first current driving direction, and a positive Hall electromotive force between electrodes 63 and electrodes 61 and 65 in the third current driving direction. On the other hand, the vertical Hall element 60 generates a negative Hall electromotive force between electrodes 64 and 62 in the second current driving direction, and a negative Hall electromotive force between electrodes 63 and electrodes 61 and 65 in the fourth current driving direction.

[0161] The semiconductor device 1B and magnetic switch 10B configured in this way can operate in the same way as the semiconductor device 1A and magnetic switch 10A. By performing the same operation as the semiconductor device 1A and magnetic switch 10A, the semiconductor device 1B and magnetic switch 10B obtain the same effect as the semiconductor device 1A and magnetic switch 10A.

[0162] Accordingly, based on this embodiment, a linearly symmetrical electromagnetic switching characteristic can be obtained using a bidirectional driving rotating current method that switches the direction of the driving current according to the level of signal S3. That is, the same effects as in the first embodiment can be obtained, such as electromagnetic switching characteristics that can suppress the influence of residual offset voltage to the same extent as the four-directional driving rotating current method.

[0163] Furthermore, regarding the vertical Hall element 60, compared to the horizontal Hall element 20, its magnetic offset B is due to the asymmetrical geometry of the vertical Hall element 60. OSDP A greater tendency. Therefore, the advantage of obtaining the linearly symmetric electromagnetic conversion characteristics in this embodiment is arguably more significant than the advantage of obtaining the linearly symmetric electromagnetic conversion characteristics in the first embodiment.

[0164] also, Figure 16 The vertical Hall element 60 shown is an example in which electrodes 61-65 are arranged along the Y-axis and the direction of the magnetic flux density Bin is parallel to the X-axis, but the vertical Hall element 60 is not limited to this example. Regarding the vertical Hall element 60, the direction in which the electrodes 61-65 are arranged is orthogonal to the direction of the magnetic flux density Bin. For example, the vertical Hall element 60 may also have electrodes 61-65 arranged along the X-axis and the direction of the magnetic flux density Bin parallel to the Y-axis.

[0165] [Third Implementation Method]

[0166] Figure 17 This is a schematic diagram showing the configuration of the semiconductor device 1C according to the third embodiment.

[0167] Regarding semiconductor device 1C, it differs from semiconductor device 1A in that it also includes a knife switch 70 that switches the input terminal and output destination based on signal S3, an SH comparator 40C instead of SH comparator 40A, and a latch circuit 80C instead of latch circuit 80A, but other aspects are the same. Therefore, in this embodiment, the description will focus on the above-mentioned differences, and descriptions that are repeated with semiconductor device 1A will be omitted.

[0168] Semiconductor device 1C includes a magnetic switch 10C disposed on semiconductor substrate 2. The magnetic switch 10C includes drive terminals 11P and 11N, output terminal 12, horizontal Hall element 20, switches SP1 to SP4, SN1 to SN4, switches SS1 to SS4, knife switch 70, amplifier 30, SH comparator 40C, control circuit 50, and latching circuit 80C.

[0169] The knife switch 70 is more conveniently located in the preamplifier stage than the SH comparator 40C, which serves as a comparison circuit. Figure 17 In the illustrated semiconductor device 1C, the second terminals of each of the switches SS1 to SS4 are connected between the non-inverting input terminal INP and the inverting input terminal INN of the amplifier 30.

[0170] The knife switch 70 includes: a differential input section; a differential output section; a switching section that enables switching the path connecting the differential input section and the differential output section to two types; and a control terminal that receives a signal S3 as a control signal for switching the path.

[0171] In the knife switch 70, the differential input section includes a first input terminal and a second input terminal. The first input terminal and the second input terminal are respectively connected to the second terminals of switches SS1, SS2 and SS3, SS4. The differential output section includes a first output terminal and a second output terminal. The first output terminal and the second output terminal are respectively connected to the positive input terminal INP and the negative input terminal INN.

[0172] The switching section of the knife switch 70 has four paths that are closably connected between a first input terminal and a second input terminal, and between a first output terminal and a second output terminal. These four paths consist of: a first path that closably connects the first input terminal to the first output terminal; a second path that closably connects the first input terminal to the second output terminal; a third path that closably connects the second input terminal to the first output terminal; and a fourth path that closably connects the second input terminal to the second output terminal. The four paths can switch their open / closed states based on a control signal input from a control terminal.

[0173] The knife switch 70 is configured to switch between a first connection state where the first and fourth paths are closed and the second and third paths are open, and a second connection state where the first and fourth paths are open and the second and third paths are closed. Here, the first connection state is a straight-line state, and the second connection state is a cross-connection state.

[0174] The knife switch 70 can output signals input from the first input terminal and the second input terminal with the same polarity in the first connection state (i.e., direct line state) and output them from the first output terminal and the second output terminal. In the second connection state (i.e., cross-connection state), it can reverse the polarity of signals input from the first input terminal and the second input terminal (make them opposite polarities) and output them from the first output terminal and the second output terminal.

[0175] Figure 18 This is a circuit diagram showing an example of an SH comparator 40C.

[0176] Regarding the SH comparator 40C, it differs from the SH comparator 40A in that it has a reference voltage circuit 48 instead of a reference voltage circuit 46, but otherwise they are not substantially different.

[0177] The reference voltage circuit 48 is configured to output a predetermined reference voltage (constant voltage). That is, the SH comparator 40C omits the function of making the reference voltage variable from the SH comparator 40A, and is used to set the operating point B of the horizontal Hall element 20. OP and reset point B RP The reference voltage is integrated (combined into one). This is because the knife switch 70 can reverse the polarity of the differential input signal, thus unifying the polarity of the signal input to amplifier 30 to either positive or negative. In this embodiment, a predetermined reference voltage is used as the reference voltage V. BOP Reference voltage V BOP It is a voltage with positive polarity.

[0178] Regarding latch circuit 80C, compared to latch circuit 80A, the logic for determining the output signal S3 based on the input signal S2, i.e., the latch output signal generation unit (not shown), is different, but other aspects are essentially the same. Latch circuit 80C is configured to output signal S3 as either a signal with the same level as signal S2 or a signal with the opposite level to signal S2, based on the input signal S2 and the inverting reference clock signal CLKX. In other words, latch circuit 80C is a so-called trigger-type latch circuit configured to perform a triggering operation.

[0179] Next, the function of magnetic switch 10C will be explained.

[0180] In magnetic switch 10C, similarly to magnetic switch 10A, the output signal of horizontal Hall element 20 is input to knife switch 70 via switches SS1 to SS4 from the first and second input terminals, which are differential input sections. Additionally, signal S3 output from latching circuit 80A is input to knife switch 70 from the control terminal.

[0181] The knife switch 70 changes to either a first connection state (outputting the differential input signal as is without reversing its polarity) or a second connection state (outputting the differential input signal with its polarity reversed) depending on the level of signal S3. Therefore, the knife switch 70 outputs the differential input signal either as is or with its polarity reversed, depending on the level of signal S3. The polarity of the differential input signal to the knife switch 70 is switched according to the level of signal S3, thus obtaining a connection relative to Bin=0 (described later). Figure 19 and Figure 20 The characteristics of a linear and line-symmetrical electromagnetic switching device.

[0182] The signals output from the first and second output terminals of the knife switch 70 are input to the non-inverting input terminal INP and the inverting input terminal INN. The operation within the amplifier 30 is as described above.

[0183] In the SH comparator 40C connected to amplifier 30, a comparison is performed similarly to that of SH comparator 40A, comparing a predetermined reference voltage with a differential voltage signal, which is the differential signal of the signal S1 within the first sampling period Φ1 and the signal S1 within the second sampling period Φ2. SH comparator 40C outputs a signal S2 corresponding to the comparison result and level of the differential voltage signal with the predetermined reference voltage. The predetermined reference voltage is a constant voltage output from reference voltage circuit 48 and is independent of the level of signal S3. Signal S2 is input from SH comparator 40C to latch circuit 80C.

[0184] The latch circuit 80C is triggered at the last moment of the second period Φ2, i.e., the falling edge of the inverting reference clock signal CLKX. Specifically, when signal S2 is at level H, the output signal S3 switches from the currently held level of signal S3 to its opposite level. When signal S2 is at level L, the output signal S3 maintains the currently held level of signal S3. The signal S3 output from the latch circuit 80C is transmitted to output terminal 12, control circuit 50, and knife switch 70. The operation of control circuit 50 is as described above.

[0185] Next, the electromagnetic switching characteristics of the magnetic switch 10C will be explained.

[0186] In magnetic switch 10C, not only does it switch the combination of driving current directions in the same way as magnetic switch 10A, but it also further switches the electromagnetic conversion characteristics after offsetting the offset when selecting the first direction pair according to signal S3, so that the polarity of the signal input to knife switch 70 is reversed or not reversed.

[0187] Figure 19 This is a schematic diagram illustrating the relationship between signals S1 and S3 and magnetic flux density Bin when the magnetic deflection of the horizontal Hall element 20 in the semiconductor device 1C is positive.

[0188] exist Figure 19 In the middle, the solid line L DP1S This shows the magnetic deflection B when the direction pair of the driving current is the first direction pair. OSDP It becomes a positive electromagnetic conversion characteristic. Solid line L DP2C This shows the magnetic deflection B when the direction pair of the driving current is the second direction pair. OSDP It becomes a negative electromagnetic conversion characteristic. (Dashed line BL) id1 This refers to the differential electromagnetic conversion characteristic obtained when the driving current is in the first direction pair, representing the electromagnetic conversion characteristics in the two directions. (Dashed line BL) id2It is the electromagnetic conversion characteristic obtained by taking the difference between the electromagnetic conversion characteristics in the two directions when the driving current is in the second direction pair. The blank arrows (1), (1a), (2), (3), (3a) and (4) represent the hysteresis trajectory of the electromagnetic conversion characteristic.

[0189] in addition, Figure 19 The electromagnetic conversion characteristics shown are an example under the following conditions: signal S3 is at level H and selects a third direction during the first period Φ1; signal S3 is at level H and selects a first direction during the second period Φ2; signal S3 is at level L and selects a fourth direction during the first period Φ1; signal S3 is at level L and selects a second direction during the second period Φ2. Furthermore, in this example, during the period when signal S3 is at level H, the knife switch 70 is in a direct-wire state as the first connection state. During the period when signal S3 is at level L, the knife switch 70 is in a cross-wiring state as the second connection state.

[0190] The magnetic switch 10C includes a knife switch 70, which allows the polarity of the signal input to the knife switch 70 to be reversed for output. Therefore, the solid line L... DP1S and the following Figure 20 The solid line L shown DP1C It becomes a line segment symmetrical with respect to the magnetic flux density Bin, which serves as the horizontal axis. Additionally, the solid line L... DP2C and the following Figure 20 The solid line L shown DP2S It becomes a line segment that is symmetrical with respect to the magnetic flux density Bin, which is the horizontal axis.

[0191] The blank arrow (1) indicates the situation when signal S3 is at level H and magnetic flux density Bin increases towards the S pole side, compared to the solid line L. DP1S The corresponding electromagnetic conversion characteristic trajectory. If the voltage input to SH comparator 40C, i.e., the voltage of signal S1, exceeds the reference voltage V. BOP (ΔV･G>V) BOP If ), then signal S3 will transition to the L level.

[0192] If signal S3 changes to the L level, the direction of the selected drive current switches to the second direction pair, thereby switching the knife switch 70 from the direct line state to the cross-connection state. Accompanying the level change of signal S3, from the solid line L... DP1S The corresponding trajectory on the electromagnetic conversion characteristic changes to correspond with the solid line L. DP2C The corresponding trajectory on the electromagnetic conversion characteristic (blank arrow (2)). Subsequently, as the magnetic flux density Bin further increases towards the S pole side, the voltage V moves along the solid line L. DP2C It increases further toward the negative side (blank arrow (3a)).

[0193] On the other hand, the trajectory of the magnetic flux density Bin when it decreases at the S pole, Bin=0, and then increases at the N pole is a blank arrow (3). Moreover, if the magnetic flux density Bin increases towards the N pole side, the voltage of the signal S1 exceeds the reference voltage V. BOP (ΔV･G>V) BOP If the signal S3 changes to the H level, then the signal S3 will change to the H level.

[0194] If signal S3 transitions to level H, the direction of the selected drive current switches to the first direction pair, thereby switching the knife switch 70 from the cross-connection state to the direct-line state. Accompanying the level transition of signal S3, from the solid line L... DP2C The corresponding trajectory on the electromagnetic conversion characteristic changes to correspond with the solid line L. DP1S The corresponding trajectory on the electromagnetic conversion characteristic (blank arrow (4)). Subsequently, as the magnetic flux density Bin further increases towards the N-pole side, the voltage V moves along the solid line L. DP1S Further increase towards the negative side (blank arrow (1a)). On the other hand, the trajectory of the magnetic flux density Bin when it decreases at the N pole, Bin=0, and then increases at the S pole is the blank arrow (1) mentioned above.

[0195] Figure 20 This is a schematic diagram illustrating the relationship between signals S1 and S3 and magnetic flux density Bin when the magnetic deflection of the horizontal Hall element 20 in the semiconductor device 1C is negative. Additionally, Figure 21 This is to part of Pa (refer to) Figure 20 (This is an enlarged view.)

[0196] exist Figure 20 In the middle, the solid line L DP1C This shows the magnetic deflection B when the direction pair of the driving current is the first direction pair. OSDP It becomes a positive electromagnetic conversion characteristic. Solid line L DP2S This shows the magnetic deflection B when the direction pair of the driving current is the second direction pair. OSDP It becomes a negative electromagnetic conversion characteristic. (Dashed line BL) id1 This refers to the differential electromagnetic conversion characteristic obtained when the driving current is in the first direction pair, representing the electromagnetic conversion characteristics in the two directions. (Dashed line BL) id2 It is the electromagnetic conversion characteristic obtained by taking the difference between the electromagnetic conversion characteristics in the two directions when the driving current is in the second direction pair. The blank arrows (1), (1a), (2), (3), (3a) and (4) represent the hysteresis trajectory of the electromagnetic conversion characteristic.

[0197] in addition, Figure 20The electromagnetic conversion characteristics shown are illustrated in the following examples: signal S3 is at level H and selects the fourth direction during the first period Φ1; signal S3 is at level H and selects the second direction during the second period Φ2; signal S3 is at level L and selects the third direction during the first period Φ1; signal S3 is at level L and selects the first direction during the second period Φ2. Furthermore, in this example, during the period when signal S3 is at level H, the knife switch 70 is in a direct-wire state as the first connection state. During the period when signal S3 is at level L, the knife switch 70 is in a cross-wiring state as the second connection state.

[0198] The blank arrow (1) indicates the situation when signal S3 is at level H and magnetic flux density Bin increases towards the S pole side, compared to the solid line L. DP2S The corresponding electromagnetic conversion characteristic trajectory. If the voltage input to SH comparator 40C, i.e., the voltage of signal S1, exceeds the reference voltage V. BOP (ΔV･G>V) BOP If ), then signal S3 will transition to the L level.

[0199] If signal S3 changes to level L, the direction of the selected drive current switches to the first direction pair, thereby switching the knife switch 70 from the direct line state to the cross-connection state. Along with the level change of signal S3, the direction of the selected drive current changes from the solid line L... DP2S The corresponding trajectory on the electromagnetic conversion characteristic changes to correspond with the solid line L. DP1C The corresponding trajectory on the electromagnetic conversion characteristic (blank arrow (2)). Subsequently, as the magnetic flux density Bin further increases towards the S pole side, the voltage V moves along the solid line L. DP1C Further increase towards the positive side (blank arrow (3a)).

[0200] On the other hand, the trajectory of the magnetic flux density Bin when it decreases at the S pole, Bin=0, and then increases at the N pole is a blank arrow (3). Moreover, if the magnetic flux density Bin increases towards the N pole side, the voltage of the signal S1 exceeds the reference voltage V. BOP (ΔV･G>V) BOP If the signal S3 changes to the H level, then the signal S3 will change to the H level.

[0201] If signal S3 transitions to level H, the direction of the selected drive current switches to the second direction pair, thereby switching the knife switch 70 from the cross-connection state to the direct-line state. Accompanying the level transition of signal S3, from the solid line L... DP1C The corresponding trajectory on the electromagnetic conversion characteristic changes to correspond with the solid line L. DP2S The corresponding electromagnetic conversion characteristic trajectory (blank arrow (4)).

[0202] Subsequently, as the magnetic flux density Bin further increases towards the N-pole side, the voltage V increases along the solid line L. DP2SFurther increasing towards the negative side (blank arrow (1a)). On the other hand, the trajectory of the magnetic flux density Bin when it decreases at the N pole, Bin=0, and then increases at the S pole is the aforementioned blank arrow (1). In this embodiment, the shape of the hysteresis trajectory in the electromagnetic conversion characteristic is figure-eight shaped. Accordingly, the shape of the hysteresis trajectory in the electromagnetic conversion characteristic of this embodiment is different from the shape of the hysteresis trajectory in the electromagnetic conversion characteristic of the first and second embodiments, i.e., the parallelogram shape.

[0203] In this embodiment, a reference voltage V can be applied, for example. BOP The electromagnetic switching characteristics are switched when a predetermined reference voltage is applied. Furthermore, in this embodiment, since the electromagnetic switching characteristics are switched when a reference voltage is applied, the magnetic switch 10C can be used with a reference voltage circuit 48 that has a smaller circuit specification than the reference voltage circuit 46. Therefore, the magnetic switch 10C can be configured to have a smaller circuit specification than the magnetic switches 10A and 10B.

[0204] According to this embodiment, the electromagnetic conversion characteristics are switched for a reference voltage and for a reference voltage V. BOP and reference voltage V BRP Compared to the first and second embodiments that use two reference voltages to switch the electromagnetic conversion characteristics, it is easier to suppress the deviation of the reference voltage, which is the cause of the asymmetry between the S and N poles. Furthermore, the reference voltage V of the magnetic switch 10C... BOP The deviation is compared to the two independent reference voltages V in magnetic switches 10A and 10B. BOP and reference voltage V BRP The deviation is suppressed to a greater extent. Therefore, according to this embodiment, electromagnetic switching characteristics with good symmetry between the S and N poles can be obtained.

[0205] Furthermore, the present invention is not limited to the original embodiments described above, and can be implemented in various ways other than the examples described above during the implementation stage. Various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, a delay element or buffer memory may also be provided to output the drive control signals Sd1 to Sd4 and the transmission control signals St1 and St2 with a predetermined time delay.

[0206] The semiconductor device 1C and magnetic switch 10C described above are examples of having a horizontal Hall element 20 as Hall elements. However, a vertical Hall element 60 can also be used instead of the horizontal Hall element 20, as in semiconductor device 1B and magnetic switch 10B. Furthermore, the knife switch 70 can be any other circuit with the same function. That is, in the magnetic switch 10C, a circuit can be used instead of the knife switch 70 that has the aforementioned differential input section, differential output section, switching section, and control terminal, and can switch the input signal to in-phase or out-of-phase output based on the signal S3 input from the control terminal.

[0207] For example, a switching circuit can be used instead of the knife switch 70, which is configured by connecting a switch that is turned on (short-circuited) or off (open-circuited) based on the signal S3 input from the control terminal in parallel with the signal transmission path. Compared with the magnetic switch 10C used with the knife switch 70, the magnetic switch 10C used with this switching circuit can suppress the series resistance component and obtain better noise characteristics. Therefore, if the above-described switching circuit is used instead of the knife switch 70, a magnetic switch 10C with electromagnetic switching characteristics with good reproducibility can be provided.

[0208] The magnetic switch 10C can also replace the knife switch 70 and the amplifier 30 without polarity reversal function, thus enabling the amplifier 30 to have polarity reversal function.

[0209] Furthermore, while the aforementioned magnetic switches 10A to 10C are alternating detection type magnetic switches, they can also be configured as two-pole detection type magnetic switches. When the magnetic switches 10A to 10C are configured as two-pole detection type magnetic switches, they can be configured such that they can switch the amplification rate of amplifier 30 or the amplification rate of amplifier 30 and the absolute value of the predetermined reference voltage of SH comparators 40A and 40C according to the signal level of signal S3.

[0210] The ability to switch the amplification rate of amplifier 30 or the amplification rate of amplifier 30 and the absolute value of the predetermined reference voltage of SH comparators 40A and 40C can be formed by, for example, logic circuits, switching circuits including switches that are turned on and off based on signal S3, or combinations of these circuits. Furthermore, when magnetic switches 10A to 10C are formed as bipolar detection type magnetic switches, even without managing the polarity of the combined magnets, the deviation in the inspection distance of the magnetic material inspection mechanism of the semiconductor device according to this embodiment can be reduced.

[0211] Furthermore, the aforementioned magnetic switches 10A to 10C can also be configured as so-called single-pole test type magnetic switches. A single-pole test type magnetic switch has an operating point B in either the S or N pole. OP and reset point B RPBoth magnetic switches. When magnetic switches 10A to 10C are configured as single-pole verification type magnetic switches, if a switching process for control logic is added during manufacturing, the operating point B can be adjusted. OP and reset point B RP So that it has an action point B at either the S or N pole. OP and reset point B RP both sides.

[0212] In the above embodiments, the horizontal Hall element 20 is illustrated by having electrodes 21 to 24 formed at the four corners of a square (for example, see reference). Figure 1 , 17 However, this is not a limitation. The horizontal Hall element 20 can be shaped such that at least the direction of the driving current can define the four directions described above (first to fourth). That is, in addition to a square, the horizontal Hall element 20 can also be formed in shapes such as a cross, octagon, or circle. Furthermore, the number of electrodes 21 to 24 can be four or more.

[0213] Furthermore, in the above embodiment, a vertical Hall element 60 having five electrodes 61 to 65, i.e., five terminals, is illustrated, but it is not limited to this. The vertical Hall element 60 may be configured such that at least the direction of the driving current can define the four directions described above, from the first to the fourth.

[0214] In the above embodiments, the logic circuit 57 is not limited to Figure 3 The illustrated logic operation elements and circuit configurations are not limited to any particular logic operation element or circuit configuration if the same logic operation result is obtained when the above-described input signals are input.

[0215] Furthermore, in the above embodiments, a switching circuit 58 for switching control logic patterns was described as an example of a device for switching control logic patterns, but the device for switching control logic patterns is not limited to this. For example, switches SL1a, SL2a, SL1b, SL2b, SL1c, and SL2c may also be mechanical switches, electronic switches such as transistors, or combinations of these switches.

[0216] Alternatively, switches SL1a, SL2a, SL1b, SL2b, SL1c, and SL2c can also be switches with control terminals. When switches SL1a, SL2a, SL1b, SL2b, SL1c, and SL2c that can open and close based on signals input from the control terminals are used, semiconductor devices and magnetic switches capable of automatically switching between a first control logic mode and a second control logic mode based on changes in the primary factors of interest can be constructed.

[0217] For example, taking the polarity of the voltage offset asymmetry of the Hall element as the primary factor of interest, the magnetic switches 10A-10C also include a detection circuit for detecting the polarity of the voltage offset asymmetry of the Hall element. The detection circuit outputs a signal based on the result of detecting the polarity of the voltage offset asymmetry of the Hall element. The magnetic switches are configured such that the signal output from the detection circuit is input to each control terminal of switches SL1a, SL2a, SL1b, SL2b, SL1c, and SL2c. The magnetic switches configured in this way and the semiconductor device equipped with these magnetic switches can switch the control logic mode to a first control logic mode or a second control logic mode according to the polarity of the voltage offset asymmetry of the Hall element.

[0218] Alternatively, it can be configured such that a circuit is provided to evaluate the absolute value of the voltage offset difference of the Hall element, and the amplification G of the amplifier 30 and the reference voltage V of the comparator 40A are corrected based on a signal showing the evaluation result of the circuit. BOP and reference voltage V BRP At least one of them. In this case, it is possible not only to make the magnetic deflection B on the electromagnetic switching characteristics... OS It becomes zero, and it can also suppress the magnetic deflection B due to the Hall element. OSDP The resulting action point B OP and reset point B RP Deviation from design value.

[0219] Furthermore, the device for switching control logic patterns may also be configured with: a control circuit that performs control actions according to the first control logic pattern; a second control circuit that performs control actions according to the second control logic pattern; and a control circuit selection switch that switches to one of the aforementioned control circuit and the aforementioned second control circuit.

[0220] For example, it will make Figure 3 The control circuit 50, which is configured with switches SL1a, SL1b, and SL1c "on" and switches SL2a, SL2b, and SL2c "off", serves as the control circuit for performing control actions according to the first control logic pattern. Furthermore, the control circuit 50 with switches SL1a, SL1b, and SL1c "off" and switches SL2a, SL2b, and SL2c "on" serves as the second control circuit. In this case, a control circuit selection switch connects the control circuit and the second control circuit in parallel. The circuit that serves as the destination of the input signal S3 and the origin of the output drive control signals Sd1 to Sd4 and the transmission control signals St1 and St2 can be configured to switch between functioning as the control circuit and the second control circuit.

[0221] In the above embodiment, the switching circuit 58 is provided in the control circuit 50, but it can also be formed as an independent circuit separate from the control circuit 50. In this case, the reference clock signal CLK and signal S3, whose signal levels are switched by the switching circuit 58, are input to the control circuit 50.

[0222] In the above embodiments, the horizontal Hall element 20 and the vertical Hall element 60 are described as single elements, but in order to suppress magnetic deflection B OSDP From the perspective of size, a configuration can also be adopted by connecting multiple Hall element units in parallel. Based on this configuration, the operating point B can be reduced. OP and reset point B RP The deviation from the design value. Therefore, magnetic switches 10A to 10C that use Hall elements composed of multiple Hall element units connected in parallel can achieve electromagnetic switching characteristics that are closer to the design value than magnetic switches 10A to 10C that are not composed of multiple Hall element units connected in parallel, i.e., have a Hall element as a single element.

[0223] Furthermore, when processing speed is a priority, the magnetic switches 10A to 10C, which are composed of Hall elements formed by connecting multiple Hall element units in parallel, can suppress the output resistance and time constant of the Hall element, thereby enabling a processing speed higher than that of the magnetic switches 10A to 10C, which are composed of a single element.

[0224] In the above embodiments, the case where the drive terminal 11P is connected to the first power supply and the drive terminal 11N is connected to the second power supply is described (that is, the case where the drive power supply for the magnetic switches 10A to 10C is a constant voltage source), but the drive power supply for the magnetic switches 10A to 10C can also be a constant current source.

[0225] When a constant voltage source is used as the driving power supply, since a constant current source circuit for driving is not required, the circuit specifications are smaller compared to the case where a constant current source is used as the driving power supply. Furthermore, when a constant current source is used as the driving power supply, the residual offset voltage of the Hall element is smaller compared to the case where a constant voltage source is used as the driving power supply.

[0226] Furthermore, in the above embodiments, the signal processing of magnetic switches 10A to 10C was described as voltage mode, but it is also possible to make part or all of the signal processing current mode. Current mode signal processing is faster than voltage mode signal processing, and therefore it is easier to increase the reference clock frequency compared to the case where voltage mode signal processing is used. Therefore, compared to magnetic switches 10A to 10C with voltage mode signal processing, magnetic switches 10A to 10C with current mode signal processing can further improve detection accuracy and signal processing speed.

[0227] In the above embodiments, an example configuration of magnetic switches 10A to 10C applicable to a differential input single-phase output amplifier 30 and single-phase input SH comparators 40A and 40C has been described. However, the amplifier 30 and SH comparators 40A and 40C are not limited to this example. Differential input output amplifiers 30 and differential input SH comparators 40A and 40C can also be applied to the magnetic switches 10A to 10C. In this case, magnetic switches 10A to 10C can be provided that are relatively robust against overlapping in-phase noise from the power supply, etc.

[0228] These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0229] [Symbol Explanation]

[0230] 1A~1C Semiconductor Devices

[0231] 2 Semiconductor substrate

[0232] 10A~10C magnetic switch

[0233] 20 Horizontal Hall Elements

[0234] Electrodes 21-24

[0235] 30 Amplifier

[0236] 40A, 40C SH comparators

[0237] 50 Control Circuit

[0238] 51a, 51b Input Terminals

[0239] 56a~56f Output terminals

[0240] 57 Logic Circuits (Control Signal Generation Circuits)

[0241] 58 Switching Circuit (Second Switching Circuit)

[0242] 60 Vertical Hall element

[0243] 70 Knife switch

[0244] 80A and 80C latch circuits

[0245] SP1~SP4, SN1~SN4 switches (first switching circuit)

[0246] Φ1, Φ2 First period, Second period

[0247] CLK reference clock signal

[0248] S3 signal (latch output signal).

Claims

1. A semiconductor device, characterized in that, It is a semiconductor device equipped with a magnetic switch mounted on a semiconductor substrate. The magnetic switch includes: A Hall element includes a first electrode and a second electrode arranged on a first straight line, and a third electrode and a fourth electrode arranged on a second straight line orthogonal to the first straight line; The first switching circuit has multiple switches configured to select one of four directions from the first electrode toward the second electrode, the second electrode toward the first electrode, the third electrode toward the fourth electrode, and the fourth electrode toward the third electrode. The comparison circuit alternately performs a first action of sampling the signal transmitted from the Hall element and a second action of outputting a result signal, which is a result signal based on a comparison of a reference value and the value of a differential signal of the signal transmitted from the Hall element with the signal sampled by the first action; A latching circuit that holds the result signal output from the comparison circuit and outputs the held signal as a latched output signal; as well as The control circuit is configured to select one of a first mode and a second mode based on the latched output signal. The first mode controls the opening and closing state of the switch by causing the drive current to flow in the third direction during a first period of performing the first action and by causing the drive current to flow in the first direction during a second period of performing the second action. The second mode controls the opening and closing state of the switch by causing the drive current to flow in the second direction during the first period and by causing the drive current to flow in the fourth direction during the second period.

2. The semiconductor device according to claim 1, characterized in that, The control circuit has: The first input terminal is input with the latched output signal; The second input terminal is input with a reference clock signal that has a period equal to the sum of the first period and the second period. A control signal generation circuit generates four control signals that are synchronized with the reference clock signal input from the second input terminal, based on the latched output signal input from the first input terminal. as well as The system includes a first control signal output terminal for outputting the first control signal, a second control signal output terminal for outputting the second control signal, a third control signal output terminal for outputting the third control signal, and a fourth control signal output terminal for outputting the fourth control signal.

3. The semiconductor device according to claim 1, characterized in that, The control circuit has: The first input terminal is input with the latched output signal; The second input terminal is input with a reference clock signal that has a period equal to the sum of the first period and the second period. A logic circuit comprising logic operation elements connected to the first input terminal and the second input terminal, and generating four control signals synchronized with the reference clock signal input from the second input terminal based on the latched output signal input from the first input terminal; as well as The system includes a first control signal output terminal for outputting the first control signal, a second control signal output terminal for outputting the second control signal, a third control signal output terminal for outputting the third control signal, and a fourth control signal output terminal for outputting the fourth control signal.

4. The semiconductor device according to claim 3, characterized in that, The logic circuit has a second switching circuit disposed between the first input terminal and the second input terminal and the logic operation element. The second switching circuit is configured to include a first path capable of switching between the first input terminal and the second input terminal and the logic operation element, and a second path different from the first path.

5. The semiconductor device according to claim 4, characterized in that, The control circuit, The configuration is as follows: based on the latched output signal input via the first path, a first control signal, a second control signal, a third control signal, and a fourth control signal are generated as four control signals synchronized with the reference clock signal input from the second input terminal; the first control signal is output from the first control signal output terminal; the second control signal is output from the second control signal output terminal; the third control signal is output from the third control signal output terminal; and the fourth control signal is output from the fourth control signal output terminal. The configuration is as follows: based on the latched output signal input via the second path, a fifth control signal, a sixth control signal, a seventh control signal, and an eighth control signal are generated as four control signals synchronized with the reference clock signal input from the second input terminal; the fifth control signal is output from the first control signal output terminal; the sixth control signal is output from the second control signal output terminal; the seventh control signal is output from the third control signal output terminal; and the eighth control signal is output from the fourth control signal output terminal.

6. The semiconductor device according to claim 2, characterized in that, It also has: The second control circuit has a first input terminal and a second input terminal, the control signal generation circuit and the first to fourth control signal output terminals, and is configured to select one of the first mode and the second mode relative to one mode based on the latched output signal; and The control circuit selection switch is configured to switch the terminal on which the latched output signal is input and the terminal on which the four control signals are output as either the first input terminal and the first to fourth control signal output terminals of the control circuit or the first input terminal and the first to fourth control signal output terminals of the second control circuit.

7. The semiconductor device according to claim 2, characterized in that, It also has: The first drive terminal is connected to the first power supply; and The second drive terminal is connected to the second power supply. The Hall element is connected to the first drive terminal and the second drive terminal respectively via the plurality of switches. The plurality of switches have: The first switch includes a control terminal that receives a control signal output from the first control signal output terminal and is capable of opening and closing the path between the first drive terminal and the first electrode. The second switch includes a control terminal that receives a control signal output from the first control signal output terminal and is capable of opening and closing the path between the second electrode and the second drive terminal. The third switch includes a control terminal that receives a control signal output from the second control signal output terminal and is capable of opening or closing the path between the first drive terminal and the third electrode. The fourth switch includes a control terminal that receives a control signal output from the second control signal output terminal and is capable of opening or closing the path between the fourth electrode and the second drive terminal. The fifth switch includes a control terminal that receives a control signal output from the third control signal output terminal and is capable of opening or closing the path between the first drive terminal and the second electrode. The sixth switch includes a control terminal that receives a control signal output from the third control signal output terminal and is capable of opening or closing the path between the first electrode and the second drive terminal. The seventh switch includes a control terminal that receives a control signal output from the fourth control signal output terminal and is capable of opening or closing the path between the first drive terminal and the fourth electrode. as well as The eighth switch includes a control terminal that receives a control signal output from the fourth control signal output terminal and is capable of opening or closing the path between the third electrode and the second drive terminal.

8. The semiconductor device according to claim 1, characterized in that, The comparator circuit has: A reference voltage circuit includes an output terminal that outputs a voltage selected from a first voltage and a second voltage different from the first voltage as the reference value; A sample-and-hold amplifier includes a first input terminal to which a signal transmitted from the Hall element is input, a second input terminal to which a reference clock signal is input with a period equal to the sum of the first period and the second period, and an output terminal to which the value of the differential signal between the signal sampled during the first period and the signal transmitted from the Hall element during the second period is output. as well as The comparator includes a first input terminal connected to the output of the sample-and-hold amplifier, a second input terminal connected to the output of the reference voltage circuit, and an output terminal for an output result signal, the result signal being a result signal based on a comparison of the value of a signal input from the first input terminal with the reference value input from the second input terminal.

9. The semiconductor device according to any one of claims 1 to 7, characterized in that, It also includes a knife switch having a first input terminal and a second input terminal, a first output terminal connected to the first input terminal via an openable and closable first path and connected to the second input terminal via an openable and closable second path, a second output terminal connected to the second input terminal via an openable and closable third path and connected to the second input terminal via an openable and closable fourth path, and a control terminal on which the latched output signal is input. The knife switch is configured to switch between a first connection state that closes the first path and the fourth path and disconnects the second path and the third path, and a second connection state that disconnects the first path and the fourth path and closes the second path and the third path, based on the latched output signal input from the control terminal. The knife switch is located in the preceding stage compared to the comparator circuit. The comparator circuit has: A sample-and-hold amplifier includes a reference voltage circuit that outputs a predetermined reference voltage, a first input terminal receiving a signal transmitted from the Hall element, a second input terminal receiving a reference clock signal with a period equal to the sum of the first period and the second period, and an output terminal that outputs the value of the differential signal between the signal sampled during the first period and the signal transmitted from the Hall element during the second period. and The comparator includes a first input terminal connected to the output of the sample-and-hold amplifier, a second input terminal connected to the output of the reference voltage circuit, and an output terminal for an output result signal, the result signal being a result signal based on a comparison of the value of a signal input from the first input terminal with the reference value input from the second input terminal.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that, The Hall element is either a horizontal Hall element that produces an output corresponding to a magnetic flux density perpendicular to the semiconductor substrate, or a vertical Hall element that produces an output corresponding to a magnetic flux density parallel to the semiconductor substrate.

11. The semiconductor device according to claim 9, characterized in that, The Hall element is either a horizontal Hall element that produces an output corresponding to a magnetic flux density perpendicular to the semiconductor substrate, or a vertical Hall element that produces an output corresponding to a magnetic flux density parallel to the semiconductor substrate.

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