Image sensor ramp signal generation circuit and its implementation method

Abstract

The present invention provides an image sensor ramp signal generation circuit and an implementation method thereof. The implementation method of the image sensor ramp signal generation circuit includes: providing a clock signal to drive cascaded state storage units, and realizing the step-by-step transmission of the switching signal of the control current source unit through the state storage units, so as to realize the accumulation or decrease of the output current, and thus realize the accumulation or decrease of the output current through the corresponding current source unit to form a ramp signal. In the image sensor ramp signal generation circuit and the implementation method thereof provided by the present invention, the ramp signal generation circuit does not require multiple high-frequency transmission lines to transmit high-frequency clock signals and digital code signals, and does not require decoding, and there will be no glitch problem caused by decoding errors, thereby improving the image quality.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular, to an image sensor ramp signal generation circuit and a method for implementing the same. Background Art

[0002] Since the CMOS process has the characteristic of high integration and can integrate the pixel part and the signal processing circuit part on a single chip, it is very suitable for implementing the image sensors in current popular mobile devices.

[0003] In a CMOS image sensor, as the scale of the pixel unit array continues to expand, the traditional chip-level analog-to-digital converter is either slow or has a relatively large area and power consumption, and can no longer meet the requirements of high frame rate, high pixel count, and low power consumption. Therefore, a column-level analog-to-digital converter is adopted for high frame rate, high pixel count, and low power consumption image sensors. Among them, the Single Slope Analog to Digital Converter (SSADC) has the characteristic of achieving high precision with only a small area and power consumption, and is widely used in high pixel count, high frame rate, and low power consumption image sensors.

[0004] In the SS ADC, a ramp signal is required as the comparison level of the comparator, and its accuracy directly affects the output accuracy of the SS ADC. Therefore, how to generate a high-precision ramp signal is a very important research topic.

[0005] In the existing ramp signal generation circuit, the current steering digital-to-analog converter (CSDAC) is widely used in high-speed and high-precision ramp signal generation circuits because its structure is more suitable for high-speed and high-precision characteristics.

[0006] The block diagram of the traditional CSDAC structure is as Figure 1 shown. The CSDAC usually consists of a group of current source arrays 20 and a corresponding switch array 30. The differential switch array 30 determines the current flow direction to the positive or negative output terminal according to the input digital code. A series of currents passing through the switch array 30 are summed up at the output terminal to finally obtain the required current, and the required voltage Vramp is generated after this current flows through the resistor R.

[0007] In the traditional CSDAC, at the control end of the switch array 30, a clock signal Dacclk and a digital code signal Din need to be input <n:0>To generate a signal for controlling the switch. When the required accuracy of the ramp signal Vramp is higher, the digital code signal Din input <n:0>The more; when the required speed is faster, the clock signal Dacclk and the digital code signal Din <n:0>The higher the frequency.

[0008] In high frame rate and high precision application scenarios, traditional CSDAC requires multiple high-speed transmission lines to transmit high-frequency clock signal Dacclk and digital code signal Din. <n:0>, they are easily affected by external factors (such as parasitic capacitance, parasitic resistance, voltage drop, mutual crosstalk, etc.), resulting in noise and other interferences in the output ramp signal, thus leading to a decline in image quality.

[0009] In addition, traditional CSDAC needs to decode digital codes, and the decoding results control the switching of current units. The decoding process is prone to generating glitches in the output ramp signal, which will also lead to a decline in image quality. Summary of the Invention

[0010] To solve the problem of the decline in image quality caused by traditional CSDAC in the prior art, the present invention provides a method for implementing a ramp signal generation circuit of an image sensor, including providing a clock signal to drive cascaded state storage units, and realizing the step-by-step transmission of the switching signal of the current source unit through the state storage units, so as to realize the accumulation or decrease of the output current at the output end through the corresponding current source units to form a ramp signal.

[0011] Preferably, when the currents of the current source units are the same, the generated ramp signal is a linear ramp signal; when the output current values of the current source units are different, a non-linear ramp signal is generated.

[0012] Preferably, the ramp signal is a completely linear ramp signal, a completely non-linear ramp signal, or a ramp signal in which stage linearity is connected to stage non-linearity.

[0013] Preferably, when the ramp signal generation circuit of the image sensor is working normally, only the clock signal flips, so that the generated ramp signal has fewer glitches.

[0014] Preferably, the state control signal controls the state of the state storage unit, and can set all the outputs of the state storage unit to 0 or 1, or perform step-by-step transmission of the output result according to the flip of the clock signal.

[0015] Preferably, all the cascaded state storage units are divided into N groups, including 1 group of state storage units in the enabled state and N - 1 groups of state storage units in the sleep state, so as to reduce the crosstalk of the image sensor and reduce the overall power consumption.

[0016] Preferably, each group of the state storage units includes M cascaded state storage units. When the state storage units numbered from N to N + M - 1 are working, the output of the state storage units in other groups is a fixed value and there is no clock signal flipping inside; where M is greater than or equal to 2.

[0017] Preferably, the state storage units correspond to the current source units one by one, and the switching signal of one or more current source units is controlled by controlling one or more of the state storage units.

[0018] Preferably, the sizes of the current source units are the same as each other, different from each other, partially the same or partially different.

[0019] Preferably, when the output current values of the current units are partially the same and partially different, the generated ramp signal is a ramp signal that is connected by stagewise linearity and stagewise non-linearity.

[0020] Preferably, any shape and slope of the non-linear ramp signal are achieved by controlling the switching signals of the current source units with different current magnitudes.

[0021] Preferably, one or more current source units are simultaneously controlled to be turned on to achieve the accumulation or decrement of the ramp signal at different rates.

[0022] The present invention also provides a ramp signal generation circuit, which includes at least one current source unit and a state storage unit, and the current source units are connected in parallel with each other;

[0023] The state storage unit levels correspond one-to-one with the current source units and are connected in cascade. The state storage unit is adapted to control the step-by-step transmission of the switching signal of the current source under the drive of a clock signal, so as to achieve the accumulation or decrement of the current at the output end and generate a ramp signal.

[0024] Preferably, further included is: a differential switch group controlled by the state storage unit is arranged between the current source unit and the state storage unit, and the differential switch group is respectively connected to the output of the state storage unit and its inverted differential output.

[0025] Preferably, adjacent state storage units are respectively input with differential clock signals or the same clock signal.

[0026] Preferably, all the cascaded state storage units are divided into N groups, including 1 group of state storage units in the enabled state and N - 1 groups of state storage units in the sleep state.

[0027] Preferably, each group of the state storage units includes M state storage units connected in cascade. When the state storage units numbered from N to N + M - 1 work, the state storage units of other groups output fixed values and there is no internal clock signal flipping; where M is greater than or equal to 2.

[0028] Preferably, the sizes of the current source units are the same as each other or different from each other.

[0029] In the image sensor ramp signal generation circuit and its implementation method provided by the present invention, the ramp signal generation circuit does not require multiple high-frequency transmission lines to transmit high-frequency clock signals and digital code signals, and does not require decoding, so there will be no glitch problem caused by decoding errors, thereby improving the image quality. Description of the Drawings

[0030] Other features, objects, and advantages of the present invention will become more apparent by referring to the following detailed description of non-limiting embodiments read in conjunction with the accompanying drawings.

[0031] Figure 1 It is a circuit diagram of a current-steering architecture digital-to-analog converter in the prior art;

[0032] Figure 2 It is a circuit diagram of the ramp signal generation circuit in Embodiment 1 provided by the present invention;

[0033] Figure 3 and Figure 4 It is a schematic diagram of the ramp signal in Embodiment 2 provided by the present invention;

[0034] Figure 5 It is a circuit diagram of the ramp signal generation circuit in Embodiment 3 provided by the present invention.

[0035] In the figures, throughout the different views, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Embodiments

[0036] In the following detailed description of the preferred embodiments, reference will be made to the accompanying drawings which form a part of the present invention. The accompanying drawings illustrate, by way of example, specific embodiments that can be implemented in accordance with the present invention. The example embodiments are not intended to be exhaustive. All embodiments in accordance with the present invention are understood. It is understood that other embodiments may be utilized and structural or logical modifications may be made without departing from the scope of the present invention. Therefore, the following detailed description is not restrictive, and the scope of the present invention is defined by the appended claims.

[0037] The present invention provides an implementation method of an image sensor ramp signal generation circuit, including providing a clock signal to drive a cascaded state storage unit, and realizing the step-by-step transmission of the switching signal of the control current source unit through the state storage unit, so as to realize the accumulation or decrease of the output current to generate a ramp signal.

[0038] The following specifically describes the content of the present invention in conjunction with specific embodiments.

[0039] Embodiment 1

[0040] In this embodiment, referring to Figure 2 as shown, Figure 2 A ramp signal generation circuit is provided. A plurality of state storage units 401 are cascaded in sequence. The input of the first-stage state storage unit 401 is a high level or a low level (i.e., the power supply level or the ground level), and the input of each subsequent stage of the state storage unit 401 is the output of the previous-stage state storage unit 401.

[0041] Specifically, the ramp signal generation circuit is suitable for being applied to an image sensor, and includes at least one current source unit 201, and the current source units are connected in parallel with each other;

[0042] State storage units 401 that are in one-to-one correspondence with the current source units 201 and are cascaded;

[0043] The state storage unit 401 is suitable for controlling the step-by-step transmission of the switching signals of the current source unit 201 under the drive of a clock signal (dacclk and its opposite signal dacclkb), so as to realize the accumulation or decrease of the output current, and generate a ramp signal Vramp1.

[0044] Preferably, by controlling one or more of the state storage units 401, the switching signals of one or more of the current source units 201 are controlled.

[0045] Specifically, in this embodiment, the ramp signal generation circuit further includes: a differential switch group 301 controlled by the state storage unit 401 is arranged between the current source unit 201 and the state storage unit 401, and the differential switch group 301 is respectively connected to the output of the state storage unit 401 and its inverted differential output.

[0046] In this embodiment, adjacent state storage units 401 respectively input differential clock signals, or the same clock signal.

[0047] When the state storage unit 401 detects the change edge of the differentially input clock signal (dacclk and its opposite signal dacclkb), it transmits the input level to the output end. The state control signal controls the working state of the state storage unit 401, and the state storage unit 401 can be reset (all outputs are set to 0 or all outputs are set to 1), or the state storage unit 401 can be flipped according to the clock signal (dacclk and its opposite signal dacclkb) to perform step-by-step transmission of the output result. The level at the output end can be used to control the switch array 301 to select to turn on or off the current source unit 201. When the current source unit 201 is turned on (or off) in sequence, the ramp signal Vramp1 can be generated.

[0048] In this embodiment, when the ramp signal generation circuit of the image sensor operates normally, only the clock signal flips, so that the generated ramp signal has less glitches. The ramp signal generation circuit does not require multiple high-frequency transmission lines to transmit high-frequency clock signals and digital code signals, and does not require decoding, thus avoiding the glitch problem caused by decoding errors, and improving the image quality.

[0049] Embodiment Two

[0050] In Figure 2 In the shown ramp signal generation circuit, the magnitudes of the current source units 201 are the same as each other or different from each other.

[0051] When the weights of each current unit 201 in the current source array are the same, the generated ramp signal Vramp1 is a linear ramp signal; when the weights of each current unit 201 in the current source array are different, the generated ramp signal Vramp1 is a non-linear ramp signal.

[0052] As Figure 3 shown, it is a schematic diagram of a linear ramp signal and a non-linear ramp signal. In the linear ramp signal, the height of each step is equal; in the non-linear ramp signal, the height of the steps is not necessarily equal.

[0053] As Figure 4 shown, in some application scenarios of image sensors, the required ramp signal is a ramp signal formed by connecting a linear stage and a non-linear stage.

[0054] Preferably, the arbitrary shape and slope of the non-linear ramp signal are realized by controlling the switching signals of the current source units with different current magnitudes.

[0055] Preferably, one or more current source units are simultaneously controlled to enable the cumulative addition or subtraction of the ramp signal at different rates.

[0056] The non-linear ramp signal can greatly shorten the time required for the ramp signal to cover the entire amplitude range. In this way, the time of the analog-to-digital conversion process of converting the pixel output voltage signal into a digital signal in the image sensor can be significantly shortened. Therefore, using the non-linear ramp signal can better adapt to high-speed application scenarios.

[0057] Embodiment Three

[0058] In this embodiment, all the cascaded state storage units are divided into N groups, including 1 group of state storage units in the enabled state and N - 1 groups of state storage units in the sleep state, so as to reduce the crosstalk of the image sensor and lower the overall power consumption.

[0059] Preferably, each group of the state storage units includes M state storage units connected in cascade. When the state storage units numbered from N to N+M-1 are working, the state storage units of other groups output fixed values and there is no clock signal toggling inside. Herein, M is greater than or equal to 2.

[0060] With such a setting, the entire digital-to-analog ramp signal generator is divided into several parts. When one part is working, the other parts are not working, thus avoiding mutual interference and saving power consumption.

[0061] The cascaded state storage units are divided into multiple groups of cascaded state storage unit groups. The number of state storage units included in the state storage unit group only needs to be greater than 1. For example, the typical value can be set to 31. When the output signal of the last state storage unit of the state storage unit group toggles, a control signal is generated simultaneously to turn off the clock signal of this state storage unit group. That is, when all the current sources corresponding to all the state storage units of this state storage unit group have been turned on (or off), the clock signal of this group will be turned off and will no longer work.

[0062] In this embodiment, the ramp signal generation circuit does not require multiple high-frequency transmission lines to transmit high-frequency clock signals and digital code signals, and does not require decoding, thus avoiding the glitch problem caused by decoding errors, thereby improving the image quality. In addition, only some state storage units are working in the same time period, which can reduce noise, improve the image quality, and save power consumption at the same time.

[0063] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any case, the embodiments should be regarded as exemplary and non-limiting. In addition, obviously, the word "including" does not exclude other elements and steps, and the term "one" does not exclude a plurality. Multiple elements stated in the apparatus claims can also be implemented by one element. The words such as first and second are used to represent names and do not represent any specific order.

Claims

1. A method for implementing an image sensor ramp signal generation circuit, characterized in that, Including: Providing a clock signal to drive cascaded state storage units, and realizing the step-by-step transmission of the switching signal for controlling the current source unit through the state storage units, so as to realize the accumulation or decrease of the output current through the corresponding current source unit to form a ramp signal.

2. The implementation method of the image sensor ramp signal generation circuit according to claim 1, wherein When the currents of the current source units are of the same magnitude, the generated ramp signal is a linear ramp signal; when the output current values of the current source units are different, a non-linear ramp signal is generated.

3. The implementation method of the image sensor ramp signal generation circuit according to claim 1 or 2, wherein the ramp signal is a completely linear ramp signal, a completely non-linear ramp signal, or a ramp signal in which the stage linearity is connected to the stage non-linearity.

4. The implementation method of the image sensor ramp signal generation circuit according to claim 1, wherein When the image sensor ramp signal generation circuit is working properly, only the clock signal flips, so that the generated ramp signal has less glitches.

5. The implementation method of the image sensor ramp signal generation circuit according to claim 1, characterized in that The state control signal controls the states of the state storage units, and can set all the outputs of the state storage units to 0 or 1, or perform step-by-step transmission of the output results according to the flip of the clock signal.

6. The implementation method of the image sensor ramp signal generation circuit according to claim 1, characterized in that All the cascaded state storage units are divided into N groups, including 1 group of state storage units in the enabled state and N - 1 groups of state storage units in the sleep state, so as to reduce the crosstalk of the image sensor and reduce the overall power consumption.

7. The implementation method of the image sensor ramp signal generation circuit according to claim 4, characterized in that, Each group of the state storage units includes M cascaded state storage units. When the state storage units numbered from N to N + M - 1 work, the output of the state storage units in other groups is a fixed value and there is no clock signal flipping inside; where M is greater than or equal to 2.

8. The implementation method of the image sensor ramp signal generation circuit according to claim 1, characterized in that, The state storage units correspond to the current source units one by one, and the switching signal for controlling one or more current source units is realized by controlling one or more of the state storage units.

9. The implementation method of the image sensor ramp signal generation circuit according to claim 1, characterized in that, The magnitudes of the current source units are the same as each other, different from each other, partially the same or partially different.

10. The implementation method of the image sensor ramp signal generation circuit according to claim 9, characterized in that, When the output current values of the current source units are partially the same and partially different, the generated ramp signal is a ramp signal in which the stage linearity is connected to the stage non-linearity.

11. The implementation method of the image sensor ramp signal generation circuit according to claim 9, wherein Arbitrary shapes and slopes of non-linear ramp signals are realized by controlling the switching signals of the current source units with different current magnitudes.

12. The implementation method of the image sensor ramp signal generation circuit according to claim 1, characterized in that, One or more current source units are simultaneously controlled to be turned on to realize the accumulation or decrease of the ramp signal at different rates.

13. A ramp signal generation circuit, characterized in that The ramp signal generation circuit includes at least one current source unit and a state storage unit; The current source units are connected in parallel with each other; The state storage units correspond to the current source units one by one, and the state storage units are connected in cascade. The state storage units are adapted to control the step-by-step transmission of the switching signal of the current source under the drive of the clock signal, so as to realize the accumulation or decrease of the output current to generate a ramp signal.

14. The ramp signal generation circuit according to claim 13, wherein Further including: A differential switch group controlled by the state storage unit is arranged between the current source unit and the state storage unit, and the differential switch group is respectively connected to the output of the state storage unit and its inverted differential output.

15. The ramp signal generation circuit according to claim 13, characterized in that, Adjacent state storage units respectively input differential clock signals, or the same clock signal.

16. The ramp signal generation circuit according to claim 13, wherein All the cascaded state storage units are divided into N groups, including one group of enabled state storage units and N - 1 groups of dormant state storage units.

17. The ramp signal generation circuit according to claim 16, wherein, Each group of the state storage units contains M cascaded state storage units. When the state storage units numbered from N to N + M - 1 are working, the state storage units of other groups output fixed values and there is no internal clock signal toggling; where M is greater than or equal to 2.

18. The ramp signal generation circuit according to claim 13, wherein, The sizes of the current source units are the same as each other or different from each other.

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