Multicore systems and methods for operating cores

Abstract

A system includes multiple cores. Each core includes a processing unit, an on-chip memory (OCM), and an idle detector unit. Data is received and stored in the OCM. Instructions are received to process the data in the OCM. If the idle detector unit detects that the core has been idle for a first number of clock signals, the core enters an idle mode. While in idle mode, the core receives a pending command and transitions from idle mode to operating mode. A number of No-Op commands are inserted within each time segment. No-Op commands prevent the core from processing instructions for a certain number of clock signals. The number of No-Op commands inserted in the first time segment is greater than the number inserted in the last time segment. No No-Op commands are inserted after the last time segment.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 62 / 971,650, filed February 7, 2020, the entire contents of which are incorporated herein by reference. Background Technology

[0003] In recent years, especially given technologies such as artificial intelligence (AI) and machine learning (ML), the use of multi-core systems has become widespread. It should be understood that each core within a multi-core system comprises various components, such as on-chip memory, one or more processing units, and / or logic circuitry. When multiple cores transition from idle mode to full operation, a large number of components within those cores (e.g., logic circuitry and on-chip memory) simultaneously turn on, resulting in a sudden power surge over a short period. A sudden power surge can be characterized as Di / Dt, which is a sudden increase in current over a short time. It should be understood that throughout this application, Di / Dt is referred to as a power surge. Unfortunately, it is difficult to mitigate such sudden power surges over a short period. Traditionally, large-capacity capacitors have been used on chips, but the types of large-capacity capacitors that can be used may be limited by the actual implementation of the chip design. Moreover, if the capacitance is not large enough, the voltage supply may drop significantly, impacting system performance.

[0004] The foregoing examples and related limitations of the relevant art are intended to be illustrative rather than exclusive. Further limitations of the relevant art will become apparent after reading the specification and studying the accompanying drawings. Summary of the Invention

[0005] This application provides a multi-core system, including: a first core, comprising a first processing unit, a first on-chip memory (OCM), and a first idle detector unit, wherein the first core is configured to: receive data and store the received data in the first OCM, and is further configured to receive instructions to process the data stored in the first OCM based on the received instructions; if the first idle detector unit detects that the first core has been idle for a first number of clock signals, it enters an idle mode; while in the idle mode, it receives a first pending command; and in response to receiving the first pending command, it transitions from the idle mode to an operating mode, wherein a plurality of non-operational No-Op commands are inserted in each of a first plurality of time segments, wherein the No-Op commands prevent the first core from processing instructions for a certain number of clock signals, wherein each of the first plurality of time segments corresponds to a second number of clock signals, and wherein the number of No-Op commands inserted in the first time segment of the first plurality of time segments is greater than the number of No-Op commands inserted in the last time segment of the first plurality of time segments, and wherein in the first plurality of time segments... The number of No-Op commands inserted after the last time segment in the time segment is zero; and a second core, including a second processing unit, a second OCM, and a second idle detector unit, wherein the second core is configured to: receive data and store the received data in the second OCM, and is also configured to receive instructions to process the data stored in the second OCM based on the received instructions; if the second idle detector unit detects that the second core has been idle for a third number of clock signals, it enters an idle mode; while in the idle mode, it receives a second pending command; and in response to receiving the second pending command, it transitions from the idle mode to an operating mode, wherein a plurality of No-Op commands are inserted in each of the second plurality of time segments, wherein the No-Op commands prevent the second core from processing instructions for another specific number of clock signals, wherein each of the second plurality of time segments corresponds to a fourth number of clock signals, and wherein the number of No-Op commands inserted in the first time segment of the second plurality of time segments is greater than the number of No-Op commands inserted in the last time segment of the second plurality of time segments. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of this disclosure can be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1An example diagram of a hardware-based architecture for transitioning idle cores to operating mode in a multi-core system, according to one aspect of this embodiment, is depicted.

[0008] Figure 2 A non-limiting example is described in which a core in a multi-core system according to one aspect of this embodiment enters an idle mode and transitions to an operating mode.

[0009] Figures 3A to 3B A clock signal is described for the operation of a core entering an idle mode and transitioning from an idle mode to an operating mode in a multi-core system according to one aspect of this embodiment.

[0010] Figure 4 A power throttling process during the transition from idle mode to operating mode in a multi-core system is described according to one aspect of this embodiment.

[0011] Figure 5 A flowchart depicts a non-limiting example of a core in a multi-core system according to one aspect of this embodiment entering an idle mode and transitioning from an idle mode to an operating mode. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of this subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Before providing a more detailed description of the various embodiments, it should be understood that these embodiments are not limiting, as elements in such embodiments can vary. It should also be understood that the particular embodiments described and / or illustrated herein have elements that can be readily separated from the particular embodiments and can optionally be combined with or substituted for any of the other embodiments described herein. It should also be understood that the terminology used herein is for the purpose of describing certain concepts and is not intended to be limiting. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood in the art to which the embodiments pertain.

[0014] A novel system and method for transitioning cores in a multi-core system from an idle state to an operational state are disclosed. It should be understood that an idle mode or state of a core can refer to a period of time during which the core is inactive and not processing data, while an operational state or mode refers to a period of time during which the core is active and processing data. It should be understood that the terms inactive, idle, and not processing are used interchangeably throughout the application. Generally, if a core is idle for a period of time, any core in the multi-core system can enter an idle mode (independent of other cores in the multi-core system). If multiple cores transition from idle mode to full operational mode (i.e., maximum performance) in a short period, a sudden power surge may occur. Thus, a core is transitioned from idle mode to operational mode in such a way that the core gradually becomes fully operational over time, thereby preventing a sudden power surge. In other words, the performance of the core transitioning from idle mode to operational mode is throttled, thereby reducing power consumption. In some embodiments, performance throttling is achieved by inserting several non-operational (No-Op) commands between the actual commands and instructions to be executed by the core. No-Op commands prevent the kernel from processing actual commands and instructions within a certain time period. For example, a No-Op command might prevent the kernel from processing within one clock cycle, or it might prevent it from processing within three clock cycles. Over time, the number of inserted No-Op commands decreases, gradually transitioning the kernel from idle mode to full operating mode.

[0015] Figure 1 Examples of diagrams illustrating a hardware-based architecture for transitioning idle cores to operating mode in a multi-core system, according to one aspect of this embodiment. Although these diagrams depict components as functionally independent, this depiction is for illustrative purposes only. It will be apparent that the components depicted in the diagrams can be arbitrarily combined or divided into individual software components, firmware components, and / or hardware components. Furthermore, it will also be apparent that regardless of how these components are combined or divided, they can execute on the same host or multiple hosts, and that these multiple hosts can be connected via one or more networks.

[0016] exist Figure 1 In one example, an architecture includes a multi-core system 100 comprising cores 101 to 164. Each of these components in the architecture is a dedicated hardware block / component that can be programmed by a user on a host (not shown) via software instructions that operate in various ways. When the software instructions are executed, each of the hardware components becomes a dedicated hardware component for implementing certain machine learning functions. In some embodiments, the multi-core system 100 resides on a single chip (e.g., a system-on-a-chip (SoC)).

[0017] exist Figure 1In the example, the multi-core system 100 includes multiple cores 101 to 164 typically arranged in multiple rows and columns. In this non-limiting example, the multi-core system 100 includes cores 101 to 108 in its first row, cores 109 to 116 in its second row, cores 117 to 124 in its third row, cores 125 to 132 in its fourth row, cores 133 to 140 in its fifth row, cores 141 to 148 in its sixth row, cores 149 to 156 in its seventh row, and cores 157 to 164 in its eighth row. It should be understood that embodiments with respect to 64 cores arranged in 8 rows × 8 columns have been described for illustrative purposes only, and these embodiments should not be construed as limiting the scope of the embodiments. For example, any number of cores and any number of rows / columns can be used. It should be understood that cores 101 to 164 can be configured to process data, for example, in an inference engine for ML or AI.

[0018] It should be understood that, as a non-limiting example, a sudden power surge could occur if cores 101 through 164 are idle and become operational at the same time or approximately the same time. It should be understood that, to prevent sudden power surges caused by simultaneously transitioning idle cores to operational mode, idle cores transition gradually from their idle mode to operational mode. In some non-limiting examples, this gradual transition is achieved by inserting several No-Op commands within the actual commands used by the idle cores transitioning to operational mode. The number of No-Op commands decreases over time, thus gradually transitioning the idle cores to operational mode, throttling their performance when exiting idle mode and gradually improving their performance over time.

[0019] It should be understood that in some embodiments, each core of the multi-core system 100 receives a clock signal 183. If a core is idle for a period of time, for example, when it is in an idle state and does not perform any processing for 8, 9, 10 clock cycles, etc., as non-limiting examples, then the core enters an idle mode. It should be understood that the amount of time a core remains idle before entering an idle mode, for a multi-core system or on a per-core basis, can be programmed by the user. In other words, if each core 101 to 164 remains idle / inactive for a period of time (e.g., t1 of 8, 9, 10, 11, 12, or any number of clock cycles), it can enter an idle mode. As a non-limiting and illustrative example, if core 101 remains inactive for a period of time t1, this period of time may or may not coincide with, or coincide with, another core such as core 155 entering an idle mode due to inactivity during the t1 period. It should be understood that each core can be programmed independently of the other cores in the multi-core system 100 (in some embodiments, it is user-programmable) and has a different time period before entering idle mode. For example, with different t1 and t2, core 101 may enter idle mode due to inactivity during time period t1, while core 143 may enter idle mode due to inactivity during time period t2.

[0020] Once in idle mode, the idle core can receive commands to be executed. It should be understood that the terms command / instruction are used interchangeably throughout the application. For illustrative purposes, it is only assumed that core 101 is in idle mode. Core 101 can receive one or more commands to be executed. Thus, a signal can be triggered to wake core 101. In some non-limiting examples, core 101 gradually transitions from idle mode to operating mode (full performance). In some embodiments, No-Op commands are inserted within the instructions to be executed by core 101 to gradually transition core 101 to full-performance operating mode. In some non-limiting examples, the number of No-Op commands initially inserted decreases over time to gradually improve performance and prevent sudden power surges. It should be understood that No-Op commands keep the core inactive for a period of time (e.g., one clock cycle). Thus, inserting four No-Op commands for each instruction / command to be processed by the core results in the core operating at 20% performance. Over time, reducing the number of No-Op commands leads to improved performance. For example, inserting two No-Op commands for three instructions / commands results in a 60% performance improvement, until eventually no No-Op commands are inserted to achieve 100% performance.

[0021] Figure 2A non-limiting example is depicted of a core 101 in a multi-core system according to one aspect of this embodiment entering an idle mode and transitioning to an operating mode. Core 101 may include a processing unit 210, an on-chip memory (OCM) 220, and an idle detector 230. In some non-limiting examples, the OCM 220 receives input data 218 and stores the received data. In some embodiments, the processing unit 210 receives instructions / commands 208 and processes the data stored in the OCM 220 based on the received instructions / commands 208. It should be understood that core 101 receives a clock signal 183. For non-limiting examples, the processing unit 210, the OCM 220, and the idle detector 230 may each receive the clock signal 183. It should be understood that in one non-limiting example, the processed data may be stored in the OCM 220. Core 101 may output the processed data as output data 235. Idle detector 230 can receive clock signal 183 and determine whether core 101 (in some non-limiting examples, processing unit 210) is idle / inactive for a period of time (which may be user-programmable). For illustrative purposes only, it is assumed that if core 101 (in some non-limiting examples, processing unit 210) is idle / inactive for, for example, 8 clock cycles, it has been programmed to enter idle mode. Idle detector 230 receives clock signal 183 and determines whether processing unit 210 is active or inactive. If core 101 (which is processing unit 210 in this non-limiting example) has been inactive for 8 cycles, core 101 enters idle mode. In some non-limiting examples, idle detector 230 uses counter 232 to determine whether core 101 should enter idle mode. For one non-limiting example, counter 232 can be reset for each clock cycle of clock signal 183 for which processing unit 210 is active. However, counter 232 is incremented for each clock cycle of clock signal 183 for which processing unit 210 is inactive / idle. If the value stored in counter 232 reaches 8 cycles, then idle detector 230 determines that core 101 should enter idle mode.

[0022] Once in idle mode, core 101 can receive command 208 to wake it up. In some embodiments, to gradually transition core 101 from idle mode to operating mode (full performance), a number of No-Op commands are inserted between actual commands to be processed by processing unit 210. As an illustrative example, in the first 5 clock cycles (also called a time slice), 4 No-Op commands and 1 actual command to be processed are inserted. In the next 5 clock cycles (i.e., 6 to 10 clock cycles), the number of inserted No-Op commands can be reduced or kept the same as in the first 5 clock cycles. For a non-limiting example, 3 No-Op commands can be inserted for 2 actual commands to be processed. Similarly, in each subsequent time slice, the number of No-Op commands is maintained or reduced until no other No-Op commands are inserted and core 101 reaches full performance (i.e., 100% performance). As a non-limiting example, for the three pending actual commands in the next time slice (i.e., clock cycles 11 to 15), two No-Op commands are inserted; for the four pending actual commands in the next time slice (i.e., clock cycles 16 to 20), one No-Op command is inserted; finally, no No-Op commands are inserted in subsequent time slices (i.e., after clock cycle 21). It should be understood that if core 101 remains inactive / idle for the programmed amount of time, it can transition back to idle mode. It should be understood that No-Op commands can be inserted by the core itself or by a controller external to the core.

[0023] It should be understood that, as described above, the operation of the other cores in the multi-core system 100 is similar to that of core 101. It should also be understood that the amount of time a core is idle / inactive (i.e., the time period) before entering idle mode can be programmable (in some non-limiting examples, user-programmable) and can be independent of the other cores in the multi-core system. It should also be understood that each core can be programmed to transition from idle mode to operating mode independently of the other cores; for example, one core can be programmed with a throttling scheme to transition from 0% performance to 20%, 40%, 60%, 80%, 100%, while another core can be programmed to transition from 0% to 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, 100%. In other words, the operations described above regarding the amount of time before entering idle mode and the number of No-Op commands used to control throttling can be programmed based on a multi-core system or a single core.

[0024] Figures 3A to 3BAn example of clock signals is described for the operation of a core entering an idle mode and transitioning from an idle mode to an operating mode in a multi-core system according to one aspect of this embodiment. In a non-limiting example, the core receives a command designated OP 301 at the first clock signal. Thus, the counter does not increment and remains at 0. At the second clock pulse, no command is received (i.e., idle 302), and the counter value increments to 1. At the third clock pulse of the clock signal, OP 303 is received, thereby resetting the counter. At the fourth to eleventh clock pulses of the clock signal, the core remains idle, as shown in idle 305 to 311. Therefore, for each clock pulse for which the core remains idle / inactive, the counter value increments. Thus, the counter value reaches 8. In this non-limiting example, if the core remains inactive / idle for 8 clock cycles, the core enters an idle mode. Thus, the core enters an idle mode.

[0025] Now, for reference Figure 3B When the core is in idle mode, it receives OP 312 and is thus woken up. To prevent sudden power surges, the performance of the core entering operating mode is throttled. In this non-limiting example, the core transitions to operating mode with a 25% performance increment. Therefore, at time slice 332, which includes four clock cycles, three No-Op commands are inserted for one actual command. In other words, No-Op commands 313 to 315 are inserted for the OP 312 command within time slice 332. Thus, a 25% performance improvement is achieved at time slice 332. In contrast, at time slice 334, which includes four clock cycles, two No-Op commands are inserted for two actual commands. In other words, No-Op commands 317 and 319 are inserted for the OP 316 and 318 commands. Thus, a 50% performance improvement is achieved at time slice 334. It should be understood that a No-Op command can be inserted anywhere within a time slice (e.g., it can be at the beginning of the slice, at the end of the slice, interleaved with actual commands, etc.). At time slice 336, which comprises four clock cycles, a No-Op command 323 is inserted for the three actual commands OP 320 through 322. Thus, at time slice 336, 75% performance is achieved. It should be understood that no No-Op commands are inserted in subsequent time slices, resulting in 100% performance. As illustrated in this non-limiting example, the core transitions from idle mode to an operating mode with 100% performance within 12 clock cycles, thus preventing sudden power surges. It should be understood that once no No-Op command is inserted, the core's counter can be reset to 0, and as described above, the core's counter only tracks when the core should transition back to idle mode.

[0026] Figure 4An example of power throttling during the transition from idle mode to operating mode in a multi-core system according to one aspect of this embodiment is depicted. In this non-limiting example, the core in idle mode transitions to operating mode after 70 clock cycles and achieves 100% performance. In this example, for one OP command 414, nine No-Op commands 412 are inserted at time slice 410 spanning ten clock cycles, thereby achieving a 10% performance improvement. At time slice 420 immediately following time slice 410, eight No-Op commands are inserted for two OP commands. For a non-limiting example, for two OP commands 426, No-Op commands 422 and 424 are inserted, thereby achieving a 20% performance improvement. At time slice 430 immediately following time slice 420, seven No-Op commands are inserted for three OP commands. For a non-limiting example, for OP command 436, No-Op commands 432 and 434 are inserted, thereby achieving a 30% performance improvement. At time segment 440, immediately following time segment 430, seven No-Op commands are inserted for three OP commands. In other words, the number of No-Op commands is the same as in the previous time segment, thus maintaining performance at 30%. At time segment 450, immediately following time segment 440, four No-Op commands are inserted for six OP commands. For example, for OP command 456, No-Op commands 452 and 454 are inserted, achieving 60% performance. At time segment 460, immediately following time segment 450, two No-Op commands are inserted for eight OP commands. For example, for OP command 466, No-Op commands 462 and 464 are inserted, achieving 80% performance. At time segment 470, immediately following time segment 460, one No-Op command is inserted for nine OP commands. For a non-limiting example, for OP command 476, No-Op command 474 is inserted, achieving 90% performance. It should be understood that in the non-restrictive example illustrated, no No-Op command is inserted after time segment 470, thus achieving 100% performance. For a non-restrictive example, regarding OP command 486, no No-Op command is inserted at time segment 480.

[0027] Therefore, as illustrated, the core transitions from idle mode to operating mode, during which its performance is throttled to prevent sudden power surges. It should also be understood that this throttling can be implemented, allowing performance to increase gradually. It should also be understood that, as illustrated, the number of No-Op commands decreases or remains constant from its previous time slice until 100% performance is achieved.

[0028] Figure 5A flowchart depicts a non-limiting example of a core entering an idle mode and transitioning from an idle mode to an operating mode within a multi-core system according to one aspect of this embodiment. At step 510, a clock signal is received. At step 520, it is determined whether the core has been idle for a first number of clock signals. It should be understood that a counter can be incremented for each clock signal that the core (in one non-limiting example, a processing unit) is idle / inactive, and the counter can be reset when the core becomes active. In some embodiments, a signal is generated in response to the counter value reaching a first number of clock signals (e.g., 8 clock cycles, as an example). At step 530, in response to determining that the core has been idle for the first number of clock signals, the core enters an idle mode. In idle mode, at step 540, the core receives a command for execution. At step 550, in response to receiving the command, the core transitions from the idle mode to the operating mode. At step 560, a first number of No-Op commands are inserted in a first time segment of a plurality of time segments. It should be understood that the No-Op command prevents the kernel from processing instructions that are targeted at a certain number of clock signals (e.g., a clock cycle for each No-Op command). Each of multiple time segments is associated with a second number of clock signals (e.g., as an example, such as...). Figure 4 As shown, each time segment corresponds to 10 clock cycles. At step 570, a second number of No-Op commands are inserted within the second time segment of the plurality of time segments. The second number of No-Op commands is less than the first number of No-Op commands; for example, the number of No-Op commands in time segments 420, 430, 440, 450, 460, 460, and 470 is less than the number of No-Op commands in time segment 410. At step 580, a third number of No-Op commands are inserted in the last time segment of the plurality of time segments 410 to 470 (e.g., time segment 470, as an example). The third number of No-Op commands is less than the second number of No-Op commands. It should be understood that the number of No-Op commands inserted after the last time segment (e.g., time segment 470) (e.g., time segment 480) is zero.

[0029] For purposes of illustration and description, the foregoing description of various embodiments of the claimed subject matter has been provided. It is not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed. Many modifications and variations will be apparent to those skilled in the art. Embodiments have been chosen and described in order to best illustrate the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the claimed subject matter, the various embodiments, and the various modifications suitable for the particular intended use.

Claims

1. A system comprising: a first core comprising a first processing unit, a first on-chip memory (OCM), and a first idle detector unit, wherein the first core is configured to: receive data and store the received data in the first OCM, and is further configured to receive instructions to process the data stored in the first OCM based on the received instructions; enter an idle mode if the first idle detector unit detects that the first core has been idle for a first number of clock signals; while in the idle mode, receive a first pending command; and in response to receiving the first pending command, transition from the idle mode to an operational mode, wherein a number of no-operation (No-Op) commands are inserted within each of a first plurality of time slices, wherein a No-Op command prevents the first core from processing instructions for a number of clock signals, wherein each of the first plurality of time slices corresponds to a second number of clock signals, and wherein a number of No-Op commands inserted within a first time slice of the first plurality of time slices is greater than a number of No-Op commands inserted within a last time slice of the first plurality of time slices, and wherein a number of No-Op commands inserted after the last time slice of the first plurality of time slices is zero; and a second core comprising a second processing unit, a second OCM, and a second idle detector unit, wherein the second core is configured to: receive data and store the received data in the second OCM, and is further configured to receive instructions to process the data stored in the second OCM based on the received instructions; enter an idle mode if the second idle detector unit detects that the second core has been idle for a third number of clock signals; while in the idle mode, receive a second pending command; and in response to receiving the second pending command, transition from the idle mode to an operational mode, wherein a number of No-Op commands are inserted within each of a second plurality of time slices, wherein a No-Op command prevents the second core from processing instructions for another particular number of clock signals, wherein each of the second plurality of time slices corresponds to a fourth number of clock signals, and wherein a number of No-Op commands inserted within a first time slice of the second plurality of time slices is greater than a number of No-Op commands inserted within a last time slice of the second plurality of time slices.

2. The system of claim 1, wherein the first core and the second core independently of each other enter the idle mode and transition to the operational mode.

3. The system of claim 1, wherein the first number of clock signals is different from the third number of clock signals.

4. The system of claim 1, wherein the first number of clock signals and the third number of clock signals are user programmable.

5. The system of claim 1, wherein the second number of clock signals is different than the fourth number of clock signals.

6. The system of claim 1, wherein the second number of clock signals and the fourth number of clock signals are user programmable.

7. The system of claim 1, wherein the number of No-Op commands inserted within each time slice of the first plurality of time slices is less than or equal to the number of No-Op commands inserted within its immediately preceding time slice, and wherein the number of No-Op commands inserted within each time slice of the second plurality of time slices is less than or equal to the number of No-Op commands inserted within its immediately preceding time slice.

8. The system of claim 1, wherein the first idle detector unit comprises a first counter configured to reset in response to the first core receiving a command to execute, and wherein the first idle detector unit is configured to generate a first signal in response to a value of the first counter reaching the first number of clock signals, wherein the first signal causes the first core to transition to the idle mode, and wherein the second idle detector unit comprises a second counter configured to reset in response to the second core receiving a command to execute, and wherein the second idle detector unit is configured to generate a second signal in response to a value of the second counter reaching the third number of clock signals, wherein the second signal causes the second core to transition to the idle mode.

9. The system of claim 1, wherein the number of No-Op commands inserted after a last time slice of the second plurality of time slices is zero.

10. A system comprising: a plurality of cores, wherein each core of the plurality of cores comprises a processing unit, an on-chip memory (OCM), and an idle detector unit, and wherein one core of the plurality of cores is configured to: receive data and store the received data in its OCM, and further configured to receive an instruction to process the data stored in its OCM based on the received instruction; enter an idle mode if the idle detector unit of the core detects that the core has been idle for a first number of clock signals; while in the idle mode, receive a command to process; and in response to receiving the command to process, transition from the idle mode to an operational mode, wherein a number of non-operation (No-Op) commands are inserted within each time slice of a plurality of time slices, wherein a No-Op command prevents the core from processing an instruction for a number of clock signals, wherein each time slice of the plurality of time slices corresponds to a second number of clock signals, and wherein the number of No-Op commands inserted within a first time slice of the plurality of time slices is greater than the number of No-Op commands inserted within a last time slice of the plurality of time slices.

11. The system of claim 10, wherein a number of No-Op commands inserted within each of the plurality of time slices is reduced compared to an immediately preceding time slice.

12. The system of claim 10, wherein a number of No-Op commands inserted within each of a first subset of time slices of the plurality of time slices is less than a number of No-Op commands inserted within an immediately preceding time slice, and wherein a number of No-Op commands inserted within each of a second subset of time slices of the plurality of time slices is equal to a number of No-Op commands inserted within an immediately preceding time slice.

13. The system of claim 10, wherein the idle detector unit comprises a counter configured to be reset in response to the core receiving a command to execute; and wherein the idle detector unit is configured to generate a signal in response to a value of the counter reaching the first number of clock signals, and wherein the generated signal causes the core to transition to the idle mode.

14. The system of claim 10, wherein the first number of clock signals is user programmable.

15. The system of claim 10, wherein the second number of clock signals is user programmable.

16. The system of claim 10, wherein the core reaches full performance after the last time slice.

17. The system of claim 10, wherein the core reaches partial performance during the plurality of time slices.

18. The system of claim 10, wherein the core enters the idle mode after transitioning to the operational mode in response to the idle detector unit detecting that the core has been idle for the first number of clock signals.

19. The system of claim 10, wherein a number of No-Op commands inserted after the last time slice is zero.

20. A method comprising: receiving a clock signal; determining whether a core has been idle for a first number of clock signals; entering an idle mode in response to determining that the core has been idle for the first number of clock signals; in the idle mode, receiving a command for the core to execute; transitioning from the idle mode to an operational mode in response to receipt of the command; inserting a first number of non-operative No-Op commands within a first time slice of a plurality of time slices, wherein a No-Op command prevents the core from processing instructions for a number of clock signals, wherein each of the plurality of time slices corresponds to a second number of clock signals; inserting a second number of No-Op commands within a second time slice of the plurality of time slices, wherein the second number of No-Op commands is less than the first number of No-Op commands; and inserting a third number of No-Op commands within a last time slice of the plurality of time slices, wherein the third number of No-Op commands is less than the second number of No-Op commands.

21. The method of claim 20, wherein the number of No-Op commands inserted in each time slice is less than or equal to the number of No-Op commands inserted in the immediately preceding time slice.

22. The method of claim 20, further comprising: incrementing a counter for each clock signal for which the core is idle; generating a signal in response to the value of the counter reaching the first number of clock signals, and wherein the generated signal causes the core to transition to the idle mode; and resetting the counter in response to the core receiving a command to execute if the value of the counter is less than the first number of clock signals.

23. The method of claim 20, wherein the number of No-Op commands inserted after the last time slice is zero.

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