Light-emitting component

Abstract

A light emitting part includes: a substrate; a plurality of light emitting elements provided on the substrate to emit light in a direction intersecting a surface of the substrate; and a plurality of thyristors respectively laminated on the plurality of light emitting elements to drive the light emitting elements to emit light or increase an amount of light emission by becoming an on state, the light emitting elements having a current narrow region oxidized via a hole portion provided in a laminated structure in which the light emitting elements and the thyristors are laminated.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a light emitting component. BACKGROUND

[0002] Japanese Patent Laid-Open No. 1-238962 describes an array of light emitting elements in which a plurality of light emitting elements capable of controlling a threshold voltage or a threshold current from the outside are arranged in one dimension, two dimensions, or three dimensions, electrodes for controlling the threshold voltage or the threshold current of each light emitting element are connected to each other using an electrical member, and a clock line for applying a voltage or a current from the outside is connected to each light emitting element.

[0003] Japanese Patent Laid-Open No. 2009-286048 describes a self-scanning type light source head including a substrate, a surface-emitting semiconductor laser arranged in an array on the substrate, and a thyristor as a switching element arranged on the substrate to selectively turn on / off light emission of the surface-emitting semiconductor laser.

[0004] Japanese Patent Laid-Open No. 2001-308385 describes a self-scanning type light emitting device including a light emitting element configured as a pnpnpn six-layer semiconductor structure, electrodes are provided at both ends of a p-type first layer and an n-type sixth layer and at a central p-type third layer and an n-type fourth layer, and a pn layer is responsible for a light emitting diode function and a pnpn four-layer is responsible for a thyristor function. SUMMARY

[0005] Further, for example, in a self-scanning type light emitting element array including a light emitting portion and a driving portion, if the light emitting element and the thyristor for driving the light emitting element include the same semiconductor multilayer film, it is difficult to independently set the light emitting characteristics of the light emitting element and the driving characteristics of the thyristor for driving. Therefore, a laminated structure in which the thyristor for driving and the light emitting element are laminated via a tunnel junction layer is considered to independently set the characteristics of the light emitting element and the characteristics of the thyristor for driving. However, if oxidation is performed only from an outer edge portion of the laminated structure in order to provide a current narrow region in the light emitting element, the cross-sectional area becomes small and the resistance of the path of the current flowing from the thyristor to the light emitting element becomes large.

[0006] Therefore, an object of the present disclosure is to provide a light emitting component that reduces the resistance of the path of the current flowing from the thyristor to the light emitting element compared to the case where oxidation is performed only from an outer edge portion of the laminated structure.

[0007] According to a first aspect of the present disclosure, there is provided a light emitting component, including: a substrate; a plurality of light emitting elements provided on the substrate, emitting light in a direction intersecting a surface of the substrate; and a plurality of thyristors respectively stacked on the plurality of light emitting elements, driving the light emitting elements to emit light or increase an amount of light to be emitted by becoming in an on state, the light emitting elements having a current narrow region oxidized via a hole portion provided in a stacked structure in which the light emitting elements and the thyristors are stacked.

[0008] According to a second aspect of the present disclosure, the plurality of hole portions are arranged in a circular shape around an exit port of the light emitting elements in the stacked structure.

[0009] According to a third aspect of the present disclosure, the thyristor has an opening portion in a path of light toward the light emitting elements.

[0010] According to a fourth aspect of the present disclosure, the thyristor is stacked on the light emitting element via a tunnel junction layer or a III-V compound layer having metal conductivity.

[0011] According to a fifth aspect of the present disclosure, the light emitting component includes a plurality of transfer elements respectively connected to the plurality of thyristors, sequentially transferring the on state, and setting the thyristors in the on state by becoming in the on state.

[0012] According to a sixth aspect of the present disclosure, the light emitting elements are vertical cavity surface emitting laser elements.

[0013] According to a seventh aspect of the present disclosure, there is provided a light emitting component, including: a substrate; a plurality of light emitting elements provided on the substrate, emitting light in a direction intersecting a surface of the substrate; and a plurality of thyristors respectively stacked between the substrate and the plurality of light emitting elements, driving the light emitting elements to emit light or increase an amount of light to be emitted by becoming in an on state, the light emitting elements having a current narrow region oxidized via a hole portion provided in a stacked structure in which the light emitting elements and the thyristors are stacked.

[0014] (EFFECTS)

[0015] According to the first aspect or the seventh aspect, compared to a case in which oxidation is performed only from an outer edge portion of the stacked structure, a resistance of a path of current flowing from the thyristor to the light emitting element becomes smaller.

[0016] According to the second aspect, compared to a case in which the exit port of the light is not arranged in a circular shape, the exit port of the light is closer to a circular shape.

[0017] According to the third aspect, compared to a case in which the opening portion is not included, a decrease in the amount of light is suppressed.

[0018] According to the fourth aspect, the voltage for driving can be reduced compared to the case where the tunnel junction layer or the group III-V compound layer having metallic conductivity is not included.

[0019] According to the fifth aspect, the driving of the light emitting part becomes easy compared to the case where the transfer element is not included.

[0020] According to the sixth aspect, the light quantity can be increased compared to the case where the vertical cavity surface emitting laser element is not included. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a view showing an example of the overall structure of an image forming apparatus.

[0022] Figure 2 is a cross-sectional view showing an example of the structure of a print head.

[0023] Figure 3 is a plan view of an example of a light emitting apparatus.

[0024] Figure 4 (a) of FIG. 1 and Figure 4 (b) of FIG. 1 are views showing an example of the structure of a light emitting chip, the structure of a signal generating circuit of a light emitting apparatus, and the structure of a wiring (line) on a circuit substrate.

[0025] Figure 5 is an equivalent circuit view explaining the circuit structure of a light emitting chip.

[0026] Figure 6 (a) of FIG. 2 and Figure 6 (b) of FIG. 2 are an example of a plan layout view and a cross-sectional view of a light emitting chip to which the present embodiment is applied. Figure 6 (a) of FIG. 3 is a plan layout view of a light emitting chip, Figure 6 (b) of FIG. 3 is Figure 6 (a) of FIG. 4 is a cross-sectional view at the VIIB-VIIB line of (a) of FIG. 3.

[0027] Figure 7 (a) to Figure 7 (c) of FIG. 5 are enlarged views of a laminated structure in which a surface emitting laser element and a thyristor are laminated, in a light emitting chip to which the present embodiment is applied. Figure 7 (a) of FIG. 6 is a plan view of a laminated structure, Figure 7 (b) of FIG. 6 is Figure 7 (a) of FIG. 7 is a cross-sectional view at the VIIB-VIIB line of (a) of FIG. 6, Figure 7 (c) of FIG. 7 is Figure 7 (a) of FIG. 8 is a cross-sectional view at the VIIC-VIIC line of (a) of FIG. 6.

[0028] Figure 8(a) to (c) of FIG. 1 are a schematic band diagram of the layered structure of the surface-emitting laser element and the thyristor S set. Figure 8 (a) of FIG. 1 is a schematic band diagram of the layered structure of the surface-emitting laser element and the thyristor S set. Figure 8 (a) of FIG. 1 is a schematic band diagram of the layered structure of the surface-emitting laser element and the thyristor S set. Figure 8 (b) of FIG. 1 is a band diagram of the tunnel junction layer in a reverse bias state. Figure 8 (c) of FIG. 1 indicates a current-voltage characteristic of the tunnel junction layer.

[0029] Figure 9 is a time chart illustrating the operation of the light-emitting device and the light-emitting chip.

[0030] Figure 10 (a) and Figure 10 (b) of FIG. 1 is an enlarged view of the layered structure in which the surface-emitting laser element and the thyristor S are layered, in the light-emitting chip to which the present embodiment is not applied. Figure 10 (a) of FIG. 1 is a plan view of the layered structure, Figure 10 (b) of FIG. 1 is Figure 10 (a) of FIG. 1 is a cross-sectional view at XB-XB line. DETAILED DESCRIPTION

[0031] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0032] Further, hereinafter, elements will be described using element symbols, for example, Al for aluminum, and the like.

[0033] Here, a light-emitting chip C, which is an example of a light-emitting component, will be described as applied to an image forming apparatus 1, which is an example.

[0034] (Image Forming Apparatus 1)

[0035] Figure 1 is a view indicating an example of the overall structure of the image forming apparatus 1. Figure 1 The image forming apparatus 1 illustrated in FIG. 1 is an image forming apparatus generally called a tandem type. The image forming apparatus 1 includes an image forming process section 10 which performs image formation corresponding to image data of each color, an image output control section 30 which controls the image forming process section 10, and an image processing section 40 which, for example, is connected to a personal computer (PC) 2 or an image reading apparatus 3, and performs predetermined image processing on image data received from them.

[0036] The image forming processing section 10 includes image forming units 11Y, 11M, 11C, 11K (referred to as image forming units 11 in the case of no distinction) arranged side by side at a predetermined interval. The image forming units 11 include, as an example of an image holding body, a photosensitive drum 12 that forms a latent image and holds a toner image; a charger 13, as an example of a charging member, that charges the surface of the photosensitive drum 12 at a predetermined potential; a print head 14 that exposes the photosensitive drum 12 charged by the charger 13; and a developer 15, as an example of a developing member, that develops a latent image obtained by the print head 14. The image forming units 11Y, 11M, 11C, 11K respectively form a yellow (Y), a magenta (M), a cyan (C), and a black (K) toner image.

[0037] Further, in order to transfer the respective color toner images formed by the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, 11K onto a recording sheet 25, as an example of a transfer body, the image forming processing section 10 includes a sheet conveyance belt 21 that conveys the recording sheet 25; a drive roller 22 that drives the sheet conveyance belt 21; a transfer roller 23, as an example of a transfer member, that transfers the toner image of the photosensitive drum 12 onto the recording sheet 25; and a fuser 24 that fixes the toner image onto the recording sheet 25.

[0038] In the image forming apparatus 1, the image forming processing section 10 performs an image forming operation based on various control signals supplied from the image output control section 30. Further, under the control of the image output control section 30, image data received from a personal computer (PC) 2 or an image reading apparatus 3 is subjected to image processing by an image processing section 40 and is supplied to the image forming units 11. Further, for example, in the black (K) image forming unit 11K, the photosensitive drum 12 is rotated in the direction of an arrow A while being charged to a predetermined potential by the charger 13 and is exposed by the print head 14 that emits light based on the image data supplied from the image processing section 40. Thus, on the photosensitive drum 12, a latent image related to a black (K) image is formed. Further, the latent image formed on the photosensitive drum 12 is developed by the developer 15, so that a black (K) toner image is formed on the photosensitive drum 12. In the image forming units 11Y, 11M, 11C, yellow (Y), magenta (M), and cyan (C) toner images are respectively formed.

[0039] The respective color toner images formed on the photosensitive drum 12 by the respective image forming units 11 are sequentially electrostatically transferred to the recording paper 25 supplied in accordance with the movement of the paper conveyance belt 21 in the direction of the arrow B by a transfer electric field applied to the transfer roller 23, thereby forming a composite toner image in which the respective color toners overlap on the recording paper 25.

[0040] Subsequently, the recording paper 25 on which the composite toner image is electrostatically transferred is conveyed to the fuser 24. The composite toner image on the recording paper 25 conveyed to the fuser 24 is subjected to a fixing process by heat and pressure by the fuser 24, thereby being fixed to the recording paper 25 and being discharged from the image forming apparatus 1.

[0041] (Printing head 14)

[0042] Figure 2 is a cross-sectional view showing an example of the structure of the printing head 14. The printing head 14, which is an example of an exposure member, includes a housing 61, a light emitting device 65, which is an example of a light emitting member, including a light source portion 63 including a plurality of light emitting elements that expose the photosensitive drum 12, and a rod lens array 64, which is an example of an optical member, that images light emitted from the light source portion 63 on the surface of the photosensitive drum 12. In the present embodiment, the light emitting elements are vertical cavity surface emitting laser elements VCSEL (Vertical Cavity Surface Emitting Laser) as an example. Hereinafter, the light emitting elements are referred to as vertical cavity surface emitting laser elements VCSEL, which are surface emitting laser elements VCSEL. The surface emitting laser elements VCSEL resonate light in a light emitting layer sandwiched by two Distributed Bragg Reflector (DBR) layers (hereinafter referred to as DBR layers) to perform laser oscillation. When the reflectance of the two DBR layers is, for example, 99% or more, laser oscillation is performed.

[0043] The light emitting device 65 includes a circuit board 62 that mounts the aforementioned light source portion 63, a signal generating circuit 110 (refer to Figure 3 ) that drives the light source portion 63, and the like.

[0044] The housing 61 is formed of, for example, metal, supports the circuit board 62 and the rod lens array 64, and the surface that emits light from the light emitting elements of the light source portion 63 is set to be the focal plane of the rod lens array 64. Also, the rod lens array 64 is disposed in the axial direction of the photosensitive drum 12 (the X direction of (b) of the main scanning direction and the Figure 3 、 Figure 4 described later).

[0045] (Light emitting device 65)

[0046] Figure 3 This is a top view of an example of the light-emitting device 65.

[0047] Figure 3 In the light-emitting device 65 illustrated, the light source unit 63 is constructed by arranging 40 light-emitting chips C1 to C40 (hereinafter referred to as light-emitting chips C) in a zigzag pattern along the X direction, which is the main scanning direction, in two rows on the circuit board 62. The structures of light-emitting chips C1 to C40 can be the same.

[0048] In this specification, "~" indicates multiple constituent elements distinguished by numbering, including the elements listed before and after "~" and the numbered elements between them. For example, light-emitting chip C1 to light-emitting chip C40 are included from light-emitting chip C1 to light-emitting chip C40 in numerical order.

[0049] In addition, in the first embodiment, a total of 40 light-emitting chips C were used, but it is not limited to this.

[0050] Furthermore, the light-emitting device 65 is equipped with a signal generation circuit 110 for driving the light source unit 63. The signal generation circuit 110 may include, for example, an integrated circuit (IC). Alternatively, the light-emitting device 65 may not be equipped with a signal generation circuit 110. In this case, the signal generation circuit 110 is located outside the light-emitting device 65 and supplies control signals for controlling the light-emitting chip C via cables or the like. Here, the light-emitting device 65 will be described with the signal generation circuit 110 included.

[0051] Details regarding the arrangement of the light-emitting chip C will be discussed later.

[0052] Figure 4 (a) and Figure 4 (b) is a diagram showing an example of the structure of the light-emitting chip C, the structure of the signal generation circuit 110 of the light-emitting device 65, and the structure of the wiring (wires) on the circuit board 62. Figure 4 (a) represents the structure of the light-emitting chip C. Figure 4 (b) shows the structure of the signal generation circuit 110 of the light-emitting device 65 and the structure of the wiring (lines) on the circuit board 62. Additionally, Figure 4 In (b), the portion of light-emitting chips C1 to C9 within light-emitting chips C1 to C40 is represented.

[0053] First of all, Figure 4 The structure of the light-emitting chip C shown in (a) will be explained.

[0054] The light-emitting chip C includes a light-emitting portion 102 on the surface of a rectangular substrate 80. The light-emitting portion 102 is composed of a plurality of surface-emitting laser elements (VCSELs) arranged in a row along the long side, with VCSEL1 to VCSEL128 on one side near the long side. Furthermore, at both ends of the light-emitting chip C along the long side of the substrate 80 surface, there are multiple bonding pads, i.e., terminals, for transmitting various control signals, etc. terminal, Terminal, Vgk terminal, Terminals). Additionally, these terminals extend from one end of the substrate 80 according to... terminal, The terminals are arranged in sequence, and from the other end of the substrate 80, according to the Vgk terminal, The terminals are arranged in order. Furthermore, the light-emitting part 102 is provided at... Terminals and Between the terminals. Furthermore, on the back side of the substrate 80, a back electrode 91 serving as a Vsub terminal is provided (see below). Figure 6 (a) and Figure 6 (b) Here, on the surface of the substrate 80, the direction in which the surface-emitting laser elements VCSEL1 to VCSEL128 are arranged is set as the x-direction, and the direction orthogonal to the x-direction is set as the y-direction.

[0055] Furthermore, the term "list" is not limited to, for example, Figure 4 The arrangement of multiple surface-emitting laser elements (VCSELs) in a straight line as shown in (a) can also be achieved by arranging each VCSEL with a different offset relative to a direction orthogonal to the column direction. For example, each VCSEL may be arranged with an offset in a direction orthogonal to the column direction. Furthermore, adjacent VCSELs may be arranged alternately, or each of the multiple VCSELs may be arranged in a zigzag pattern.

[0056] Next, through Figure 4 (b) will be used to explain the structure of the signal generation circuit 110 of the light-emitting device 65 and the structure of the wiring (wires) on the circuit board 62.

[0057] As mentioned above, a signal generation circuit 110 and light-emitting chips C1 to C40 are mounted on the circuit board 62 of the light-emitting device 65, and wiring (wires) connecting the signal generation circuit 110 and the light-emitting chips C1 to C40 are provided.

[0058] First, the structure of the signal generation circuit 110 will be explained.

[0059] For the signal generation circuit 110, from the image output control unit 30 and the image processing unit 40 (see reference) Figure 1 The input consists of image data processed by the image processing circuit and various control signals. The signal generation circuit 110 uses this image data and various control signals to perform image data selection, sorting, or light quantity correction, etc.

[0060] Furthermore, the signal generation circuit 110 includes a transmission signal generation unit 120, which sends a first transmission signal to the light-emitting chips C1 to C40 based on various control signals. Second transmission signal

[0061] Furthermore, the signal generation circuit 110 includes a lighting signal generation unit 140, which sends lighting signals to the light-emitting chips C1 to C40 respectively based on various control signals. ~Light up signal (In the absence of distinction, it is called the lighting signal) ).

[0062] Furthermore, the signal generation circuit 110 includes: a reference potential supply unit 160, which supplies a reference potential Vsub as a potential reference to the light-emitting chips C1 to C40; and a power supply potential supply unit 170, which supplies a power supply potential Vgk for driving the light-emitting chips C1 to C40.

[0063] Next, the arrangement of light-emitting chips C1 to C40 will be explained.

[0064] Odd-numbered light-emitting chips C1, C3, C5, ... are arranged in a row with intervals along the long side of each substrate 80. Even-numbered light-emitting chips C2, C4, C6, ... are also arranged in a row with intervals along the long side of each substrate 80. Furthermore, the odd-numbered light-emitting chips C1, C3, C5, ... and the even-numbered light-emitting chips C2, C4, C6, ... are arranged in a zigzag pattern, with their long sides facing each other on the light-emitting portion 102 side of the light-emitting chip C, rotated 180° relative to each other. The positions of the light-emitting chips C are also set such that surface-emitting laser elements (VCSELs) are arranged at predetermined intervals along the main scanning direction (X direction). Additionally, in... Figure 4 On the light-emitting chips C1 to C40 of (b), arrows indicate... Figure 4 The arrangement direction of the surface-emitting laser elements (VCSELs) of the light-emitting part 102 shown in (a) (numbering sequence of surface-emitting laser elements VCSEL1 to VCSEL128).

[0065] The wiring (line) connecting the signal generating circuit 110 to the light emitting chips C1 to C40 will be described.

[0066] On the circuit substrate 62, a power supply line 200a is provided, which is connected to the Vsub terminal, i.e., the back electrode 91 (see FIG. 2) provided on the back surface of the substrate 80 of the light emitting chip C, and supplies the reference potential Vsub. Figure 6 (a) and (b) of FIG. 1) of the light emitting chip C. Figure 6

[0067] Further, on the circuit substrate 62, a power supply line 200b is provided, which is connected to the Vgk terminal of the light emitting chip C, and supplies the power supply potential Vgk for driving.

[0068] On the circuit substrate 62, a first transfer signal line 201 is provided, which transmits a first transfer signal from the transfer signal generating section 120 of the signal generating circuit 110 to the terminal of the light emitting chips C1 to C40. Further, a second transfer signal line 202 is provided, which transmits a second transfer signal to the terminal of the light emitting chips C1 to C40. The first transfer signal The second transfer signal are commonly (in parallel) transmitted to the light emitting chips C1 to C40.

[0069] Further, on the circuit substrate 62, light-up signal lines 204-1 to 204-40 (referred to as light-up signal lines 204 when not distinguished) are provided, which transmit light-up signals from the light-up signal generating section 140 of the signal generating circuit 110 to the terminal of each of the light emitting chips C1 to C40 via a current limiting resistor Rl, respectively.

[0070] As described above, the reference potential Vsub and the power supply potential Vgk are commonly supplied to all of the light emitting chips C1 to C40 on the circuit substrate 62. The first transfer signal The second transfer signal are also commonly (in parallel) transmitted to the light emitting chips C1 to C40. On the other hand, the light-up signals are individually transmitted to the light emitting chips C1 to C40, respectively.

[0071] (Light emitting chip C) ​​​

[0072] Figure 5 is an equivalent circuit diagram illustrating the circuit structure of the light emitting chip C. Each element described below is arranged based on the layout on the light emitting chip C (refer to (a) and (b) of FIG. 9 described later) except for the terminals (Vsub terminal, Vgk terminal, and Vd terminal). terminal, terminal, Vgk terminal, terminal). In addition, the positions of the terminals (Vsub terminal, Figure 6 terminal, Figure 6 terminal, Vgk terminal, terminal) are different from (a) of FIG. 9, but are shown at the left end in the figure for the sake of explanation of the connection relationship with the signal generating circuit 110. Also, the Vsub terminal provided on the back surface of the substrate 80 is drawn out to the outside of the substrate 80. Figure 4

[0073] Here, the light emitting chip C is explained taking the light emitting chip Cl as an example in relation to the signal generating circuit 110. Therefore, Figure 5 in (a) of FIG. 10, the light emitting chip C is denoted as the light emitting chip Cl (C). The structures of the other light emitting chips C2 to C40 are the same as that of the light emitting chip Cl.

[0074] The light emitting chip Cl (C) includes the light emitting portion 102 including the surface-emitting laser elements VCSEL1 to VCSEL128 (refer to (a) of FIG. 10). Figure 4

[0075] Also, the light emitting chip Cl (C) includes the setting thyristors S1 to S128 (referred to as the setting thyristors S in the case of not distinguishing). Among the surface-emitting laser elements VCSEL1 to VCSEL128 and the setting thyristors S1 to S128, the surface-emitting laser elements VCSEL and the setting thyristors S of the same number are connected in series.

[0076] In addition, as shown in (b) of FIG. 10 described later, the setting thyristors S are stacked on the surface-emitting laser elements VCSEL arranged in a column on the substrate 80. Thus, the setting thyristors S1 to S128 are also arranged in a column. As described later, the setting thyristors S set (control) the on / off of the surface-emitting laser elements VCSEL, and thus are elements for driving the surface-emitting laser elements VCSEL. In addition, the setting thyristors S are sometimes referred to as thyristors. Figure 6

[0077] ​​​​​Furthermore, the light-emitting chip C1(C) includes transmission thyristors T1 to transmission thyristors T128 (which are referred to as transmission thyristors T when not distinguished) arranged in a row in the same manner as the surface-emitting laser elements VCSEL1 to VCSEL128 and the setting thyristors S1 to S128.

[0078] Furthermore, the light-emitting chip C1(C) includes lower diodes UD1 to UD128, which have the same structure (diode structure) as the surface-emitting laser elements VCSEL1 to VCSEL128 (hereinafter referred to as lower diodes UD if no distinction is made). Among the lower diodes UD1 to UD128 and the transmission thyristors T1 to T128, the lower diodes UD with the same number are connected in series with the transmission thyristors T.

[0079] In addition, as will be discussed later Figure 6 As shown in (b), the transmission thyristor T is stacked on the lower diodes UD arranged in a row on the substrate 80. Therefore, the lower diodes UD1 to UD128 are also arranged in a row.

[0080] In addition, this example uses a transmission thyristor T as the transmission element, but other circuit elements can also be used as long as the elements are sequentially turned on. For example, a shift register or a circuit element composed of multiple transistors can also be used.

[0081] Furthermore, the light-emitting chip C1(C) sets two of the transmission thyristors T1 to T128 as a pair according to the numbering order, and includes coupling diodes D1 to D127 (which are referred to as coupling diodes D when not distinguished) between each pair.

[0082] Furthermore, the light-emitting chip C1(C) includes power line resistors Rg1 to Rg128 (which are referred to as power line resistors Rg if no distinction is made).

[0083] Furthermore, the light-emitting chip C1(C) includes a startup diode SD. It also includes current-limiting resistors R1 and R2, which are used to prevent excessive current from flowing into the transmission of the first transmission signal (described later). The first transmission signal line 72 and the transmission of the second transmission signal The second transmission signal line 73.

[0084] Here, the drive section 101 is configured by the set thyristors S1 to S128, the transfer thyristors T1 to T128, the lower diodes UD1 to UD128, the power line resistors Rg1 to Rg128, the coupling diodes D1 to D127, the start diode SD, the current-limiting resistor R1, and the current-limiting resistor R2.

[0085] The surface-emission laser elements VCSEL1 to VCSEL128 of the light-emitting section 102, the drive section 101, and the set thyristors S1 to S128, the transfer thyristors T1 to T128, and the lower diodes UD1 to UD128 are arranged in the order of the numbers from the left side in the figure. Figure 5 Further, the coupling diodes D1 to D127 and the power line resistors Rg1 to Rg128 are also arranged in the order of the numbers from the left side in the figure.

[0086] In the present embodiment, the number of the surface-emission laser elements VCSEL, the set thyristors S, the transfer thyristors T, the lower diodes UD, and the power line resistors Rg in the light-emitting section 102 and the drive section 101 is 128. In addition, the number of the coupling diodes D is 127, which is one less than the number of the transfer thyristors T.

[0087] The number of the surface-emission laser elements VCSEL and the like is not limited to this, and can be any number as long as it is a predetermined number. Also, the number of the transfer thyristors T can be more than the number of the surface-emission laser elements VCSEL.

[0088] The surface-emission laser elements VCSEL, the lower diodes UD, the coupling diodes D, and the start diode SD are two-terminal semiconductor elements of a diode structure including an anode terminal (anode) and a cathode terminal (cathode), and the set thyristors S and the transfer thyristors T are semiconductor elements of a thyristor structure having three terminals of an anode terminal (anode), a gate terminal (gate), and a cathode terminal (cathode).

[0089] In addition, the surface-emission laser elements VCSEL, the lower diodes UD, the coupling diodes D, the start diode SD, the set thyristors S, and the transfer thyristors T can not necessarily include the anode terminal, the gate terminal, and the cathode terminal configured as electrodes. Thus, hereinafter, the terminals can be omitted in some cases.

[0090] Next, the electrical connection of each element in the light-emitting chip C1 (C) will be described.

[0091] The anodes of the surface-emission laser elements VCSEL and the lower diodes UD are connected to the substrate 80 of the light-emitting chip C1 (C) (common anode).

[0092] These anodes are located via Vsub terminals, i.e., back electrodes 91, on the back side of the substrate 80 (see below). Figure 6 (b) is connected to power cord 200a (refer to) Figure 4 (b)). The power line 200a supplies a reference potential Vsub from the reference potential supply section 160.

[0093] Furthermore, the cathodes of each surface-emitting laser element (VCSEL) are connected to the anode of the set thyristor S. Also, the cathodes of each lower diode (UD) are connected to the anode of the transmission thyristor T.

[0094] Furthermore, this connection is the structure when using a p-type substrate 80. When using an n-type substrate, the polarity becomes reversed. When using an intrinsic (i) type substrate without added impurities, a terminal is provided on the side of the substrate where the driving part 101 and the light-emitting part 102 are provided, which is connected to the power line 200a that supplies the reference potential Vsub.

[0095] Along the arrangement of the transmission thyristors T, the cathodes of odd-numbered transmission thyristors T1, T3, ... are connected to the first transmission signal line 72. Furthermore, the first transmission signal line 72 is connected to the current-limiting resistor R1. Terminals. In the... Terminal, connected to the first transmission signal line 201 (see reference) Figure 4 (b) The first transmission signal is sent from the transmission signal generation unit 120.

[0096] On the other hand, along the arrangement of the transmission thyristors T, the cathodes of even-numbered transmission thyristors T2, T4, ... are connected to the second transmission signal line 73. Furthermore, the second transmission signal line 73 is connected to the current-limiting resistor R2. Terminals. In the... The terminal is connected to the second transmission signal line 202 (see reference). Figure 4 (b) sends a second transmission signal from the transmission signal generation unit 120.

[0097] The cathodes of each thyristor S are connected to the lighting signal line 75. The lighting signal line 75 is connected to... Terminal. In the light-emitting chip C1, The terminal is connected to the lighting signal line 204-1 via a current-limiting resistor RI located outside the light-emitting chip C1(C), and a lighting signal is sent from the lighting signal generation unit 140. (Refer to Figure 4 (b) of the signal. The surface-emitting laser elements VCSEL1 to VCSEL128 are supplied with current for illumination. Additionally, the other light-emitting chips C2 to C40... The terminals are connected to the lighting signal lines 204-2 to 204-40 via current-limiting resistors RI, respectively, and lighting signals are sent from the lighting signal generation unit 140. ~Light up signal (Refer to Figure 4 (b)

[0098] The gates Gt1 to Gt128 (hereinafter referred to as gate Gt if not distinguished) of each of the transmission thyristors T1 to T128 are connected one-to-one to the gates Gs1 to Gs128 (hereinafter referred to as gate Gs if not distinguished) of the setting thyristors S1 to S128 with the same number. Therefore, among the gates Gt1 to Gt128 and the gates Gs1 to Gs128, the gates Gt and Gs with the same number are electrically at the same potential. Therefore, for example, gate Gt1 (gate Gs1) indicates that they are at the same potential.

[0099] Between the gates Gt1 to Gt128 of each of the transmission thyristors T1 to T128, which are arranged in pairs according to their numbering sequence, coupling diodes D1 to D127 are connected respectively. That is, coupling diodes D1 to D127 are connected in series, sandwiched between their respective gates Gt1 and Gt128. Furthermore, the direction of coupling diode D1 is from gate Gt1 towards gate Gt2 in the direction of current flow. The other coupling diodes D2 to D127 are connected in the same way.

[0100] The gate Gt (gate Gs) of the transmission thyristor T is connected to the power supply line 71 via a power supply line resistor Rg corresponding to that of the transmission thyristor T. The power supply line 71 is connected to the Vgk terminal. A power supply line 200b (see reference) is connected to the Vgk terminal. Figure 4 (b) The power supply potential Vgk is supplied from the power supply potential supply unit 170.

[0101] Furthermore, the gate Gt1 of the transmission thyristor T1 is connected to the cathode terminal of the start-up diode SD. On the other hand, the anode of the start-up diode SD is connected to the second transmission signal line 73.

[0102] Figure 6 (a) and Figure 6 (b) is an example of a plan view and a cross-sectional view of the light-emitting chip C to which this embodiment is applicable. Figure 6 (a) is a planar layout diagram of the light-emitting chip C. Figure 6 (b) isFigure 6 The cross-sectional view at line VIB-VIB in (a) is shown here. The connection between the light-emitting chip C and the signal generation circuit 110 is not shown, therefore it is not necessary to use the light-emitting chip C1 as an example. It is therefore referred to as light-emitting chip C. Figure 6 In (a), the rightward direction of the paper is the x-direction, the upward direction of the paper is the y-direction, and the surface direction of the paper is the z-direction. Furthermore, a plane is defined as a surface viewed from the surface side (z-direction) of the paper. Therefore, Figure 6 In (b), the left direction of the paper is the z direction, and the top direction of the paper is the y direction.

[0103] Figure 6 In (a), the portion centered on the surface-emitting laser elements VCSEL1 to VCSEL128, the setting thyristors S1 to S4, the transmission thyristors T1 to T4, and the lower diodes UD1 to UD4 is shown. Additionally, the terminals ( terminal, Terminal, Vgk terminal, The position of the terminal) and Figure 4 (a) is different, but is shown at the left end of the figure for ease of explanation. Furthermore, the Vsub terminal (back electrode 91) located on the back side of the substrate 80 is shown as extending beyond the substrate 80. If compared with... Figure 4 If terminal is provided correspondingly in (a), then terminal, The terminal and current-limiting resistor R2 are located at the right end of the substrate 80. Furthermore, the start-up diode SD may also be located at the right end of the substrate 80.

[0104] Figure 6 The cross-sectional view at line VIB-VIB in (a) is... Figure 6 In (b), the lower part of the diagram shows the configuration of thyristor S1 / surface-emitting laser element VCSEL1, transmission thyristor T1 / lower diode UD1, coupling diode D1, and power line resistor Rg1. Furthermore, thyristor S1 and surface-emitting laser element VCSEL1 are stacked. Similarly, transmission thyristor T1 and lower diode UD1 are stacked. And, in Figure 6 (a) and Figure 6 In Figure (b), the main components or terminals are labeled by name. In addition, on the surface of the substrate 80, surface-emitting laser elements (VCSELs) (VCSEL1 to VCSEL4) are arranged along the x-direction.

[0105] First, through Figure 6 (b) illustrates the cross-sectional structure of the light-emitting chip C.

[0106] On a p-type substrate 80, an anode layer 81 (p-anode (DBR) layer 81), an emissive layer 82, and an n-type DBR structure cathode layer 83 (n-cathode (DBR) layer 83) constituting a surface-emitting laser element VCSEL and a lower diode UD are provided. A tunnel junction (tunneling diode) layer 84 (tunneling junction layer 84) is provided on the n-type DBR structure cathode layer 83 (n-cathode (DBR) layer 83). Furthermore, on the tunnel junction layer 84, a p-type anode layer 85 (p-anode layer 85), an n-type gate layer 86 (n-gate layer 86), a p-type gate layer 87 (p-gate layer 87), and an n-type cathode layer 88 (n-cathode layer 88) constituting a setting thyristor S, a transmission thyristor T, a coupling diode D1, and a power line resistor Rg1 are sequentially provided. The description in parentheses follows. The same applies to other cases. Here, the semiconductor layer formed by stacking p anode (DBR) layer 81, light-emitting layer 82, n cathode (DBR) layer 83, tunnel junction layer 84, p anode layer 85, n gate layer 86, p gate layer 87, and n cathode layer 88 is referred to as a semiconductor stack.

[0107] Furthermore, on the light-emitting chip C, such as Figure 6 As shown in (b), a protective layer 90 containing a light-transmitting insulating material is provided to cover the surface and sides of these stacked structures. Figure 6 In (b), the arrow indicates the direction of light emission from the surface-emitting laser element VCSEL (light emission direction). Here, it is the direction intersecting the surface of the substrate 80 (the z-direction).

[0108] Furthermore, these stacked structures are wired to power lines 71, first transmission signal lines 72, second transmission signal lines 73, lighting signal lines 75, etc., via through holes provided in the protective layer 90. Figure 6 (A) is connected by ○. In the following description, the description of the protective layer 90 and the through hole is omitted.

[0109] Moreover, such as Figure 6 As shown in (b), a back electrode 91 serving as a Vsub terminal is provided on the back side of the substrate 80.

[0110] The p-anode (DBR) layer 81, light-emitting layer 82, n-cathode (DBR) layer 83, tunnel junction layer 84, p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88 are semiconductor layers, stacked on a monolithic substrate through epitaxial growth. Furthermore, the semiconductor layers between the stacked structures are removed by etching (mesa etching) to create multiple electrically separated stacked structures (islands) (later described as stacked structures 301, 302, 303, ...). Alternatively, the multiple stacked structures can also be electrically separated by ion implantation or other methods besides etching.

[0111] Here, the description of the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 corresponds to their functions in constituting a surface-emitting laser element (VCSEL). That is, the p-anode (DBR) layer 81 functions as the anode of the VCSEL, and the n-cathode (DBR) layer 83 functions as the cathode of the VCSEL. In other words, the VCSEL has a diode structure including both an anode and a cathode. Furthermore, the lower diode UD has the same diode structure as the VCSEL and is therefore called a diode.

[0112] The descriptions of the p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88 correspond to their functions when configuring the setting thyristor S and the transmission thyristor T. That is, the p-anode layer 85 functions as the anode, the n-gate layer 86 and p-gate layer 87 function as the gate, and the n-cathode layer 88 functions as the cathode.

[0113] In addition, when the coupling diode D and the power line resistor Rg are configured, they have different functions as described later.

[0114] As described below, the multiple stacked structures include a portion of a plurality of layers, excluding a p-anode (DBR) layer 81, a light-emitting layer 82, an n-cathode (DBR) layer 83, a tunnel junction layer 84, a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88. For example, the stacked structure 301 does not include a portion of the tunnel junction layer 84, the p-anode layer 85, the n-gate layer 86, the p-gate layer 87, and the n-cathode layer 88.

[0115] Next, through Figure 6 (a) illustrates the planar layout of the light-emitting chip C.

[0116] The stacked structure 301 includes a surface-emitting laser element VCSEL1 and a setting thyristor S1. The stacked structure 302 includes a lower diode UD1, a transmission thyristor T1, and a coupling diode D1. The stacked structure 303 includes a power line resistor Rg1. The stacked structure 304 includes a start-up diode SD. The stacked structure 305 includes a current-limiting resistor R1, and the stacked structure 306 includes a current-limiting resistor R2.

[0117] Furthermore, multiple stacked structures identical to those in stacked structures 301, 302, and 303 are formed side-by-side on the light-emitting chip C. These stacked structures, like those in stacked structures 301, 302, and 303, include surface-emitting laser elements VCSEL2, VCSEL3, VCSEL4, ..., setting thyristors S2, S3, S4, ..., transmission thyristors T2, T3, T4, ..., lower diodes UD2, UD3, UD4, ..., coupling diodes D2, D3, D4, ..., etc.

[0118] Here, through Figure 6 (a) and Figure 6 (b) will be used to describe in detail the stacked structures 301 to 306.

[0119] like Figure 6 As shown in (b), the surface-emitting laser element VCSEL1 in the stacked structure 301 includes a p-anode (DBR) layer 81, an emitting layer 82, and an n-cathode (DBR) layer 83. The thyristor S1 includes a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88 stacked via a tunneling junction layer 84 stacked on the n-cathode (DBR) layer 83 of the surface-emitting laser element VCSEL1.

[0120] In the p-anode (DBR) layer 81 of the surface-emitting laser element VCSEL, such as Figure 7 As shown in black in (b), it contains a current-straining layer (described later) that restricts the current. Figure 7 (a) to Figure 6The current constriction layer 81b) in (c) is provided to restrict the current flowing to the surface-emitting laser element VCSEL to the central portion of the surface-emitting laser element VCSEL. That is, the peripheral portion of the surface-emitting laser element VCSEL is defective due to mesa etching. Therefore, non-luminescence recombination is easily caused. Therefore, the current constriction layer is provided to make the central portion of the surface-emitting laser element VCSEL a current passing portion (region) α in which the current easily flows, and the peripheral portion a current stopping portion (region) β in which the current hardly flows. In addition, the current stopping portion β is sometimes referred to as a current constriction region.

[0121] When the current stopping portion β is provided, the power consumed by non-luminescence recombination is suppressed, and thus the power consumption is reduced and the light extraction efficiency is improved. In addition, the light extraction efficiency refers to the amount of light that can be extracted per unit power.

[0122] In addition, the current constriction layer will be described later.

[0123] Furthermore, the setting thyristor S1 is provided with an opening portion 51 at a portion overlapping with the exit port 50 of the exit light of the surface-emitting laser element VCSEL (as an example, the central portion of the current passing portion α as viewed from the exit surface side) to suppress the loss of the light emitted from the surface-emitting laser element VCSEL due to the setting thyristor S. Here, in the opening portion 51, the n-cathode layer 88, the p-gate layer 87, the n-gate layer 86, the p-anode layer 85, and the tunnel junction layer 84 are removed. That is, the opening portion 51 is surrounded by the setting thyristor S. Furthermore, the opening portion 51 is provided on the path of the light from the surface-emitting laser element VCSEL. That is, the setting thyristor S is stacked on the surface-emitting laser element VCSEL at a portion deviated from the exit port 50 of the exit light of the surface-emitting laser element VCSEL (the central portion of the current passing portion α). In addition, the exit port 50 can be said to be a portion on the exit surface of the surface-emitting laser element VCSEL at which the amount of exit light is the largest. That is, the setting thyristor S has the opening portion 51 at a position overlapping with the portion on the exit surface of the surface-emitting laser element VCSEL at which the amount of exit light is the largest. In addition, the light can be made to exit by being transmitted through the setting thyristor S without providing the opening portion 51. At this time, it is only necessary to make the setting thyristor S have a light-transmitting property with respect to the light emitted from the surface-emitting laser element VCSEL.

[0124] Further, the thyristor S1 is provided with a plurality of hole portions 55. Eight hole portions 55 are provided here. The eight hole portions 55 are provided in a manner of surrounding the emission port 50. The hole portions 55 are portions in which the semiconductor laminate is removed from the p-anode (DBR) layer 81, the light-emitting layer 82, the n-cathode (DBR) layer 83, the tunnel junction layer 84, the p-anode layer 85, the n-gate layer 86, the p-gate layer 87, and the n-cathode layer 88, like the laminate structure body. As will be described later, the current-narrowing layer 81b is oxidized via the edge portion of the laminate structure body 301 and the hole portions 55, thereby forming a current-stopping portion β. Further, the edge portion of the laminate structure body 301 refers to the end portion of the laminate structure body 301 formed by removing the semiconductor laminate. That is, the edge portion of the laminate structure body 301 refers to the side surface of the laminate structure body 301 exposed by the semiconductor laminate.

[0125] Further, an n-type ohmic electrode 321 (n-ohmic electrode 321) provided on the n-cathode layer 88 (region 311) is provided as a cathode electrode. Further, the n-ohmic electrode 321 is provided between the emission port 50 and the hole portions 55 in a manner of surrounding the emission port 50. Further, a p-type ohmic electrode 331 (p-ohmic electrode 331) provided on the p-gate layer 87 exposed by removing the n-cathode layer 88 is provided as a gate electrode Gs1.

[0126] The lower diode UD1 provided in the laminate structure body 302 includes the p-anode (DBR) layer 81, the light-emitting layer 82, and the n-cathode (DBR) layer 83. The transfer thyristor T1 includes the p-anode layer 85, the n-gate layer 86, the p-gate layer 87, and the n-cathode layer 88 laminated via the tunnel junction layer 84 laminated on the n-cathode (DBR) layer 83 of the lower diode UD1. Further, an n-ohmic electrode 323 provided on the n-cathode layer 88 (region 313) is provided as a cathode terminal. Further, a p-ohmic electrode 332 provided on the p-gate layer 87 exposed by removing the n-cathode layer 88 is provided as a terminal of the gate electrode Gt1 (sometimes referred to as a gate terminal Gt1).

[0127] Similarly, the coupling diode D1 provided in the laminate structure body 302 includes the p-gate layer 87 and the n-cathode layer 88. Further, an n-ohmic electrode 324 provided on the n-cathode layer 88 (region 314) is provided as a cathode terminal. Further, a p-ohmic electrode 332 provided on the p-gate layer 87 exposed by removing the n-cathode layer 88 is provided as an anode terminal. Here, the anode terminal of the coupling diode D1 is the same as the gate electrode Gt1 (gate terminal Gt1).

[0128] The power line resistance Rg1 provided in the laminate structure body 303 includes the p-gate layer 87. That is, the power line resistance Rg1 is provided as a resistance using the p-gate layer 87 between the p-ohmic electrode 333 and the p-ohmic electrode 334 provided on the p-gate layer 87 exposed by removing the n-cathode layer 88.

[0129] The start diode SD in the stacked structure 304 includes the p-gate layer 87 and the n-cathode layer 88. That is, the start diode SD sets the n-ohmic electrode 325 provided on the n-cathode layer 88 (region 315) as a cathode terminal. Further, the p-ohmic electrode 335 provided on the p-gate layer 87 exposed by removing the n-cathode layer 88 is set as an anode terminal.

[0130] The current-limiting resistor Rl provided in the stacked structure 305 and the current-limiting resistor R2 provided in the stacked structure 306 are provided as the p-gate layer 87 between two p-ohmic electrodes (no sign) as a resistor, like the power supply line resistor Rgl provided in the stacked structure 303.

[0131] In (a) of FIG. 10, the connection relationship between the elements is described. Figure 6 The lighting signal line 75 includes a stem 75a and a plurality of branch portions 75b. The stem 75a is provided so as to extend in the column direction of the VCSELs provided on the thyristor SI. The branch portions 75b branch from the stem 75a and are connected to the n-ohmic electrodes 321 provided on the cathode terminals of the thyristor SI provided in the stacked structure 301. The same applies to the cathode terminals of the other thyristors S.

[0132] The lighting signal line 75 is connected to the

[0133] terminal provided on the side of the VCSELl provided on the thyristor SI. The first transfer signal line 72 is connected to the n-ohmic electrode 323 provided on the cathode terminal of the transfer thyristor Tl provided in the stacked structure 302. On the first transfer signal line 72, the cathode terminals of the other odd-numbered transfer thyristors T provided in the same stacked structure as the stacked structure 302 are connected. The first transfer signal line 72 is connected to the

[0134] terminal via the current-limiting resistor Rl provided in the stacked structure 305. On the other hand, the second transfer signal line 73 is connected to the n-ohmic electrode (no sign) provided on the cathode terminal of the even-numbered transfer thyristor T provided in the stacked structure not marked with a sign. The second transfer signal line 73 is connected to the

[0135] terminal via the current-limiting resistor R2 provided in the stacked structure 306.

[0136] The power supply line 71 is connected to one of the terminals of the power supply line resistor Rgl provided in the stacked structure 303, that is, the p-ohmic electrode 334. The other terminal of the power supply line resistor Rg is also connected to the power supply line 71. The power supply line 71 is connected to the Vgk terminal.

[0137] ​Further, the p ohm electrode 331 (gate terminal Gs 1) of the set thyristor S 1 provided in the stacked structure 301 is connected to the p ohm electrode 332 (gate terminal Gt 1) of the stacked structure 302 by the connection wiring 76.

[0138] Further, the p ohm electrode 332 (gate terminal Gt 1) is connected to the p ohm electrode 333 (the other terminal of the power supply line resistance Rg 1) of the stacked structure 303 by the connection wiring 77.

[0139] The n ohm electrode 324 (cathode terminal of the coupling diode D 1) provided in the stacked structure 302 is connected to the gate terminal Gt 2, i.e., the p type ohm electrode (no sign) of the adjacent transfer thyristor T 2 by the connection wiring 79.

[0140] Although not described here, the same applies to the other surface-emission laser elements VCSEL, set thyristors S, transfer thyristors T, coupling diodes D, and the like.

[0141] The p ohm electrode 332 (gate terminal Gt 1) of the stacked structure 302 is connected to the n ohm electrode 325 (cathode terminal of the start diode SD) provided in the stacked structure 304 by the connection wiring 78. The p ohm electrode 335 (anode terminal of the start diode SD) is connected to the second transfer signal line 73.

[0142] In addition, the connection and structure are when a p type substrate 80 is used, and in the case of using an n type substrate, the polarity becomes reversed. Further, in the case of using an i type substrate, a terminal connected to the power supply line 200a that supplies the reference potential Vsub is provided on the side of the substrate on which the driving portion 101 and the light-emitting portion 102 are provided. Further, the connection and structure are the same as in either of the case of using a p type substrate and the case of using an n type substrate.

[0143] Here, the manufacturing method of the light-emitting chip C will be described with reference to (b) of Figure 8

[0144] First, on a p type substrate 80, a p anode (DBR) layer 81, a light-emitting layer 82, an n cathode (DBR) layer 83, a tunnel junction layer 84, a p anode layer 85, an n gate layer 86, a p gate layer 87, and an n cathode layer 88 are sequentially epitaxially grown to form a semiconductor stacked body. Here, the substrate 80 is described by way of example using a p type GaAs, but can be an n type GaAs or an intrinsic (i) type GaAs to which no impurities are added.

[0145] The DBR layer includes, for example, a low-refractive-index layer of a high Al component of Al 0.9 Ga 0.1 As and a high-refractive-index layer of, for example, Al 0.2 Ga​0.8 The composition is a combination of As with a low Al content and a high refractive index layer. The thickness (optical path length) of each layer is set, for example, to 0.25 (1 / 4) of the center wavelength. Furthermore, the Al content ratio of the low-refractive-index layer to the high-refractive-index layer can be varied within the range of 0 to 1.

[0146] The p-anode (DBR) layer 81 is formed by sequentially stacking the lower p-anode (DBR) layer 81a, the current-limiting layer 81b, and the upper p-anode (DBR) layer 81c. For example, the impurity concentration of the lower p-anode (DBR) layer 81a and the upper p-anode (DBR) layer 81c is 1 × 10⁻⁶. 18 / cm 3 The current-narrowing layer 81b is, for example, AlAs or p-type AlGaAs with a high concentration of Al impurities. Any material that narrows the current path by increasing resistance through Al oxidation to form Al₂O₃ is acceptable.

[0147] The thickness (optical path length) of the current-restricting layer 81b in the p-anode (DBR) layer 81 is determined based on the structure employed. When extraction efficiency or process reproducibility is important, it can be set to an integer multiple of the thickness (optical path length) of the low-refractive-index layer and the high-refractive-index layer constituting the DBR layer, for example, 0.75 (3 / 4) of the center wavelength. Furthermore, in the case of odd multiples, it is preferable that the current-restricting layer 81b is sandwiched between two high-refractive-index layers. Moreover, in the case of even multiples, it is preferable that the current-restricting layer 81b is sandwiched between a high-refractive-index layer and a low-refractive-index layer. That is, the current-restricting layer 81b is preferably designed to suppress the disruption of the refractive index period caused by the DBR layer. Conversely, when it is desirable to reduce the effects (refractive index or deformation) of the oxidized portion, the thickness of the current-restricting layer 81b is preferably tens of nm, and it is preferably inserted into the section of the standing wave junction within the DBR layer.

[0148] The light-emitting layer 82 is a quantum well structure composed of alternating well layers and barrier layers. Examples of well layers include GaAs, AlGaAs, InGaAs, GaAsP, AlGaInP, GaInAsP, and GaInP, while barrier layers include AlGaAs, GaAs, GaInP, and GaInAsP. Alternatively, the light-emitting layer 82 can also be a quantum wire or a quantum dot.

[0149] n-cathode (DBR) layer 83, for example, has an impurity concentration of 1×10⁻⁶. 18 / cm 3 .

[0150] Tunneling layer 84 contains a high concentration of n-type impurities. ++Layer 84a and p with high concentration of n-type impurities ++ The junction of layer 84b (see below) Figure 7 (a) of (a) n ++ Layer 84a and p ++ Layer 84b, for example, has an impurity concentration of 1×10⁻⁶. 20 / cm 3 High concentration. Additionally, the typical impurity concentration in the junction is 10. 17 / cm 3 Level ~ 10 18 / cm 3 Level. n ++ Layer 84a and p ++ Combinations of layer 84b (hereinafter referred to as n) ++ Layer 84a / p ++ (represented by layer 84b, for example, n) ++ GaInP / p ++ GaAs, n ++ GaInP / p ++ AlGaAs, n ++ GaAs / p ++ GaAs, n ++ AlGaAs / p ++ AlGaAs, n ++ InGaAs / p ++ InGaAs, n ++ GaInAsP / p ++ GaInAsP,n ++ GaAsSb / p ++ GaAsSb. Alternatively, the combinations can be interchanged.

[0151] For example, the impurity concentration of the p-anode layer 85 is 1×10⁻⁵. 18 / cm 3 p-type Al 0.9 The Al content in GaAs can also be varied within the range of 0 to 1.

[0152] The n-gate layer 86, for example, has an impurity concentration of 1×10⁶. 17 / cm 3 n-type Al 0.9 The Al content in GaAs can also be varied within the range of 0 to 1.

[0153] For example, the impurity concentration of the p-gate layer 87 is 1×10⁻⁶. 17 / cm 3 p-type Al 0.9 The Al content in GaAs can also be varied within the range of 0 to 1.

[0154] For example, the impurity concentration of the n-cathode layer 88 is 1×10⁸.18 / cm 3 n-type Al 0.9 GaAs. The Al composition can also be varied in the range of 0 to 1.

[0155] These semiconductor layers are, for example, stacked by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or the like, to form a semiconductor stack.

[0156] Next, an n ohmic electrode 321, an n ohmic electrode 323, an n ohmic electrode 324, and the like are formed on the n cathode layer 88. The n ohmic electrode (n ohmic electrode 321, n ohmic electrode 323, n ohmic electrode 324, and the like) is, for example, Au (AuGe) or the like containing Ge that easily makes ohmic contact with the n-type semiconductor layer such as the n cathode layer 88. The n ohmic electrode (n ohmic electrode 321, n ohmic electrode 323, n ohmic electrode 324, and the like) is, for example, formed by a lift off method or the like.

[0157] Next, the n cathode layer 88, the p gate layer 87, the n gate layer 86, the p anode layer 85, the tunnel junction layer 84, the n cathode (DBR) layer 83, the light emitting layer 82, and the p anode (DBR) layer 81 are sequentially etched to be separated into a stacked structure 301, a stacked structure 302, and the like. At the same time, a hole portion 55 in the stacked structure 301 is formed. The etching can be performed by wet etching using a sulfuric acid-based etching solution (sulfuric acid : hydrogen peroxide water : water = 1 : 10 : 300 by weight ratio) or the like, or by anisotropic dry etching (reactive ion etching (RIE)) using, for example, boron chloride or the like. The etching to separate into the stacked structure is sometimes referred to as mesa etching or post etching.

[0158] Next, the n cathode layer 88, the p gate layer 87, the n gate layer 86, the p anode layer 85, and the tunnel junction layer 84 are sequentially etched to form an opening portion 51 in the exit port 50.

[0159] Next, the current flow stopper β is formed by oxidizing the current flow narrow layer 81b exposed from the side surface to the side surface at the edge portion and the hole portion 55 of the stacked structure. The oxidation of the current flow narrow layer 81b is performed, for example, by oxidizing Al of the current flow narrow layer 81b which is AlAs, AlGaAs, or the like, by steam oxidation at 300°C to 400°C. At this time, the oxidation is performed from the exposed side surface, and the current flow stopper β including Al2O3 which is an oxide of Al is formed. The unoxidized portion of the current flow narrow layer 81b becomes the current flow passage α.

[0160] Next, the p gate layer 87 is exposed by etching the n cathode layer 88. The etching can be performed by wet etching using a sulfuric acid-based etching solution (sulfuric acid : hydrogen peroxide water : water = 1 : 10 : 300 by weight ratio), or by anisotropic dry etching using, for example, boron chloride. Further, a p ohmic electrode (p ohmic electrode 331, p ohmic electrode 332, and the like) is formed on the p gate layer 87. The p ohmic electrode is, for example, Au (AuZn) or the like including Zn which easily makes ohmic contact with the p-type semiconductor layer such as the p gate layer 87. Further, the p ohmic electrode (p ohmic electrode 331, p ohmic electrode 332, and the like) is formed, for example, by lift-off or the like.

[0161] Next, a protective layer 90 is formed, for example, by covering the surface of the stacked structure 301, the stacked structure 302, and the like with an insulating material such as SiO2, SiON, SiN, or the like. Further, a through hole (an opening) is provided in the protective layer 90 on the n ohmic electrode (n ohmic electrode 321, n ohmic electrode 323, n ohmic electrode 324, and the like) and the p ohmic electrode (p ohmic electrode 331, p ohmic electrode 332, and the like). Further, a wiring (power supply line 71, first transfer signal line 72, second transfer signal line 73, lighting signal line 75, and the like) and a back electrode 91 which connect the n ohmic electrode (n ohmic electrode 321, n ohmic electrode 323, n ohmic electrode 324, and the like) and the p ohmic electrode (p ohmic electrode 331, p ohmic electrode 332, and the like) via the through hole provided in the protective layer 90 are formed. The wiring and the back electrode 91 are Al, Au, or the like.

[0162] The light emitting chip C is manufactured as described above.

[0163] In addition, for the substrate 80, a semiconductor substrate including InP, GaN, InAs, other III-V group, II-VI material, sapphire, Si, Ge, or the like can also be used. In the case where the substrate is changed, the material of the semiconductor stacked body laminated on the substrate in a monolithic manner uses a material that substantially matches the lattice constant of the substrate (including a strained structure, a strain relaxation layer, metamorphic growth). As an example, InAs, InAsSb, GaInAsSb, or the like is used on an InAs substrate, InP, InGaAsP, or the like is used on an InP substrate, GaN, AlGaN, InGaN, or the like is used on a GaN substrate or a sapphire substrate, Si, SiGe, GaP, or the like is used on a Si substrate. However, in the case where the crystal is grown and then attached to another support substrate, the semiconductor material does not need to be substantially lattice-matched with respect to the support substrate.

[0164] (a) to (c) of FIG. 12 are enlarged views of the laminated structure 301 in which the surface-emission laser element VCSEL and the set thyristor S are laminated, in the light-emitting chip C to which the present embodiment is applied.

[0165] Figure 7 (a) to (c) of FIG. 12 are enlarged views of the laminated structure 301 in which the surface-emission laser element VCSEL and the set thyristor S are laminated, in the light-emitting chip C to which the present embodiment is applied. Figure 7 (a) of FIG. 12 is a plan view of the laminated structure 301, Figure 7 (b) of FIG. 12 is a cross-sectional view taken along the line VIIB-VIIB of (a) of FIG. 12, Figure 7 (c) of FIG. 12 is a cross-sectional view taken along the line VIIC-VIIC of (a) of FIG. 12. In the laminated structure 301, the surface-emission laser element VCSEL and the set thyristor S are laminated. In addition, Figure 7 (a) of FIG. 12, Figure 7 (b) of FIG. 12, and Figure 7 (c) of FIG. 12, the protective layer 90 and the lighting signal line 75 are omitted. Figure 7 Figure 7 As shown in (a) of FIG. 12, eight hole portions 55 are provided in the laminated structure 301. The hole portions 55 are provided in such a manner that the n-cathode layer 88, the p-gate layer 87, the n-gate layer 86, the p-anode layer 85, the tunnel junction layer 84, the n-cathode (DBR) layer 83, the light-emitting layer 82, and the p-anode (DBR) layer 81 are removed by etching to reach the substrate 80, as shown in (b) of FIG. 12. Figure 7

[0166] As shown in (a) of FIG. 12, eight hole portions 55 are provided in the laminated structure 301. The hole portions 55 are provided in such a manner that the n-cathode layer 88, the p-gate layer 87, the n-gate layer 86, the p-anode layer 85, the tunnel junction layer 84, the n-cathode (DBR) layer 83, the light-emitting layer 82, and the p-anode (DBR) layer 81 are removed by etching to reach the substrate 80, as shown in (b) of FIG. 12. Figure 7 Figure 7 Figure 7 ​​​​In (a), the front end of the oxidized portion (current blocking portion β) extending from the orifice 55 toward the outlet 50 (where the opening 51 is provided) is indicated by a dashed line. That is, the central portion surrounded by the eight orifices 55 is the unoxidized portion (current passing portion α).

[0167] like Figure 7 (b) and Figure 7 As shown in (c), except for the current passage α of the outlet 50, the current narrowing layer 81b is oxidized from the adjacent holes 55 and the outer side of the stacked structure 301.

[0168] like Figure 8 As shown in (a), multiple apertures 55 are arranged on a circle 56 that surrounds the emission port 50, thereby making the planar shape of the unoxidized portion (current passage α) nearly circular. In a surface-emitting laser element (VCSEL), the smaller the diameter of the emission port 50, the easier it is for it to oscillate in a single mode, and the more likely the intensity distribution is to become a single peak. Therefore, it is preferable that the multiple apertures 55 are arranged on the circle 56, and that the current passage α is nearly circular.

[0169] The p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88 of the stacked structure 301, excluding the opening 51 and the hole 55, function as a setting thyristor S. Furthermore, the n-cathode (DBR) layer 83, the light-emitting layer 82, and the upper p-anode (DBR) layer 81c, located above the narrower current layer 81b, function as current paths. Therefore, the larger the area of ​​the stacked structure 301 excluding the opening 51 and the hole 55, the smaller the resistance to the current flowing from the setting thyristor S to the surface-emitting laser element (VCSEL). Therefore, the number of holes 55 can be set based on the shape of the unoxidized portion (current-passing portion α) and the resistance of the current path flowing from the setting thyristor S to the surface-emitting laser element (VCSEL) via the tunneling junction layer 84. Additionally, the number of holes 55 need to be at least four. Moreover, the planar shape of the holes 55... Figure 8 In (a), it is set to a square, but it can also be a circle, rectangle, or other shapes. When the planar shape of the hole 55 is a square, the side length can be about 5μm.

[0170] <Tunneling Strata 84>

[0171] Figure 8 (a) to Figure 8 (c) is a diagram further illustrating the stacked structure of the surface-emitting laser element VCSEL and the set thyristor S. Figure 8 (a) is a schematic energy band diagram of the stacked structure of a surface-emitting laser element (VCSEL) and a thyristor (S). Figure 8 (b) is the band structure diagram of tunnel junction 84 under reverse bias.Figure 7 (c) represents the current-voltage characteristics of the tunnel junction 84.

[0172] like Figure 7 As shown in the band diagram of (a), when for Figure 8 (a) to Figure 8 When a voltage is applied between the n-ohm electrode 321 and the back electrode 91 to make the surface-emitting laser element VCSEL and the set thyristor S a forward bias, the n-ohm of the tunneling junction layer 84... ++ Layer 84a and p ++ The layers 84b are reverse biased.

[0173] Tunneling layer 84 is composed of a high concentration of n-type impurities. ++ Layer 84a and p with high concentration of p-type impurities ++ The junction of layer 84b. Therefore, if the width of the depletion region is narrow and it is forward biased, electrons will escape from n... ++ The conduction band on the 84a side tunnels to p ++ The valence band on the 84b side exhibits negative resistance characteristics.

[0174] On the other hand, such as Figure 8 As shown in (b), when the tunnel junction 84 (tunnel junction) is subjected to a reverse bias (-V), p ++ The valence band potential Ev on the 84b side is higher than that on the n side. ++ The potential Ec of the conduction band (conduction band) on the 84a side increases. Furthermore, electrons move from p... ++ The valence electron band (valence band) of layer 84b tunnels to n. ++ The conduction band (conduction band) on the 84a side. Furthermore, the greater the reverse bias voltage (-V), the easier it is for electrons to tunnel through. That is, as... Figure 5 As shown in (c), current flows easily through the tunnel junction 84 (tunnel junction) under reverse bias.

[0175] Therefore, such as Figure 6 As shown in (a), when the set thyristor S is turned on, even if the tunneling junction 84 is reverse biased, current will flow between the surface-emitting laser element VCSEL and the set thyristor S. As a result, the surface-emitting laser element VCSEL emits light (lights up).

[0176] As described later, when the connected transmission thyristor T is turned on and becomes in the conducting state, the thyristor S is configured to become a state that can be switched to the conducting state. Furthermore, when the lighting signal... As will be described later, when it becomes "L", the thyristor S is set to be on and becomes an on state, and the surface-emission laser element VCSEL is caused to emit light (set to emit light). Thus, in the present specification, it is referred to as "set thyristor".

[0177] Further, the lower diode UD has the same relationship with the transfer thyristor T as the surface-emission laser element VCSEL has with the set thyristor S. However, the light emission from the lower diode UD is not used. Thus, in the case where the light emission from the lower diode UD sometimes becomes a leak light, the size of the lower diode UD can be reduced, or light shielding can be performed by using a material constituting a wiring or the like.

[0178] Further, instead of the tunnel junction layer 84, a III-V compound layer having metallic conductivity and epitaxially grown on a III-V compound semiconductor layer can be used. As an example of a material of the metallic conductivity III-V compound layer, InNAs described as an example is negative in band gap energy in a range where the composition ratio x of InN is about 0.1 to about 0.8. Further, InNSb is negative in band gap energy in a range where the composition ratio x of InN is about 0.2 to about 0.75. Being negative in band gap energy means not having a band gap. Thus, it exhibits the same conduction characteristics (conductivity) as a metal. That is, the so-called metallic conduction characteristics (conductivity) means that a current can flow as long as there is a gradient in the same potential as a metal.

[0179] Further, the lattice constant of the III-V compound (semiconductor) such as GaAs, InP, and the like is in the range of about Further, the lattice constant is close to the lattice constant of Si, that is, about The lattice constant of Ge is about

[0180] In contrast, the lattice constant of InN, which is also a III-V compound, is about The lattice constant of InAs is about Thus, the lattice constant of the compound of InN and InAs, that is, InNAs, can become a value close to that of GaAs or the like.

[0181] Further, the lattice constant of InSb, which is a III-V compound, is about Thus, since the lattice constant of InN is about Thus, the lattice constant of the compound of InSb and InN, that is, InNSb, can become a value close to that of GaAs or the like.

[0182] ​​That is, InNAs and InNSb are epitaxially grown as a monolithic layer with respect to a layer of a Group III-V compound (semiconductor) such as GaAs. Also, a layer of a Group III-V compound (semiconductor) such as GaAs can be stacked as a monolithic layer by epitaxial growth on a layer of InNAs or InNSb.

[0183] Thus, if the thyristor S and the surface-emission laser element VCSEL are stacked in series connection by a metal conductive Group III-V compound layer instead of the tunnel junction layer 84, the n-cathode (DBR) layer 83 of the surface-emission laser element VCSEL and the p-anode layer 85 of the thyristor S can be prevented from being reverse-biased.

[0184] <Thyristor>

[0185] Next, the basic operation of the thyristor (transfer thyristor T, set thyristor S) will be described. As described above, the thyristor is a semiconductor element having three terminals of an anode terminal (anode), a cathode terminal (cathode), and a gate terminal (gate), and is configured by stacking, for example, a p-type semiconductor layer (p-anode layer 85, p-gate layer 87) and an n-type semiconductor layer (n-gate layer 86, n-cathode layer 88) including GaAs, GaAlAs, AlAs, and the like on a substrate 80. That is, the thyristor has a pnpn structure. Here, the forward potential (diffusion potential) Vd of the pn junction including the p-type semiconductor layer and the n-type semiconductor layer will be described as 1.5 V as an example.

[0186] Hereinafter, as an example, the reference potential Vsub supplied to the back electrode 91 (see FIG. 2 (a) and FIG. 2 (b)) as a Vsub terminal will be described as 0 V as a high-level potential (hereinafter referred to as "H"), and the power supply potential Vgk supplied to the Vgk terminal will be described as -5 V as a low-level potential (hereinafter referred to as "L"). Thus, it is sometimes written as "H" (0 V), "L" (-5 V). Figure 6 Figure 5 Figure 3

[0187] First, the operation of the thyristor alone will be described. Here, the anode of the thyristor is assumed to be 0 V.

[0188] The thyristor in an off state in which no current flows between the anode and the cathode is turned on when a potential lower than the threshold voltage (a negative potential having a large absolute value) is applied to the cathode. Here, the threshold voltage of the thyristor is a value obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the gate.

[0189] ​​​When the thyristor is in the ON state, the gate of the thyristor is at a potential close to that of the anode terminal. Here, since the anode is 0V, the gate is 0V. Furthermore, the cathode of the thyristor in the ON state is at a potential close to the potential obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the anode potential. Here, since the anode is 0V, the cathode of the thyristor in the ON state is at a potential close to -1.5V (a negative potential with an absolute value greater than 1.5V). Additionally, the cathode potential is set based on its relationship to the power supply providing current to the thyristor in the ON state.

[0190] When a thyristor in the on state becomes in the off state (turn off) when the cathode becomes a potential higher than the potential required to maintain the on state (the potential close to -1.5V), it becomes a negative potential with a small absolute value, 0V or a positive potential.

[0191] On the other hand, when a potential lower than that required to maintain the conduction state (a negative potential with a large absolute value) is continuously applied to the cathode of a thyristor in the conduction state, and a current that can maintain the conduction state (maintaining current) is supplied, the thyristor maintains the conduction state.

[0192] Next, the operation of the surface-emitting laser element VCSEL and the set thyristor S in the stacked state will be explained.

[0193] The thyristor S is stacked and connected in series with a surface-emitting laser element (VCSEL). Therefore, the illumination signal... The potential is divided between the surface-emitting laser element VCSEL and the setting thyristor S. Here, the voltage applied to the surface-emitting laser element VCSEL will be temporarily set to -1.7V for explanation. Therefore, with the setting thyristor S in the off state, -3.3V is applied to the setting thyristor S.

[0194] As described above, when the absolute value of the threshold voltage of the setting thyristor S, which is in the off state, is less than -3.3V, the setting thyristor S is turned on. Current then flows to the surface-emitting laser element VCSEL connected in series with the setting thyristor S, and the surface-emitting laser element VCSEL emits light. On the other hand, when the absolute value of the threshold voltage of the setting thyristor S is less than -3.3V, the setting thyristor S remains off and remains in the off state. Therefore, the surface-emitting laser element VCSEL also remains off (off state).

[0195] Furthermore, when the set thyristor S is turned on, the absolute value of the voltage applied to the series-connected surface-emitting laser element VCSEL and the set thyristor S is affected by the current-limiting resistor RI (refer to...). Figure 4) and decreases. However, if the voltage applied to the set thyristor S is a voltage that maintains the on state of the set thyristor S, the set thyristor S maintains the on state. Thus, the surface-emission laser element VCSEL also continues to emit light.

[0196] In addition, the voltage shown above is an example, and will change depending on the emission wavelength or light amount of the surface-emission laser element VCSEL. At this time, the potential of the lighting signal may be adjusted.

[0197] In addition, the thyristor includes a semiconductor such as GaAs, and thus light is sometimes emitted between the n-gate layer 86 and the p-gate layer 87 in the on state. In addition, the amount of light emitted from the thyristor is determined depending on the area of the cathode and the current flowing between the cathode and the anode. Thus, in a case where light emission from the thyristor is not utilized, for example, the area of the cathode can be reduced, or light shielding can be performed by the material of the electrode (the n-ohmic electrode 321 in the set thyristor S1 or the n-ohmic electrode 323 in the transfer thyristor T1) or the wiring, and the like, thereby suppressing unnecessary light.

[0198] (Action of the light-emitting device 65)

[0199] Next, the action of the light-emitting device 65 will be described.

[0200] As described above, the light-emitting device 65 includes the light-emitting chips C1 to C40 (refer to (a) of FIG. 10 and (b) of FIG. 11). Figure 4 Figure 9 Figure 9

[0201] The light-emitting chips C1 to C40 are driven in parallel, and thus the action of the light-emitting chip C1 will be described.

[0202] <Time chart>

[0203] Figure 9 is a time chart that explains the action of the light-emitting device 65 and the light-emitting chip C.

[0204] Figure 9 In (a) of FIG. 12, the lighting (oscillation) or non-lighting of the five surface-emission laser elements VCSELs of the light-emitting chip C1, VCSEL1 to VCSEL5, is controlled (referred to as lighting control). In addition, in (b) of FIG. 12, the lighting or non-lighting of the five surface-emission laser elements VCSELs of the light-emitting chip C2, VCSEL1 to VCSEL5, is controlled. Figure 5 In (a) of FIG. 12, the lighting (oscillation) or non-lighting of the five surface-emission laser elements VCSELs of the light-emitting chip C1, VCSEL1 to VCSEL5, is controlled (referred to as lighting control). In addition, in (b) of FIG. 12, the lighting or non-lighting of the five surface-emission laser elements VCSELs of the light-emitting chip C2, VCSEL1 to VCSEL5, is controlled.

[0205] ​​​Figure 6 In the above, the time intervals are arranged alphabetically from time a to time k. Surface-emitting laser element VCSEL1 is controlled to be lit or not lit during period T(1) (lighting control), surface-emitting laser element VCSEL2 is controlled to be lit or not lit during period T(2) (lighting control), surface-emitting laser element VCSEL3 is controlled to be lit or not lit during period T(3) (lighting control), and surface-emitting laser element VCSEL4 is controlled to be lit or not lit during period T(4) (lighting control). The same lighting control is applied to surface-emitting laser elements VCSELs numbered 5 and above.

[0206] Here, periods T(1), T(2), T(3), ... are set as periods of the same length, and are called periods T when they are not distinguished.

[0207] right Terminal (refer to Figure 6 , Figure 5 (a) and Figure 6 (b)) The first transmission signal sent And to Terminal (refer to Figure 6 , Figure 4 (a) and Figure 4 (b)) The second transmission signal sent It is a signal with two potentials: "H" (0V) and "L" (-5V). Furthermore, the first transmitted signal... and the second transmission signal The waveform is repeated in units of two consecutive periods T (e.g., period T(1) and period T(2)).

[0208] In the following, "H" (0V) and "L" (-5V) will sometimes be omitted as "H" and "L".

[0209] First transmission signal At the beginning of period T(1), b changes from “H” (0V) to “L” (-5V), and at time f, it changes from “L” to “H”. Furthermore, at the end of period T(2), i changes from “H” to “L”.

[0210] Second transmission signal At the beginning of period T(1), time b is “H” (0V), and at time e, it changes from “H” (0V) to “L” (-5V). Furthermore, between the end of period T(2) and time j, it changes from “L” to “H”.

[0211] If the first transmission signal With the second transmission signal The second transmitted signal is compared. This is equivalent to making the first transmission signal The signal that has shifted backward by period T on the time axis. On the other hand, the second transmitted signal... During period T(1), the waveform shown by the dashed line and the waveform during period T(2) are repeated after period T(3). Second transmission signal The waveform of period T(1) is different from that of period T(3) and later because period T(1) is the period during which the light-emitting device 65 starts to operate.

[0212] As will be described later, the first transmission signal With the second transmission signal This set of transmission signals propagates the conduction state of the transmission thyristor T in numerical order, thereby designating the surface-emitting laser element VCSEL with the same number as the transmission thyristor T in the conduction state as the object to be lit (oscillated) or not lit (lighting control).

[0213] The following explains the LED chip C1. Light-up signal sent by the terminal In addition, lighting signals are sent to the other light-emitting chips C2 to C40 respectively. ~Light up signal Light up signal It is a signal with two potentials: "H" (0V) and "L" (-5V).

[0214] Here, during the lighting control period T(1) of the surface-emitting laser element VCSEL1 for the light-emitting chip C1, the lighting signal is... Explanation. Light-up signal. During the period T(1), the initial time b is "H" (0V), and at time c it changes from "H" (0V) to "L" (-5V). Furthermore, at time d it changes from "L" to "H", and at time e it remains "H".

[0215] Reference Figure 5 (a) and Figure 9 (b) Figure 4 ,pass Figure 4 The timing diagram shown illustrates the operation of the light-emitting device 65 and the light-emitting chip C1. Furthermore, the following describes the periods T(1) and T(2) for controlling the illumination of the surface-emitting laser element VCSEL1 and the surface-emitting laser element VCSEL2.

[0216] (1) Time a

[0217] <Light-emitting device 65>

[0218] At time a, the reference potential supply unit 160 of the signal generation circuit 110 of the light-emitting device 65 sets the reference potential Vsub to "H" (0V). The power supply potential supply unit 170 sets the power supply potential Vgk to "L" (-5V). Therefore, the power line 200a on the circuit board 62 of the light-emitting device 65 becomes "H" (0V) of the reference potential Vsub, and the Vsub terminals of each of the light-emitting chips C1 to C40 become "H". Similarly, the power line 200b becomes "L" (-5V) of the power supply potential Vgk, and the Vgk terminals of each of the light-emitting chips C1 to C40 become "L" (see reference). Figure 5 (a) and Figure 4 (b)). Therefore, the power lines 71 of each of the light-emitting chips C1 to C40 become "L" (see reference). Figure 4 ).

[0219] Furthermore, the transmission signal generation unit 120 of the signal generation circuit 110 transmits the first transmission signal. Second transmission signal They are respectively set to "H" (0V). Therefore, the first transmission signal line 201 and the second transmission signal line 202 become "H" (refer to...). Figure 5 (a) and Figure 4 (b)). Therefore, each of the light-emitting chips C1 to C40... Terminals and The terminal is designated "H". It is connected to the current-limiting resistor R1. The potential of the first transmission signal line 72 of the terminal is also called "H", and it is connected to the current limiting resistor R2. The second transmission signal line 73 of the terminal is also called "H" (see reference). Figure 4 ).

[0220] Furthermore, the lighting signal generation unit 140 of the signal generation circuit 110 generates a lighting signal. ~Light up signal Each is set to "H" (0V). Therefore, signal lines 204-1 to 204-40 become "H" (refer to...). Figure 5 (a) and Figure 9 (b)). Therefore, each of the light-emitting chips C1 to C40... The terminal, designated "H" via the current-limiting resistor RI, is connected to... The terminal's lighting signal line 75 is also designated as "H" (0V) (see reference). Figure 9 ).

[0221] <Light-emitting chip C1>

[0222] The anode (p-anode layer 85) of the set thyristor S is connected to the cathode (n-cathode (DBR) layer 83) of the surface-emission laser element VCSEL via the tunnel junction layer 84, and the anode (p-anode (DBR) layer 81) of the surface-emission laser element VCSEL is connected to the Vsub terminal set to "H".

[0223] The anode (p-anode layer 85) of the transfer thyristor T is connected to the cathode (n-cathode (DBR) layer 83) of the lower diode UD via the tunnel junction layer 84, and the anode (p-anode (DBR) layer 81) of the lower diode UD is connected to the Vsub terminal set to "H".

[0224] The cathodes of the odd-numbered transfer thyristors Tl, T3, T5,... are connected to the first transfer signal line 72 and set to "H" (0 V). The cathodes of the even-numbered transfer thyristors T2, T4, T6,... are connected to the second transfer signal line 73 and set to "H". Thus, the anodes and the cathodes of the transfer thyristors T both become "H" and are in an off state. Also, the anodes and the cathodes of the lower diodes UD both become "H" and are in an off state.

[0225] The cathode terminal of the set thyristor S is connected to the lighting signal line 75 set to "H" (0 V). Thus, the anodes and the cathodes of the set thyristor S both become "H" and are in an off state. Also, the anodes and the cathodes of the surface-emission laser element VCSEL both become "H" and are in an off state.

[0226] As described above, the gate Gtl is connected to the cathode of the start diode SD. The gate Gtl is connected to the power supply line 71 of the power supply potential Vgk ("L" (-5 V)) via the power supply line resistor Rgl. Also, the anode terminal of the start diode SD is connected to the second transfer signal line 73 and to the "H" (0 V) of the power supply line 71 via the current-limiting resistor R2. Terminals. Therefore, the startup diode SD is forward biased, and the cathode (gate Gt1) of the startup diode SD becomes -1.5V, obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the anode potential ("H" (0V)) of the startup diode SD. Furthermore, when the gate Gt1 becomes -1.5V, since the anode (gate Gt1) is -1.5V and the cathode is connected to the power line 71 ("L" (-5V)) via the power line resistor Rg2, the coupling diode D1 becomes forward biased. Therefore, the potential of the gate Gt2 becomes -3V, obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential of the gate Gt1 (-1.5V). Furthermore, the anode (gate Gt1) of the coupling diode D2 is -3V, and the cathode is connected to the power line 71 ("L" (-5V)) via the power line resistor Rg2, thus becoming forward biased. Therefore, the potential of gate Gt3 becomes -4.5V, obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential of gate Gt2 (-3V). However, the effect of the anode of the startup diode SD being "H" (0V) does not affect gate Gts numbered 4 and above, whose potentials become the potential of power line 71, i.e., "L" (-5V).

[0227] Furthermore, since gate Gt is gate Gs, the potential of gate Gs is the same as the potential of gate Gt. Therefore, the threshold voltage of the transmission thyristor T and the setting thyristor S is the value obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potentials of gate Gt and gate Gs. That is, the threshold voltage of the transmission thyristor T1 and the setting thyristor S1 is -3V, the threshold voltage of the transmission thyristor T2 and the setting thyristor S2 is -4.5V, the threshold voltage of the transmission thyristor T3 and the setting thyristor S3 is -6V, and the threshold voltage of the transmission thyristor T and the setting thyristor S numbered 4 and above is -6.5V.

[0228] (2) Time b

[0229] exist Figure 10 At time b, the first transmission signal is shown. The voltage changes from "H" (0V) to "L" (-5V). This activates the light-emitting device 65.

[0230] When the first transmission signal When the signal changes from "H" to "L", the potential of the first transmission signal line 72 is transmitted via... The voltage applied to the transfer thyristor Tl becomes -3.3 V, and thus the transfer thyristor Tl of which the threshold voltage is -3 V turns on. At this time, the current flows in the lower diode UDl to turn from the off state to the on state. By the turn-on of the transfer thyristor Tl, the potential of the first transfer signal line 72 becomes a potential close to -3.2 V, which is obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential at the anode of the transfer thyristor Tl (the potential applied to the lower diode UDl, i.e., -1.7 V) (a negative potential having an absolute value greater than 3.2 V).

[0231] In addition, the threshold voltage of the transfer thyristor T3 is -6 V, and the threshold voltage of the transfer thyristors T of odd numbers equal to or greater than 5 is -6.5 V. The voltage applied to the transfer thyristor T3 and the transfer thyristors T of odd numbers equal to or greater than 5 becomes -1.5 V, which is obtained by adding -3.2 V to the voltage 1.7 V applied to the surface-emission laser element VCSEL, and thus the transfer thyristor T3 and the transfer thyristors T of odd numbers equal to or greater than 5 do not turn on.

[0232] On the other hand, the transfer thyristors T of even numbers turn on because the second transfer signal line 73 is "H" (0 V) and the second transfer signal line 73 is "H" (0 V), and thus cannot turn on.

[0233] When the transfer thyristor Tl turns on, the potential of the gate Gtl / Gsl becomes the potential at the anode of the transfer thyristor Tl, i.e., "H" (0 V). Also, the potential of the gate Gt2 (gate Gs2) becomes -1.5 V, the potential of the gate Gt3 (gate Gs3) becomes -3 V, the potential of the gate Gt4 (gate Gs4) becomes -4.5 V, and the potential of the gates Gt (gates Gl) of odd numbers equal to or greater than 5 becomes "L".

[0234] Thus, the threshold voltage of the set thyristor Sl becomes -1.5 V, the threshold voltage of the transfer thyristor T2 and the set thyristor S2 becomes -3 V, the threshold voltage of the transfer thyristor T3 and the set thyristor S3 becomes -4.5 V, the threshold voltage of the transfer thyristor T4 and the set thyristor S4 becomes -6 V, and the threshold voltage of the transfer thyristors T and the set thyristors S of odd numbers equal to or greater than 5 becomes -6.5 V.

[0235] However, the first transfer signal line 72 becomes -1.5 V through the transfer thyristor Tl in the on state, and thus the transfer thyristors T of odd numbers in the off state do not turn on. Since the second transfer signal line 73 is "H" (0 V), the transfer thyristors T of even numbers do not turn on. Since the lighting signal line 75 is "H" (0 V), none of the surface-emission laser elements VCSEL is lit. ​

[0236] After time b (which refers to the time when the thyristor and other components change due to the potential change of the signal at time b and then become constant; the same applies to other cases), the transmission thyristor T1 and the lower diode UD1 are in the conducting state, while the other transmission thyristor T, the lower diode UD, the setting thyristor S, and the surface-emitting laser element VCSEL are in the off state.

[0237] (3) Time c

[0238] At time c, the signal is lit. The voltage changes from "H" (0V) to "L" (-5V).

[0239] When the signal is lit When changing from "H" to "L", the lighting signal line 75 passes through the current-limiting resistor RI and The terminal changes from "H" (0V) to "L" (-5V). Then, -3.3V, obtained by adding the 1.7V voltage applied to the surface-emitting laser element VCSEL, is applied to the setting thyristor S1. The setting thyristor S1, with a threshold voltage of -1.5V, is turned on, and the surface-emitting laser element VCSEL1 lights up (emits light). As a result, the potential of the lighting signal line 75 becomes close to -3.2V. Meanwhile, the threshold voltage of the setting thyristor S2 is -3V, but the voltage applied to the setting thyristor S2 is -1.5V, obtained by adding -3.2V to the 1.7V voltage applied to the surface-emitting laser element VCSEL. Therefore, the setting thyristor S2 is not turned on.

[0240] After time c, the transmission thyristor T1, the lower diode UD1, and the setting thyristor S1 are in the on state, and the surface-emitting laser element VCSEL1 is lit (emitting light).

[0241] (4) Time d

[0242] At time d, the signal is lit. The voltage changes from "L" (-5V) to "H" (0V).

[0243] When the signal is lit When the signal changes from "L" to "H", the potential of the lighting signal line 75 is controlled by the current-limiting resistor RI and... The terminal voltage changes from -3.2V to "H". Therefore, both the cathode of thyristor S1 and the anode of surface-emitting laser element VCSEL1 become "H", thus turning off thyristor S1 and extinguishing (not lighting) VCSEL1. The lighting period of surface-emitting laser element VCSEL1 is from the lighting signal... The time c from the transition from "H" to "L" until the lighting signal is activated. The lighting signal up to the moment d when it changes from "L" to "H". the period of "L".

[0244] After the time point d, the transfer thyristor Tl is in the on state.

[0245] (5) Time point e

[0246] At the time point e, the second transfer signal is changed from "H" (0 V) to "L" (-5 V). Here, the period T(l) of the lighting control of the opposite surface light emitting laser element VCSELl ends and the period T(2) of the lighting control of the opposite surface light emitting laser element VCSEL2 starts.

[0247] When the second transfer signal is changed from "H" to "L", the potential of the second transfer signal line 73 is changed from "H" to "L" via the terminal. As described above, the transfer thyristor T2 is turned on because the threshold voltage becomes -3 V. At this time, the current also flows in the lower diode UD2 and is changed from the off state to the on state.

[0248] Thus, the potential of the gate terminal Gt2 (gate terminal Gs2) becomes "H" (0 V), the potential of the gate Gt3 (gate Gs3) becomes -1.5 V, the potential of the gate Gt4 (gate Gs4) becomes -3 V, and the potential of the gate Gt4 (gate Gs4) becomes -4.5 V. Also, the potential of the gate Gt (gate Gs) numbered 6 or more becomes -5 V.

[0249] After the time point e, the transfer thyristor Tl, the transfer thyristor T2, the lower diode UDl, and the lower diode UD2 are in the on state.

[0250] (6) Time point f

[0251] At the time point f, the first transfer signal is changed from "L" (-5 V) to "H" (0 V).

[0252] When the first transfer signal is changed from "L" to "H", the potential of the first transfer signal line 72 is changed from "L" to "H" via the terminal. Then, the anode and the cathode of the transfer thyristor Tl in the on state both become "H" and are turned off. At this time, the anode and the cathode of the lower diode UDl also both become "H" and are changed from the on state to the off state.

[0253] Thus, the potential of the gate Gtl (the gate Gsl) is changed toward the power supply potential Vgk ("L" (-5 V)) via the power supply line resistance Rgl. By this, the coupling diode Dl becomes a state in which the potential is applied to the direction in which no current flows (reverse bias). Thus, the influence of the gate Gt2 (the gate Gs2) of "H" (0 V) no longer reaches the gate Gtl (the gate Gsl). That is, the threshold voltage of the transfer thyristor T having the gate Gt connected with the coupling diode D using the reverse bias becomes -6.5 V, and even if the first transfer signal or the second transfer signal becomes "L" (-5 V), the transfer thyristor T is no longer turned on.

[0254] After the time f, the transfer thyristor T2 and the lower diode UD2 are in the on state.

[0255] (7) Others

[0256] At the time g, when the lighting signal is changed from "H" (0 V) to "L" (-5 V), similarly to the surface-emitting laser element VCSELl and the set thyristor Sl at the time c, the set thyristor S2 is turned on and the surface-emitting laser element VCSEL2 is lit (emits light).

[0257] Also, at the time h, when the lighting signal is changed from "L" (-5 V) to "H" (0 V), similarly to the surface-emitting laser element VCSELl and the set thyristor Sl at the time d, the set thyristor S2 is turned off and the surface-emitting laser element VCSEL2 is extinguished.

[0258] Further, at the time i, when the first transfer signal is changed from "H" (0 V) to "L" (-5 V), similarly to the transfer thyristor Tl at the time b or the transfer thyristor T2 at the time e, the transfer thyristor T3 having a threshold voltage of -3 V is turned on. At the time i, the period T (2) during which the surface-emitting laser element VCSEL2 is controlled to be lit ends and the period T (3) during which the surface-emitting laser element VCSEL3 is controlled to be lit starts.

[0259] Hereinafter, the processing explained so far is repeated.

[0260] In addition, when the surface-emitting laser element VCSEL is not lit (emits light) but remains extinguished (not lit), as long as the lighting signal Figure 10 is changed as shown in the lighting signal at the time j to the time k of the period T (4) during which the surface-emitting laser element VCSEL4 is controlled to be lit The "H" (0 V) is maintained. By this, even if the threshold voltage of the set thyristor S4 is set to -1.5 V, the set thyristor S4 does not turn on, and the surface-emission laser element VCSEL4 remains turned off (not lit up).

[0261] As explained above, the gate terminals Gt of the transfer thyristors T are connected to each other through the coupling diodes D. Thus, when the potential of the gate Gt changes, the potential of the gate Gt connected to the gate Gt whose potential has changed changes through the forward-biased coupling diode D. Also, the threshold voltage of the transfer thyristor T having the gate whose potential has changed changes. The transfer thyristor T turns on when the threshold voltage is higher than -3.3 V (a negative value having a small absolute value) at the first transfer signal or the second transfer signal turns on at the timing of the transition from "H" (0 V) to "L" (-5 V).

[0262] Also, the set thyristor S to which the gate Gs and the gate Gt of the transfer thyristor T in the on state are connected turns on when the lit-up signal turns from "H" (0 V) to "Lo" (-5 V), and the surface-emission laser element VCSEL connected in series to the set thyristor S is lit up (emits light).

[0263] That is, by the transfer thyristor T becoming in the on state, the surface-emission laser element VCSEL designated as a lit-up control object is specified, and the lit-up signal turns on the set thyristor S connected in series to the surface-emission laser element VCSEL as a lit-up control object, and the surface-emission laser element VCSEL is lit up (emits light).

[0264] In addition, the lit-up signal maintains the set thyristor S in the off state, and the surface-emission laser element VCSEL is maintained not lit up. That is, the lit-up signal sets the lit up (emits light) / not lit up (does not emit light) of the surface-emission laser element VCSEL.

[0265] Thus, the lit-up signal is set according to the image data, and the lit up or not lit up of each surface-emission laser element VCSEL is controlled.

[0266] Also, the set thyristor S can be controlled so that the amount of light emission of the surface-emission laser element VCSEL maintained in the light emission state increases.

[0267] As explained above, the light emitting chip C is configured as a Self-Scanning Light Emitting Device (SLED).

[0268] (a) and (b) of FIG. 10 are enlarged views of the layer stack 301 in the light emitting chip C' shown for comparison, which is not applied to the present embodiment.

[0269] Next, the light emitting chip C' shown for comparison, which is applied to the present embodiment, will be explained. In the light emitting chip C', the structure of the layer stack 301 is different from that of the light emitting chip C applied to the present embodiment, but the other structures are the same. Thus, the different layer stack 301' will be explained, and the explanation of the same parts will be omitted. In addition, in the light emitting chip C', the same symbols are attached to the parts having the same functions as those of the light emitting chip C.

[0270] Figure 10 (a) and (b) of FIG. 10 are enlarged views of the layer stack 301 in the light emitting chip C' shown for comparison, which is not applied to the present embodiment. Figure 10 (a) of FIG. 10 is a plan view of the layer stack 301', Figure 10 (b) of FIG. 10 is a cross-sectional view taken along the XB-XB line of (a) of FIG. 10. Figure 10 (a) of FIG. 10 is a plan view of the layer stack 301', Figure 10 (a) of FIG. 10 is a plan view of the layer stack 301',

[0271] As shown in (a) and (b) of FIG. 10, the layer stack 301' of the light emitting chip C' is etched to the substrate 80 to be cylindrical. Also, the layer stack 301' does not include the hole part 55 provided in the layer stack 301 of the light emitting chip C. Thus, the current constriction layer 81b of the p-anode (DBR) layer 81 exposed to the outer edge part of the layer stack 301' is oxidized from the side surface of the current constriction layer 81b. Thus, the part not oxidized (current passing part a) is formed in a circular shape. Figure 10 (a) and (b) of FIG. 10 are enlarged views of the layer stack 301 in the light emitting chip C' shown for comparison, which is not applied to the present embodiment. Figure 10 (a) of FIG. 10 is a plan view of the layer stack 301', (a) and (b) of FIG. 10 are enlarged views of the layer stack 301 in the light emitting chip C' shown for comparison, which is not applied to the present embodiment.

[0272] (a) and (b) of FIG. 10 are enlarged views of the layer stack 301 in the light emitting chip C' shown for comparison, which is not applied to the present embodiment. Figure 7 (a) and (b) of FIG. 10 are enlarged views of the layer stack 301 in the light emitting chip C' shown for comparison, which is not applied to the present embodiment. Figure 7The area of the planar shape of the portion (part of the n cathode layer 88, the p gate layer 87, the n gate layer 86, the p anode layer 85) of the set thyristor S and the area of the planar shape of the tunnel junction layer 84 indicated in (b) will become smaller than Figure 7 the area of the planar shape of the portion (part of the n cathode layer 88, the p gate layer 87, the n gate layer 86, the p anode layer 85) of the set thyristor S and the area of the planar shape of the tunnel junction layer 84 indicated in (b) will become smaller than Figure 7 the area of the planar shape of the portion (the n cathode (DBR) layer 83, the light emitting layer 82, the p anode (DBR) layer 81c) of the current path from the set thyristor S toward the surface emitting laser element VCSEL indicated in (b) will also become smaller than Figure 10 the area of the planar shape of the portion (the n cathode (DBR) layer 83, the light emitting layer 82, the p anode (DBR) layer 81c) of the current path from the set thyristor S toward the surface emitting laser element VCSEL indicated in (b) will also become smaller than ​ the area of the planar shape of the portion (the n cathode (DBR) layer 83, the light emitting layer 82, the p anode (DBR) layer 81c) of the current path from the set thyristor S toward the surface emitting laser element VCSEL indicated in (b) will also become smaller than. In particular, since the resistance of the tunnel junction layer 84 is high, if the area of the tunnel junction layer 84 becomes small, the resistance of the path of the current from the set thyristor S toward the surface emitting laser element VCSEL via the tunnel junction layer 84 becomes large, and the operation becomes slow.

[0273] Further, as indicated in (a), in the laminated structure 301', the area of the portion of the p gate layer 87 exposed to set the p ohmic electrode 331 of the set thyristor S also becomes narrow. Therefore, if the area of the portion of the p ohmic electrode 331 of the set thyristor S is desired to be reduced to ensure the area of the portion of the p ohmic electrode 331 of the set thyristor S, the time of oxidation will become long. ​

[0274] As explained above, in the light emitting chip C to which the present embodiment is applied, the current constriction layer 81b is oxidized from the outer edge portion and the hole portion 55 of the laminated structure 301 to form the current stop portion β. Therefore, it is not necessary to reduce the area of the planar shape of the set thyristor S. Thus, even if the resistance of the tunnel junction layer 84 is high, the resistance of the path of the current from the set thyristor S toward the surface emitting laser element VCSEL via the tunnel junction layer 84 can be reduced. Moreover, since the oxidation is performed from the hole portion 55, it is not necessary to extend the time of oxidation. Furthermore, the area of the portion of the p gate layer 87 exposed to set the p ohmic electrode 331 of the set thyristor S is also difficult to be limited.

[0275] In the above, the current constriction layer 81b is provided to the p anode (DBR) layer 81. Therefore, the hole portion 55 is provided in a manner that the side surface of the current constriction layer 81b of the p anode (DBR) layer 81 is exposed. The current constriction layer can also be provided to the n cathode (DBR) layer 83. At this time, the hole portion 55 can be provided in a manner that the side surface of the current constriction layer provided to the n cathode (DBR) layer 83 is exposed.

[0276] ​Further, in the light emitting chip C to which the present embodiment is applied, the lower diode UD is included, but it can also be excluded. That is, as long as the p-anode (DBR) layer 81, the light emitting layer 82, the n-cathode (DBR) layer 83, and the tunnel junction layer 84 are removed by etching in the portion of the layered structure 302 constituting the lower diode UD, the layered p-anode layer 85, the n-gate layer 86, the p-gate layer 87, and the n-cathode layer 88 can be included.

[0277] In the light emitting chip C to which the present embodiment is applied, a surface emitting laser element VCSEL (light emitting element) is provided on the substrate 80, and a layered structure in which a thyristor S (thyristor) is layered on the surface emitting laser element VCSEL (light emitting element) is layered. A layered structure in which a thyristor is provided on a substrate and a light emitting element is provided on the thyristor can also be used.

[0278] Further, as the light emitting element, a surface emitting laser element VCSEL is used, but other light emitting elements such as a light emitting diode LED can also be used.

Claims

1. A light emitting component comprising: a substrate; a plurality of light emitting elements provided on the substrate, which emit light in a direction intersecting a surface of the substrate; and a plurality of thyristors respectively stacked on the plurality of light emitting elements, which drive the light emitting elements to emit light or increase the amount of light emission by becoming in an on state, the light emitting elements have a current narrow region which is oxidized via a plurality of hole portions provided in a stacked structure in which the light emitting elements and the thyristors are stacked and an outer edge portion of the stacked structure, the thyristors are stacked on the light emitting elements via a tunnel junction layer, the thyristors and the tunnel junction layer have the same area of a planar shape, the thyristors have an opening portion in a path of light toward the thyristors from the light emitting elements, in a case where an oxidation time and an area of an opening portion of a stacked structure which is cylindrical and does not have the hole portions and an oxidation time and an area of the opening portion of the stacked structure having the plurality of hole portions are set to be the same, an area of a planar shape of a tunnel junction layer of the stacked structure which is cylindrical and does not have the hole portions is smaller than the area of the planar shape of the tunnel junction layer of the stacked structure having the plurality of hole portions.

2. The light emitting component according to claim 1, wherein the plurality of hole portions are arranged in a circular shape around an exit port of light emission of the light emitting elements in the stacked structure.

3. The light emitting component according to claim 1 or 2, comprising: a plurality of transfer elements connected to the plurality of thyristors respectively, which sequentially transfer the on state and set the thyristors to be in the on state by becoming in the on state.

4. The light emitting component according to claim 1 or 2, the light emitting elements are vertical cavity surface emitting laser elements.

5. A light emitting component comprising: a substrate; a plurality of light emitting elements provided on the substrate, which emit light in a direction intersecting a surface of the substrate; and a plurality of thyristors respectively stacked between the substrate and the plurality of light emitting elements, which drive the light emitting elements to emit light or increase the amount of light emission by becoming in an on state, the light emitting elements have a current narrow region which is oxidized via a plurality of hole portions provided in a stacked structure in which the light emitting elements and the thyristors are stacked and an outer edge portion of the stacked structure, the thyristors are stacked on the light emitting elements via a tunnel junction layer, the thyristors and the tunnel junction layer have the same area of a planar shape, the thyristors have an opening portion in a path of light toward the thyristors from the light emitting elements, in a case where an oxidation time and an area of an opening portion of a stacked structure which is cylindrical and does not have the hole portions and an oxidation time and an area of the opening portion of the stacked structure having the plurality of hole portions are set to be the same, an area of a planar shape of a tunnel junction layer of the stacked structure which is cylindrical and does not have the hole portions is smaller than the area of the planar shape of the tunnel junction layer of the stacked structure having the plurality of hole portions. ​ ​

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