Directed interrupts for multi-level virtualization

Abstract

The present invention relates to a method for providing an interrupt signal to a first client operating system. A first interrupt signal with an interrupt target ID is received from a first bus connection module by a bus attachment device, and the interrupt target ID identifies a processor of the processor that is assigned to be used by the first client operating system as a first target processor for processing the first interrupt signal. The bus attachment device checks whether the first target processor is scheduled for use by the first client operating system. If the target processor is not scheduled for use, the bus attachment device forwards the interrupt signal using a broadcast and updates a forwarding vector entry stored in a memory segment assigned to a second client operating system hosting the first client operating system. The update is used to indicate to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be processed.

Description

Background Art

[0001] The present invention relates generally to interrupt processing within a computer system and, more particularly, to handling interrupts generated by bus connection modules in a multiprocessor computer system.

[0002] Interrupts are used to signal a processor that an event requires the processor's attention. For example, hardware devices (e.g., hardware devices connected to a processor via a bus) use interrupts to communicate that they require attention from an operating system. In the case where a receiving processor is currently performing some activity, the receiving processor can suspend its current activity in response to receiving an interrupt signal, save its state, and handle the interrupt, for example, by executing an interrupt handler. The interruption of the processor's current activity caused by receiving an interrupt signal is only temporary. After handling the interrupt, the processor can resume its suspended activity. Therefore, interrupts can improve performance by eliminating the non-productive waiting time of the processor waiting for external events in a polling loop.

[0003] In a multi-processor computer system, interrupt routing efficiency issues may arise. The challenge is to efficiently forward interrupt signals sent by hardware devices such as bus connection modules to processors among the multiple processors assigned to the operating system. This can be particularly challenging in the case where interrupts are used to communicate with a client operating system on a virtual machine. A hypervisor or virtual machine monitor (VMM) creates and runs one or more virtual machines, or guest machines. A virtual machine provides a guest operating system running on the same platform as the virtual operating platform while hiding the physical characteristics of the underlying platform. Using multiple virtual machines allows multiple operating systems to run in parallel. Because it is executed on the virtual operating platform, the client operating system has a limited view of the processor. Figure 1 The virtual processor ID (ID) used by the guest operating system is generally different from the underlying (e.g., physical view of the processor). The guest operating system uses a virtual processor ID (identifier) ​​to identify the processor, which is generally inconsistent with the underlying logical processor ID. The hypervisor that manages the execution of the guest operating system defines the mapping between the underlying logical processor ID and the virtual processor ID used by the guest operating system. However, this mapping and the selection of the processor scheduled for use by the guest operating system is not static, but can be changed by the hypervisor while the guest operating system is running without the knowledge of the guest operating system.

[0004] In the case of a non-native (i.e., hosted hypervisor), this challenge may be further increased. In this case, the hosted hypervisor may itself be running on an underlying client operating system that is executed on an underlying native hypervisor or on another hosted hypervisor. The underlying hypervisor may provide a first mapping of an underlying logical processor ID to a first virtual processor ID used by the underlying client operating system, while the hosted hypervisor may provide a second mapping of the first virtual processor ID to a second virtual processor ID. Again, the first and second mappings may generally not be static, but may change dynamically without knowledge of the first and / or second client operating systems that use the first and second virtual processor IDs, respectively.

[0005] This challenge is usually addressed by forwarding interrupt signals using broadcast. When broadcast is used, the interrupt signal is forwarded continuously between multiple processors until a processor suitable for handling the interrupt signal is encountered. However, in the case of multiple processors, the probability that the processor that first receives the broadcast interrupt signal is indeed suitable for handling the interrupt signal may be quite low. In addition, being suitable for handling the interrupt signal does not necessarily mean that the corresponding processor is the best choice for handling the interrupt. Summary of the invention

[0006] Various embodiments provide a method, a computer system and a computer program product for providing an interrupt signal to a client operating system executed using one or more processors of a plurality of processors of a computer system allocated for use by the client operating system as described by the subject matter of the independent claims. Advantageous embodiments are described in the dependent claims. The embodiments of the invention can be freely combined with each other insofar as they are not mutually exclusive.

[0007] On the one hand, the present invention relates to a method for providing an interrupt signal to a first client operating system, wherein the first client operating system is executed by one or more processors of a plurality of processors assigned to be used by the first client operating system of a computer system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory operably connected to the bus attachment device, each of the plurality of processors being assigned a logical processor ID used by the bus attachment device to address the corresponding processor, each of the plurality of processors assigned to be used by the first client operating system being further assigned an interrupt target ID used by the first client operating system and the one or more first bus connection modules to address the corresponding processor, the first client operating system being implemented using a second client operating system as a host for hosting the first client operating system, the memory comprising a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID in a first memory segment assigned to the first client operating system, each directional interrupt summary indicator being assigned to an interrupt target ID indicating whether there is a pending first interrupt signal addressed to the corresponding interrupt target ID, the memory comprising a forwarding vector in a second memory segment assigned to the second client operating system, the forwarding vector comprising a first set of forwarding vector entries, the first set of forwarding vector entries being for a directional interrupt summary vector. Each of the directional interrupt summary indicators to the interrupt summary vector includes a forwarding vector entry assigned to the corresponding directional interrupt summary indicator, each forwarding vector entry indicating whether to update the corresponding directional interrupt summary indicator to which it is assigned, so as to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID, the method comprising: receiving, by a bus-attached device from a first bus connection module, the first interrupt signal with an interrupt target ID, the interrupt target ID identifying one of the processors assigned to be used by the first client operating system as a first target processor for processing the first interrupt signal, checking, by the bus-attached device, whether the first target processor is scheduled for use by the first client operating system, and if the first target processor is scheduled for use by the first client operating system, the target processor is scheduled for use by the first client operating system, the bus-attached device converts the received interrupt target ID into a logical processor ID, and forwards the first interrupt signal to the first target processor for processing by directly addressing the first target processor with the logical processor ID generated by the conversion, otherwise, the bus-attached device forwards the first interrupt signal for processing to the first operating system using a broadcast, the broadcast comprising selecting, by the bus-attached device, a forwarding vector entry in a first set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that a directional interrupt summary indicator to which the selected forwarding vector entry is assigned is to be updated,In order to indicate to the first operating system that there is a first interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0008] On the other hand, the present invention relates to a computer system for providing an interrupt signal to a first client operating system, the first client operating system being executed by one or more processors of a plurality of processors of the computer system assigned to be used by the first client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory operably connected to the bus attachment device, each of the plurality of processors being assigned a logical processor ID used by the bus attachment device to address the corresponding processor, each of the plurality of processors assigned to be used by the first client operating system being further assigned an interrupt target ID used by the first client operating system and the one or more first bus connection modules to address the corresponding processor, the first client operating system being implemented using a second client operating system as a host for hosting the first client operating system, the memory comprising a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID in a first memory segment assigned to the first client operating system, each directional interrupt summary indicator being assigned to an interrupt target ID indicating whether there is a pending first interrupt signal addressed to the corresponding interrupt target ID, the memory comprising a forwarding vector in a second memory segment assigned to the second client operating system, the forwarding vector comprising a first set of forwarding vectors entries, the first set of forwarding vector entries for each of the directional interrupt summary indicators of the directional interrupt summary vector includes a forwarding vector entry assigned to the corresponding directional interrupt summary indicator, each forwarding vector entry indicates whether to update the corresponding directional interrupt summary indicator to which it is assigned, so as to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID, the computer system being configured to perform a method, the method comprising: receiving, by a bus-attached device from a first bus connection module, a first interrupt signal with an interrupt target ID, the interrupt target ID identifying one of the processors assigned to be used by the first client operating system as a first target processor for processing the first interrupt signal, by The bus-attached device checks whether the first target processor is scheduled for use by the first client operating system. If the first target processor is scheduled for use by the first client operating system, the bus-attached device converts the received interrupt target ID into a logical processor ID, and forwards the first interrupt signal to the first target processor for processing by directly addressing the first target processor with the logical processor ID generated by the conversion. Otherwise, the bus-attached device forwards the first interrupt signal for processing to the first operating system using a broadcast, wherein the broadcast includes selecting, by the bus-attached device, a forwarding vector entry in a first set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry.The selected forwarding vector entry indicates that the directional interrupt summary indicator assigned to the selected forwarding vector entry is to be updated to indicate to the first operating system that there is a first interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0009] On the other hand, the present invention relates to a computer program product for providing an interrupt signal to a first client operating system, the first client operating system being executed using one or more processors of a plurality of processors of a computer system assigned for use by the first client operating system, the computer system further comprising one or more bus connection modules, the one or more bus connection modules being operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory operably connected to the bus attachment device, each of the plurality of processors being assigned a logical processor ID used by the bus attachment device to address the corresponding processor, each of the plurality of processors assigned for use by the first client operating system being further assigned an interrupt target ID used by the first client operating system and the one or more first bus connection modules to address the corresponding processor, the first client operating system being implemented using a second client operating system as a host for hosting the first client operating system, the memory comprising a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID in a first memory segment assigned to the first client operating system, each directional interrupt summary indicator being assigned to an interrupt target ID indicating whether there is a pending first interrupt signal addressed to the corresponding interrupt target ID, the memory comprising a translation vector in a second memory segment assigned to the second client operating system The forwarding vector comprises a first set of forwarding vector entries, the first set of forwarding vector entries comprises a forwarding vector entry assigned to the corresponding directional interrupt summary indicator for each of the directional interrupt summary indicators of the directional interrupt summary vector, each forwarding vector entry indicates whether to update the corresponding directional interrupt summary indicator to which it is assigned, so as to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID, the computer program product comprises a computer-readable non-transitory medium, the computer-readable non-transitory medium is readable by a processing circuit and stores instructions for being executed by the processing circuit to perform a method, the method comprising: receiving, by a bus-attached device, a first bus connection module with an interrupt target ID. The first interrupt signal of D is received, the interrupt target ID identifies a processor among the processors that is assigned to be used by the first client operating system as a first target processor for processing the first interrupt signal, the bus-attached device checks whether the first target processor is scheduled for use by the first client operating system, if the first target processor is scheduled for use by the first client operating system, the bus-attached device converts the received interrupt target ID into a logical processor ID, and forwards the first interrupt signal to the first target processor for processing by directly addressing the first target processor with the logical processor ID generated by the conversion, otherwise, the bus-attached device forwards the first interrupt signal for processing to the first operating system using broadcast,The broadcast includes selecting, by the bus-attached device, a forwarding vector entry of a first set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that a directed interrupt summary indicator to which the selected forwarding vector entry is assigned is to be updated to indicate to the first operating system that there is a first interrupt signal addressed to the corresponding interrupt target ID to be processed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the following, embodiments of the invention are explained in more detail, by way of example only, with reference to the accompanying drawings, in which:

[0011] Figure 1 depicts a schematic diagram of an exemplary computer system,

[0012] Figure 2 depicts a schematic diagram of an exemplary virtualization scheme,

[0013] Figure 3 depicts a schematic diagram of an exemplary virtualization scheme,

[0014] Figure 4 depicts a schematic diagram of an exemplary computer system,

[0015] Figure 5 depicts a schematic diagram of an exemplary computer system,

[0016] Figure 6 A schematic flow chart of an exemplary method is depicted,

[0017] FIG7 depicts a schematic flow chart of an exemplary method,

[0018] Figure 8 depicts a schematic diagram of an exemplary computer system,

[0019] Fig. 9 A schematic flow chart of an exemplary method is depicted,

[0020] Fig.10 A schematic diagram depicting an exemplary vector structure,

[0021] Fig.11 A schematic diagram depicting an exemplary vector structure,

[0022] FIG. 12 depicts a schematic diagram of an exemplary vector structure,

[0023] FIG. 13 depicts a schematic diagram of an exemplary vector structure,

[0024] Fig.14 is a schematic diagram of an exemplary data structure,

[0025] Fig.15 is a schematic diagram of an exemplary vector structure,

[0026] Fig.16 depicts a schematic diagram of an exemplary computer system,

[0027] Fig.17 depicts a schematic diagram of an exemplary computer system,

[0028] Fig.18 depicts a schematic diagram of an exemplary computer system,

[0029] Fig.19 depicts a schematic diagram of an exemplary computer system,

[0030] FIG20 depicts a schematic diagram of an exemplary unit, and

[0031] Fig.21 A schematic diagram of an exemplary computer system is depicted. DETAILED DESCRIPTION

[0032] The description of different embodiments of the present invention will be given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements in technology appearing in the market, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

[0033] The first-level hypervisor defines a first mapping of logical processor IDs to first virtual processor IDs, and the first virtual processor IDs are used by a client operating system running on a virtual machine provided by the hypervisor. A bus connection module that sends a request (e.g., including an interrupt signal) to the first-level client operating system can use one of the first virtual processor IDs as a target ID to identify a target processor for the request. According to an embodiment, instead of the first virtual processor ID, some other unique ID derived from the first virtual processor ID and / or explicitly assigned to the corresponding first virtual processor ID can also be used.

[0034] In the case where the second-level hypervisor runs on the first-level client operating system, the second-level hypervisor can provide a virtual machine on which the second-level client operating system runs. The second-level hypervisor can further define a second mapping of a first virtual processor ID used by the first-level client operating system hosting the second-level client operating system with the second-level client operating system to a second virtual processor ID used by the second-level client operating system. The bus connection module that sends a request (e.g., including an interrupt signal) for the second-level client operating system can use one of the second virtual processor IDs as a target ID to identify the target processor of the request. According to an embodiment, instead of the second virtual processor ID itself, some other unique ID derived from the second virtual processor ID and / or explicitly assigned to the corresponding second virtual processor ID can also be used.

[0035] According to various embodiments, a bus connection module (eg, PCIe function) may be assigned to exactly one second-level client (if not assigned to a first-level client).

[0036] Embodiments may have the beneficial effect of minimizing the impact on existing multi-level hypervisor implementations.

[0037] According to an embodiment, one or more forwarding vectors are provided by the first level operating system. The forwarding vectors are stored in a memory segment reserved for use by the first level operating system. The number of forwarding vectors may depend on the number of second level operating systems running on the second level hypervisor. A forwarding vector for each second level client operating system may be provided, wherein each forwarding vector is assigned to one of the second client operating systems. An entry of a forwarding vector may be used to indicate the presence of an interrupt signal to be handled by the second level client operating system to which the corresponding forwarding vector is assigned.

[0038] The entries of the forwarding vector may each reference entries of one or more interrupt summary vectors assigned to the second-level guest operating system. Each interrupt summary vector is stored in a memory segment reserved for use by the second-level operating system to which the corresponding interrupt summary vector is assigned.

[0039] The forwarding vectors include entries assigned to interrupt target IDs, which are used by the one or more bus connection modules to identify a target processor assigned for use by the second-level client operating system to which the corresponding forwarding vector is assigned as a target for the interrupt signal. The entries of the corresponding forwarding vectors additionally each reference an entry of an interrupt summary vector of the second-level client operating system assigned to the same target processor. Interrupt summary vectors having entries assigned to individual target processors can be used as direct interrupt summary vectors because their entries provide direct references to individual target processors.

[0040] An entry of a forwarding vector assigned to a target processor identified by a target ID may be updated by the bus-attached device to indicate that there is an interrupt signal to be processed by the second-level guest operating system using the corresponding target processor. Based on a reference to an entry of a direct interrupt summary vector in a memory segment of the second-level guest operating system, it may be determined whether there is an interrupt signal to be processed by the target processor assigned for use by the second-level guest operating system. For example, from the location of the referenced entry in the direct interrupt summary vector, the interrupt target ID of the target processor may be determinable.

[0041] The embodiment may have the following beneficial effects: Two at least partially similar vector structures are provided, one for the first-level client operating system, namely the forwarding vector, and the other for the second-level client operating system, namely the direct interrupt summary vector. Both vector structures include entries assigned to each other and to the target processor. Therefore, through the entries of these two vector structures, each of the client operating systems is provided with information about the processor on which the interrupt signal to be processed exists. In the case where no processor allocated for use by the second-level operating system is available, the first-level operating system can take over and determine the target of the interrupt signal to be processed based on the forwarding vector targeted by the target processor allocated for use by the second-level operating system. In the case where the target processor is deactivated, the first-level operating system can trigger the scheduling of the target processor so that it can process the corresponding interrupt signal.

[0042] Embodiments may have the beneficial effect of enabling a bus-attached device to directly address a target processor. Thus, an interrupt signal may be directed to a specific processor, i.e., a target processor of a multi-processor computer system, by a publishing bus connection module that selects a target processor ID. For example, a processor that has previously performed an activity related to an interrupt may be selected as the target processor for the interrupt signal. Processing an interrupt signal by the same processor as the corresponding activity may result in a performance advantage because, in the case where the same processor also processes the interrupt signal, all data in the context of the interrupt may already be available to that processor and / or stored in a local cache, enabling the corresponding processor to quickly access it without requiring a large amount of cache traffic.

[0043] Therefore, the broadcast of interrupt signals that cannot be guaranteed to ultimately handle the interrupt to the processor that is best suited for the task from a performance perspective (such as minimizing cache traffic) can be avoided. Instead of submitting the interrupt signal to all processors, each processor trying to handle the interrupt signal, and one processor winning, the interrupt signal can be directly provided to the target processor to improve the efficiency of interrupt signal processing.

[0044] The interrupt mechanism may be implemented using directed interrupts. A bus-attached device may be enabled to directly address a target processor using its logical processor ID when forwarding an interrupt signal to be processed to a target processor that issues the interrupt signal defined by a bus connection module. The conversion of the interrupt target ID to a logical processor ID by the bus-attached device may further ensure that the same processor is always addressed from the perspective of the client operating system, even though the mapping between the interrupt target ID and the logical processor ID or the selection of the processor scheduled for use by the client operating system may be controlled by the hypervisor.

[0045] When an interrupt cannot be delivered directly, for example because the hypervisor has not yet scheduled a target processor, the client operating system can benefit from using a broadcast to deliver an interrupt with the original intended relevance - that is, information about which processor the interrupt is intended for. In this case, the bus-attached device can set a bit in the DISB that specifies the target processor after setting the DIBV and before delivering the broadcast interrupt request to the client operating system. If the client operating system receives a broadcast interrupt request, it can therefore identify which target processors have pending interrupt signals signaled in the DIBV by scanning and disabling the direct interrupt summary indicators in the DISB (e.g., scanning and resetting the direct interrupt summary bits). The client operating system can thus be enabled to decide whether the interrupt signal is handled by the current processor receiving the broadcast or forwarded further to the original target processor.

[0046] According to an embodiment, the interrupt signal is received in the form of a message signaled interrupt containing an interrupt target ID of a target processor. Using message signaled interrupt (MSI) is a method in which a bus connection module (such as a peripheral component interconnect (PCI) or a peripheral component interconnect express (PCIe) function) generates a central processing unit (CPU) interrupt to notify the client operating system using the corresponding central processing unit of the occurrence of an event or the existence of a certain state. MSI provides an in-band method for signaling an interrupt using a special in-band message, thereby avoiding the need for a dedicated path separated from the main data path, such as a dedicated interrupt pin on each device, to send such control information. MSI instead relies on exchanging special messages indicating interrupts through the main data path. When the bus connection module is configured to use MSI, the corresponding module requests an interrupt by performing an MSI write operation of a specified number of bytes of data to a specific address. The combination of this specific address (i.e., MSI address) and a unique data value (i.e., MSI data) is called an MSI vector.

[0047] Modern PCIe standard adapters have the ability to submit multiple interrupts. For example, MSI-X allows the bus connection module to allocate up to 2048 interrupts. Thus, it is possible to direct individual interrupts to different processors, for example in high-speed networking applications that rely on multi-processor systems. MSI-X allows multiple interrupts to be allocated, each with a separate MSI address and MSI data value.

[0048] To transmit interrupt signals, MSI-X messages may be used. An MSI-X data table may be used to determine the required content of an MSI-X message. An MSI-X data table local to a bus connection module (i.e., a PCIe adapter / function) may be indexed by a number assigned to each interrupt signal, also known as an interrupt request (IRQ). The MSI-X data table content is controlled by the client operating system and may be set to the operating system under the guidance of hardware and / or firmware. A single PCIe adapter may include multiple PCIe functions, each of which may have an independent MSI-X data table. This may be the case, for example, for single root input / output virtualization (SR-IOV) or multifunction devices.

[0049] The interrupt target ID (such as, for example, a virtual processor ID) can be directly encoded as part of a message (such as an MSI-X message) sent by the bus connection module that includes the interrupt signal. The message (e.g., an MSI-X message) can include a requester ID, i.e., the ID of the bus connection module, the aforementioned interrupt target ID, a DIBV or AIBV index, an MSI address, and MSI data. The MSI-X message can provide 64 bits for the MSI address and 32 bits for the data. The bus connection module can use the MSI to request an interrupt by performing an MSI write operation of a specific MSI data value to a specific MSI address.

[0050] The device table is a shared table that can be fully indexed by the requester ID (RID) of the interrupt requester (i.e., the bus-attached module). The bus-attached device remaps and issues interrupts, i.e., the bus-attached device translates the interrupt target ID and uses the interrupt target ID to directly address the target processor.

[0051] A client operating system may use a virtual processor ID to identify a processor in a multi-processor computer system. Thus, a client operating system's view of a processor may differ from the view of the underlying system using logical processor IDs. A bus connection module that provides resources used by a client operating system may use a virtual processor ID as a resource for communicating with the client operating system, for example, an MSI-X data table may be under the control of the client operating system. As an alternative to a virtual processor ID, any other ID may be defined for the bus connection module to address a processor.

[0052] The interrupt is delivered to the client operating system or other software executing thereon, such as other programs, etc. As used herein, the term operating system includes operating system device drivers.

[0053] As used herein, the term bus connected module may include any type of bus connected module. According to an embodiment, a module may be a hardware module, such as a storage function, a processing module, a network module, a cryptographic module, a PCI / PCIe adapter, other types of input / output modules, etc. According to other embodiments, a module may be a software module, i.e., functions such as storage functions, processing functions, network functions, cryptographic functions, PCI / PCIe functions, other types of input / output functions, etc. Therefore, in the examples given herein, unless otherwise noted, modules are used interchangeably with functions (e.g., PCI / PCIe functions) and adapters (e.g., PCI / PCIe functions).

[0054] Embodiments may have the following benefits: Provide an interrupt signal routing mechanism (e.g., MSI-X message routing mechanism) that allows it to keep bus connection modules (e.g., PCIe adapters and functions) and device drivers for operating or controlling the bus connection modules unchanged. In addition, the hypervisor may be prevented from intercepting the underlying architecture used to implement communication between the bus connection module and the client operating system, such as the PCIe MSI-X architecture. In other words, changes to the interrupt signal routing mechanism may be implemented outside the hypervisor and the bus connection module.

[0055] According to an embodiment, a forwarding vector (also referred to herein as a forwarding DISB vector) for each second-level guest operating system may be provided in a memory segment allocated to the first-level guest operating system.

[0056] References between forwarding vectors and direct interrupt summary vectors (also referred to herein as DISB vectors and / or interrupt summary vectors (also referred to herein as AISB vectors)) can be implemented using a client interrupt table (GAIT) and / or a client interrupt status area (GISA), both of which are provided in a memory segment allocated to the first-level client operating system.

[0057] For example, each entry of the forwarding vector may reference an entry in the GAIT. The GAIT entries may each include a memory address indicator indicating an entry of the DISB vector or an entry of the AISB vector of the second-level client operating system. The GAIT entry may further provide an interrupt subclass ID of the second-level client operating system for an interrupt request directed to the second-level client operating system. In addition, a GISA for each client may be provided that hosts a pending interrupt indicator of a floating interrupt request directed to the second-level client operating system for each interrupt subclass of the second-level client operating system.

[0058] An individual entry (eg, bit) in the forwarding DISB can represent activity (ie, interrupt) of an individual target processor, which can be assigned to a single second-level guest operating system.

[0059] In addition, the forwarding DISB may include additional entries (e.g., additional bits), each of which may represent activity (i.e., interrupt requests) of an individual bus connection module (e.g., PCIe function) that may be assigned to an individual second-level client operating system.

[0060] The processor's firmware (e.g., millicode) can wake up the second-level guest operating system and enable entries in the DISB vector of the corresponding second-level guest operating system by scanning the forwarding DISB and GAIT provided by the first-level guest operating system, where the data lookup indicates which entry in the DISB vector of the corresponding second-level guest operating system is to be set so as to reflect information about which target processor an interrupt to be handled by the awakened second-level guest operating system exists.

[0061] Using this mechanism, a mapping may be made from any forwarding vector entry to any entry of the DISB vector of the same second-level guest operating system to which the forwarding vector is also assigned.

[0062] According to an embodiment, if the target processor for use by the first-level guest operating system and assigned to the corresponding entry is not running and the broadcast has been initialized, then the entry in the DISB vector of the first-level guest operating system may only need to be enabled, for example, one bit needs to be set.

[0063] The mechanism may be reused to enable entries in the DISB vector of a second-level guest operating system using a forwarding DISB vector assigned to the same second-level guest operating system and provided by the first-level guest operating system. If the target processor is not running and the broadcast has been initialized, then only entries of the forwarding DISB vector that reference entries of the DISB vector of the second-level guest operating system assigned to a single target processor may need to be enabled, e.g., one bit needs to be set.

[0064] Therefore, this mechanism can effectively map the interrupt target ID used by the first-level guest operating system to the interrupt target ID used by the second-level guest operating system.

[0065] According to an embodiment, the forwarding vector may include entries allocated to each bus connection module and entries allocated to each target processor.

[0066] According to an embodiment, the second memory segment further includes a client interrupt table, the client interrupt table includes a first group of client interrupt table entries, the first group of client interrupt table entries includes a directional interrupt summary address indicator for each of the directional interrupt summary indicators of the directional interrupt summary vector, wherein the corresponding directional interrupt summary address indicator indicates the memory address of the corresponding directional interrupt summary indicator in the second memory segment, and the client interrupt table is used to implement the allocation of the forwarding vector entries in the first group of forwarding vector entries, wherein each forwarding vector in the first group of forwarding vector entries is allocated a client interrupt table entry in the first group of client interrupt table entries, and the directional interrupt summary address indicator of the corresponding client interrupt table entry indicates the memory address of the directional interrupt summary to which the corresponding forwarding vector entry is allocated. According to an embodiment, the forwarding vector entries are each implemented in a single bit. The embodiment can have the beneficial effect of providing the forwarding vector entries in a form that is fast and efficiently processable with minimal memory space. According to an embodiment, the directional interrupt summary vector is implemented in a continuous area in the memory. The embodiment can have the beneficial effect of providing the interrupt summary vector in a form that is fast and efficiently processable with minimal memory space. The continuous area can be, for example, a single cache line. According to an embodiment, the directional interruption summary indicators are each implemented as a single bit. Embodiments may have the beneficial effect of providing directional interruption summary indicators in a form that minimizes memory space and is quickly and efficiently processable.

[0067] According to an embodiment, the memory further includes an interrupt table, the interrupt table having an interrupt table entry for each interrupt target ID, each of the interrupt table entries including a forwarding vector entry address indicator indicating a memory address of a corresponding forwarding vector entry in a second memory segment, wherein the method further includes: retrieving, by a bus-attached device, a copy of the interrupt table entry in the interrupt table assigned to the received interrupt target ID, the retrieved copy including a forwarding vector entry address indicator indicating the memory address of the forwarding vector entry in the second memory segment assigned to the received interrupt target ID; and selecting, by the bus-attached device, a forwarding vector entry address indicator contained in the retrieved copy of the interrupt table entry to assign to the received interrupt target ID.

[0068] According to an embodiment, the retrieved copy of the interrupt table entry also includes a mapping of the received interrupt target ID to the logical processor ID, and the method further includes: using the mapping included in the copy of the interrupt table entry by the bus-attached device to convert the received interrupt target ID to the logical processor ID.

[0069] Embodiments may have the beneficial effect of providing an interrupt table (IRT) comprising interrupt table entries (IRTEs), each entry providing a mapping of an interrupt target ID to a logical processor ID. Thus, the entry may define a unique assignment of each interrupt target ID to a logical processor ID. According to embodiments, the interrupt target ID may be provided in the form of a virtual processor ID. According to embodiments, the interrupt target ID may be any other ID used by a client operating system to identify the respective processor being used.

[0070] According to an embodiment, an IRT is provided in a memory for use by a bus-attached device to map an interrupt target ID to a logical processor ID. According to an embodiment, the IRT may be provided in a single location. An address indicator, such as a pointer, may be provided indicating the memory address of the IRT. The address indicator may be provided, for example, by an entry in a device table extracted from memory by the bus-attached device. An embodiment may have the beneficial effect of not having to store a large mapping table in the bus-attached device. Instead, the interrupt table used for mapping may be stored in a memory and accessed by the bus-attached device when necessary. Therefore, the bus-attached device may only need to process a working copy of one or more interrupt table entries for each interrupt signal to be forwarded. Preferably, the number of interrupt table entries may be small, such as one.

[0071] According to an embodiment, the IRT or individual IRTEs may be updated when a processor is rescheduled. According to an embodiment, the IRT may be stored in an internal section of memory (ie, the HSA).

[0072] According to an embodiment, a double fetch of IRTE may be performed to prevent an interrupt signal from being sent to a processor that has been deactivated at the same time, for example. According to various embodiments, after forwarding the interrupt signal to the processor identified by the logical processor ID generated by converting the interrupt target ID using the first copy of IRTE, a second copy of the same IRTE may be extracted to check whether any changes have occurred to IRTE at the same time. In the case where IRTE has been updated at the same time, there is a risk that the interrupt signal has been forwarded to the deactivated processor. Therefore, the interrupt target ID may be converted again with the second copy of IRTE, and the interrupt signal may be forwarded to the processor identified by the logical processor ID generated by the second conversion. According to an alternative embodiment, in the case where the second copy of IRTE does not match the first copy, the complete method starting from obtaining the first copy of IRTE may be repeated. For example, a third copy of IRTE may be extracted to replace the first copy of IRTE, or the first copy of IRTE may be replaced by the second copy of IRTE, and a third copy of IRTE may be extracted to implement a double fetch scheme also for partially repeating the method. This scheme may be repeated until a match is achieved. According to another alternative embodiment, in the case where the second copy of IRTE does not match the first copy, broadcasting may be used to forward the interrupt signal. According to an embodiment, the bus-attached device participates in a memory cache coherence protocol and detects changes on the IRTE through the same mechanism (eg, cache snooping) by which a CPU can detect cache line changes.

[0073] Embodiments may have the beneficial effect of avoiding cache flushes which may have inefficient scaling.Can be global or IRTE specific, ie the entire entry is double fetched or limited to specific information comprised by the corresponding entry.

[0074] According to an embodiment, the race condition caused by the time required to convert the interrupt target ID and forward the interrupt signal to the target processor until it reaches the processor can be captured by checking logic on the CPU to check whether the receiving processor is still the correct target processor until the interrupt signal reaches the processor. For inspection, the interrupt target ID and / or logical partition ID received with the interrupt request can be compared with the current interrupt target ID and / or logical partition ID assigned to the receiving processor as a reference. In the case of a match, the receiving processor directly addressed using the logical processor ID generated by the conversion of the copy of the IRTE is indeed the correct target processor. Therefore, the information provided by the copy of the IRTE is already up to date. In the case of a mismatch, the copy of the IRTE is not yet up to date, and the receiving processor is no longer the target processor. In the case of a mismatch, the interrupt signal can be forwarded to the target operating system, for example, using a broadcast.

[0075] According to an embodiment, there may be three entities operating in parallel, namely, a bus-attached device and a target processor that handles interrupt signals and a hypervisor that can change the assignment between interrupt target IDs and logical processor IDs. According to an embodiment, in a physically distributed system, there may be no central synchronization point other than a memory that provides a virtual appearance of such a system at the cost of latency. An embodiment using a double fetch scheme may have the beneficial effect of providing a method that is optimized for speed against double delivery or even loss of interrupt requests.

[0076] Regarding the interrupt signal, the following actions may be performed: A1) read a first copy of the IRTE, A2) send an interrupt request to the directly addressed processor, and A3) read a second copy of the IRTE. Meanwhile, regarding the change in the assignment between the interrupt target ID and the logical processor ID, the following sequence may occur: B1) activate an additional processor with the additional logical processor ID and deactivate the previous processor with the previous logical processor ID, and B2) update the IRTE with the additional logical processor ID, i.e., replace the previous logical processor ID with the additional logical processor ID.

[0077] In certain error situations, a processor (e.g., a target processor) may be reset to a checkpoint and lose intermediate information. To regain the lost information, the processor may scan all IRTE entries for that particular processor, i.e., assigned to its logical processor ID, and pass direct interrupt requests indicated by pending direct interrupt indicators (e.g., dPIA bits) present in memory that are not affected by processor recovery.

[0078] If an interrupt signal should be delivered, the pending direct interrupt indicator included by IRTE (e.g., the IRTE.dPIA bit) can be used as a master copy, i.e., a single point of truth. To simplify processor recovery, the pending direct interrupt indicator in the processor can be used as a shadow copy, such as the IRTE.dPIA bit, to maintain pending direct interrupts on the processor.

[0079] In the case of strict ordering of the memory, only the following order of steps A1, A2 and B1 may be possible: Alternative 1 with A1→A3→B1 and Alternative 2 with A1→B1→A3. In the case of Alternative 1, the first and second copies of IRTE may match. Therefore, the interrupt signal may be forwarded to the previous processor instead of the current target processor. The previous processor can see the mismatch of the interrupt target ID and / or logical partition ID and initiate a broadcast of the received interrupt signal. In the case of Alternative 2, the bus-attached device can see the mismatch between the first and second copies of IRTE. In response to the mismatch, the bus-attached device can broadcast the interrupt signal. Due to the broadcast, the interrupt signal can be received by additional processors that see the hit and directly handle the received interrupt request. An embodiment can have the beneficial effect of closing the timing window in an overly proactive manner.

[0080] According to an embodiment, the retrieved copy of the interrupt table entry further includes a run indicator indicating whether the first target processor identified by the interrupt target ID is scheduled for use by the first guest operating system, and the method further includes: using the run indicator included by the copy of the interrupt table entry by the bus-attached device to check whether the first target processor is scheduled for use by the first guest operating system. Embodiments can have the beneficial effect of preventing interrupts from being sent to a processor that is not running (i.e., a processor that is not scheduled for use by the guest operating system). Embodiments can have the beneficial effect of supporting the hypervisor to reschedule a processor.

[0081] The run indicator indicates whether the target processor identified by the interrupt target ID received with the interrupt signal is scheduled for use by the client operating system. The run indicator can be implemented, for example, in the form of a run bit, which is a single bit that indicates whether the processor assigned the corresponding bit is running (i.e., scheduled for use by the client operating system). Therefore, an enabled run bit can inform the bus-attached device that the target processor is currently scheduled, while a disabled run bit can inform the bus-attached device that the target processor is currently not scheduled. In the event that the target processor is not running, the bus-attached device can immediately send a backup broadcast interrupt request without attempting to directly address one of the processors.

[0082] According to an embodiment, the operation indicator is implemented as a single bit. Embodiments may have the beneficial effect of providing the operation indicator in a form that minimizes storage space and is quickly and efficiently processable.

[0083] According to an embodiment, a direct interrupt blocking indicator is introduced into an interrupt entry of an interrupt table in a memory. The direct interrupt blocking indicator may be implemented in the form of a single bit (ie, the dlBPIA bit).

[0084] According to an embodiment, IRTE is extracted from memory and the run indicator is checked to determine whether the target processor is scheduled. In the case where the target processor is scheduled, the direct interrupt blocking indicator is enabled to block the target processor from receiving another interrupt signal while processing the current interrupt signal. Other interrupt signals may interfere with the processing of the current interrupt signal in other ways. In order to ensure that the target processor has not been rescheduled in the meantime, IRTE is re-acquired and the current run indicator is checked again to determine whether the target processor is still scheduled. In the case where the target processor is still scheduled, the interrupt signal can be forwarded to the target processor using the logical processor ID of the target processor to directly address the target processor. In addition, it can be checked whether the logical processor ID of the target processor provided by IRTE for the received interrupt target ID is still the same.

[0085] According to an embodiment, the interrupt table is included by the second memory segment. The embodiment can have the beneficial effect of ensuring that there is sufficient memory space for processing the interrupt table even when the number of processors is huge. The embodiment can have the beneficial effect of providing a forwarding mechanism for multi-level virtualization to support direct interrupt forwarding and broadcasting. The embodiment can have the beneficial effect of storing the interrupt table assigned to the second-level client operating system in the memory segment assigned to the first-level client operating system.

[0086] According to an embodiment, the interrupt table assigned to the first-level guest operating system is stored in an internal section of memory also known as the hardware system area (HSA), which is a memory area reserved for hardware use. The HSA may include a fixed size and may be isolated from the client purchased memory (i.e., memory that can be allocated to the host and / or guest operating system).

[0087] According to an embodiment, an interrupt table entry for each interrupt target ID identifying a processor may be required. Therefore, the amount of memory required to store the interrupt table is related to the number of interrupt target IDs and may increase to a size that is difficult to handle with HSA.

[0088] Embodiments may further provide safety checks to prevent errors caused by unauthorized changes to the interrupt entry table by the first-level guest operating system or hypervisor, including the end of interrupt signaling from the operating system to the hardware. Since by storing the interrupt table in a memory segment allocated to the first-level operating system, there may be a risk that the first-level operating system changes the interrupt table.

[0089] According to an embodiment, an interrupt table providing a mapping between an interrupt target ID and a logical processor ID is stored in a memory segment allocated to an n-th level client operating system, where n≥1 (e.g., 1 or 2). A device table reserved for hardware stored in an internal segment of memory may include an entry allocated to a bus connection module that provides an address indicator (e.g., a pointer) indicating a memory address of an IRT in a memory segment allocated to an n-th level client operating system (e.g., a first-level client operating system).

[0090] According to an embodiment, the retrieved copy of the interrupt table entry also includes a first logical partition ID and a first client interrupt status area address indicator, wherein the first logical partition ID identifies the logical partition to which the first client operating system is assigned, and the first client interrupt status area address indicator indicates a memory address of a client interrupt status area in a second memory segment assigned to the first client operating system.

[0091] According to an embodiment, the method further includes retrieving, by the bus-attached device, a copy of a device table entry from the device table, the device table entry including an interrupt table address indicator indicating a memory address of the interrupt table, the bus-attached device using the memory address of the interrupt table to retrieve the first copy of the interrupt table entry.

[0092] According to an embodiment, the device table is stored in a third memory section of the memory, which is protected from access by the first and second operating systems. This section may be, for example, a HAS to ensure that the device table is prevented from being tampered with by any client operating system.

[0093] According to an embodiment, the retrieved copy of the device table entry also includes a second logical partition ID and a second client interrupt status area address indicator, the second logical partition ID identifying the logical partition to which the first client operating system is assigned, and the second client interrupt status area address indicator indicating a memory address of a client interrupt status area in a second memory segment assigned to the first client operating system, wherein the method further includes using a first combination of the first logical partition ID and the first client interrupt status area address indicator provided by the interrupt table entry by the bus-attached device to compare with a second combination of the second logical partition ID and the second client interrupt status area address indicator provided by the device table entry stored in a protected third memory segment, to check that the interrupt table entry stored in a second memory segment accessible to the second client operating system has not been changed by the second client operating system, and a match between the first combination and the second combination indicates that the interrupt table entry has not been changed.

[0094] Embodiments may have the beneficial effect of providing a safety mechanism to exclude that an interrupt table has been tampered with.

[0095] According to an embodiment, the device table entry further includes a logical partition ID identifying the logical partition to which the client operating system is assigned, and forwarding the first interrupt signal by the bus-attached device further includes forwarding the logical partition ID together with the first interrupt signal. Embodiments can have the beneficial effect of enabling a receiving processor to check which client operating system the interrupt signal is addressed to.

[0096] According to an embodiment, the device table entry further includes an interrupt subclass ID identifying an interrupt subclass to which the first interrupt signal is assigned, and forwarding the first interrupt signal by the bus-attached device further includes forwarding the interrupt subclass ID together with the first interrupt signal.

[0097] According to an embodiment, the second memory segment further includes a first directional interrupt signal vector assigned to each interrupt target ID of the corresponding interrupt target ID, each directional first interrupt signal vector includes a first interrupt signal indicator assigned to each first bus connection module of the first bus connection module, and each directional first interrupt signal vector indicates whether there is a first interrupt signal to be processed that is issued by the first bus connection module and addressed to the corresponding interrupt target ID, wherein the method further includes: selecting, by the bus attachment device, the directional first interrupt signal vector assigned to the interrupt target ID addressed by the first interrupt signal; selecting, by the bus attachment device, the directional first interrupt signal indicator assigned to the first bus connection module that issues the first interrupt signal in the selected directional first interrupt signal vector; and updating, by the bus attachment device, the selected directional first interrupt signal indicator so that the updated directional first interrupt signal indicator indicates that there is a first interrupt signal to be processed that is issued by the first bus connection module and addressed to the corresponding interrupt target ID.

[0098] The directional interrupt signal vectors are ordered according to the target processor ID, i.e., optimized for tracking directional interrupts. In other words, the primary order criterion is the target processor ID rather than the requester ID that identifies the bus connection module that issued the interrupt request. Depending on the number of bus connection modules, each directional interrupt signal vector may include one or more directional interrupt signal indicators.

[0099] Thus, sorting of interrupt signal indicators (e.g. in the form of interrupt signaling bits) indicating that a single interrupt signal (e.g. in the form of an MSI-X message) has been sequentially received within a contiguous region of memory (e.g., a cache line) of a single bus-connected module (e.g., a PCIe function) can be avoided. Enabling and / or disabling the interrupt signal indicator (e.g., by setting or resetting the interrupt signaling bit) requires transferring the corresponding contiguous region of memory to one of the processors to change the corresponding interrupt signal indicator accordingly.

[0100] A processor may process all indicators for which it is responsible from the perspective of the client operating system, i.e., in particular, all indicators assigned to the corresponding processor. This may achieve performance advantages because, in the case where each processor is processing all data assigned to the processor, the likelihood that the data required in this context is provided to the processor and / or stored in a local cache may be high, so that the processor's corresponding data can be quickly accessed without requiring a large amount of cache traffic.

[0101] However, each processor attempting to handle all indicators for which it is responsible may still result in higher cache traffic between processors, since each processor needs to write all cache lines for all functions, since the indicators assigned to each individual processor may be distributed over all contiguous areas, such as cache lines.

[0102] The interrupt signaling indicators can be reordered in the form of a directional interrupt signaling vector so that all interrupt signaling indicators assigned to the same interrupt target ID are combined in the same continuous area of ​​memory (e.g., cache line). Therefore, a processor that intends to process the indicator (i.e., interrupt target ID) assigned to the corresponding processor may only need to load a single continuous area of ​​memory. Therefore, a continuous area for each interrupt target ID is used instead of a continuous area for each bus connection module. Each processor may only need to scan and update a single continuous area of ​​memory, for example, a cache line of all interrupt signals targeted to a specific processor identified as the target processor by the interrupt target ID received from all available bus connection modules.

[0103] According to an embodiment, an offset may be applied by a hypervisor for a guest operating system to align bits to a different offset.

[0104] According to an embodiment, the second memory segment further includes an interrupt summary vector, the interrupt summary vector has an interrupt summary indicator for each bus connection module, each interrupt summary indicator is assigned to the bus connection module to indicate whether there is an interrupt signal issued by the corresponding bus connection module to be processed, the forwarding vector includes a second group of forwarding vector entries, the second group of forwarding vector entries includes a forwarding vector entry assigned to the corresponding directional interrupt summary indicator for each of the directional interrupt summary indicators of the directional interrupt summary vector, each forwarding vector entry indicates whether the corresponding interrupt summary indicator to which it is assigned is to be updated to indicate to the first operating system that there is a first interrupt signal issued by the corresponding bus connection module to be processed, wherein the method further includes: receiving, by the bus-attached device, a second interrupt signal with an interrupt target ID from the second bus connection module, the interrupt target ID identifying the processor assigned to be used by the first client operating system to process the second interrupt signal a processor of a second target processor of the bus-attached device, checking by the bus-attached device whether the second target processor is scheduled for use by the first client operating system, and if the second target processor is scheduled for use by the first client operating system, converting the received interrupt target ID into a logical processor ID by the bus-attached device, and forwarding the second interrupt signal to the second target processor for processing by directly addressing the second target processor with the logical processor ID generated by the conversion, otherwise, forwarding the second interrupt signal to the first operating system for processing by the bus-attached device using a broadcast, the broadcast including selecting by the bus-attached device a forwarding vector entry in a second group of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that the interrupt summary indicator assigned to it is to be updated, so as to indicate to the first operating system that there is a first interrupt signal issued by the second bus connection module to be processed.

[0105] According to an embodiment, the forwarding vector may further include additional entries assigned to the respective bus connection modules. These additional entries may thus indicate in which bus connection modules there are pending interrupt signals. In addition, these additional entries of the corresponding forwarding vector may each reference an entry of the interrupt summary vector of the second-level client operating system assigned to the same bus connection module.

[0106] The entry of the forwarding vector assigned to the bus connection module can be updated by the bus attachment device to indicate that there is an interrupt signal from the corresponding bus connection module to be processed by the second-level client operating system. Based on the reference to the entry of the direct interrupt summary vector in the memory segment of the second-level client operating system, it can be determined in which bus connection modules there is an interrupt signal to be processed by the second-level client operating system. For example, from the position of the referenced entry in the interrupt summary vector, the bus connection module that issued the corresponding interrupt signal can be determined.

[0107] According to an embodiment, a client interrupt table includes a second group of client interrupt table entries, the second group of client interrupt table entries includes an interrupt summary address indicator for each of the interrupt summary indicators of the interrupt summary vector, the corresponding interrupt summary address indicator indicates a memory address of the corresponding interrupt summary indicator in the second memory segment, and the client interrupt table is used to implement the allocation of forwarding vector entries in the second group of forwarding vector entries, wherein each forwarding vector in the second group of forwarding vector entries is allocated a client interrupt table entry in the second group of client interrupt table entries, and the directional interrupt summary address indicator of the corresponding client interrupt table entry indicates the memory address of the interrupt summary indicator to which the corresponding forwarding vector entry is allocated.

[0108] According to an embodiment, the second memory segment further includes an interrupt signal vector assigned to each bus connection module of the corresponding bus connection module, each interrupt signal vector includes an interrupt signal indicator assigned to each interrupt target ID of the corresponding bus connection module, and each interrupt signal vector indicates whether there is an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID to be processed, wherein the method further includes: the bus attachment device selects the directional interrupt signal vector assigned to the second bus connection module, the bus attachment device selects the interrupt signal indicator assigned to the interrupt target ID addressed to the second interrupt signal in the selected interrupt signal vector, and the bus attachment device updates the selected interrupt signal indicator so that the updated interrupt signal indicator indicates that there is an interrupt signal issued by the second bus connection module and addressed to the corresponding interrupt target ID to be processed.

[0109] According to an embodiment, the first client operating system is a client operating system of the second virtualization level, and the second client operating system is a client operating system of the first virtualization level. According to an embodiment, the first client operating system is a client operating system of the third virtualization level, and the second client operating system is a client operating system of the second virtualization level.

[0110] The embodiments may have the beneficial effect of implementing a multi-level virtualization solution.

[0111] According to an embodiment, instructions provided on a computer-readable non-transitory medium for execution by a processing circuit are configured to perform any embodiment of the method of providing an interrupt signal to a client operating system as described herein.

[0112] According to an embodiment, the computer system is further configured to perform any embodiment of the method of providing an interrupt signal to a client operating system as described herein.

[0113] Figure 1 An exemplary computer system 100 for providing interrupt signals to a client operating system is depicted. The computer system 100 includes a plurality of processors 130 for executing a client operating system. The computer system 100 also includes a memory 140, also referred to as a memory storage or a main memory. The memory 140 may provide a memory space, i.e., a memory segment, allocated for use by the hardware, firmware, and software components included in the computer system 100. The memory 140 may be used by the hardware and firmware of the computer system 100 and software (e.g., a hypervisor, a host / client operating system, an application, etc.). One or more bus connection modules 120 are operably connected to the plurality of processors 130 and the memory 140 via a bus 102 and a bus attachment device 110. The bus attachment device 110 manages the communication between the bus connection module 120 and the processor 130 on the one hand, and the communication between the bus connection module 120 and the memory 140 on the other hand. The bus connection module 120 may be connected to the bus 102 directly or via one or more intermediate components such as a converter 104.

[0114] The bus connection module 120 may be provided, for example, in the form of a Peripheral Component Interconnect Express (PCIe) module (also known as a PCIe adapter or a PCIe function provided by a PCIe adapter). The PCIe function 120 may issue a request that is sent to a bus attachment device 110, such as a PCI host bridge (PHB), also known as a PCI bridge unit (PBU). The bus attachment device 110 receives the request from the bus connection module 120. These requests may, for example, include an input / output address for performing a direct memory access (DMA) to the memory 140 by the bus attachment device 110 or an input / output address indicating an interrupt signal (e.g., a message signaled interrupt (MSI)).

[0115] Figure 2Depicted is exemplary virtual machine support provided by computer system 100. Computer system 100 may include one or more virtual machines 202 and at least one hypervisor 200. Virtual machine support may provide the ability to operate a large number of virtual machines, each capable of executing a client operating system 204, such as z / Linux. Each virtual machine 201 may be capable of acting as a separate system. Thus, each virtual machine may be independently reset, execute a client operating system, and run different programs, such as applications. An operating system or application running in a virtual machine may appear to have access to the entire and complete computer system. In reality, however, only a portion of the available resources of the computer system are available to the corresponding operating system or application.

[0116] Virtual machines may use a V=V model in which memory allocated to a virtual machine is backed by virtual memory rather than real memory. Thus, each virtual machine has a virtual linear memory space. Physical resources are owned by a hypervisor 200 (e.g., a VM hypervisor), and the hypervisor allocates shared physical resources to client operating systems as needed to meet the processing needs of the client operating systems. The V=V virtual machine model assumes that the interaction between the client operating system and the physical shared machine resources is controlled by the VM hypervisor, because a large number of guests may prevent the hypervisor from simply dividing and allocating hardware resources to configured guests.

[0117] Processor 120 may be assigned to virtual machine 202 by hypervisor 200. Virtual machine 202 may, for example, be assigned one or more logical processors. Each logical processor may represent all or part of a physical processor 120 that may be dynamically assigned to virtual machine 202 by hypervisor 200. Virtual machine 202 is managed by hypervisor 200. Hypervisor 200 may, for example, be implemented in firmware running on processor 120 or may be part of an operating system executing on computer system 100. Hypervisor 200 may, for example, be a VM hypervisor, such as provided by International Business Machines Corporation of Armonk, New York, USA.

[0118] In addition to the first level virtualization, a second level virtualization is provided with a second hypervisor 210 that executes on one of the first level guest operating systems, the first level guest operating system acting as a host operating system for the second hypervisor 210. The second hypervisor 210 can manage one or more second level virtual machines 212, each of which is capable of executing a second level guest operating system 212.

[0119] Figure 3An exemplary mode showing the use of different types of IDs to identify processors at different levels of the computer system 100 is depicted. The bottom-level firmware 220 may provide a logical processor ID, ICPU 222, to identify the processor 130 of the computer system 100. The first-level hypervisor 200 communicates with the processor 130 using the logical processor ID ICPU 222. The first-level hypervisor may provide a first virtual processor ID vCPU 224 for use by a client operating system 204 or a second-level hypervisor 210 executing on a virtual machine managed by the first-level hypervisor 200. The hypervisor 200 may group the first virtual processor ID vCPU 224 to provide a logical partition, also known as a zone, for the client operating system 204 and / or the hypervisor 210. The first-level hypervisor 200 maps the first virtual processor ID vCPU 224 to the logical processor ID lCPU 222. One or more first virtual processor ID vCPUs 224 provided by the first level hypervisor 200 may be assigned to each client operating system 204 or hypervisor 210 executed using the first level hypervisor 200. The second level hypervisor 210 executing on the first level hypervisor 200 may provide one or more virtual machines that execute software such as another client operating system 214. To this end, the second level hypervisor manages a second virtual processor ID vCPU 226 for use by the second level client operating system 214 executing on the virtual machine of the first level hypervisor 200. The second virtual processor ID vCPU 226 is mapped to the first virtual processor ID vCPU 224 by the second level hypervisor 200.

[0120] The bus connection module 120 used by the first / second level guest operating system 204 to address the processor 130 may use the first / second virtual processor ID vCPU 224 , 226 or a target processor ID in the form of an alternative ID derived from the first / second virtual processor ID vCPU 224 , 226 .

[0121] Figure 4A simplified schematic setup of a computer system 100 is depicted, showing the main players in a method for providing an interrupt signal to a client operating system executing on the computer system 100. For purposes of illustration, the simplified setup includes a bus connection module (BCM) 120 that sends an interrupt signal to a client operating system executing on one or more processors (CPUs) 130. The interrupt signal is sent to a bus attachment device 110 along with an interrupt target ID (IT_ID) that identifies one of the processors 130 as a target processor. The bus attachment device 110 is an intermediary device that manages communications between the bus connection module 120 and the processors 130 and memory 140 of the computer system 100. The bus attachment device 110 receives the interrupt signal and uses the interrupt target ID to identify the logical processor ID of the target processor in order to directly address the corresponding target processor. Directed forwarding to the target processor can improve the efficiency of data processing, for example, by reducing cache traffic.

[0122] Figure 5 Depicted Figure 4 Computer system 100. As shown by the segmentation of memory 140, there are two virtualization levels implemented. The first segment 143 of the memory is allocated to the first-level client operating system, and the second segment 141 of the memory is allocated to the second-level client operating system. The second-level client operating system runs on the first-level client operating system, and the first-level client operating system acts as a host for the second-level client operating system. In order to address the processor used by the second-level client operation, an interrupt target ID based on at least two mappings can be used, the two mappings being: a first mapping mapping the logical processor ID to the first virtual processor ID by the first-level hypervisor and a second mapping mapping the first virtual processor ID to the first virtual processor ID by the second-level hypervisor, the first-level hypervisor is also called a native hypervisor), and the second-level hypervisor is also called a hosted hypervisor hosted by the first-level client operating system running on the virtual machine managed by the first hypervisor.

[0123] The bus attached device 110 is configured to perform a status update on the status of the bus connected module 120 in a module specific area (MSA) 148 of the memory 140. This status update may be performed in response to receiving a direct memory access (DMA) write from the bus connected module specifying a status update to be written to the memory 140.

[0124] The memory further includes a device table (DT) 144 in an internal section 145 of the memory reserved for use by the hardware of the computer system 100, having a device table entry (DTE) 146 for each bus connection module 120. This internal section, also referred to as a hardware system area (HAS), may include a fixed size and is isolated from client purchased memory (i.e., memory that is allocable to host and / or guest operating systems).

[0125] Upon receiving an interrupt signal (e.g., an MSI-X write message with an interrupt target ID identifying the target processor of the interrupt request), the bus attachment device 110 extracts the DTE 146 assigned to the bus connection module 120 that issued the request. For this purpose, a requester ID identifying the origin of the interrupt request in the form of the bus connection module 120 may also be received. The interrupt may, for example, be targeted at a second-level client operating system, i.e., the interrupt target ID identifies the target processor assigned for use by the second-level operating system. The DTE 146 may, for example, use the dIRQ bit to indicate whether directional addressing of the target processor is enabled for the bus connection module 120 that issued the request. The bus attachment device 110 updates a client directional interrupt signal vector (DIBV) 162 (i.e., a DIBV assigned to the second-level client operating system and stored in the client memory segment 141 of the memory 140) to track which bus connection module received the interrupt signal for which processor of the processors 130. Each client DIBV 162 is assigned to one of the interrupt target IDs (i.e., the processors 130) and may include one or more entries. Each entry is assigned to one of the bus connection modules 120. Thus, the client DIBV 162 indicates from which bus connection modules there are pending interrupt signals for a particular processor 130. This may have the advantage that only a signal entry (e.g., a bit) or a signal vector (e.g., a bit vector) needs to be read from the memory 140 in order to check whether there is any interrupt signal or from which bus connection modules 120 there are pending interrupt signals for a particular processor 130.

[0126] Further, the bus-attached device 110 may update a forwarding vector (also known as a forwarding directed interrupt summary vector (DISB) 164) to keep track of which of the processors 130 there are any pending interrupt signals for in the case of a broadcast. Each entry of the forwarding DISB 164 is assigned to an entry of a client interrupt table (GAIT) 166, and the GAIT entry may include a memory address indicator indicating the memory address of the entry of the client DISB 160 assigned to the interrupt target ID. For example, the GAIT 166 may provide the address of the client DISB 160 (Gst_DISB@) and the offset (Gst_DISBO) of the corresponding entry within the client DISB 160. Thus, the GAIT 166 may provide a mapping of the interrupt target ID for selecting an entry in the forwarding DISB 164 to the entry in the client DISB 160 assigned to the corresponding interrupt target ID.

[0127] In addition to the entries assigned to the interrupt target ID and linked to the entries of the client DISB 160 via the address data provided by the GAIT entries, the forwarding DISB 164 may also include entries assigned to the bus connection module, such as requester IDs. The requester IDs are linked to the entries of the client AISB 170 via the address data provided by the GAIT entries. For example, the GAIT 166 may provide the address of the client AISB 170 (Gst_AISB@) and the offset address (Gst_AISBO) of the corresponding entry within the client AISB 170. Therefore, the GAIT 166 may further provide a mapping of the requester ID for selecting an entry in the forwarding DISB 164 to an entry in the client AISB 160 assigned to the corresponding requester (i.e., the bus connection module 120). In this case, the bus attachment device may update the entry of the client interrupt signal vector (AIBV) 172 assigned to the bus connection module. Each entry of the AIBV 172 assigned to the bus connection module 120 may be further assigned to the processor 130. Thus, the AIBV itself may identify the bus connection module 120 , while the entry identifies the processor 130 .

[0128] The bus-attached device 110 uses an entry (IRTE) 152 of an interrupt table (IRT) 150 stored in memory 140 (e.g., in internal section 145) to convert the interrupt target ID (IT_ID) to a logical processor ID (ICPU) and use the logical processor ID to directly address the target processor and forward the received interrupt signal to the target processor. For the conversion, the bus-attached device 110 obtains a copy 114 of the entry (IRTE) 152. The copy may be obtained from a local cache or from memory 140 using the address (IRT@) of the interrupt table 150 provided by the copy of the DTE 146. The IRTE 152 provides a mapping of the interrupt target ID to the logical processor ID, which is used by the bus-attached device 110 to directly address the target processor in the case of directed interrupt forwarding.

[0129] IRTE 152 additionally provides a running indicator 154, which indicates whether the target processor identified by the interrupt target ID is scheduled, that is, whether it is running. In the case where the target processor is not scheduled, a broadcast can be initiated to achieve timely interrupt processing.

[0130] Each processor includes firmware (e.g., millicode 132) for receiving and processing direct interrupt signals. The firmware may further include, for example, microcode and / or macrocode of the processor 130. It may include hardware-level instructions and / or data structures used in the implementation of higher-level machine code. According to various embodiments, it may include proprietary code that can be delivered as a microcode including trusted software or a microcode specific to the underlying hardware and controls operating system access to system hardware. In addition, the firmware of the processor 130 may include a check logic 134 for checking whether the receiving processor is the same as the target processor based on the interrupt target ID forwarded to the receiving processor 130 by the bus-attached device 110. In the case where the receiving processor 130 is not the target processor, that is, in the case where the received interrupt target ID does not match the reference interrupt target ID of the receiving processor 130, the interrupt signal is broadcast to the logical partition to find a processor for processing the interrupt signal.

[0131] Figure 6Flowchart of an exemplary method for performing a state update of a bus connection module 120 via a bus attachment device 110 using a DMA write request. In step 300, the bus connection module may decide to update its state and trigger an interrupt, for example, to indicate that the signal is complete. In step 310, the bus connection module initiates a direct memory access (DMA) write to a memory segment (host memory) allocated to a host running on a computer system via the bus attachment device to update the state of the bus connection module. DMA is a hardware mechanism that allows peripheral components of a computer system to transfer their I / O data directly to and from the main memory without involving the system processor. To perform DMA, the bus connection module sends a DMA write request to the bus attachment device, for example in the form of an MSI-X message. In the case of PCIe, the bus connection module may, for example, refer to a PCIe function provided on a PCIe adapter. In step 320, the bus connection module receives a DMA write request with a state update of the bus connection module and updates the memory using the received update. The update may be performed in an area of ​​the host memory reserved for the corresponding bus connection module.

[0132] Figure 7 is for use Figure 6 Flowchart of an exemplary method for providing an interrupt signal to a client operating system by a computer system 100 of the present invention. In step 330, the bus-attached device receives an interrupt signal sent by a bus connection module (e.g., in the form of an MSI-X write message). The transmission of the interrupt signal can be performed according to the specification of the PCI architecture. The MSI-X write message includes an interrupt target ID that identifies the target processor of the interrupt. The interrupt target ID can be, for example, a virtual processor ID used by the client operating system to identify the processor of a multi-processor computer system. According to an embodiment, the interrupt target ID can be any other ID agreed upon by the client operating system and the bus connection module in order to be able to identify the processor. Such another ID can be, for example, the result of a mapping of the virtual processor ID. In addition, the MSI-X write message can also include an interrupt requester ID (RID) (i.e., the ID of the PCIe function that issues the interrupt request), a vector index that defines the offset of the vector entry within the vector, an MSI address (e.g., a 64-bit address), and MSI data (e.g., 32-bit data). The MSI address and the MSI data can indicate that the corresponding write message is actually an interrupt request in the form of an MSI message.

[0133] In step 340, the bus-attached device obtains a copy of an entry of a device table stored in memory. The device table entry (DTE) provides an address indicator of one or more vectors or vector entries to be updated to indicate that an interrupt signal has been received for a target processor. The address indicator of a vector entry may, for example, include the address of the vector in memory and an offset within the vector. In addition, the DTE may provide a direct signaling indicator that indicates whether the target processor will be directly addressed by the bus-attached device using an interrupt target ID provided with the interrupt signal. In addition, the DTE may provide a logical partition ID (also known as a zone ID) and an interrupt subclass ID. The corresponding copy of the device table entry may be obtained from a cache or from memory.

[0134] In step 342, the bus-attached device obtains a copy of the IRTE from memory using the interrupt target ID received with the interrupt signal and the address indicator of the memory indicating the IRT provided by the DTE. In step 350, the bus-attached device updates the vector specified in the DTE, such as the client DIBV or client AIBV.

[0135] In step 360, the bus-attached device checks the direct signaling indicator provided with the interrupt signal. In the case where the direct signaling indicator indicates indirect signaling, the bus-attached device forwards the interrupt signal by broadcasting using the region identifier and the interrupt subclass identifier in step 370 so as to provide the interrupt signal to the processor used by the client operating system. In the case where the direct signaling indicator indicates direct signaling, the bus-attached device further checks in step 362 whether the running indicator included in the copy of the IRTE indicates that the target processor identified by the interrupt target ID is running.

[0136] In the event that the target processor is not running, in step 364, the bus-attached device uses, for example, a logical partition ID and / or an interrupt subclass ID to send a broadcast interrupt as a backup to identify a processor suitable for handling the interrupt. If no suitable processor matching the logical partition ID and / or interrupt subclass ID is found, the hypervisor, i.e., the processor assigned for use by the hypervisor, can receive the interrupt request instead of the processor assigned to the client operating system. If one or more processors assigned to the client operating system are scheduled, the hypervisor can decide to broadcast the interrupt request again. On the entry for the processor assigned to the operating system, the hypervisor can check a direct interrupt pending indicator, such as a dPIA bit, to be submitted to the entering processor. According to an embodiment, the hypervisor can, for example, selectively reschedule (i.e., wake up) the target processor.

[0137] In the case where the target processor is running, in step 380, the bus-attached device converts the interrupt target ID provided with the interrupt signal to the logical processor ID of the processor assigned for use by the client operating system. To perform the conversion, the bus-attached device can use a mapping table included by the bus-attached device. The bus-attached device may include a mapping table or sub-table for each zone (i.e., logical partition). In step 390, the bus-attached device forwards the interrupt signal to the target processor by directly addressing the corresponding processor using the logical processor ID, i.e., sending a direct message. The direct message may further include a zone ID and / or an interrupt subclass ID. The receiving processor includes interrupt target ID checking logic. In the case where the interrupt target ID is unique only for each logical partition, the checking logic may further take the logical partition ID into account.

[0138] In step 392, the check logic checks whether the received interrupt target ID and / or logical partition ID matches the interrupt target ID and / or logical partition currently assigned to the receiving processor and accessible by the check logic. In the case of a mismatch, in step 393, the receiving firmware initiates a broadcast to broadcast the received interrupt request to the remaining processors using the logical partition ID and / or interrupt subclass ID of the valid target processor used to identify the processing interrupt. In the case of a positive match, in step 394, the receiving firmware (e.g., millicode) of the target processor accepts the directly addressed interrupt for submission to the client operating system. In response, the firmware can interrupt its activity (e.g., program execution) and switch to execute the interrupt handler of the client operating system. Direct signaling can be used to indicate the submission of an interrupt to the client operating system.

[0139] In step 364, with the run indicator disabled (i.e., the target processor is not scheduled), the bus-attached device initiates a broadcast of an interrupt signal using the logical partition ID and / or interrupt subclass ID. The broadcast using the logical partition ID is handled by the hypervisor / first-level guest operating system.

[0140] Such a broadcast may also be initiated by the receiving processor in step 393 when there is a mismatch between the received interrupt target ID and / or logical partition ID and the interrupt target ID and / or logical partition currently assigned to the receiving processor. The currently assigned interrupt target ID and / or logical partition is accessible to the check logic as a reference value for checking.

[0141] In step 395, upon receiving the broadcast interrupt request, the processor executing the hypervisor / first-level client operating system scans the forwarding vector. The forwarding vector is provided in the memory segment allocated to the first-level client operating system. This scan can be performed by firmware (e.g., millicode) of the corresponding processor. Each entry (e.g., bit) of the forwarding vector corresponds to an entry in a client interrupt table (GAIT) provided in the memory segment allocated to the first-level client operating system. The corresponding entry of the GAIT can, for example, specify that the interrupt signal is forwarded to the target processor using direct addressing or using broadcast.

[0142] At step 396, a GAIT entry corresponding to the enabled entry of the forwarding vector is read. The GAIT entry specifies an entry of the directional interrupt summary vector of the second-level client operating system. The GAIT entry provides, for example, an address indicator indicating the address of the directional interrupt summary vector in the memory segment assigned to the second-level client operating system. The indicator may, for example, include the memory address of the directional interrupt summary vector and an offset within the directional interrupt summary vector. The offset may specify a particular entry of the directional interrupt summary vector.

[0143] In step 397, the firmware enables the entry of the directed interrupt summary vector for the second-level guest operating system specified in the GAIT. For example, the bit of the client DISB can be set. The corresponding entry of the directed interrupt summary vector for the second-level guest operating system references the interrupt target ID of the processor used by the second-level guest operating system to which the interrupt signal is addressed.

[0144] In step 398, the firmware enables entries in the client interrupt status area (GISA) of the corresponding second-level client operating system (e.g., sets a position bit in the GISA) to make a floating interrupt request (floating interrupt request) for the second-level operating system pending. The GISA is assigned to the second-level client operating system and stored in the memory segment assigned to the first-level client operating system. In the case of multiple second-level client operating systems, a GISA is provided for each second-level client operating system. To address the GISA, a GISA memory address and / or a client interrupt subclass ID (GISC) can be used. The GISA memory address and GISC can be provided by the GAITE entry read in step 396.

[0145] In step 399, if the second level guest operating system is dispatched on one of the CPUs, the firmware interrupts execution and switches execution to the second level guest operating system interrupt handler to process the pending interrupt for the second level operating system.

[0146] Figure 8 Depicted Figure 5 A further embodiment of the computer system 100, Figure 8 The computer system 100 and Figure 6 The only difference between the computer systems 100 of FIG. 1 and FIG. 2 is that the IRT is stored in the memory segment 143 allocated to the host (i.e., the first-level guest operating system) rather than in the internal segment 145 of the memory. This may be advantageous because when the size of the IRT increases to a large size due to a large number of processors, the internal segment 145 may include a limited size that causes problems.

[0147] Fig. 9 Is used for Figure 8 7 is an extension of the method of FIG. 7 . In order to ensure that the IRTE has not been tampered with by the first-level client operating system, additional checks are performed. In step 342, a copy of the IRTE is read from a memory segment assigned to the first-level client operating system using the received interrupt target ID. The bus-attached device reads the logical processor ID, logical partition ID, and GISA address indicator assigned to the received interrupt target ID from the acquired copy of the IRTE. In step 344, the PBU compares the logical partition ID and GISA address indicator included in the copy of the device table entry with the logical partition ID and GISA address indicator provided by the copy of the IRTE to ensure that the first-level client operating system has not changed any of them in the IRTE. Therefore, the data redundantly provided by the device table entry is used as reference data to check the correctness of the data provided by the IRTE. In the event of a mismatch, it is determined in step 346 that the IRTE is erroneous. If the logical partition ID and GISA address indicator provided by the copy of the IRTE are correct, it is assumed that all data included in the IRTE is correct, and the method continues with step 350.

[0148] Fig.10The schematic structure of a client DISB 160 and a plurality of client DIBVs 162 is depicted. The client DISB 160 may be provided in the form of a continuous memory segment, for example, in the form of a cache line, which includes an entry 161, for example, a bit, for each interrupt target ID. Each entry indicates whether there is an interrupt request (IRQ) to be processed by the corresponding processor identified by the interrupt target ID. A client DIBV 162 is provided for each interrupt target ID (i.e., an entry of the client DISB 160). Each client DIBV 162 is assigned to a specific interrupt target ID and includes one or more entries 163 for each bus connection module MNA, MN B. Each client DIBV 162 may be provided in the form of a continuous memory segment, for example, in the form of a cache line, which includes entries 163 assigned to the same interrupt target ID. The entries of different bus connection modules may be in the order of different offset client DIBVOs for each bus connection module.

[0149] Fig.11 A schematic structure of a client AISB 170 and a plurality of client AIBVs 172 is depicted. The client AISB 170 may be provided in the form of a continuous memory segment, for example, in the form of a cache line, which includes entries 171, for example, bits, for each bus connection module MN A to MN D. Each entry indicates whether there is a pending interrupt request (IRQ) from the corresponding bus connection module. A client AIBV 172 is provided for each bus connection module (i.e., an entry of the AISB 170). Each client AIBV 172 is assigned to a specific bus connection module and one or more entries 173 for each interrupt target ID. The client AIBVs 172 may each be provided in the form of a continuous memory segment, for example, in the form of a cache line, which includes entries 173 assigned to the same bus connection module. The entries regarding different bus connection modules may be in the order of client AIBVOs using different offset addresses for each bus connection module.

[0150] Fig. 12A An exemplary client DIBV 162 is shown. The memory address of the entry of the client DIBV 162 is a combination of the DIBV address DIBV@ provided by the IRTE assigned to the interrupt target ID (e.g., vCPU), the offset DIBVO provided by the DTE, and the DIBV index DIBV-Idx provided with the interrupt signal. Thus, each client DIBV 162 is assigned to an interrupt target ID, and the entry is assigned to the bus connection module.

[0151] Fig. 12BAn exemplary client AIBV 172 is shown. The memory address of the entry of the client DIBV 172 is a combination of the AIBV address AIBV@ provided by the DTE assigned to the bus connection module, the offset AIBVO provided by the DTE, and the AIBV index AIBV-Idx (e.g., MSI index) provided with the interrupt signal. Thus, each client AIBV 162 is assigned to a bus connection module, and the entry is assigned to the interrupt target ID.

[0152] Fig.13A An exemplary client DISB 160 is shown. The memory address of the entry of the client DISB 160 is provided by the host DISB address Host_DISB@ and the host DISB offset Host_DISBO, both of which are provided by the IRTE assigned to the interrupt target ID (e.g., vCPU), thereby identifying the memory address of the forwarding DISB array in the host memory. The corresponding entry of the forwarding DISB array identifies the GAIT entry, which identifies the address Gst_DISB@ and the offset Gst_DISBO of the client DISB 160. The corresponding entry is assigned to the interrupt target ID.

[0153] Fig. 13B An exemplary client AISB 170 is shown. The memory address of the entry of the client AISB 170 is provided by the host DISB address Host_DISB@ and the host DISB offset Host_DISBO, both of which are provided by the DTE assigned to the bus connection module, thereby identifying the memory address of the forwarding DISB array in the host memory. The corresponding entry of the forwarding DISB array identifies the GAIT entry, which identifies the address Gst_AISB@ and the offset Gst_AISBO of the client AISB 170. The corresponding entry is assigned to the bus connection module.

[0154] Fig.14An exemplary DTE 146 is depicted, which includes a logical partition ID (region), an interrupt subclass ISC, Host_DISB, Host_DISBO, AIBV@, AIBVO, and a number of interrupts (NOI) that defines the maximum number of bits reserved for the corresponding bus connection module in the DIBV. In addition, an exemplary IRTE 152 is depicted. The IRTE 152 may include a logical partition ID (region), Host_DISB, Host_DISBO, DIBV@, and an address GISA@ of a client interrupt status area (GISA). GISA 174 may include an IPM and an IAM, and the IPM makes a second-level guest operating system interrupt pending. If no vCPU of the second-level guest operating system is scheduled, the IAM bit is set, thereby putting GISA in the alert list (Alert-List) and generating a first-level guest operating system interrupt. If a vCPU of a second-level guest operating system is scheduled, it gets a second-level guest operating system interrupt directly detected by a cache line monitor (Cache-Line-Monitor) (CLM). Finally, an exemplary GAIT entry GAITE 173 may include Gst_DISB@, Gst_DISBO, GISC, and GISA@. In the case where the GAIT identifies a client AISB entry instead of a client DISB entry, it may include Gst_AISB@ and Gst_AISBO.

[0155] Fig.15 Depicted is a forwarding DISB array including a forwarding DISB vector 164 having entries 165. Each entry 165 is assigned to a GAITE 167 of a GAIT 166.

[0156] The client operating system may be implemented, for example, using a pageable memory mode client. For example, The pageable guest in the second interpretation layer can be interpreted and executed by the Start Interpretive Execution (SIE) instruction. For example, the logical partition (LPAR) management program executes the SIE instruction to start the logical partition in the physical, fixed memory. The operating system (e.g., ) can issue SIE instructions to execute the guest (virtual) machines in its virtual storage. Therefore, the LPAR hypervisor can use level 1 SIE, A hypervisor may use a level 2 SIE.

[0157] According to various embodiments, the computer system is provided by International Business Machines Corporation System Server. System Based on the IBM 6000 FPGA provided by International Business Machines Corporation about The details of the z / Architecture Principles of Operation are given in the paper entitled "z / Architecture Principles of Operation" ( The invention is described in the publication of , Publication No. SA22-7832-11, August 25, 2017), which is hereby incorporated by reference in its entirety. System and is a registered trademark of International Business Machines Corporation, Armonk, New York, U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.

[0158] According to various embodiments, computer systems with other architectures may implement and use one or more aspects of the present invention. Servers other than servers (e.g., Power Systems servers or other servers provided by International Business Machines Corporation) or servers of other companies implement, use and / or benefit from one or more aspects of the present invention. Further, although in the examples herein, the bus connection module and the bus attachment device are considered as part of the server, in other embodiments, they do not necessarily have to be considered as part of the server, but can simply be considered as being coupled to the system memory and / or other components of the computer system. The computer system does not have to be a server. Further, although the bus connection module can be PCIe, one or more aspects of the present invention can be used with other bus connection modules. PCIe adapters and PCIe functions are only examples. Further, one or more aspects of the present invention can be applied to interrupt schemes other than PCIMSI and PCIMSI-X. Further, although examples in which bits are set are described, in other embodiments, bytes or other types of indicators can be set. In addition, DTE and other structures can include more, less or different information.

[0159] In addition, other types of computer systems may benefit from one or more aspects of the present invention. As an example, a data processing system that is suitable for storing and / or executing program code and includes at least two processors that are directly or indirectly coupled to a memory element through a system bus is available. The memory element includes, for example, a local memory, a mass storage device, and a temporary storage of at least some program codes that is provided to reduce the number of times that code must be retrieved from a mass storage device during execution.

[0160] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASD, tapes, CDs, DVDs, thumb drives and other storage media, etc.) may be coupled to the system either directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems and Ethernet cards are just a few of the available types of network adapters.

[0161] Reference Fig.16 , depicts representative components of a host computer system 400 for implementing one or more aspects of the present invention. The representative host computer 400 includes one or more processors (e.g., CPUs) 401 in communication with a computer memory 402, and an I / O interface connected to a storage media device 411 and a network 410 for communicating with other computers or SANs, etc. The CPU 401 conforms to an architecture having an architecture instruction set and architecture functions. The CPU 401 may have a dynamic address translation (DAT) 403 for translating program addresses, virtual addresses, into real addresses of memory. The DAT may include a translation lookaside buffer (TLB) 407 for caching translations so that later access to blocks of the computer memory 402 does not require delays in address translation. A cache 409 may be employed between the computer memory 402 and the CPU 401. The cache 409 may be hierarchically structured, thereby providing a large high-level cache that can be used for more than one CPU and a smaller, faster, lower-level cache between the high-level cache and each CPU. In some embodiments, the lower-level cache may be divided into separate low-level caches that provide for instruction fetching and data access. According to an embodiment, the instruction may be obtained from the memory 402 by the instruction fetch unit 404 via the cache 409. The instruction may be encoded in the instruction decode unit 406 and, in some embodiments, dispatched to one or more instruction execution units 408 along with other instructions. Several execution units 408 may be employed, such as an arithmetic execution unit, a floating point execution unit, and a branch instruction execution unit. The instruction is executed by the execution unit, accessing operands from registers or memories specified by the instruction as needed. If an operand is to be accessed (e.g., loaded or stored) from the memory 402, the load / store unit 405 may handle the access under the control of the instruction being executed. The instruction may be executed in hardware circuitry or in internal microcode (i.e., firmware) or by a combination of both.

[0162] A computer system may include information in local or main storage, as well as addressing, protection, and reference and change records. Some aspects of addressing include the format of addresses, the concept of address space, different types of addresses, and ways to convert one type of address to another type of address. Some of the main storage devices include permanently allocated storage locations. The main storage device provides the system with directly addressable, fast-access storage of data. Both data and programs are loaded into the main storage device, for example, from an input device, before they can be processed.

[0163] The main storage device may include one or more smaller, faster access buffer memories, sometimes called caches. The cache may be physically associated with the CPU or I / O processor. The physical construction and use of different storage media may not generally be visible to the executed program, except for the impact on performance.

[0164] Separate caches may be maintained for instructions and for data operands. Information within the cache may be maintained in contiguous bytes on intact boundaries called cache blocks or cache lines. The model may provide an EXTRACT CACHEATTRIBUTE instruction that returns the size of a cache line in bytes. The model may also provide PREFETCH DATA and PREFETCH DATA RELATIVE LONG instructions that implement prefetching of storage into a data or instruction cache or release of data from a cache.

[0165] The storage device can be viewed as a long horizontal bit string. For most operations, access to the storage device can be performed in a left-to-right order. The bit string is subdivided into units of eight bits. This eight-bit unit is called a byte, which is the basic building block of all information formats. Each byte position in the storage device can be identified by a unique non-negative integer, which is the address of the byte position, also known as the byte address. Adjacent byte positions can have consecutive addresses, starting with 0 on the left and continuing in a left-to-right order. The address is an unsigned binary integer, for example, can be 24, 31 or 64 bits.

[0166] Transfer information between memory and the CPU one byte or a group of bytes at a time. Unless otherwise specified, in e.g. In , groups of bytes in memory are addressed by the leftmost byte of the group. The number of bytes in a group is implied or explicitly specified by the operation to be performed. When used in CPU operations, a group of bytes is called a field. Within each group of bytes, for example, In , the bits are numbered from left to right. In the storage device, the leftmost bit is sometimes called the "high-order" bit and the rightmost bit is called the "low-order" bit. However, the number of bits is not the storage address. Only bytes are addressable. In order to operate on a single bit of a byte in a storage device, the entire byte can be accessed. The bits in a byte can be numbered from left to right, for example, 0 to 7 in the z / Architecture. The bits in the address can be numbered 8-31 or 40-63 for a 24-bit address, or 1-31 or 33-63 for a 31-bit address; for a 64-bit address, they are numbered 0-63. In any other fixed-length format of multiple bytes, the bits that make up the format can be numbered consecutively starting from 0. For the purpose of error detection, and preferably for correction, one or more check bits can be transmitted with each byte or a group of bytes. Such check bits are automatically generated by the machine and cannot be directly controlled by the program. The storage capacity is expressed in bytes. When the length of the storage operand field is implied by the operation code of the instruction, the field is said to have a fixed length, which can be one byte, two bytes, four bytes, eight bytes, or sixteen bytes. Larger fields may be implied for some instructions. When the length of a storage operand field is not implied but explicitly stated, the field is said to have a variable length. The length of a variable length operand may vary in increments of one byte or some instructions, in multiples of two bytes, or other multiples. When information is placed in a storage device, only the contents of those byte positions included in the specified field are replaced, even if the width of the physical path to the storage device may be greater than the length of the field being stored.

[0167] Certain units of information will be on integral boundaries in the storage device. When the storage address of information is a multiple of the unit length in bytes, the boundaries are called integral units of information. Fields of 2, 4, 8, and 16 bytes on integral boundaries have special names. A halfword is a group of two consecutive bytes on a two-byte boundary and is the basic building block of instructions. A word is a group of four consecutive bytes on a four-byte boundary. A doubleword is a group of eight consecutive bytes on an eight-byte boundary. A quadword is a group of sixteen consecutive bytes on a sixteen-byte boundary. When a storage address specifies a halfword, word, doubleword, and quadword, the binary representation of the address contains one, two, three, or four rightmost zero bits, respectively. Instructions are to be on two-byte integral boundaries. Most instructions have no boundary alignment requirements for storage operands.

[0168] On devices that implement separate caches for instructions and data operands, a program may experience significant delays if it stores into a cache line from which instructions are subsequently fetched, regardless of whether the store changes the subsequently fetched instructions.

[0169] In one embodiment, the present invention may be implemented in software, which is sometimes referred to as licensed internal code, firmware, microcode, millicode, picocode, etc., any of which would be consistent with the present invention. Fig.16 , software program code embodying the present invention may be accessed from a long-term storage media device 411, such as a CD-ROM drive, a tape drive, or a hard drive. The software program code may be embodied on any of a variety of known media for use with data processing systems, such as a disk, a hard drive, or a CD-ROM. The code may be distributed on such media, or may be distributed to users from computer memory 402 or storage of one computer system over a network 410 connected to other computer systems for use by users of such other systems.

[0170] The software program code may include an operating system that controls the functions and interactions of different computer components and one or more application programs. The program code may be paged from a storage medium device 411 to a relatively high-speed computer memory 402, where it may be used to be processed by a processor 401. Well-known techniques and methods for embodying the software program code in a memory, on a physical medium, and / or distributing the software code via a network may be used. When created and stored on a tangible medium (including but not limited to an electronic memory module (RAM), a flash memory, a compact disk (CD), a DVD, a magnetic tape), the program code may be referred to as a "computer program product". The computer program product medium may be readable by a processing circuit preferably located in a computer system so as to be executed by the processing circuit.

[0171] Fig.17 A representative workstation or server hardware system is shown in which embodiments of the present invention may be implemented. Fig.17 The system 420 includes a representative basic computer system 421, such as a personal computer, workstation or server, including optional peripheral devices. The basic computer system 421 includes one or more processors 426 and a bus for connecting and implementing communication between the processor 426 and other components of the system 421 according to known techniques. The bus connects the processor 426 to the memory 425 and the long-term storage 427, and the long-term storage 427 may include a hard drive (including, for example, any one of magnetic media, CD, DVD and flash memory) or a tape drive. The system 421 may also include a user interface adapter, which connects the microprocessor 426 to one or more interface devices, such as a keyboard 424, a mouse 423, a printer / scanner 430 and / or other interface devices via the bus, and the interface device can be any user interface device, such as a touch screen, a digitizing input board, etc. The bus also connects a display device 422 (such as an LCD screen or monitor) to the microprocessor 426 via a display adapter.

[0172] System 421 can communicate with other computers or computer networks through a network adapter capable of communicating 428 with network 429. Example network adapters are communications channels, token rings, Ethernet, or modems. Alternatively, system 421 can communicate using a wireless interface, such as a cellular digital packet data (CDPD) card. System 421 can be associated with such other computers in a local area network (LAN) or wide area network (WAN), or system 421 can be a client in a client / server arrangement with another computer or the like.

[0173] Fig.18 A data processing network 440 is shown in which embodiments of the present invention may be implemented. The data processing network 440 may include multiple individual networks, such as wireless networks and wired networks, each of which may include multiple individual workstations 441, 442, 443, 444. Additionally, as will be appreciated by those skilled in the art, one or more LANs may be included, wherein the LAN may include multiple intelligent workstations coupled to a host processor.

[0174] Still reference Fig.18 , the network may also include a large computer or server, such as a gateway computer (e.g., client server 446) or an application server (e.g., remote server 448), that can access the data repository and can also be accessed directly from the workstation 445. The gateway computer 446 can be used as an entry point into each individual network. When connecting one networking protocol to another, a gateway may be required. The gateway 446 can preferably be coupled to another network, such as the Internet 447, via a communication link. The gateway 446 can also be directly coupled to one or more workstations 441, 442, 443, 444 using a communication link. The IBM eServer 446 available from International Business Machines Corporation can be used. TM System The server implements the gateway computer.

[0175] Also refer to Fig.17 and Fig.18 , software programming code that may embody the present invention may be accessed by processor 426 of system 420 from long-term storage medium 427, such as a CD-ROM drive or hard drive. The software programming code may be embodied on any of a variety of known media for use with data processing systems, such as a disk, hard drive, or CD-ROM. The code may be distributed on such media, or may be distributed to users from the computer memory 402 or storage device of one computer system over a network connected to other computer systems for use by users of such other systems.

[0176] Alternatively, the programming code may be embodied in memory 425 and accessed by processor 426 using a processor bus. Such programming code may include an operating system that controls the functionality and interaction of the various computer components and one or more application programs 432. The program code may be paged from storage medium 427 to high-speed memory 425 where it is available for processing by processor 426. Well-known techniques and methods for embodying software programming code in memory, on physical media, and / or distributing software code via a network may be used.

[0177] The most accessible cache of the processor, i.e., it can be faster and smaller than the other caches of the processor, is the lowest cache, also called L1 or first level cache. The main memory is the highest level cache, which is also called Ln level if there are n levels, for example, n=3, then it is called L3 level. The lowest level cache can be divided into instruction cache and data cache. The instruction cache is also called I cache, which stores machine-readable instructions to be executed. The data cache is also called D cache, which stores data operands.

[0178] Reference Fig.19 , depicting an exemplary processor embodiment of a processor 426. One or more levels of cache 453 may be used to cache memory blocks in order to improve processor performance. Cache 453 is a high-speed buffer that holds cache lines of memory data that may be used. A cache line may be, for example, 64, 128, or 256 bytes of memory data. Separate caches may be used to cache instructions and cache data. Cache coherence (i.e., synchronization of copies of lines in memory and cache) may be provided by different suitable algorithms (e.g., a "snoop" algorithm). The main memory storage 425 of a processor system may be referred to as a cache. In a processor system with 4 levels of cache 453, the main memory 425 is sometimes referred to as a level 5 (L5) cache because it can be faster and only holds a portion of the non-volatile memory available to the computer system. The main memory 425 "caches" data pages that are paged in and out of the main memory 425 by the operating system.

[0179] The program counter (instruction counter) 461 keeps track of the address of the current instruction to be executed. The program counter in the processor is 64 bits and can be truncated to 31 or 24 bits to support previous addressing restrictions. The program counter can be embodied in the computer's program status word (PSW) so that it persists during context switches. Therefore, a program in progress with a program counter value may be interrupted by, for example, an operating system, resulting in a context switch from the program environment to the operating system environment. The program's PSW maintains the program counter value when the program is inactive, and uses the program counter in the operating system's PSW when the operating system is executing. The program counter can be incremented by an amount equal to the number of bytes of the current instruction. Reduced instruction set computing (RISC) instructions can be fixed length, while complex instruction set computing (CISC) instructions can be variable length. IBM The instructions are 2, 4 or 6 byte long CISC instructions. For example, the program counter 461 can be modified by a context switch operation or a branch taken operation of a branch instruction. In a context switch operation, the current program counter value is saved in the program status word along with other status information about the program being executed (e.g., condition code), and then a new program counter value pointing to the instruction of the new program module to be executed is loaded. The branch taken operation can be performed to allow the program to make decisions or loops within the program by loading the result of the branch instruction into the program counter 461.

[0180] An instruction fetch unit 455 may be employed to fetch instructions on behalf of the processor 426. The fetch unit fetches the "next sequential instruction", the target instruction of a branch taken instruction, or the first instruction of a program after a context switch. Modern instruction fetch units may employ prefetch techniques to speculatively prefetch instructions based on the likelihood that the prefetched instruction may be used. For example, the fetch unit may fetch 16 bytes of instructions containing the next sequential instruction and additional bytes of further sequential instructions.

[0181] The fetched instructions may then be executed by the processor 426. According to an embodiment, the fetched instructions may be passed from the fetch unit to the dispatch unit 456. The dispatch unit decodes the instructions and forwards information about the decoded instructions to the appropriate units 457, 458, 460. The execution unit 457 may receive information about the decoded arithmetic instructions from the instruction fetch unit 455 and may perform arithmetic operations on operands according to the opcode of the instruction. The operands may preferably be provided to the execution unit 457 from the memory 425, the architected registers 459, or from the immediate field of the instruction being executed. When the results of the execution are to be stored, they may be stored in the memory 425, the registers 459, or other machine hardware such as control registers, PSW registers, and the like.

[0182] The processor 426 may include one or more units 457, 458, 460 for executing the functions of the instructions. Fig. 20A , the execution unit 457 can communicate with the architected general registers 459, the decode / dispatch unit 456, the load / store unit 460, and other 465 processor units through the interface logic 471. The execution unit 457 can use several register circuits 467, 468, 469 to hold information operated by the arithmetic logic unit (ALU) 466. The ALU performs arithmetic operations such as addition, subtraction, multiplication and division, as well as logical functions such as And, Or, XOR, rotation and shift. Preferably, the ALU can support specialized operations that depend on the design. Other circuits can provide other architected facilities 472 including, for example, conditional codes and recovery support logic. The results of the ALU operations can be stored in the output register circuit 470, which is configured to forward the results to various other processing functions. There are many ways to arrange the processor units, and this specification is only intended to provide a representative understanding of one embodiment.

[0183] An addition (ADD) instruction may be executed, for example, in an execution unit 457 having arithmetic and logic functions, while a floating point instruction will be executed, for example, in a floating point execution unit having specialized floating point capabilities. Preferably, the execution unit operates on operands by performing a function defined by an opcode on the operands identified by the instruction. For example, an addition instruction may be executed by the execution unit 457 on operands found in two registers 459 identified by the register field of the instruction.

[0184] The execution unit 457 performs arithmetic addition on the two operands and stores the result in a third operand, which may be a third register or one of the two source registers. The execution unit preferably utilizes an arithmetic logic unit (ALU) 466, which is capable of performing various logic functions such as shifts, rotations, and XOR, as well as various algebraic functions including any of addition, subtraction, multiplication, and division. Some ALUs 466 are designed for scalar operations, and some ALUs 466 are designed for floating point. Depending on the architecture, the data may be big endian (where the least significant byte is at the highest byte address) or little endian (where the least significant byte is at the lowest byte address). is big endian. Signed fields can be sign and magnitude, 1's complement, or 2's complement, depending on the architecture. 2's complement can be advantageous because the ALU does not need to be designed with a subtraction function, since negative or positive values ​​in 2's complement only require addition within the ALU. Numbers can be described using shorthand where a 12-bit field defines the address of a 4,096-byte block and described as, for example, a 4K byte (kilobyte) block.

[0185] See also Fig. 20B, the branch instruction information for executing the branch instruction can be sent to the branch unit 458, and the branch unit 458 usually adopts a branch prediction algorithm (such as a branch history table 482) to predict the result of the branch before other conditional operations are completed. Before the conditional operation is completed, the target of the current branch instruction will be extracted and speculatively executed. When the conditional operation is completed, based on the condition of the conditional operation and the result of the speculation, the branch instruction that is speculatively executed is either completed or discarded. The branch instruction can test the condition code, and if the condition code meets the branch requirement of the branch instruction, the branch instruction can branch to the target address, and the target address can be calculated based on several numbers (including, for example, numbers found in the register field or immediate field of the instruction). The branch unit 458 can adopt an ALU474 with multiple input register circuits 475, 476, 477 and an output register circuit 480. For example, the branch unit 458 can communicate with a general register 459, a decoding / dispatch unit 456 or other circuits 473.

[0186] The execution of a set of instructions may be interrupted for a variety of reasons, including, for example, a context switch initiated by an operating system, a program exception or error that causes a context switch, an I / O interrupt signal that causes a context switch, or multithreaded activity of multiple programs in a multithreaded environment. Preferably, the context switch action saves state information about the currently executing program and then loads state information about another program that is called. The state information may be saved, for example, in a hardware register or in a memory. The state information preferably includes a program counter value pointing to the next instruction to be executed, condition codes, memory conversion information, and architected register contents. The context switch activity may be implemented by hardware circuits, application programs, operating system programs, or firmware code, for example. Microcode, picocode, or licensed internal code (LIC), either individually or in combination.

[0187] The processor accesses operands according to the method defined by the instruction. An instruction may provide an immediate operand using the value of a portion of the instruction, or may provide one or more register fields that explicitly point to a general purpose register or a special purpose register (such as a floating point register). An instruction may use an implicit register identified by the opcode field as an operand. An instruction may use the memory location of an operand. The memory location of an operand may be provided by a register, an immediate field, or a combination of a register and an immediate field, such as The long displacement facility is exemplified in that the instruction defines a base register, an index register, and an immediate field, the displacement field, which are added together to provide the memory address of the operand. Unless otherwise indicated, locations herein may imply locations in main storage.

[0188] Reference Fig. 20C , the processor uses a load / store unit 460 to access memory. The load / store unit 460 can perform a load operation by obtaining the address of the target operand in the memory 453 and loading the operand into the register 459 or another memory 453 location, or can perform a store operation by obtaining the address of the target operand in the memory 453 and storing the data obtained from the register 459 or another memory 453 location in the target operand location in the memory 453. The load / store unit 460 can be speculative and can access memory in an order that is out of order relative to the instruction sequence, however, the load / store unit 460 will keep the program from appearing to execute instructions in order. The load / store unit 460 can communicate with the general registers 459, the decode / dispatch unit 456, the cache / memory interface 453, or other elements 483, and includes various register circuits, ALU 485, and control logic 490 to calculate storage addresses and provide pipeline sequencing to maintain in-order operation. Some operations may be performed out of order, but the load / store unit provides functionality to make the out-of-order operations appear to the program to have been performed in order.

[0189] Preferably, the addresses that an application "sees" are typically referred to as virtual addresses. Virtual addresses are sometimes also referred to as "logical addresses" and "effective addresses." These virtual addresses are virtual because they are redirected to physical memory locations through one of a variety of dynamic address translation (DAT) techniques. Dynamic address translation techniques include, but are not limited to, simply prefixing the virtual address with an offset value, translating the virtual address via one or more translation tables, the translation tables preferably including at least one of a separate segment table, a separate page table, or a combination of a segment table and a page table, preferably, the segment table has an entry pointing to the page table. In A translation hierarchy is provided in which a region first table, a region second table, a region third table, a segment table, and an optional page table are included. The performance of address translation is often improved by utilizing a translation lookaside buffer (TLB) that contains entries that map virtual addresses to associated physical memory locations. When DAT uses a translation table to translate a virtual address, an entry is created. Subsequent uses of the virtual address can then utilize entries of a fast TLB rather than a slow sequential translation table access. TLB contents can be managed by various replacement algorithms including least recently used (LRU).

[0190] Each processor in a multiprocessor system is responsible for maintaining interlocks of shared resources (e.g., I / O, cache, TLB, and memory) to achieve coherency. So-called "snooping" techniques can be used to maintain cache coherency. In a snooping environment, each cache line can be marked as being in any of the shared, exclusive, changed, invalid, etc. states to facilitate sharing.

[0191] I / O unit 454 may provide the processor with a means for attaching to peripheral devices including, for example, tapes, optical disks, printers, displays, and networks. I / O units are typically presented to computer programs by software drivers. System In a host computer, channel adapters and open system adapters are I / O units of the host computer that provide communication between the operating system and peripheral devices.

[0192] Further, other types of computer systems can benefit from one or more aspects of the present invention.As an example, the computer system may include a simulator, such as software or other simulation mechanisms, wherein the simulation includes a specific architecture or a subset thereof such as instruction execution, an architected function (such as address conversion) and an architected register, such as being simulated on a native computer system with a processor and a memory.In such an environment, one or more simulation functions of the simulator can realize one or more aspects of the present invention, even if the computer executing the simulator can have a different architecture from the ability being simulated.For example, in the simulation mode, the specific instruction or operation being simulated can be decoded, and suitable simulation functions can be constructed to realize independent instructions or operations.

[0193] In a simulation environment, a host computer may, for example, include: a memory for storing instructions and data; an instruction fetch unit for fetching instructions from the memory and optionally providing a local buffer for the fetched instructions; an instruction decoding unit for receiving the fetched instructions and for determining the type of instructions that have been fetched; and an instruction execution unit for executing the instructions. Execution may include loading data from the memory into registers, storing data from registers back to the memory, and / or performing a certain type of arithmetic or logical operation as determined by the decoding unit. For example, each unit may be implemented in software. The operations performed by these units may be implemented as one or more subroutines within the simulator software.

[0194] More specifically, in a mainframe, programmers (e.g., "C" programmers) use architected machine instructions, such as through a compiler application. These instructions, stored in a storage medium, may be stored in a computer program that is compatible with the mainframe. The server executes natively, or on machines running other architectures. They can be used in existing and future Mainframe servers and Other machines (for example, Power Systems servers and System server). They can be used in AMD TM It can be executed on a variety of machines running Linux on hardware manufactured by In addition to executing on this hardware, Linux can be used and machines emulated by Hercules, UMX or FSI (Fundamental Software, Inc) can be used, which usually execute in emulation mode. In emulation mode, emulation software is executed by the native processor to emulate the architecture of the emulated processor.

[0195] The native processor can execute the simulation software including firmware or native operating system to simulate the simulation processor. The simulation software is responsible for obtaining and executing the instructions of the simulation processor architecture. The simulation software maintains the simulation program counter to track the instruction boundary. The simulation software can obtain one or more simulation machine instructions at a time, and convert the one or more simulation machine instructions into a corresponding set of native machine instructions for the native processor to execute. These converted instructions can be cached so that faster conversion can be achieved. Nevertheless, the simulation software will maintain the architecture rules of the simulation processor architecture to ensure that the operating system and application programs written for the simulation processor operate correctly. In addition, the simulation software will provide resources identified by the simulation processor architecture, including but not limited to control registers, general registers, floating point registers, dynamic address translation functions including, for example, segment tables and page tables, interrupt mechanisms, context switching mechanisms, time of day (TOD) clocks, and architectural interfaces to the I / O subsystem, so that the operating system or application programs designed to run on the simulation processor can run on the native processor with the simulation software.

[0196] Decodes the specific instruction being emulated and calls a subroutine to perform the function of the single instruction. For example, in a "C" subroutine or driver, or in some other method of providing a driver for specific hardware, the emulation software function that emulates the function of the emulated processor is implemented.

[0197] exist Fig.21, an example of an emulated host computer system 492 of a host computer system 400' emulating a host architecture is provided. In the emulated host computer system 492, a host processor (i.e., CPU) 491 is an emulated host processor or a virtual host processor and includes an emulated processor 493 having a native instruction set architecture different from the native instruction set architecture of the processor 491 of the host computer 400'. The emulated host computer system 492 has a memory 494 accessible to the emulated processor 493. In an exemplary embodiment, the memory 494 is divided into a host computer memory 496 portion and an emulation routine memory 497 portion. The host computer memory 496 is available to programs of the emulated host computer 492 in accordance with the host computer architecture. The emulation processor 493 executes native instructions of the architecture instruction set of the architecture other than the emulation processor 491, native instructions obtained from the emulation routine memory 497, and can access the host instructions for execution from the program in the host memory 496 by using one or more instructions obtained in the sequence, and access / decode the routine that can decode the accessed host instructions to determine the native instruction execution routine for simulating the function of the accessed host instructions. Other facilities defined for the architecture of the host system 400' can be emulated by the architected facility routine, including facilities such as general registers, control registers, dynamic address translation and I / O subsystem support and processor cache. The emulation routine can also improve the performance of the emulation routine by utilizing the functions available in the emulation processor 493 (e.g., dynamic translation of general registers and virtual addresses). Special hardware and offload engines can also be provided to assist the processor 493 in emulating the functions of the host 400'.

[0198] It is understood that one or more of the above-described embodiments of the present invention may be combined as long as the combined embodiments are not mutually exclusive. Ordinal numbers such as "first" and "second" are used herein to indicate different elements assigned the same name, but do not necessarily establish any order of the individual elements.

[0199] The present invention is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present invention. It should be understood that each box of the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer readable program instructions.

[0200] The present invention may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium (or medium) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of the present invention.

[0201] A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punched card or a raised structure in a groove having instructions recorded thereon, and any suitable combination of the above. As used herein, a computer-readable storage medium should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by a fiber optic cable), or an electrical signal transmitted by a wire.

[0202] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0203] The computer-readable program instructions for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as the 'C' programming language or similar programming languages. The computer-readable program instructions may be executed entirely on a computer of a "user computer system", partially on a computer of a "user computer system", as a separate software package, partially on a computer of a "user computer system" and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the computer of the user computer system via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit (including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA)) may execute computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit so as to perform aspects of the present invention.

[0204] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0205] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine that is executed by a processor of a computer or other programmable data processing device to create a device for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing device, and / or other device to function in a particular manner, such that a computer-readable storage medium having instructions stored therein includes an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0206] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other device, so that a series of operational steps are performed on the computer, other programmable data processing device, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing device, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0207] The flow chart and block diagram in the accompanying drawings show the architecture, function and operation of the possible implementation of the system, method and computer program product according to different embodiments of the present invention. To this end, each box in the flow chart or block diagram can represent a part of a module, segment or instruction, which includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the function marked in the box may not occur in the order marked in the figure. For example, depending on the function involved, the two boxes shown in succession can actually be performed substantially at the same time, or these boxes can sometimes be performed in the opposite order. It will also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a system based on special-purpose hardware, and the system based on special-purpose hardware performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

[0208] The above features can have the following possible combinations:

[0209] 1. A method for providing an interrupt signal to a first client operating system, the first client operating system being executed by one or more processors of a plurality of processors of a computer system assigned for use by the first client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory operably connected to the bus attachment device,

[0210] Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor,

[0211] Each processor of the plurality of processors assigned for use by the first client operating system is further assigned an interrupt target ID used by the first client operating system and the one or more first bus connection modules to address the corresponding processor,

[0212] Implementing the first client operating system using the second client operating system as a host for hosting the first client operating system,

[0213] The memory includes, in a first memory segment allocated to the first guest operating system, a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator being assigned to an interrupt target ID indicating whether there is a pending first interrupt signal addressed to the corresponding interrupt target ID,

[0214] the memory including, in a second memory segment allocated to the second guest operating system, a forwarding vector including a first set of forwarding vector entries, the first set of forwarding vector entries including, for each of the directional interrupt summary indicators of the directional interrupt summary vector, a forwarding vector entry allocated to the corresponding directional interrupt summary indicator, each forwarding vector entry indicating whether to update the corresponding directional interrupt summary indicator to which it is allocated so as to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID,

[0215] The method includes:

[0216] receiving, by the bus-attached device from the first bus connection module, a first interrupt signal with an interrupt target ID, the interrupt target ID identifying one of the processors that is assigned by the first client operating system to serve as a first target processor for processing the first interrupt signal,

[0217] checking, by the bus-attached device, whether the first target processor is scheduled for use by the first guest operating system,

[0218] if the first target processor is scheduled for use by the first guest operating system, translating, by the bus-attached device, the received interrupt target ID into a logical processor ID, and forwarding the first interrupt signal to the first target processor for processing by directly addressing the first target processor with the logical processor ID resulting from the translation,

[0219] Otherwise, the bus-attached device forwards the first interrupt signal for processing to the first operating system using a broadcast, the broadcast including selecting, by the bus-attached device, a forwarding vector entry from a first set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that a directional interrupt summary indicator to which the selected forwarding vector entry is assigned is to be updated to indicate to the first operating system that there is a first interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0220] 2. The method of item 1, the second memory segment further comprises a client interrupt table, the client interrupt table comprises a first set of client interrupt table entries, the first set of client interrupt table entries comprises a directional interrupt summary address indicator for each of the directional interrupt summary indicators of the directional interrupt summary vector, wherein the corresponding directional interrupt summary address indicator indicates a memory address of the corresponding directional interrupt summary indicator in the second memory segment,

[0221] The allocation of forwarding vector entries in the first set of forwarding vector entries is implemented using a client interrupt table, wherein each forwarding vector in the first set of forwarding vector entries is allocated one of the client interrupt table entries in the first set of client interrupt table entries, and a directional interrupt summary address indicator of the corresponding client interrupt table entry indicates a memory address of a directional interrupt summary to which the corresponding forwarding vector entry is allocated.

[0222] 3. The method of any of the preceding items, wherein the forwarding vector entries are each implemented as a single bit.

[0223] 4. The method of any one of the above items, wherein the directional interrupt summary vector is implemented as a continuous area in the memory.

[0224] 5. The method of any of the preceding items, wherein the directional interrupt summary indicators are each implemented as a single bit.

[0225] 6. The method of any of the preceding items, wherein the memory further comprises an interrupt table, the interrupt table having an interrupt table entry for each interrupt target ID, each of the interrupt table entries comprising a forwarding vector entry address indicator indicating a memory address of a corresponding forwarding vector entry in the second memory segment,

[0226] The method further comprises:

[0227] retrieving, by the bus-attached device, a copy of an interrupt table entry in an interrupt table that is assigned to the received interrupt target ID, the retrieved copy including a forwarding vector entry address indicator that indicates a memory address of a forwarding vector entry in a second memory segment that is assigned to the received interrupt target ID,

[0228] The forwarding vector entry address indicator contained by the retrieved copy of the interrupt table entry is used by the bus-attached device to select a forwarding vector entry assigned to the received interrupt target ID.

[0229] 7. The method of item 6, wherein the retrieved copy of the interrupt table entry also includes a mapping of the received interrupt target ID to the logical processor ID, and the method further includes: the bus-attached device uses the mapping included in the copy of the interrupt table entry to convert the received interrupt target ID into the logical processor ID.

[0230] 8. In the method of items 6 to 7, the retrieved copy of the interrupt table entry further includes an operation indicator indicating whether the first target processor identified by the interrupt target ID is scheduled for use by the first client operating system, and the method further includes: the bus-attached device uses the operation indicator included by the copy of the interrupt table entry to check whether the first target processor is scheduled for use by the first client operating system.

[0231] 9. The method of item 8, wherein the operation indicator is implemented as a single bit.

[0232] 10. In the method of items 6 to 9, the interrupt table is included in the second memory segment.

[0233] 11. In methods 6 to 9, the retrieved copy of the interrupt table entry also includes a first logical partition ID and a first client interrupt status area address indicator, the first logical partition ID identifies the logical partition to which the first client operating system is assigned, and the first client interrupt status area address indicator indicates a memory address of a client interrupt status area in the second memory segment assigned to the first client operating system.

[0234] 12. The method of items 6 to 10, further comprising retrieving, by the bus-attached device, a copy of a device table entry from a device table, the device table entry comprising an interrupt table address indicator indicating a memory address of an interrupt table, the bus-attached device using the memory address of the interrupt table to retrieve a first copy of the interrupt table entry.

[0235] 13. The method of item 12, the device table is stored in a third memory segment of the memory, and the third memory segment is protected from access by the first and second operating systems.

[0236] 14. The method of item 13, wherein the retrieved copy of the device table entry further includes a second logical partition ID and a second client interrupt status area address indicator, the second logical partition ID identifying the logical partition to which the first client operating system is assigned, the second client interrupt status area address indicator indicating a memory address of a client interrupt status area in the second memory segment assigned to the first client operating system,

[0237] The method further includes checking, by the bus-attached device, that an interrupt table entry stored in a second memory segment accessible to a second client operating system has not been changed by the second client operating system by comparing a first combination of a first logical partition ID and a first client interrupt status area address indicator provided by an interrupt table entry with a second combination of a second logical partition ID and a second client interrupt status area address indicator provided by a device table entry stored in a protected third memory segment, wherein a match between the first combination and the second combination indicates that the interrupt table entry has not been changed.

[0238] 15. The method of item 14, the device table entry further includes a logical partition ID identifying the logical partition to which the client operating system is assigned, and forwarding the first interrupt signal by the bus-attached device further includes forwarding the logical partition ID together with the first interrupt signal.

[0239] 16. The method of items 12 to 15, the device table entry further includes an interrupt subclass ID identifying the interrupt subclass to which the first interrupt signal is assigned, and forwarding the first interrupt signal by the bus-attached device further includes forwarding the interrupt subclass ID together with the first interrupt signal.

[0240] 17. The method of any one of the preceding items, wherein the second memory segment further comprises a first directional interrupt signal vector assigned to each interrupt target ID of the corresponding interrupt target ID, each directional first interrupt signal vector comprises a first interrupt signal indicator of each first bus connection module assigned to the first bus connection module, each directional first interrupt signal vector indicates whether there is a first interrupt signal issued by the first bus connection module and addressed to the corresponding interrupt target ID to be processed,

[0241] The method further comprises:

[0242] selecting, by the bus-attached device, a directional first interrupt signal vector assigned to an interrupt target ID addressed by the first interrupt signal,

[0243] selecting, by the bus-attached device, in the selected directional first interrupt signal vector, a directional first interrupt signal indicator assigned to a first bus connection module issuing a first interrupt signal,

[0244] The selected directional first interrupt signal indicator is updated by the bus-attached device such that the updated directional first interrupt signal indicator indicates that there is a first interrupt signal issued by the first bus connection module and addressed to the corresponding interrupt target ID to be processed.

[0245] 18. The method of any of the preceding items, wherein the first interrupt signal is received in the form of a message signal interrupt including an interrupt target ID of a target processor.

[0246] 19. The method of any one of the preceding items, wherein the second memory segment further comprises an interrupt summary vector, the interrupt summary vector having an interrupt summary indicator for each bus connection module, each interrupt summary indicator being assigned to a bus connection module to indicate whether there is an interrupt signal to be processed issued by the corresponding bus connection module,

[0247] the forwarding vector comprises a second set of forwarding vector entries, the second set of forwarding vector entries comprising, for each of the directional interrupt summary indicators of the directional interrupt summary vector, a forwarding vector entry assigned to the corresponding directional interrupt summary indicator, each forwarding vector entry indicating whether the corresponding interrupt summary indicator to which it is assigned is to be updated to indicate to the first operating system that there is a first interrupt signal issued by the corresponding bus connection module to be processed,

[0248] The method further comprises:

[0249] receiving, by the bus-attached device from the second bus connection module, a second interrupt signal having an interrupt target ID, the interrupt target ID identifying one of the processors that is assigned to be used by the first guest operating system as a second target processor for processing the second interrupt signal,

[0250] checking, by the bus-attached device, whether the second target processor is scheduled for use by the first guest operating system,

[0251] if the second target processor is scheduled for use by the first client operating system, translating, by the bus-attached device, the received interrupt target ID into a logical processor ID, and forwarding the second interrupt signal to the second target processor for processing by directly addressing the second target processor with the logical processor ID resulting from the translation,

[0252] Otherwise, the second interrupt signal is forwarded by the bus-attached device to the first operating system for processing using a broadcast, the broadcast comprising selecting, by the bus-attached device, a forwarding vector entry from a second set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that an interrupt summary indicator assigned to it is to be updated to indicate to the first operating system that there is a first interrupt signal issued by the second bus connection module to be processed.

[0253] 20. The method of item 19, the client interrupt table comprising a second set of client interrupt table entries, the second set of client interrupt table entries comprising an interrupt summary address indicator for each of the interrupt summary indicators of the interrupt summary vector, the respective interrupt summary address indicator indicating a memory address of the respective interrupt summary indicator in the second memory segment,

[0254] The allocation of forwarding vector entries in the second set of forwarding vector entries is implemented using a client interrupt table, wherein each forwarding vector in the second set of forwarding vector entries is allocated a client interrupt table entry in the second set of client interrupt table entries, and a directed interrupt summary address indicator of the corresponding client interrupt table entry indicates a memory address of an interrupt summary indicator to which the corresponding forwarding vector entry is allocated.

[0255] 21. The method of items 19 to 20, wherein the second memory segment further comprises an interrupt signal vector assigned to each bus connection module of the corresponding bus connection module, each interrupt signal vector comprises an interrupt signal indicator for each interrupt target ID assigned to the corresponding bus connection module, each interrupt signal vector indicates whether there is an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID to be processed,

[0256] The method further comprises:

[0257] selecting, by the bus attached device, a directional interrupt signal vector assigned to the second bus connection module,

[0258] selecting, by the bus-attached device, in the selected interrupt signal vector, an interrupt signal indicator assigned to the interrupt target ID addressed by the second interrupt signal,

[0259] The selected interrupt signal indicator is updated by the bus-attached device such that the updated interrupt signal indicator indicates the presence of an interrupt signal issued by the second bus connection module and addressed to the corresponding interrupt target ID to be processed.

[0260] 22. The method of any of the preceding items, wherein the first guest operating system is a guest operating system of the second virtualization level, and the second guest operating system is a guest operating system of the first virtualization level.

[0261] 23. The method of any of the preceding items, wherein the first guest operating system is a guest operating system of the third virtualization level, and the second guest operating system is a guest operating system of the second virtualization level.

[0262] 24. A computer system for providing an interrupt signal to a first client operating system, the first client operating system being executed using one or more processors of a plurality of processors of the computer system assigned for use by the first client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory operably connected to the bus attachment device,

[0263] Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor,

[0264] Each processor of the plurality of processors assigned for use by the first client operating system is further assigned an interrupt target ID used by the first client operating system and the one or more first bus connection modules to address the corresponding processor,

[0265] Implementing the first client operating system using the second client operating system as a host for hosting the first client operating system,

[0266] The memory includes, in a first memory segment allocated to the first guest operating system, a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator being assigned to an interrupt target ID indicating whether there is a pending first interrupt signal addressed to the corresponding interrupt target ID,

[0267] the memory including, in a second memory segment allocated to the second guest operating system, a forwarding vector including a first set of forwarding vector entries, the first set of forwarding vector entries including, for each of the directional interrupt summary indicators of the directional interrupt summary vector, a forwarding vector entry allocated to the corresponding directional interrupt summary indicator, each forwarding vector entry indicating whether to update the corresponding directional interrupt summary indicator to which it is allocated so as to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID,

[0268] The computer system is configured to perform a method comprising:

[0269] receiving, by the bus-attached device from the first bus connection module, a first interrupt signal with an interrupt target ID, the interrupt target ID identifying one of the processors that is assigned by the first client operating system to serve as a first target processor for processing the first interrupt signal,

[0270] checking, by the bus-attached device, whether the first target processor is scheduled for use by the first guest operating system,

[0271] if the first target processor is scheduled for use by the first guest operating system, translating, by the bus-attached device, the received interrupt target ID into a logical processor ID, and forwarding the first interrupt signal to the first target processor for processing by directly addressing the first target processor with the logical processor ID resulting from the translation,

[0272] Otherwise, the bus-attached device forwards the first interrupt signal for processing to the first operating system using a broadcast, the broadcast including selecting, by the bus-attached device, a forwarding vector entry from a first set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that a directional interrupt summary indicator to which the selected forwarding vector entry is assigned is to be updated to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0273] 25. A computer program product for providing an interrupt signal to a first client operating system, the first client operating system being executed using one or more processors of a plurality of processors of a computer system assigned for use by the first client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory operably connected to the bus attachment device,

[0274] Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor,

[0275] Each processor of the plurality of processors assigned for use by the first client operating system is further assigned an interrupt target ID used by the first client operating system and the one or more first bus connection modules to address the corresponding processor,

[0276] implementing the first client operating system using the second client operating system as a host for hosting the first client operating system,

[0277] The memory includes, in a first memory segment allocated to the first guest operating system, a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator being assigned to an interrupt target ID indicating whether there is a pending first interrupt signal addressed to the corresponding interrupt target ID,

[0278] the memory including, in a second memory segment allocated to the second guest operating system, a forwarding vector including a first set of forwarding vector entries, the first set of forwarding vector entries including, for each of the directional interrupt summary indicators of the directional interrupt summary vector, a forwarding vector entry allocated to the corresponding directional interrupt summary indicator, each forwarding vector entry indicating whether to update the corresponding directional interrupt summary indicator to which it is allocated so as to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID,

[0279] A computer program product includes a computer readable non-transitory medium readable by a processing circuit and storing instructions for execution by the processing circuit to perform a method, the method comprising:

[0280] receiving, by the bus-attached device from the first bus connection module, a first interrupt signal with an interrupt target ID, the interrupt target ID identifying one of the processors that is assigned by the first client operating system to serve as a first target processor for processing the first interrupt signal,

[0281] checking, by the bus-attached device, whether the first target processor is scheduled for use by the first guest operating system,

[0282] if the first target processor is scheduled for use by the first guest operating system, translating, by the bus-attached device, the received interrupt target ID into a logical processor ID, and forwarding the first interrupt signal to the first target processor for processing by directly addressing the first target processor with the logical processor ID resulting from the translation,

[0283] Otherwise, the bus-attached device forwards the first interrupt signal for processing to the first operating system using a broadcast, the broadcast including selecting, by the bus-attached device, a forwarding vector entry from a first set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that a directional interrupt summary indicator to which the selected forwarding vector entry is assigned is to be updated to indicate to the first operating system that there is a first interrupt signal addressed to the corresponding interrupt target ID to be processed.

Claims

1. A method for providing an interrupt signal to a first client operating system, the first client operating system being executed by one or more processors of a plurality of processors of a computer system assigned for use by the first client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory operably connected to the bus attachment device, Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor, Each processor of the plurality of processors assigned for use by the first client operating system is further assigned an interrupt target ID used by the first client operating system and the one or more first bus connection modules to address the corresponding processor, Implementing the first client operating system using the second client operating system as a host for hosting the first client operating system, The memory includes, in a first memory segment allocated to the first guest operating system, a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator being assigned to an interrupt target ID indicating whether there is a pending first interrupt signal addressed to the corresponding interrupt target ID, the memory including, in a second memory segment allocated to the second guest operating system, a forwarding vector including a first set of forwarding vector entries, the first set of forwarding vector entries including, for each of the directional interrupt summary indicators of the directional interrupt summary vector, a forwarding vector entry allocated to the corresponding directional interrupt summary indicator, each forwarding vector entry indicating whether to update the corresponding directional interrupt summary indicator to which it is allocated so as to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID, The method includes: receiving, by the bus-attached device from the first bus connection module, a first interrupt signal with an interrupt target ID, the interrupt target ID identifying one of the processors that is assigned by the first client operating system to serve as a first target processor for processing the first interrupt signal, checking, by the bus-attached device, whether the first target processor is scheduled for use by the first guest operating system, if the first target processor is scheduled for use by the first guest operating system, translating, by the bus-attached device, the received interrupt target ID into a logical processor ID, and forwarding the first interrupt signal to the first target processor for processing by directly addressing the first target processor with the logical processor ID resulting from the translation, Otherwise, the bus-attached device forwards the first interrupt signal for processing to the first operating system using a broadcast, the broadcast comprising selecting, by the bus-attached device, a forwarding vector entry in a first set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that a directional interrupt summary indicator to which the selected forwarding vector entry is assigned is to be updated to indicate to the first operating system that there is a first interrupt signal addressed to the corresponding interrupt target ID to be processed, wherein the forwarding comprises: retrieving, by the bus-attached device, a copy of an interrupt table entry in an interrupt table assigned to the received interrupt target ID, the retrieved copy including a forwarding vector entry address indicator indicating a memory address of a forwarding vector entry in a second memory segment assigned to the received interrupt target ID, and The forwarding vector entry address indicator contained by the retrieved copy of the interrupt table entry is used by the bus-attached device to select a forwarding vector entry assigned to the received interrupt target ID.

2. The method of claim 1 , the second memory segment further comprising a client interrupt table, the client interrupt table comprising a first set of client interrupt table entries, the first set of client interrupt table entries comprising a directional interrupt summary address indicator for each of the directional interrupt summary indicators of the directional interrupt summary vector, wherein The corresponding directional interrupt summary address indicator indicates a memory address of the corresponding directional interrupt summary indicator in the second memory segment, The allocation of forwarding vector entries in the first set of forwarding vector entries is implemented using a client interrupt table, wherein each forwarding vector in the first set of forwarding vector entries is allocated one of the client interrupt table entries in the first set of client interrupt table entries, and a directional interrupt summary address indicator of the corresponding client interrupt table entry indicates a memory address of a directional interrupt summary to which the corresponding forwarding vector entry is allocated.

3. The method of claim 1, wherein the forwarding vector entries are each implemented as a single bit.

4. The method of claim 1, wherein the directional interrupt summary vector is implemented as a continuous area in a memory.

5. The method of claim 1, the directional interruption summary indicators are each implemented as a single bit.

6. The method of claim 1, the memory further comprising an interrupt table, the interrupt table having an interrupt table entry for each interrupt target ID, each of the interrupt table entries comprising a forwarding vector entry address indicator indicating a memory address of a corresponding forwarding vector entry in the second memory segment.

7. The method of claim 6, the retrieved copy of the interrupt table entry further comprising a mapping of the received interrupt target ID to a logical processor ID, the method further comprising: The mapping included in the copy of the interrupt table entry is used by the bus-attached device to convert a received interrupt target ID into a logical processor ID.

8. The method of claim 6, the retrieved copy of the interrupt table entry further comprising an execution indicator indicating whether the first target processor identified by the interrupt target ID is scheduled for use by the first guest operating system, the method further comprising: An operational indicator included by the copy of the interrupt table entry is used by the bus-attached device to check whether the first target processor is scheduled for use by the first guest operating system.

9. The method of claim 8, wherein the operation indicator is implemented as a single bit.

10. The method of claim 6, wherein the interrupt table is comprised by the second memory segment.

11. According to the method according to claim 6, the retrieved copy of the interrupt table entry also includes a first logical partition ID and a first client interrupt status area address indicator, the first logical partition ID identifies the logical partition to which the first client operating system is assigned, and the first client interrupt status area address indicator indicates a memory address of a client interrupt status area in the second memory segment assigned to the first client operating system.

12. The method of claim 6, further comprising retrieving, by the bus-attached device, a copy of a device table entry from a device table, the device table entry comprising an interrupt table address indicator indicating a memory address of an interrupt table, the bus-attached device using the memory address of the interrupt table to retrieve the first copy of the interrupt table entry.

13. The method of claim 12, the device table being stored in a third memory segment of the memory, the third memory segment being protected from access by the first and second operating systems.

14. The method of claim 13, wherein the retrieved copy of the device table entry further comprises a second logical partition ID identifying the logical partition to which the first client operating system is assigned, and a second client interrupt status region address indicator indicating a memory address of a client interrupt status region in the second memory segment assigned to the first client operating system, The method further includes checking, by the bus-attached device, that an interrupt table entry stored in a second memory segment accessible to a second client operating system has not been changed by the second client operating system by comparing a first combination of a first logical partition ID and a first client interrupt status area address indicator provided by an interrupt table entry with a second combination of a second logical partition ID and a second client interrupt status area address indicator provided by a device table entry stored in a protected third memory segment, wherein a match between the first combination and the second combination indicates that the interrupt table entry has not been changed.

15. The method of claim 14, the device table entry further comprising a logical partition ID identifying the logical partition to which the guest operating system is assigned, forwarding the first interrupt signal by the bus-attached device further comprising forwarding the logical partition ID together with the first interrupt signal.

16. The method of claim 12, the device table entry further comprising an interrupt subclass ID identifying an interrupt subclass to which the first interrupt signal is assigned, forwarding the first interrupt signal by the bus-attached device further comprising forwarding the interrupt subclass ID together with the first interrupt signal.

17. The method according to claim 1, wherein the second memory segment further comprises a first directional interrupt signal vector for each interrupt target ID assigned to a corresponding interrupt target ID, each directional first interrupt signal vector comprises a first interrupt signal indicator for each first bus connection module assigned to the first bus connection module, each directional first interrupt signal vector indicates whether there is a first interrupt signal issued by the first bus connection module and addressed to the corresponding interrupt target ID to be processed, The method further comprises: selecting, by the bus-attached device, a directional first interrupt signal vector assigned to an interrupt target ID addressed by the first interrupt signal, selecting, by the bus-attached device, in the selected directional first interrupt signal vector, a directional first interrupt signal indicator assigned to a first bus connection module issuing a first interrupt signal, The selected directional first interrupt signal indicator is updated by the bus-attached device such that the updated directional first interrupt signal indicator indicates that there is a first interrupt signal issued by the first bus connection module and addressed to the corresponding interrupt target ID to be processed.

18. The method of claim 1, wherein the first interrupt signal is received in the form of a message signal interrupt including an interrupt target ID of a target processor.

19. The method according to claim 1, wherein the second memory segment further comprises an interrupt summary vector, the interrupt summary vector having an interrupt summary indicator for each bus connection module, each interrupt summary indicator being assigned to the bus connection module to indicate whether there is an interrupt signal issued by the corresponding bus connection module to be processed, the forwarding vector comprises a second set of forwarding vector entries, the second set of forwarding vector entries comprising, for each of the directional interrupt summary indicators of the directional interrupt summary vector, a forwarding vector entry assigned to the corresponding directional interrupt summary indicator, each forwarding vector entry indicating whether the corresponding interrupt summary indicator to which it is assigned is to be updated to indicate to the first operating system that there is a first interrupt signal issued by the corresponding bus connection module to be processed, The method further comprises: receiving, by the bus-attached device from the second bus connection module, a second interrupt signal having an interrupt target ID, the interrupt target ID identifying one of the processors that is assigned to be used by the first guest operating system as a second target processor for processing the second interrupt signal, checking, by the bus-attached device, whether the second target processor is scheduled for use by the first guest operating system, if the second target processor is scheduled for use by the first client operating system, translating, by the bus-attached device, the received interrupt target ID into a logical processor ID, and forwarding the second interrupt signal to the second target processor for processing by directly addressing the second target processor with the logical processor ID resulting from the translation, Otherwise, the second interrupt signal is forwarded by the bus-attached device to the first operating system for processing using a broadcast, the broadcast comprising selecting, by the bus-attached device, a forwarding vector entry from a second set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that an interrupt summary indicator assigned to it is to be updated to indicate to the first operating system that there is a first interrupt signal issued by the second bus connection module to be processed.

20. The method of claim 19, the client interrupt table comprising a second set of client interrupt table entries, the second set of client interrupt table entries comprising an interrupt summary address indicator for each of the interrupt summary indicators of the interrupt summary vector, the respective interrupt summary address indicator indicating a memory address of the respective interrupt summary indicator in the second memory segment, The allocating of forwarding vector entries in the second set of forwarding vector entries is accomplished using a client interrupt table, wherein: Each forwarding vector in the second set of forwarding vector entries is assigned a client interrupt table entry in the second set of client interrupt table entries, and the directed interrupt summary address indicator of the corresponding client interrupt table entry indicates the memory address of the interrupt summary indicator to which the corresponding forwarding vector entry is assigned.

21. The method according to claim 19, wherein the second memory segment further comprises an interrupt signal vector for each bus connection module assigned to the corresponding bus connection module, each interrupt signal vector comprising an interrupt signal indicator for each interrupt target ID assigned to the corresponding bus connection module, each interrupt signal vector indicating whether there is an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID to be processed, The method further comprises: selecting, by the bus attached device, a directional interrupt signal vector assigned to the second bus connection module, selecting, by the bus-attached device, in the selected interrupt signal vector, an interrupt signal indicator assigned to the interrupt target ID addressed by the second interrupt signal, The selected interrupt signal indicator is updated by the bus-attached device such that the updated interrupt signal indicator indicates the presence of an interrupt signal issued by the second bus connection module and addressed to the corresponding interrupt target ID to be processed.

22. The method of claim 1, the first guest operating system is a guest operating system of the second virtualization level, and the second guest operating system is a guest operating system of the first virtualization level.

23. The method of claim 1, the first guest operating system is a guest operating system of a third virtualization level, and the second guest operating system is a guest operating system of a second virtualization level.

24. A computer system for providing an interrupt signal to a first client operating system, the first client operating system being executed using one or more processors of a plurality of processors of the computer system assigned for use by the first client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory operably connected to the bus attachment device, Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor, Each processor of the plurality of processors assigned for use by the first client operating system is further assigned an interrupt target ID used by the first client operating system and the one or more first bus connection modules to address the corresponding processor, Implementing the first client operating system using the second client operating system as a host for hosting the first client operating system, The memory includes, in a first memory segment allocated to the first guest operating system, a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator being assigned to an interrupt target ID indicating whether there is a pending first interrupt signal addressed to the corresponding interrupt target ID, the memory including, in a second memory segment allocated to the second guest operating system, a forwarding vector including a first set of forwarding vector entries, the first set of forwarding vector entries including, for each of the directional interrupt summary indicators of the directional interrupt summary vector, a forwarding vector entry allocated to the corresponding directional interrupt summary indicator, each forwarding vector entry indicating whether to update the corresponding directional interrupt summary indicator to which it is allocated so as to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID, The computer system is configured to perform a method comprising: receiving, by the bus-attached device from the first bus connection module, a first interrupt signal with an interrupt target ID, the interrupt target ID identifying one of the processors that is assigned by the first client operating system to serve as a first target processor for processing the first interrupt signal, checking, by the bus-attached device, whether the first target processor is scheduled for use by the first guest operating system, if the first target processor is scheduled for use by the first client operating system, translating, by the bus-attached device, the received interrupt target ID into a logical processor ID, and forwarding the first interrupt signal to the first target processor for processing by directly addressing the first target processor with the logical processor ID resulting from the translation, Otherwise, the bus-attached device forwards the first interrupt signal for processing to the first operating system using a broadcast, the broadcast comprising selecting, by the bus-attached device, a forwarding vector entry of a first set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that a directional interrupt summary indicator to which the selected forwarding vector entry is assigned is to be updated to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID to be processed, wherein the forwarding comprises: retrieving, by the bus-attached device, a copy of an interrupt table entry in an interrupt table assigned to the received interrupt target ID, the retrieved copy including a forwarding vector entry address indicator indicating a memory address of a forwarding vector entry in a second memory segment assigned to the received interrupt target ID, and The forwarding vector entry address indicator contained by the retrieved copy of the interrupt table entry is used by the bus-attached device to select a forwarding vector entry assigned to the received interrupt target ID.

25. A computer program product for providing an interrupt signal to a first client operating system, the first client operating system being executed using one or more processors of a plurality of processors of a computer system assigned for use by the first client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory operably connected to the bus attachment device, Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor, Each processor of the plurality of processors assigned for use by the first client operating system is further assigned an interrupt target ID used by the first client operating system and the one or more first bus connection modules to address the corresponding processor, implementing the first client operating system using the second client operating system as a host for hosting the first client operating system, The memory includes, in a first memory segment allocated to the first guest operating system, a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator being assigned to an interrupt target ID indicating whether there is a pending first interrupt signal addressed to the corresponding interrupt target ID, the memory including, in a second memory segment allocated to the second guest operating system, a forwarding vector including a first set of forwarding vector entries, the first set of forwarding vector entries including, for each of the directional interrupt summary indicators of the directional interrupt summary vector, a forwarding vector entry allocated to the corresponding directional interrupt summary indicator, each forwarding vector entry indicating whether to update the corresponding directional interrupt summary indicator to which it is allocated so as to indicate to the first operating system that there is a pending first interrupt signal addressed to the corresponding interrupt target ID, A computer program product includes a computer readable non-transitory medium readable by a processing circuit and storing instructions for execution by the processing circuit to perform a method, the method comprising: receiving, by the bus-attached device from the first bus connection module, a first interrupt signal with an interrupt target ID, the interrupt target ID identifying one of the processors that is assigned by the first client operating system to serve as a first target processor for processing the first interrupt signal, checking, by the bus-attached device, whether the first target processor is scheduled for use by the first guest operating system, if the first target processor is scheduled for use by the first client operating system, translating, by the bus-attached device, the received interrupt target ID into a logical processor ID, and forwarding the first interrupt signal to the first target processor for processing by directly addressing the first target processor with the logical processor ID resulting from the translation, Otherwise, the bus-attached device forwards the first interrupt signal for processing to the first operating system using a broadcast, the broadcast comprising selecting, by the bus-attached device, a forwarding vector entry in a first set of forwarding vector entries that is assigned to the received interrupt target ID, and updating the selected forwarding vector entry so that the selected forwarding vector entry indicates that a directional interrupt summary indicator to which the selected forwarding vector entry is assigned is to be updated to indicate to the first operating system that there is a first interrupt signal addressed to the corresponding interrupt target ID to be processed, wherein the forwarding comprises: retrieving, by the bus-attached device, a copy of an interrupt table entry in an interrupt table assigned to the received interrupt target ID, the retrieved copy including a forwarding vector entry address indicator indicating a memory address of a forwarding vector entry in a second memory segment assigned to the received interrupt target ID, and The forwarding vector entry address indicator contained by the retrieved copy of the interrupt table entry is used by the bus-attached device to select a forwarding vector entry assigned to the received interrupt target ID.

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