Enhancing Media Engagement through Deep Learning

Abstract

The present invention discloses improving media engagement through deep learning, and specifically discloses devices, systems, and techniques for using a neural network to adjust playback speed and volume based on environmental factors and other factors to facilitate understanding of media content. In at least one embodiment, if the audio associated with the media content is difficult to understand based on background noise, accent, material difficulty, and other factors that reduce the intelligibility of the media content, the playback of the media content is slowed down or accelerated.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for using a neural network to adjust playback speed and volume based on environmental factors and other factors to facilitate understanding of media content. For example, at least one embodiment relates to a processor or computing system for slowing down or accelerating media content if the audio associated with the media content is difficult to understand based on background noise, the language or accent spoken. Background Art

[0002] The widespread availability of media content worldwide has introduced unique problems related to the ability of users to understand the media content. As an example, users in one region may speak a native language but consume media content in another language. The media content may include audio spoken in an accent that is foreign to the media consumer. Environmental factors (such as background noise) may make it difficult to understand the media content. Brief Description of the Drawings

[0003] Figure 1 is a block diagram showing a media content optimizer for adjusting the speed and volume of media content from a media source according to at least one embodiment;

[0004] Figure 2 is a block diagram showing components of a media content optimizer according to at least one embodiment;

[0005] Figure 3 is a block diagram showing a text generation component of a media content optimizer according to at least one embodiment;

[0006] Figure 4 is a block diagram showing a semantic analysis component of a media content optimizer according to at least one embodiment;

[0007] Figure 5 is a block diagram showing a confidence analysis component of a media content optimizer according to at least one embodiment;

[0008] Figure 6 is a block diagram showing an adjustment determination component of a media content optimizer according to at least one embodiment;

[0009] Figure 7 shows a process for adjusting the speed and volume of media content according to factors affecting the understanding of the media content according to at least one embodiment;

[0010] Figure 8A shows inference and / or training logic according to at least one embodiment;

[0011] Figure 8B shows inference and / or training logic according to at least one embodiment;

[0012] Figure 9 Illustrates the training and deployment of a neural network according to at least one embodiment;

[0013] Figure 10 Illustrates an example data center system according to at least one embodiment;

[0014] Figure 11A Illustrates an example of an autonomous vehicle according to at least one embodiment;

[0015] Figure 11B Illustrates according to at least one embodiment Figure 11A an example of the camera positions and fields of view of an autonomous vehicle;

[0016] Figure 11C is a block diagram of an example system architecture of an autonomous vehicle according to at least one embodiment showing Figure 11A ;

[0017] Figure 11D is a diagram of a system according to at least one embodiment showing communication between one or more cloud-based servers and Figure 11A an autonomous vehicle;

[0018] Figure 12 is a block diagram of a computer system according to at least one embodiment;

[0019] Figure 13 is a block diagram of a computer system according to at least one embodiment;

[0020] Figure 14 Illustrates a computer system according to at least one embodiment;

[0021] Figure 15 Illustrates a computer system according to at least one embodiment;

[0022] Figure 16A Illustrates a computer system according to at least one embodiment;

[0023] Figure 16B Illustrates a computer system according to at least one embodiment;

[0024] Figure 16C Illustrates a computer system according to at least one embodiment;

[0025] Figure 16D Illustrates a computer system according to at least one embodiment;

[0026] Figure 16E and Figure 16F Illustrates a shared programming model according to at least one embodiment;

[0027] Figure 17 Illustrates an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

[0028] Figure 18A - Figure 18B Illustrates an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment.

[0029] Figure 19A and Figure 19B Illustrates additional exemplary graphics processor logic in accordance with at least one embodiment;

[0030] Figure 20 Illustrates a computer system in accordance with at least one embodiment;

[0031] Figure 21A Illustrates a parallel processor in accordance with at least one embodiment;

[0032] Figure 21B Illustrates a partitioning unit in accordance with at least one embodiment;

[0033] Figure 21C Illustrates a processing cluster in accordance with at least one embodiment;

[0034] Figure 21D Illustrates a graphics multiprocessor in accordance with at least one embodiment;

[0035] Figure 22 Illustrates a multi-graphics processing unit (GPU) system in accordance with at least one embodiment;

[0036] Figure 23 Illustrates a graphics processor in accordance with at least one embodiment;

[0037] Figure 24 Is a block diagram illustrating a processor microarchitecture for a processor in accordance with at least one embodiment;

[0038] Figure 25 Illustrates a deep learning application processor in accordance with at least one embodiment;

[0039] Figure 26 Is a block diagram illustrating an exemplary neuromorphic processor in accordance with at least one embodiment;

[0040] Figure 27 Illustrates at least a portion of a graphics processor in accordance with one or more embodiments;

[0041] Figure 28 Illustrates at least a portion of a graphics processor in accordance with one or more embodiments;

[0042] Figure 29Shows at least a portion of a graphics processor in accordance with one or more embodiments;

[0043] Figure 30 Is a block diagram showing a graphics processing engine of a graphics processor in accordance with at least one embodiment;

[0044] Figure 31 Is a block diagram of at least a portion of a graphics processor core in accordance with at least one embodiment;

[0045] Figure 32A And Figure 32B Shows thread execution logic in accordance with at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0046] Figure 33 Shows a parallel processing unit (“PPU”) in accordance with at least one embodiment;

[0047] Figure 34 Shows a general processing cluster (“GPC”) in accordance with at least one embodiment;

[0048] Figure 35 Shows a memory partition unit of a parallel processing unit (“PPU”) in accordance with at least one embodiment;

[0049] Figure 36 Shows a streaming multiprocessor in accordance with at least one embodiment.

[0050] Figure 37 Is an example data flow diagram of an advanced computing pipeline in accordance with at least one embodiment;

[0051] Figure 38 Is a system diagram of an example system for training, adapting, instantiating, and deploying a machine learning model in an advanced computing pipeline in accordance with at least one embodiment;

[0052] Figure 39 Includes an example illustration of an advanced computing pipeline for processing imaging data in accordance with at least one embodiment;

[0053] Figure 40A Includes an example data flow diagram of a virtual instrument supporting an ultrasound device in accordance with at least one embodiment;

[0054] Figure 40B Includes an example data flow diagram of a virtual instrument supporting a CT scanner in accordance with at least one embodiment;

[0055] Figure 41A Shows a data flow diagram of a process for training a machine learning model in accordance with at least one embodiment; and

[0056] Figure 41BAn example illustration of a client - server architecture that enhances an annotation tool using a pre - trained annotation model according to at least one embodiment. Detailed Description

[0057] Figure 1 A block diagram showing a media content optimizer 116 for adjusting the speed and volume 120 of media content 102 from a media source 104 according to at least one embodiment. In at least one embodiment, the media content optimizer 116 is a collection of software components described below, which includes instructions that, when executed, adjust the playback speed and / or volume 122, 124, 126 of media content (such as video or audio) from the media source 104. In at least one embodiment, the media content optimizer 116 includes one or more trained neural networks 118 for performing steps for media content optimization, as described below in connection with Figure 7 Outlined. In at least one embodiment, one or more trained neural networks 118 are a set of constant numerical values and instructions that, when executed, calculate numerical values indicating the likelihood that the inputs 202, 206 have specific characteristics, as described below. In at least one embodiment, one or more trained neural networks 118 are any type of neural network described herein, such as a convolutional neural network, which is used to determine factors that assist the media content optimizer 116 in adjusting the media content 122, 124, 126.

[0058] In at least one embodiment, the media content optimizer 116 receives a direct input 102 and other inputs 106. In at least one embodiment, the direct input 102 is an input containing media content (such as audio or video) to be optimized by the media content optimizer 116. In at least one embodiment, the direct input 102 includes data from the media source 104. In at least one embodiment, the media source 104 is any source, such as a streaming service, a recording device, software for playing media on a computer, or any other source capable of providing audio or video data or generating and / or distributing media content. In at least one embodiment, the media source 104 provides audio and / or video data to the media content optimizer 116, and the media content optimizer 116 determines whether the audio and / or video data is played faster 122, not adjusted 124, or played slower 126 by a media player. In at least one embodiment, the media content optimizer 116 adjusts the volume of the audio and / or video data.

[0059] In at least one embodiment, other input 102 is information for optimizing media content by media content optimizer 116. In at least one embodiment, other input 102 is data representing information for optimizing media content playback by media content optimizer 116, such as a numerical value or a set of numerical values. In at least one embodiment, other input 106 includes accent 108 information. In at least one embodiment, accent 108 information is one or more numerical values or other data types indicating whether the audio and / or video from media source 104 contains words with an accent different from the user's local accent or an accent different from the geographical location where the audio and / or video is played. In at least one embodiment, accent 108 information is an indicator of confusion for the user in playing audio and / or video content from media source 104, as described below in connection with Figure 5 as described.

[0060] In at least one embodiment, other input 106 includes usage 110 information. In at least one embodiment, usage 110 information is one or more numerical values or other data values indicating whether the user has repeated, restarted, or rewound audio or video content from media source 104. In at least one embodiment, usage 110 information also includes a numerical value indicating the number of times the user has repeated, restarted, or rewound audio or video content from media source 104. In at least one embodiment, the user repeating, restarting, or rewinding audio and / or video content from media source 104 is an indicator of confusion or lack of understanding regarding the audio and / or video content, as described below in connection with Figure 5 further described.

[0061] In at least one embodiment, other input 106 includes language 112 information. In at least one embodiment, language 112 information is one or more data values, such as numerical values, indicating one or more languages used in the audio and / or video content from media source 104. In at least one embodiment, language 112 information indicates whether the language used in the audio and / or video content from media source 104 is different from the language spoken and / or understood by the user playing the audio and / or video content. In one embodiment, language 112 information also indicates whether a language is not spoken or not understood in a particular geographical region or area where the audio and / or video content from media source 104 is played. In at least one embodiment, language 112 information is an indicator of confusion regarding the audio and / or video content or an indicator of the likelihood of confusion, as described below in connection with Figure 5 further described.

[0062] In at least one embodiment, other input 106 includes environmental 114 information. In at least one embodiment, environmental 114 information is one or more numerical values or other data types that indicate the presence of environmental factors that contribute to a user's inability to understand the audio and / or video content from media source 104. In at least one embodiment, the environmental factors indicated in environmental 114 information include background noise or other types of noise that reduce the user's understanding of the video and / or audio content from media source 104. In at least one embodiment, other types of noise include wind, thunder, or other environmental factors that reduce the understanding of the audio and / or video content from the media source. In at least one embodiment, other environmental factors indicated in environmental 114 information include the quality of the audio and / or video data from media source 104, such as encoding bit rate, signal noise, and any other information indicating audio and / or video quality. In at least one embodiment, other input 106 includes any other information other than the information outlined above that helps determine confusion regarding the audio and / or video content from media source 104, as described below in conjunction with Figure 5 as described.

[0063] In at least one embodiment, media content optimizer 116 outputs 120 one or more values of adjustments 122, 124, 126 to be made or not made to the playback of audio and / or video from media source 104. In at least one embodiment, a playback device (such as any device that plays media content or any software that facilitates the playback of audio and / or video content) uses one or more adjustment values 122, 124, 126 output 120 from media content optimizer 116 to adjust the audio and / or video content to improve the understanding of one or more users.

[0064] In at least one embodiment, media content optimizer 116 outputs 120 one or more values indicating that the playback of the audio and / or video content from the media source should be increased 122. In at least one embodiment, if the playback speed of the audio and / or video content is made faster, it is increased 122 during playback. In at least one embodiment, if the playback volume of the audio and / or video content is increased, it is increased 122 during playback.

[0065] In at least one embodiment, media content optimizer 116 outputs 120 one or more values indicating that the playback of the audio and / or video content from the media source should maintain its current value 124. In at least one embodiment, if the playback device does not make adjustments to the playback speed or volume, the audio and / or video content maintains its current value 124 during playback.

[0066] In at least one embodiment, the media content optimizer 116 outputs 120 one or more values indicating that the playback of audio and / or video content from a media source should be downscaled 126. In at least one embodiment, if the playback speed of the audio and / or video content is made slower, the audio and / or video content is downscaled 126 during playback. In at least one embodiment, if the playback volume of the audio and / or video content is decreased, the audio and / or video content is downscaled 126 during playback.

[0067] Figure 2 is a block diagram showing components 208, 210, 212, 214 of a media content optimizer 216 according to at least one embodiment. In at least one embodiment, the media content optimizer 216 takes audio and / or video data from a media source 204 as input 202, as described above in connection with Figure 1 is described. According to at least one embodiment, the media content optimizer 216 also employs other information (such as the information described above in connection with Figure 1 is described) as input 202 to facilitate determining the understanding or confidence 212 of the audio and / or video content from the media source 204.

[0068] In at least one embodiment, the media content optimizer 216 includes a text generation 208 component. In at least one embodiment, the text generation 208 component is an instruction set that, when executed, generates text from audio and / or video data. In at least one embodiment, the text generation 208 component includes one or more neural networks that are trained to generate text data from audio and / or video data during inference, as described below in connection with Figure 3 is described. In at least one embodiment, the text generation 208 component includes a speech-to-text neural network. In at least one embodiment, as further described below in connection with Figure 3 is described, the speech-to-text neural network is any type of neural network described herein for facilitating the recognition of words, phrases, and sentences in audio and / or video content and generating text representing the recognized words, phrases, and sentences.

[0069] In at least one embodiment, the media content optimizer 216 includes a semantic analysis 210 component. In at least one embodiment, the semantic analysis 210 component is an instruction set that, when executed, determines the relationships between the text words, phrases, and sentences generated by the text generation 208 component in the media content optimizer 216. In at least one embodiment, the semantic analysis 210 component includes one or more neural networks that are trained to determine the word, sentence, and paragraph relationships in the text generated by the text generation 208 component during inference, as described below in connection with Figure 4As described. In at least one embodiment, the semantic analysis 210 component determines the context associated with words, sentences, and paragraphs in the text generated by the text generation 208 component of the media content optimizer. In at least one embodiment, the context between the words, sentences, and paragraphs determined by the semantic analysis 210 component is used by the adjustment determination 214 component to determine whether to make adjustments 220, 222, 224 to the audio and / or video playback of the playback device to increase understanding.

[0070] In at least one embodiment, the media content optimizer 216 includes a confidence analysis 212 component. In at least one embodiment, the confidence analysis 212 component is an instruction set that, when executed, determines a confidence value indicating whether a user is likely to understand the audio and / or video data from the media source 204 during playback. In at least one embodiment, the confidence analysis 212 component takes other information 206 as input, as described above in connection with Figure 1 As described. In at least one embodiment, the other information 206 includes environmental information, accent information, and any other information further described below in connection with Figure 5 As further described. In at least one embodiment, the confidence analysis 212 component obtains the optional speech-to-text confidence metric described below in connection with Figure 3 As input. In at least one embodiment, the confidence analysis 212 component of the media content optimizer 216 outputs a confidence value.

[0071] In at least one embodiment, the confidence value is one or more numerical values or other data types indicating the degree of confidence that a user understands or is not confused by the audio and / or video data during playback. In at least one embodiment, the adjustment determination 214 component uses the confidence value to determine whether to make adjustments 220, 222, 224 to the audio and / or video playback performed by the playback device to increase understanding.

[0072] In at least one embodiment, the media content optimizer 216 includes an adjustment determination 214 component. In at least one embodiment, the adjustment determination 214 component of the media content optimizer 216 is an instruction set that, when executed, determines whether the playback is adjusted 220, 222, 224 by the playback device playing the audio and / or video data from the media source 204. In at least one embodiment, the adjustment determination 214 component determines the output 218 of the media content optimizer 216.

[0073] In at least one embodiment, the output 218 of the media content optimizer 216 determined by the adjustment determination 214 component includes an indication that the playback should be increased 220. In at least one embodiment, the increase 220 indication is one or more values indicating an increase in speed and / or volume during playback of video and / or audio content from the media source 204 by the playback device. In at least one embodiment, the increase 220 indication includes an increase in the rate of speed and / or an increase in the intensity of volume. In at least one embodiment, the indication that the playback should be increased 220 indicates an increase in the playback speed and / or volume, as described above in connection with Figure 1 as described.

[0074] In at least one embodiment, the output 218 of the media content optimizer 216 determined by the adjustment determination 214 component includes an indication that the playback should not be adjusted 222. In at least one embodiment, the maintain current 222 indication is one or more values indicating that no speed and / or volume change is made during playback of video and / or audio content from the media source 204 by the playback device. In at least one embodiment, the indication that the playback should not be adjusted or should maintain its current 222 playback rate and volume indicates that the playback speed and / or volume has not changed, as described above in connection with Figure 1 as described.

[0075] In at least one embodiment, the output 218 of the media content optimizer 216 determined by the adjustment determination 214 component includes an indication that the playback should be decreased 224. In at least one embodiment, the decrease 224 indication is one or more values indicating a decrease in speed and / or volume during playback of video and / or audio content from the media source 204 by the playback device. In at least one embodiment, the decrease 224 indication includes a decrease in the rate of speed and / or a decrease in the intensity of volume. In at least one embodiment, the indication that the playback should be decreased 224 indicates a decrease in the playback speed and / or volume, as described above in connection with Figure 1 as described.

[0076] Figure 3 is a block diagram showing the text generation 306 component of the media content optimizer according to at least one embodiment. In at least one embodiment, the text generation 306 component is an instruction set that, when executed, generates text from an input 302 such as media 304 data. In at least one embodiment, the input 302 to the text generation 306 component includes media 304 containing the spoken word, such as audio or video data.

[0077] In at least one embodiment, the text generation 306 component includes a speech-to-text network 308. In at least one embodiment, the speech-to-text network 308 is a set of numerical values and software instructions that, when executed, generate text data 312, 314, 316 from media 304. In at least one embodiment, the speech-to-text network 308 is a neural network. In at least one embodiment, the speech-to-text network is a recurrent neural network. In at least one embodiment, the speech-to-text network 308 is any type of neural network that generates text based on audio or video input data as further described herein.

[0078] In at least one embodiment, the text generation 306 component produces an output 310 that includes text data 312, 314, 316 and an optional confidence metric 318. In at least one embodiment, the text data 312, 314, 316 is output 310 for use by the semantic analysis 320 component, as described above in connection with Figure 2 and below in connection with Figure 4 as described. In at least one embodiment, the optional confidence metric 318 is output 310 for use by the confidence analysis 322 component, as described above in connection with Figure 2 and below in connection with Figure 5 as described.

[0079] In at least one embodiment, the text data 312, 314, 316 output 310 from the text generation 306 component includes text representing a word 312. In at least one embodiment, the text representing the word 312 is one or more data values, such as characters, hexadecimal values, strings, or any other data used to represent text information. In at least one embodiment, the text representing the word 312 is generated by the text generation 306 component as a result of an individual's spoken word, or for each individual's spoken word during the playback of the input 302 media 304.

[0080] In at least one embodiment, the text data 312, 314, 316 output 310 from the text generation 306 component includes text representing a sentence 314. In at least one embodiment, the text representing the sentence 314 is one or more data values, such as a character set, hexadecimal values, strings, or any other data used to represent text information that includes multiple words. In at least one embodiment, the text representing the sentence 314 is generated by the text generation 306 component as a result of a combination of phrases or words spoken during the playback of the input 302 media 304. In at least one embodiment, the text data representing the sentence 314 includes one or more text data items representing the word 312.

[0081] In at least one embodiment, the text data 312, 314, 316 output 310 from the text generation 306 component includes text representing a paragraph 316. In at least one embodiment, the text representing the paragraph 316 is one or more data values, such as a character set, a hexadecimal value, a string, or any other data for representing text information including multiple sentences, including any special character data such as a news line. In at least one embodiment, the text data representing the paragraph 316 includes one or more text data items representing a sentence 314.

[0082] In at least one embodiment, the confidence metric 318 is a numerical value indicating the confidence or probability that the text data 312, 314, 316 generated by the text generation 306 component from the input 302 media 304 is accurate. In at least one embodiment, the confidence metric 318 is a byproduct of the text generation 306 provided by the speech-to-text network 308. In at least one embodiment, the confidence metric 318 is optionally generated by the speech-to-text network 308 and is not available during each generation of text data by the speech-to-text network 308, depending on whether the implementation of the speech-to-text network 308 provides a confidence metric 318 output. In at least one embodiment, if the confidence metric 318 is generated by the speech-to-text network 308, the confidence metric 318 is optionally output 310 to the confidence analysis 322 component, as described below in connection with Figure 5 as described.

[0083] Figure 4 is a block diagram showing a semantic analysis 410 component of a media content optimizer according to at least one embodiment. In at least one embodiment, the semantic analysis 410 component is an instruction set that, when executed, determines the semantic similarity in blocks of input 402 text data 404, 406, 508 converted from media by a text generation component, as described above in connection with Figure 3 as described. In at least one embodiment, the semantic analysis 410 component takes text data including words 404, sentences 406, or paragraphs 408 as input 402. In at least one embodiment, the semantic analysis 410 component does not operate on individual word 404 data because a bidirectional encoder representation (BERT) 412 network from a converter requires multiple text data items to determine semantic similarity.

[0084] In at least one embodiment, the semantic analysis 410 component includes a Bidirectional Encoder Representations from Transformers (BERT) 412 network. In at least one embodiment, the BERT 412 network is a set of numerical values and instructions that, when executed, determine the meaning or context of each word in the input 402 text data 406, 408. In at least one embodiment, the BERT 410 network includes one or more neural networks or autoencoders, which are further described herein. In at least one embodiment, the BERT 410 network analyzes a block of text data, such as one or more sentences 406 or one or more paragraphs 408, to determine the context of each individual word in the sentence or paragraph.

[0085] In at least one embodiment, the BERT 412 network classifies the input 402 text data 406, 408 into one or more categories. In at least one embodiment, each category describes the context of each word, sentence, or paragraph in the input 402 text data 406, 408. In at least one embodiment, the BERT 412 network accepts input 402 text data 406, 408 having a length of from 3 to 512 words. In at least one embodiment, the BERT 412 network accepts input 402 text data 406, 408 that contains more than 512 words. In at least one embodiment, the BERT 410 network is trained in a specific language. In at least one embodiment, the BERT 410 network is trained on a language that is comparable to the language used for the text generated by the text generation component.

[0086] In at least one embodiment, the semantic analysis 410 component determines whether consecutive sentences 406 or paragraphs 408 have a similar meaning. In at least one embodiment, the semantic analysis 410 component determines whether consecutive sentences 406 or paragraphs 408 have a similar context. In at least one embodiment, if consecutive sentences 406 or paragraphs 408 do not contain a similar meaning or context, it is not possible to understand the sentences 406 or paragraphs 408, and it is more likely that an adjustment will be made by the adjustment determination 418 component, as described below in connection with Figure 6 what is described. In at least one embodiment, if a sentence 406 or paragraph 408 does not contain a meaning or context that can be established by the semantic analysis 410 component, it is not possible to understand the sentence 406 or paragraph 408, and it is more likely that an adjustment will be made by the adjustment determination 418 component.

[0087] In at least one embodiment, the BERT 412 network component in semantic analysis 410 outputs 414 one or more embedding vectors 416. In at least one embodiment, the embedding vectors 416 are a set of numerical or other data types that are vectors of individual words 404, sentences 406, or paragraphs 408 in the input 402 data that are expressed as containing context or meaning data. In at least one embodiment, the context or meaning data is descriptive data containing categories used to classify the context or meaning of words 404, sentences 406, or paragraphs 408 in the input 402 data. In at least one embodiment, one or more of the embedding vectors 416 contain information for determining whether the input 402 sentence 406 or paragraph 408 contains context or meaning that is unrelated between consecutive sentences 406 or paragraphs 408.

[0088] In at least one embodiment, the BERT 412 network in the semantic analysis 410 component optionally outputs a confusion matrix. In at least one embodiment, the confusion matrix is a set or matrix of numerical values that describe the performance of the BERT 412 network. In at least one embodiment, the confusion matrix is optionally used by the tuning determination 418 component.

[0089] Figure 5 is a block diagram showing the confidence analysis 518 component of the media content optimizer according to at least one embodiment. In at least one embodiment, the confidence analysis 518 component is a set of instructions that, when executed, determine a confidence 524 value indicating the confidence that a user can understand media content (such as the media content described above in connection with Figure 1 During playback on a playback device. In at least one embodiment, the confidence analysis 518 component includes a trained neural network 520. In at least one embodiment, the trained neural network is a set of numerical values and instructions that, when executed, determine the confidence 524 value based on the input 502 data and optional input 504 data. In at least one embodiment, the trained neural network 520 is a recurrent neural network or any type of neural network that determines a category based on one or more input 502, 504 data items, such as those neural networks described herein. In at least one embodiment, the confidence 524 value is determined by the confidence analysis 518 component based on one or more input 502 and optional input 504.

[0090] In at least one embodiment, the input 502 data to the confidence analysis 518 component includes usage 508 information. In at least one embodiment, the usage 508 information is one or more numerical values or other data values indicating whether the user repeats, restarts, or rewinds audio or video content during playback on a playback device, as described above in connection with Figure 1As described. In at least one embodiment, the usage 508 information further includes a numerical value indicating the number of times the user has repeated, restarted, or re - wound audio or video content during playback on a playback device. In at least one embodiment, the user repeating, restarting, or re - winding audio and / or video content during playback is an indicator of confusion or lack of understanding regarding the audio and / or video content.

[0091] In at least one embodiment, the input 502 data to the confidence analysis 518 component includes environment 510 information. In at least one embodiment, the environment 510 information is one or more numerical values or other data types indicating the presence of environmental factors that contribute to the user's inability to understand audio and / or video content during playback. In at least one embodiment, the environmental factors indicated in the environment 510 information include background noise or other types of noise that reduce the user's understanding of video and / or audio content during playback. In at least one embodiment, other types of noise include wind, thunder, or other environmental factors that reduce the understanding of audio and / or video content. In at least one embodiment, the other environmental factors indicated in the environment 510 information include the quality of the audio and / or video data, such as the encoding bit rate, signal - to - noise ratio, and any other information indicating the audio and / or video quality.

[0092] In at least one embodiment, the input 502 data to the confidence analysis 518 component includes language 512 information. In at least one embodiment, the language 512 information is one or more data values indicating one or more languages used in the audio and / or video content, such as numerical values, as described above in connection with Figure 1 As described. In at least one embodiment, the language 512 information indicates whether the language used in the audio and / or video content is different from the language spoken and / or understood by the user playing the audio and / or video content. In one embodiment, the language 512 information further indicates whether the language is not spoken or not understood in a particular geographical region or area where the audio and / or video content is being played. In at least one embodiment, the language 512 information is an indicator of confusion or an indicator of the likelihood of confusion regarding the audio and / or video content.

[0093] In at least one embodiment, the input 502 data to the confidence analysis 518 component includes accent 514 information. In at least one embodiment, the accent 514 information is one or more numerical values or other data types indicating whether the audio and / or video data contains words spoken with an accent different from the user's local accent, or an accent that is not local to the geographical location where the audio and / or video data is being played. In at least one embodiment, accent 414 information that is different from the user's local accent or non - local to the geographical location where the audio and / or video data is being played is more likely to confuse the user and reduce confidence.

[0094] In at least one embodiment, the input 502 data to the confidence analysis 518 component includes any other factor 516 that helps determine the confidence 524 value. In at least one embodiment, the confidence analysis 518 component optionally takes the speech-to-text confidence 506 as an input 504, as described above in connection with Figure 3 what has been described. In at least one embodiment, the speech-to-text confidence 506 as described above is not always available from a text generation component that includes a neural network. In one embodiment, when available, the speech-to-text confidence 506 indicates the likelihood that the text data input to the semantic analysis component is accurate compared to the words spoken in the media content being played. In at least one embodiment, a low speech-to-text confidence 506 indicates difficulty in generating text from the input media and indicates a higher likelihood of confusion that results in a lower confidence value generated by the confidence analysis 518 component.

[0095] In at least one embodiment, the confidence analysis 518 component produces a confidence 524 value as an output 522. In at least one embodiment, the confidence 524 value is a numerical value that indicates whether a user is likely to be confused or is likely to confuse the media content (such as audio or video) during playback on a playback device. In at least one embodiment, the confidence 524 value is output 522 to the adjustment determination 526 component, as described below in connection with Figure 6 what has been described.

[0096] Figure 6 is a block diagram showing an adjustment determination 608 component of a media content optimizer according to at least one embodiment. In at least one embodiment, the adjustment determination 608 component is a set of instructions that, when executed, determines whether media content (such as audio or video data) needs to be upscaled 614, downscaled 618, or maintained at its current settings 616 during playback. In at least one embodiment, the adjustment determination 608 component includes a trained neural network 610. In at least one embodiment, the trained neural network is a set of numerical values and instructions that, when executed, determine the class 614, 616, 618 of the output 612 based on input 602 data (such as an embedding vector 604 and a confidence 606 value). In at least one embodiment, the trained neural network 610 is any type of neural network further described herein.

[0097] In at least one embodiment, the adjustment determination 608 component takes the embedding vector 604 as an input 602 as described above in connection with Figure 4 what has been described. In at least one embodiment, the embedding vector 604 provides information about the meaning and context of each word, sentence, or paragraph in the text data provided by the speech-to-text network in the text generation component, as described above in connection with Figure 3As described above. In at least one embodiment, the adjustment determination 608 component will use the confidence 606 value as described above in connection with Figure 5 as an additional input 602. In at least one embodiment, the confidence 606 value indicates the likelihood that the user will confuse the media audio and / or video content during playback.

[0098] In at least one embodiment, the adjustment determination 608 component outputs 612 one or more values indicating adjustments 614, 616, 618 that can be made to the playback of the audio and / or video data to improve understanding based on the input 602 data. In at least one embodiment, the output 612 of the adjustment determination 608 component includes an indication that the playback should be increased 614. In at least one embodiment, the increase 614 indication is one or more numerical values indicating an increase in speed and / or volume during the playback of video and / or audio content by the playback device. In at least one embodiment, the increase 614 indication includes an increase in the rate of speed and / or an increase in the intensity of volume. In at least one embodiment, the indication that the playback should be increased 614 indicates an increase in the playback speed and / or volume, as described above in connection with Figure 1 as described.

[0099] In at least one embodiment, the output 612 of the adjustment determination 608 component includes an indication that the playback should not be adjusted or should remain at the current 616 setting. In at least one embodiment, the keep current 616 indication is one or more numerical values indicating that there is no change in speed and / or volume during the playback of video and / or audio content by the playback device. In at least one embodiment, the indication that the playback should not be adjusted or should remain at its current 616 playback rate and volume indicates no change in the playback speed and / or volume, as described above in connection with Figure 1 as described.

[0100] In at least one embodiment, the output 612 of the adjustment determination 612 component includes an indication that the playback should be decreased 618. In at least one embodiment, the decrease 618 indication is one or more numerical values indicating a decrease in speed and / or volume during the playback of video and / or audio content by the playback device. In at least one embodiment, the decrease 618 indication includes a decrease in the rate of speed and / or a decrease in the intensity of volume. In at least one embodiment, the indication that the playback should be decreased 618 indicates a decrease in the playback speed and / or volume, as described above in connection with Figure 1 as described.

[0101] Figure 7illustrates process 700 for adjusting the speed and volume of media content 712, 714, 716 based on factors that affect the understanding of the media content, according to at least one embodiment. In at least one embodiment, process 700 begins 702 by generating text 704 from input audio and / or video data using a text generation component, as described above in connection with Figure 2 and Figure 3 . In at least one embodiment, the generated text 704 includes words, sentences, and paragraphs, as well as optional speech-to-text confidence values, as described above.

[0102] In at least one embodiment, once the text is generated 704, a semantic analysis component (as described above in connection with Figure 2 and Figure 4 ) determines the semantic similarity 706 between words, sentences, and paragraphs. In at least one embodiment, as described above in connection with Figure 2 and Figure 5 , a confidence analysis component determines the confidence 708 that the user is or may be confused during the playback of the audio and / or video data. Using the semantic similarity 706 indicating the shared context between words, sentences, or paragraphs and the confidence 708, an adjustment determination component calculates whether the playback of the audio and / or video data needs to be adjusted 710.

[0103] In at least one embodiment, if the semantic similarity 706 indicates a low shared context and the confidence 708 is low, the playback of the audio and / or video is slowed down 712, as described above in connection with Figure 2 and Figure 6 . In at least one embodiment, if the semantic similarity 706 indicates a medium or average shared context and the confidence 708 is medium, the playback of the audio and / or video maintains its current playback speed and volume 714, as described above in connection with Figure 2 and Figure 6 . In at least one embodiment, if the semantic similarity 706 indicates a high shared context and the confidence 708 is high, the playback of the audio and / or video is easily understood and sped up 716, as described above in connection with Figure 2 and Figure 6 . In at least one embodiment, after determining 710 any possible adjustments 712, 714, 716, process 700 for adjusting the speed and volume of the media content ends 718.

[0104] Inference and training logic

[0105] Figure 8A illustrates inference and / or training logic 815 for performing inference and / or training operations associated with one or more embodiments. Below in connection with Figure 8A and / orFigure 8B Provide details regarding inference and / or training logic 815.

[0106] In at least one embodiment, the inference and / or training logic 815 may include, but is not limited to, code and / or data storage 801 for storing forward and / or output weights and / or input / output data, and / or other parameters that configure neurons or layers of a neural network trained to and / or for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 815 may include or be coupled to code and / or data storage 801 for storing graph code or other software to control timing and / or sequencing, where weight and / or other parameter information is loaded to configure the logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, the code and / or data storage 801 stores the weight parameters and / or input / output data of each layer of the neural network used or trained in combination with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 801 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0107] In at least one embodiment, any portion of the code and / or data storage 801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 801 may be cache memory, dynamic random-access memory (“DRAM”), static random-access memory (“SRAM”), non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 801 is internal or external to the processor, e.g., or consists of DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage space on or off the chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0108] In at least one embodiment, the inference and / or training logic 815 can include, but is not limited to, code and / or data storage 805 to store the backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained as and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, code and / or data storage 805 stores the weight parameters and / or input / output data of each layer of the neural network used or trained in conjunction with one or more embodiments during backpropagation of the input / output data and / or weight parameters. In at least one embodiment, the training logic 815 can include or be coupled to code and / or data storage 805 for storing graph code or other software to control timing and / or sequencing, where the weights and / or other parameter information is loaded to configure logic that includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0109] In at least one embodiment, the code (such as graph code) causes weight or other parameter information to be loaded into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of the code and / or data storage 805 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 805 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 805 can be cache memory, DRAM, SRAM, non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 805 is internal or external to the processor, e.g., whether it consists of DRAM, SRAM, flash memory, or some other storage type, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0110] In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be separate storage structures. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be the same storage structure. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 801 and code and / or data storage 805 may be included with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory.

[0111] In at least one embodiment, inference and / or training logic 815 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 810 (including integer and / or floating point units) for performing logical and / or mathematical operations at least in part based on training and / or inference code (e.g., graph code) or as indicated thereby, the result of which may produce activations (e.g., output values from a layer or neuron within a neural network) stored in activation storage 820, which are a function of input / output and / or weight parameter data stored in code and / or data storage 801 and / or code and / or data storage 805. In at least one embodiment, the activations are generated by linear algebra and / or matrix-based mathematics performed by ALU 810 in response to executing instructions or other code, where weight values stored in code and / or data storage 805 and / or code and / or data storage 801 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 805 or code and / or data storage 801 or other on-chip or off-chip storage.

[0112] In at least one embodiment, one or more ALUs 810 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 810 may be outside the processor or other hardware logic devices or circuits that use them (such as a coprocessor). In at least one embodiment, one or more ALUs 810 may be included within the execution unit of a processor or otherwise included in a group of ALUs accessible by the execution unit of a processor, and the execution unit of the processor may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed function unit, etc.). In at least one embodiment, code and / or data storage 801, code and / or data storage 805, and activation storage 820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 820 may be included with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory. Additionally, the inference and / or training code may be stored together with other code accessible by the processor or other hardware logic or circuits and may be extracted and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuits of the processor.

[0113] In at least one embodiment, activation storage 820 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 820 may be entirely or partially inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 820 is internal or external to the processor, e.g., or contains DRAM, SRAM, flash memory, or other storage types, may depend on the on-chip or off-chip available storage, the latency requirements for training and / or inference functions, the batch size of the data used in the inference and / or training neural network, or some combination of these factors.

[0114] In at least one embodiment, Figure 8A the inference and / or training logic 815 shown may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, Figure 8AThe inference and / or training logic 815 shown may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware, such as field programmable gate array (“FPGA”).

[0115] Figure 8B An inference and / or training logic 815 according to at least one embodiment is shown. In at least one embodiment, the inference and / or training logic 815 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise uniquely used along with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 8B the inference and / or training logic 815 shown in may be used in conjunction with an application specific integrated circuit (ASIC), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, Figure 8B the inference and / or training logic 815 shown in may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 815 includes, but is not limited to, code and / or data storage 801 and code and / or data storage 805, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 8B at least one embodiment shown, each of code and / or data storage 801 and code and / or data storage 805 is respectively associated with dedicated computing resources (e.g., computing hardware 802 and computing hardware 806). In at least one embodiment, each of computing hardware 802 and computing hardware 806 includes one or more ALUs that respectively perform mathematical functions (e.g., linear algebra functions) only on the information stored in code and / or data storage 801 and code and / or data storage 805, and the results of the executed functions are stored in activation storage 820.

[0116] In at least one embodiment, each of code and / or data stores 801 and 805 and corresponding computing hardware 802 and 806 respectively corresponds to a different layer of a neural network such that the activations obtained from one "store / compute pair 801 / 802" of code and / or data store 801 and computing hardware 802 are provided as inputs to the next "store / compute pair 805 / 806" of code and / or data store 805 and computing hardware 806 in order to reflect the conceptual organization of the neural network. In at least one embodiment, each store / compute pair 801 / 802 and 805 / 806 may correspond to more than one layer of the neural network. In at least one embodiment, additional store / compute pairs (not shown) may be included in inference and / or training logic 815 after or in parallel with store / compute pairs 801 / 802 and 805 / 806.

[0117] Neural Network Training and Deployment

[0118] Figure 9 Illustrated is the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, an untrained neural network 906 is trained using a training data set 902. In at least one embodiment, the training framework 904 is the PyTorch framework, while in other embodiments, the training framework 904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 904 trains the untrained neural network 906 and enables it to be trained using the processing resources described herein to generate a trained neural network 908. In at least one embodiment, the weights may be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0119] In at least one embodiment, a supervised learning is used to train an untrained neural network 906, where the training dataset 902 includes inputs paired with desired outputs for the inputs, or where the training dataset 902 includes inputs with known outputs and outputs for which the neural network 906 is manually graded. In at least one embodiment, the untrained neural network 906 is trained in a supervised manner, and the inputs from the training dataset 902 are processed and the resulting outputs are compared with a set of desired or wanted outputs. In at least one embodiment, the error is then propagated back through the untrained neural network 906. In at least one embodiment, the training framework 904 adjusts the weights that control the untrained neural network 906. In at least one embodiment, the training framework 904 includes tools for monitoring the degree to which the untrained neural network 906 converges to a model (e.g., a trained neural network 908), a model adapted to generate correct answers (e.g., results 914) based on input data (e.g., a new dataset 912). In at least one embodiment, the training framework 904 repeatedly trains the untrained neural network 906 while adjusting the weights to improve the output of the untrained neural network 906 using a loss function and an adjustment algorithm (e.g., stochastic gradient descent). In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 reaches a desired accuracy. In at least one embodiment, the trained neural network 908 can then be deployed to perform any number of machine learning operations.

[0120] In at least one embodiment, an unsupervised learning is used to train an untrained neural network 906, where the untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 902 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 906 can learn groupings within the training dataset 902 and can determine how individual inputs relate to the untrained dataset 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 908, which can perform operations useful for reducing the dimensionality of a new dataset 912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in a new dataset 912 that deviate from the normal pattern of the new dataset 912.

[0121] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled data and unlabeled data is included in the training data set 902. In at least one embodiment, the training framework 904 can be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 908 to adapt to a new data set 912 without forgetting the knowledge injected into the trained neural network 908 during initial training.

[0122] Data center

[0123] Figure 10 An example data center 1000 in which at least one embodiment can be used is shown. In at least one embodiment, the data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0124] In at least one embodiment, as Figure 10 shown, the data center infrastructure layer 1010 can include a resource coordinator 1012, grouped computing resources 1014, and node computing resources (“node C.R.”) 1016(1)-1016(N), where “N” represents a positive integer (which can be a different integer “N” from the integers used in other figures). In at least one embodiment, the node C.R. 1016(1)-1016(N) can include, but is not limited to, any number of central processing units (“CPU”) or other processors (including accelerators, field programmable gate arrays (FPGA), graphics processors, etc.), memory storage devices 1018(1)-1018(N) (such as dynamic read-only memory, solid-state drives, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VM”), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 1016(1)-1016(N) can be a server having one or more of the above computing resources.

[0125] In at least one embodiment, the grouped computing resources 1014 may include a separate grouping (not shown) of node C.R.s housed within one or more racks, or a number of racks (also not shown) within data centers in various geographical locations. In at least one embodiment, a separate grouping of node C.R.s within the grouped computing resources 1014 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0126] In at least one embodiment, the resource coordinator 1012 may configure or otherwise control one or more node C.R.s 1016(1)-1016(N) and / or the grouped computing resources 1014. In at least one embodiment, the resource coordinator 1012 may include a software design infrastructure (“SDI”) management entity for the data center 1000. In at least one embodiment, the resource coordinator 812 may include hardware, software, or some combination thereof.

[0127] In at least one embodiment, as Figure 10As shown, the framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, the framework layer 1020 may include a framework that supports software 1032 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1032 or the application 1042 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be, but is not limited to, a free and open-source software web application framework, such as Apache SparkTM (hereinafter referred to as "Spark") that can utilize the distributed file system 1028 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 1032 may include a Spark driver to facilitate scheduling of the workloads supported by the various layers of the data center 1000. In at least one embodiment, the configuration manager 1024 may be capable of configuring different layers, such as the software layer 1030 and the framework layer 1020 including Spark and the distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, the resource manager 1026 is capable of managing the cluster or grouped computing resources mapped to or allocated for supporting the distributed file system 1028 and the job scheduler 1022. In at least one embodiment, the cluster or grouped computing resources may include grouped computing resources 1014 on the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1026 may coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

[0128] In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least a portion of the nodes C.R. 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0129] In at least one embodiment, one or more applications 1042 included in the application layer 1040 may include one or more types of applications used by at least a portion of nodes C.R. 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0130] In at least one embodiment, any one of the configuration manager 1024, the resource manager 1026, and the resource coordinator 1012 may implement any number and type of self-modifying actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions may relieve the data center operator of the data center 1000 from making potentially poor configuration decisions and may avoid underutilization and / or poorly performing portions of the data center.

[0131] In at least one embodiment, the data center 1000 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by computing weight parameters according to a neural network architecture by using the software and computing resources described above with respect to the data center 1000. In at least one embodiment, by using the weight parameters calculated by one or more training techniques described herein, the resources described above with respect to the data center 1000 may be used to infer or predict information using the trained machine learning model corresponding to one or more neural networks.

[0132] In at least one embodiment, the data center may use a CPU, an application specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or inference using the above resources. Additionally, one or more of the above software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0133] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 8A and / or Figure 8BProvide details regarding inference and / or training logic 815. In at least one embodiment, the inference and / or training logic 815 may be used in a system Figure 10 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0134] Autonomous vehicle

[0135] Figure 11A illustrates an example of an autonomous vehicle 1100 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1100 (alternatively referred to herein as "vehicle 1100") may be, but is not limited to, a passenger vehicle such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 1100 may be a semi-trailer truck for hauling cargo. In at least one embodiment, vehicle 1100 may be an aircraft, robotic vehicle, or other type of vehicle.

[0136] Autonomous vehicles may be described according to automation levels defined by the National Highway Traffic Safety Administration ("NHTSA") under the United States Department of Transportation and the Society of Automotive Engineers ("SAE") in "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806 issued on June 15, 2018, Standard No. J3016-201609 issued on September 30, 2016, and previous and future versions of this standard). In one or more embodiments, vehicle 1100 may be capable of functioning according to one or more of automation levels 1 through 5. For example, in at least one embodiment, according to an embodiment, vehicle 1100 may be capable of conditional automation (level 3), highly automated (level 4), and / or fully automated (level 5).

[0137] In at least one embodiment, vehicle 1100 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 1100 may include, but is not limited to, a propulsion system 1150, such as an internal combustion engine, a hybrid device, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1150 may be connected to the driveline of vehicle 1100, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1100. In at least one embodiment, a signal may be received from throttle / accelerator 1152 to control propulsion system 1150.

[0138] In at least one embodiment, when propulsion system 1150 is operating (e.g., when vehicle 1100 is in motion), a steering system 1154 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1100 (e.g., along a desired path or route). In at least one embodiment, steering system 1154 may receive a signal from a steering actuator 1156. In at least one embodiment, the steering wheel may be optional for fully automated (level 5) functions. In at least one embodiment, a brake sensor system 1146 may be used to operate vehicle brakes in response to signals received from a brake actuator 1148 and / or a brake sensor.

[0139] In at least one embodiment, controller 1136 may include, but is not limited to, one or more system-on-chips (“SoC”) ( Figure 11A(not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of the vehicle 1100. For example, in at least one embodiment, the controller 1136 may send signals to operate the vehicle brakes via the brake actuator 1148, operate the steering system 1154 via one or more steering actuators 1156, and operate the propulsion system 1150 via one or more throttles / accelerators 1152. In at least one embodiment, one or more controllers 1136 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operation commands (e.g., signals representing commands) to achieve autonomous driving and / or assist the driver in driving the vehicle 1100. In at least one embodiment, one or more controllers 1136 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, and two or more controllers may handle a single function and / or any combination thereof.

[0140] In at least one embodiment, one or more controllers 1136 provide signals for controlling one or more components and / or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data may be received from sensors, the sensor types including but not limited to one or more global navigation satellite system (“GNSS”) sensors 1158 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1160, one or more ultrasonic sensors 1162, one or more LIDAR sensors 1164, one or more inertial measurement unit (IMU) sensors 1166 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1196, one or more stereo cameras 1168, one or more wide-angle cameras 1170 (e.g., fish-eye cameras), one or more infrared cameras 1172, one or more surround cameras 1174 (e.g., 360-degree cameras), remote cameras ( Figure 11A (not shown), mid-range cameras ( Figure 11Anot shown), one or more speed sensors 1144 (e.g., for measuring the speed of vehicle 1100), one or more vibration sensors 1142, one or more steering sensors 1140, one or more braking sensors (e.g., as part of a braking sensor system 1146), and / or other sensor types.

[0141] In at least one embodiment, one or more controllers 1136 may receive inputs (e.g., represented by input data) from the instrument panel 1132 of vehicle 1100 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1134, a sound annunciator, a speaker, and / or other components of vehicle 1100. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., high-definition map ( Figure 11A not shown), location data (e.g., the location of vehicle 1100, e.g., on a map), direction, the locations of other vehicles (e.g., occupancy grids), information about objects, and the status of objects sensed by one or more controllers 1136, etc. For example, in at least one embodiment, the HMI display 1134 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic signal changes, etc.) and / or information about driving operations the vehicle has made, is making, or will make (e.g., changing lanes now, exiting at Exit 34B in two miles, etc.).

[0142] In at least one embodiment, vehicle 1100 further includes a network interface 1124, which may communicate via one or more networks using one or more wireless antennas 1126 and / or one or more modems. For example, in at least one embodiment, network interface 1124 may be capable of communicating via Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1126 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter referred to as “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0143] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 8A and / orFigure 8B Provide details regarding inference and / or training logic 815. In at least one embodiment, the inference and / or training logic 815 may be in a system Figure 11A for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0144] Figure 11B illustrates an example of camera positions and fields of view of an Figure 11A autonomous vehicle 1100 according to at least one embodiment. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1100.

[0145] In at least one embodiment, the camera type for the cameras may include, but is not limited to, digital cameras that may be adapted to be used with components and / or systems of the vehicle 1100. In at least one embodiment, one or more cameras may operate at an automotive safety integrity level (“ASIL”) B and / or other ASIL. In at least one embodiment, according to the embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer (RGGB) sensor color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, transparent pixel cameras, such as cameras having RCCC, RCCB, and / or RBGC color filter arrays, may be used to attempt to improve photosensitivity.

[0146] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-functional monocular camera may be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0147] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D”) printed) assembly, to cut out stray light and reflections from within the vehicle 1100 (e.g., reflections from the dashboard reflected in the windshield mirror), which may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side cameras, one or more cameras can also be integrated within the four pillars at each corner of the cabin.

[0148] In at least one embodiment, a camera (e.g., a forward camera) having a field of view that includes a portion of the environment in front of the vehicle 1100 can be used for surround view and to help identify forward paths and obstacles with the help of one or more controllers 1136 and / or a control SoC, thus providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0149] In at least one embodiment, various cameras can be used in a forward configuration, including, for example, a monocular camera platform that includes a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1170 can be used to sense objects entering from the periphery (e.g., pedestrians, crossing the road, or bicycles). Although only one wide-angle camera 1170 is shown in Figure 11B , in other embodiments, any number (including zero) of wide-angle cameras can be present on the vehicle 1100. In at least one embodiment, any number of long-range cameras 1198 (e.g., a long-range stereo camera pair) can be used for depth-based object detection, especially for objects for which neural networks have not been trained. In at least one embodiment, the long-range cameras 1198 can also be used for object detection and classification and basic object tracking.

[0150] In at least one embodiment, any number of stereo cameras 1168 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1168 may include an integrated control unit that includes a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1100, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1168 may include, but are not limited to, a compact stereo vision sensor that may include, but is not limited to, two camera lenses (one for the left and one for the right) and an image processing chip that may measure the distance from the vehicle 1100 to a target object and use the information generated (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1168 may be used in addition to those described herein.

[0151] In at least one embodiment, a camera having a field of view that includes a portion of the environment on the side of the vehicle 1100 (e.g., a side view camera) may be used for surround viewing, thereby providing information for creating and updating an occupancy grid, as well as generating a side collision warning. For example, in at least one embodiment, surround cameras 1174 (e.g., four surround cameras as Figure 11B shown) may be positioned on the vehicle 1100. In at least one embodiment, one or more surround cameras 1174 may include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras may be located at the front, rear, and sides of the vehicle 1100. In at least one embodiment, the vehicle 1100 may use three surround cameras 1174 (e.g., left, right, and rear), and may utilize one or more other cameras (e.g., a forward camera) as the fourth surround camera.

[0152] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1100 (e.g., a rear view camera) may be used for parking assistance, surround viewing, rear collision warning, and creating and updating an occupancy raster. In at least one embodiment, a variety of cameras may be used, including but not limited to cameras that are also suitable as one or more forward cameras (e.g., a long-range camera 1198 and / or one or more mid-range cameras 1176, one or more stereo cameras 1168, one or more infrared cameras 1172, etc.), as described herein.

[0153] The inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. In conjunction with Figure 8A and / or Figure 8B , details regarding the inference and / or training logic 815 are provided herein. In at least one embodiment, the inference and / or training logic 815 can be used in a Figure 11B system to infer or predict operations based at least in part on weight parameters, neural network functions, and / or architectures computed using neural network training operations, or neural network use cases described herein.

[0154] Figure 11C FIG. shows a block diagram of an exemplary system architecture of a Figure 11A self-driving vehicle 1100 according to at least one embodiment. In at least one embodiment, Figure 11C each of one or more components, one or more features, and one or more systems of the vehicle 1100 in

[0155] In at least one embodiment, in addition to or from CAN, FlexRay and / or Ethernet protocols may be used. In at least one embodiment, there may be any number of formed buses 1102, which may include but are not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functions, and a second bus may be used for actuation control. In at least one embodiment, each bus of the buses 1102 may communicate with any component of the vehicle 1100, and two or more of the buses 1102 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chips (“SoC”) 1104 (e.g., SoC 1104(A) and SoC 1104(B)), each of one or more controllers 1136, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of the vehicle 1100) and may be connected to a common bus, such as a CAN bus.

[0156] In at least one embodiment, the vehicle 1100 may include one or more controllers 1136, such as those described herein with respect to Figure 11A In at least one embodiment, the controller 1136 may be used for a variety of functions. In at least one embodiment, the controller 1136 may be coupled to any one of a variety of other components and systems of the vehicle 1100 and may be used to control the vehicle 1100, the artificial intelligence of the vehicle 1100, the infotainment of the vehicle 1100, and / or other functions.

[0157] In at least one embodiment, the vehicle 1100 may include any number of SoC 1104. In at least one embodiment, each of the SoC 1104 may include but is not limited to a central processing unit (“one or more CPUs”) 1106, a graphics processing unit (“one or more GPUs”) 1108, one or more processors 1110, one or more caches 1112, one or more accelerators 1114, one or more data stores 1116, and / or other components and features not shown. In at least one embodiment, one or more SoC 1104 may be used to control the vehicle 1100 in various platforms and systems. For example, in at least one embodiment, one or more SoC 1104 may be combined with a high-definition (“HD”) map 1122 in a system (e.g., the system of the vehicle 1100), and the high-definition map 1122 may be obtained from one or more servers via a network interface 1124 (Figure 11C obtain map refresh and / or update (not shown in the figure).

[0158] In at least one embodiment, one or more CPUs 1106 may include a CPU cluster or CPU complex (alternatively referred to herein as "CCPLEX"). In at least one embodiment, one or more CPUs 1106 may include multiple cores and / or secondary ("L2") caches. For example, in at least one embodiment, one or more CPUs 1106 may include eight cores in a multi-processor configuration coupled to each other. In at least one embodiment, one or more CPUs 1106 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1106 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 1106 can be active at any given time.

[0159] In at least one embodiment, one or more CPUs 1106 may implement power management functions, which include but are not limited to one or more of the following features: individual hardware modules can be automatically clock-gated when idle to save dynamic power; each core clock can be gated when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core can be independently powered; each core cluster can be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster can be independently power-gated when all cores are power-gated. In at least one embodiment, one or more CPUs 1106 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for core, cluster, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, where the work is shared with the microcode.

[0160] In at least one embodiment, one or more GPUs 1108 may include an integrated GPU (referred to herein as an “iGPU”). In at least one embodiment, one or more GPUs 1108 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1108 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 1108 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having a storage capacity of 512 KB). In at least one embodiment, one or more GPUs 1108 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1108 may use a compute application programming interface (API). In at least one embodiment, one or more GPUs 1108 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0161] In at least one embodiment, one or more GPUs 1108 may be power optimized to achieve optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1108 may be fabricated on fin field-effect transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may contain multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64 KB register file may be allocated to each processing block. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computational and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable more fine-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0162] In at least one embodiment, one or more GPUs 1108 may include high bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900GB / second in some examples. In at least one embodiment, synchronous graphics random access memory (“SGRAM”), such as graphics double data rate type five synchronous random access memory (“GDDR5”), may be used in addition to or in place of HBM memory.

[0163] In at least one embodiment, one or more GPUs 1108 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1108 to directly access the page tables of one or more CPUs 1106. In at least one embodiment, when a memory management unit (“MMU”) of a GPU in one or more GPUs 1108 experiences a miss, an address translation request may be sent to one or more CPUs 1106. In response, in at least one embodiment, a CPU in one or more CPUs 1106 may look up the virtual-physical mapping of the address in its page table and transmit the translation back to one or more GPUs 1108. In at least one embodiment, unified memory technology may allow a single unified virtual address space for the memory of both one or more CPUs 1106 and one or more GPUs 1108, thereby simplifying the programming of one or more GPUs 1108 and the porting of applications to one or more GPUs 1108.

[0164] In at least one embodiment, one or more GPUs 1108 may include any number of access counters that may track the frequency of access by one or more GPUs 1108 to the memory of other processors. In at least one embodiment, one or more access counters may help ensure that memory pages are moved into the physical memory of the processor that most frequently accesses the page, thereby increasing the efficiency of the memory range shared among the processors.

[0165] In at least one embodiment, one or more SoCs 1104 may include any number of caches 1112, including those described herein. For example, in at least one embodiment, one or more caches 1112 may include a level three (“L3”) cache that may be available to one or more CPUs 1106 and one or more GPUs 1108 (e.g., connected to CPU 1106 and GPU 1108). In at least one embodiment, one or more caches 1112 may include a write-back cache that may track the state of lines, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although smaller cache sizes may be used, according to an embodiment, the L3 cache may include 4MB of memory or more.

[0166] In at least one embodiment, one or more SoCs 1104 may include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1104 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1108 and offload some tasks from one or more GPUs 1108 (e.g., freeing up more cycles of one or more GPUs 1108 to perform other tasks). In at least one embodiment, one or more accelerators 1114 may be used for target workloads that are stable enough to withstand acceleration testing (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, a CNN may include a region-based or region convolutional neural network (“RCNN”) and Fast RCNN (e.g., as used for object detection) or other types of CNNs.

[0167] In at least one embodiment, one or more accelerators 1114 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a particular set of neural network types and floating-point operations as well as inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU and generally far exceed the performance of a CPU. In at least one embodiment, one or more TPUs may perform a number of functions, including supporting, for example, INT8, INT16, and FP16 data types for single-instance convolution functions for features and weights as well as post-processor functions. In at least one embodiment, one or more DLAs may execute a neural network, especially a CNN, quickly and efficiently on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection as well as recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for security and / or safety-related events.

[0168] In at least one embodiment, a DLA may perform any of the functions of one or more GPUs 1108, and by using an inference accelerator, for example, a designer may target one or more DLAs or one or more GPUs 1108 for any function. For example, in at least one embodiment, a designer may concentrate the processing and floating-point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 1108 and / or one or more accelerators 1114.

[0169] In at least one embodiment, one or more accelerators 1114 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1138, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0170] In at least one embodiment, the RISC cores may interact with an image sensor (e.g., the image sensor of any of the cameras described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, according to the embodiment, the RISC cores may use any one of a variety of protocols. In at least one embodiment, the RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or storage devices may be used to implement the RISC cores. For example, in at least one embodiment, the RISC cores may include an instruction cache and / or tightly coupled RAM.

[0171] In at least one embodiment, the DMA may enable the components of the PVA to access system memory independently of one or more CPUs 1106. In at least one embodiment, the DMA may support any number of features for optimizing the supply to the PVA, including but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more dimensions of addressing, which may include but not limited to block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0172] In at least one embodiment, the vector processor may be a programmable processor, which may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities.

[0173] In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the primary processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, e.g., a single instruction multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0174] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general computer vision algorithms, except on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on one image, or even on sequential images or partial images. In at least one embodiment, among other things, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory to enhance overall system security.

[0175] In at least one embodiment, one or more accelerators 1114 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the one or more accelerators 1114. In at least one embodiment, the on-chip memory may include at least 4MB SRAM, which includes, for example but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0176] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and the DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0177] In at least one embodiment, one or more SoCs 1104 may include a real-time line-of-sight tracking hardware accelerator. In at least one embodiment, the real-time line-of-sight tracking hardware accelerator may be used to quickly and effectively determine the position and extent of an object (e.g., within a world model) to generate a real-time visualization simulation for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0178] In at least one embodiment, one or more accelerators 1114 have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency match well with algorithm domains that require predictable processing. In other words, the PVA performs well in semi-dense or dense conventional computations, even on small data sets that may require predictable runtimes with low latency and low power. In at least one embodiment, the PVA in a vehicle 1100 may be designed to run classical computer vision algorithms because they can be effective in object detection and integer math operations.

[0179] For example, according to at least one embodiment of the technology, the PVA is used to perform computer stereo vision. In at least one embodiment, an algorithm based on semi-global matching may be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for level 3-5 autonomous driving use dynamic estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, the PVA may perform computer stereo vision functions on inputs from two monocular cameras.

[0180] In at least one embodiment, PVA can be used to perform dense optical flow. For example, in at least one embodiment, PVA can process raw RADAR data (e.g., using a 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, for example, by processing raw time-of-flight data to provide processed time-of-flight data, PVA is used for time-of-flight depth processing.

[0181] In at least one embodiment, DLA can be used to run any type of network to enhance control and driving safety, including for example but not limited to neural networks, whose output is the confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or represented as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence measurement enables the system to make a further decision, namely which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence, and only consider detections that exceed the threshold as true positive detections. In an embodiment using an automatic emergency braking ("AEB") system, false positive detections will cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered as triggers for AEB. In at least one embodiment, DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network can take at least some subset of parameters as its input, such as bounding box dimensions, the obtained ground plane estimate (e.g., from another subsystem), the output of one or more IMU sensors 1166 related to the vehicle 1100 direction, distance, 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1164 or one or more RADAR sensors 1160).

[0182] In at least one embodiment, one or more SoCs 1104 can include one or more data storage devices 1116 (e.g., memory). In at least one embodiment, one or more data storages 1116 can be on-chip memories of one or more SoCs 1104, which can store neural networks to be executed on one or more GPUs 1108 and / or DLA. In at least one embodiment, one or more data storages 1116 can have a large enough capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, one or more data storages 1116 can include L2 or L3 caches.

[0183] In at least one embodiment, one or more SoCs 1104 may include any number of processors 1110 (e.g., embedded processors). In at least one embodiment, one or more processors 1110 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions as well as associated security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1104 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low power state transitions, manage one or more SoC 1104 thermal and temperature sensors, and / or manage one or more SoC 1104 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1104 may use the ring oscillator to detect the temperature of one or more CPUs 1106, one or more GPUs 1108, and / or one or more accelerators 1114. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1104 in a lower power state and / or place the vehicle 1100 in a safe parking pattern for the driver (e.g., safely park the vehicle 1100).

[0184] In at least one embodiment, one or more processors 1110 may further include a set of embedded processors that may be used as an audio processing engine, and the audio processing engine may be an audio subsystem that can provide full hardware support for multi-channel audio to the hardware through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0185] In at least one embodiment, one or more processors 1110 may further include an always-on processor engine that can provide the necessary hardware features to support low power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, processor cores, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0186] In at least one embodiment, one or more processors 1110 may further include a security cluster engine, which includes but is not limited to a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In the secure mode, in at least one embodiment, two or more cores may operate in a lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1110 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1110 may further include a high-dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine as part of a camera processing pipeline.

[0187] In at least one embodiment, one or more processors 1110 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required for a video playback application to produce a final video to generate a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1170, one or more surround cameras 1174, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 1104, which is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform but is not limited to lip reading to activate cellular services and make calls, indicate emails, change the destination of the vehicle, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are otherwise disabled.

[0188] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, in the case where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of the information provided by adjacent frames. In at least one embodiment, in the case where an image or a part of the image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from a previous image to reduce the noise in the current image.

[0189] In at least one embodiment, the video image synthesizer may also be configured to perform stereoscopic correction on the input stereoscopic lens frames. In at least one embodiment, when using an operating system desktop, the video image synthesizer may also be used for user interface synthesis and does not require one or more GPUs 1108 to continuously render new surfaces. In at least one embodiment, when powering one or more GPUs 1108 and making them actively perform 3D rendering, the video image synthesizer may be used to offload one or more GPUs 1108 to improve performance and responsiveness.

[0190] In at least one embodiment, one or more of the SoCs 1104 may further include a Mobile Industry Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block for receiving video and inputs from cameras, which can be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoCs 1104 may further include an input / output controller, which can be software-controlled and can be used to receive I / O signals not committed to a specific role.

[0191] In at least one embodiment, one or more of the SoCs 1104 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoder / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1104 can be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., one or more LIDAR sensors 1164, one or more RADAR sensors 1160, etc., which can be connected via Ethernet channels), data from bus 1102 (e.g., the speed, steering wheel position, etc. of vehicle 1100), data from one or more GNSS sensors 1158 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more of the SoCs 1104 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and can be used to relieve one or more CPUs 1106 from conventional data management tasks.

[0192] In at least one embodiment, one or more SoCs 1104 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thus providing an integrated functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, which provides a platform that can offer a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1104 can be faster and more reliable than conventional systems, and even more energy-efficient and space-efficient. For example, in at least one embodiment, one or more accelerators 1114, when combined with one or more CPUs 1106, one or more GPUs 1108, and one or more data storage devices 1116, can provide a fast and effective platform for level 3-5 autonomous vehicles.

[0193] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (such as C) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, a CPU generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual level 3-5 autonomous vehicles.

[0194] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve level 3-5 autonomous driving functions. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1120) can include text and word recognition, thus allowing a supercomputer to read and understand traffic signs, including signs that the neural network has not been specifically trained for. In at least one embodiment, the DLA can also include a neural network that is capable of recognizing, interpreting, and providing a semantic understanding of symbols, and passing that semantic understanding to a path planning module running on the CPU Complex.

[0195] In at least one embodiment, for a level 3, 4, or 5 drive, multiple neural networks may be run simultaneously. For example, in at least one embodiment, a warning sign consisting of a connected electric light together with "Caution: flashing lights indicate icy conditions" may be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the warning sign itself may be recognized as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executed on the CPU Complex) that when flashing lights are detected, there is an icy condition. In at least one embodiment, a third deployed neural network operating on multiple frames may be used to identify the flashing lights and notify the vehicle's path planning software of the presence (or absence) of the flashing lights. In at least one embodiment, all three neural networks may run simultaneously, e.g., within the DLA and / or on one or more GPUs 1108.

[0196] In at least one embodiment, a CNN for face recognition and vehicle owner recognition may use data from a camera sensor to identify the presence of an authorized driver and / or the owner of the vehicle 1100. In at least one embodiment, a normally open sensor processor engine may be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in a security mode, may be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1104 provide protection against theft and / or carjacking.

[0197] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1104 use the CNN to classify ambient and urban sounds, as well as to classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approach speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 1158. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1162 to perform emergency vehicle safety routines, slow down the vehicle, pull the vehicle over to the side of the road, stop, and / or idle the vehicle until the emergency vehicle has passed.

[0198] In at least one embodiment, vehicle 1100 can include one or more CPUs 1118 (e.g., one or more discrete CPUs or one or more dCPUs), which can be coupled to one or more SoCs 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, one or more CPUs 1118 can include X86 processors, e.g., one or more CPUs 1118 can be used to perform any of a variety of functions, such as including potentially arbitrating inconsistent results between ADAS sensors and one or more SoCs 1104, and / or monitoring the status and health of one or more monitoring controllers 1136 and / or the on-chip information system (“Info SoC”) 1130.

[0199] In at least one embodiment, vehicle 1100 can include one or more GPUs 1120 (e.g., one or more discrete GPUs or one or more dGPUs), which can be coupled to one or more SoCs 1104 via a high-speed interconnect (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1120 can provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and can be used for training and / or updating neural networks at least in part based on inputs from sensors of vehicle 1100 (e.g., sensor data).

[0200] In at least one embodiment, vehicle 1100 may further include a network interface 1124, which may include, but is not limited to, one or more wireless antennas 1126 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1124 may be used to enable a wireless connection with other vehicles and / or computing devices (e.g., a passenger's client device) via an Internet cloud service (e.g., using a server and / or other network devices). In at least one embodiment, to communicate with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 110 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1100 with information about vehicles in the vicinity of vehicle 1100 (e.g., vehicles in front of, to the side of, and / or behind vehicle 1100). In at least one embodiment, the foregoing function may be part of the cooperative adaptive cruise control function of vehicle 1100.

[0201] In at least one embodiment, network interface 1124 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 1136 to communicate via a wireless network. In at least one embodiment, network interface 1124 may include a radio frequency front end for upconverting from baseband to radio frequency and downconverting from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a known process and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end function may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0202] In at least one embodiment, vehicle 1100 may further include one or more data stores 1128, which may include, but are not limited to, off-chip (e.g., one or more SoCs 1104) storage. In at least one embodiment, one or more data stores 1128 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices that can store at least one bit of data.

[0203] In at least one embodiment, vehicle 1100 may further include one or more GNSS sensors 1158 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1158 may be used, including, for example but not limited to, a GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0204] In at least one embodiment, vehicle 1100 may further include one or more RADAR sensors 1160. In at least one embodiment, one or more RADAR sensors 1160 may be used by vehicle 1100 for remote vehicle detection, even in dark and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1160 may use a CAN bus and / or bus 1102 (e.g., to transmit data generated by one or more RADAR sensors 1160) for control and access to object tracking data and, in some examples, may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example but not limited to, one or more of the RADAR sensors 1160 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1160 are pulsed Doppler RADAR sensors.

[0205] In at least one embodiment, one or more RADAR sensors 1160 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, a long-range RADAR system may provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 m). In at least one embodiment, one or more RADAR sensors 1160 may assist in differentiating between static and moving objects and may be used by the ADAS system 1138 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1160 included in the long-range RADAR system may include, but are not limited to, monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas may create a focused beam pattern designed to record the surrounding environment of the vehicle 1100 at a higher speed with minimal traffic interference from adjacent lanes. In at least one embodiment, the other two antennas may widen the field of view so that vehicles 1100 entering or leaving the lane can be quickly detected.

[0206] In at least one embodiment, by way of example, a mid-range RADAR system may include, for example, a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1160 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in the ADAS system 1138 for blind spot detection and / or lane change assistance.

[0207] In at least one embodiment, the vehicle 1100 may further include one or more ultrasonic sensors 1162. In at least one embodiment, one or more ultrasonic sensors 1162 that may be positioned at the front, rear, and / or side positions of the vehicle 1100 may be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1162 may be used, and different ultrasonic sensors 1162 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1162 may operate at a functional safety level of ASIL B.

[0208] In at least one embodiment, vehicle 1100 may include one or more LIDAR sensors 1164. In at least one embodiment, one or more LIDAR sensors 1164 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LIDAR sensors 1164 may operate at a functional safety level of ASIL B. In at least one embodiment, vehicle 1100 may include multiple (e.g., two, four, six, etc.) LIDAR sensors 1164 (e.g., providing data to a gigabit Ethernet switch) that may use Ethernet channels.

[0209] In at least one embodiment, one or more LIDAR sensors 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1164 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm - 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1164 may include small devices that may be embedded in the front, rear, sides, and / or corner positions of vehicle 1100. In at least one embodiment, one or more LIDAR sensors 1164, in such an embodiment, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, and have a range of 200 m, even for low-reflectivity objects. In at least one embodiment, the forward one or more LIDAR sensors 1164 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0210] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) can also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around the vehicle 1100. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1100 to the object. In at least one embodiment, flash LIDAR can allow the use of each laser flash to generate a highly accurate and distortion-free image of the surrounding environment. In at least one embodiment, four flash LIDAR sensors can be deployed, with one sensor on each side of the vehicle 1100. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera that has no moving parts other than a fan (such as a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use Class I (eye-safe) laser pulses of 5 nanoseconds per frame and can capture the reflected laser as a 3D range point cloud and co-registered intensity data.

[0211] In at least one embodiment, the vehicle 1100 may further include one or more IMU sensors 1166. In at least one embodiment, one or more IMU sensors 1166 may be located at the center of the rear axle of the vehicle 1100. In at least one embodiment, one or more IMU sensors 1166 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, one or more IMU sensors 1166 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, one or more IMU sensors 1166 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0212] In at least one embodiment, one or more IMU sensors 1166 can be implemented as a miniature high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, one or more IMU sensors 1166 can enable the vehicle 1100 to estimate its heading without input from a magnetic sensor by directly observing and correlating the velocity changes from the GPS to one or more IMU sensors 1166. In at least one embodiment, one or more IMU sensors 1166 and one or more GNSS sensors 1158 can be combined in a single integrated unit.

[0213] In at least one embodiment, vehicle 1100 may include one or more microphones 1196 disposed within and / or around vehicle 1100. In at least one embodiment, in addition, one or more microphones 1196 may be used for emergency vehicle detection and identification.

[0214] In at least one embodiment, vehicle 1100 may further include any number of camera types, including one or more stereo cameras 1168, one or more wide-angle cameras 1170, one or more infrared cameras 1172, one or more surround cameras 1174, one or more long-range cameras 1198, one or more mid-range cameras 1176, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire perimeter of vehicle 1100. In at least one embodiment, the type of camera used depends on vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around vehicle 1100. In at least one embodiment, the number of cameras deployed may vary according to the embodiment. For example, in at least one embodiment, vehicle 1100 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications.

[0215] In at least one embodiment, each camera may be described in more detail with reference to Figure 11A and Figure 11B above.

[0216] In at least one embodiment, vehicle 1100 may further include one or more vibration sensors 1142. In at least one embodiment, one or more vibration sensors 1142 may measure the vibration of components of vehicle 1100 (e.g., an axle). For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1142 are used, the difference between the vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a powered drive axle and a freely rotating axle).

[0217] In at least one embodiment, vehicle 1100 may include an ADAS system 1138. In at least one embodiment, ADAS system 1138 may include, but is not limited to, a SoC. In at least one embodiment, ADAS system 1138 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions and combinations thereof.

[0218] In at least one embodiment, the ACC system may use one or more RADAR sensors 1160, one or more LIDAR sensors 1164, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to vehicle 1100 and automatically adjusts the speed of vehicle 1100 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that vehicle 1100 change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0219] In at least one embodiment, the CACC system uses information from other vehicles, which may be received via a wireless link or indirectly via a network connection (e.g., via the Internet) from other vehicles via a network interface 1124 and / or one or more wireless antennas 1126. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Generally, V2V communication provides information about the vehicle immediately ahead (e.g., a vehicle immediately in front of and in the same lane as vehicle 1100), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of I2V and V2V information sources. In at least one embodiment, in the case of information about vehicles ahead of a given vehicle 1100, the CACC system may be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0220] In at least one embodiment, the FCW system is designed to warn the driver of a danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward camera and / or one or more RADAR sensors 1160, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid braking pulses.

[0221] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system can use one or more forward cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a danger, it generally first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes in an attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or braking for an impending collision.

[0222] In at least one embodiment, when the vehicle 1100 crosses a lane marking, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn the driver. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system can use a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if the vehicle 1100 starts to leave the lane, the LKA system provides steering input or braking to correct the vehicle 1100.

[0223] In at least one embodiment, the BSW system detects and warns a vehicle driver in a vehicle blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, when the driver uses a turn signal, the BSW system can provide an additional warning. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0224] In at least one embodiment, when an object is detected outside the rear camera range while the vehicle 1100 is backing up, the RCTW system can provide visual, audible, and / or tactile notifications. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1160, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0225] In at least one embodiment, conventional ADAS systems may be prone to producing false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to decide whether a safety situation truly exists and take appropriate action. In at least one embodiment, in the case of conflicting results, the vehicle 1100 itself decides whether to heed the results of the primary computer or the secondary computer (e.g., the first controller or the second controller of the controller 1136). For example, in at least one embodiment, the ADAS system 1138 can be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run various software redundantly on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1138 can be provided to the monitoring MCU. In at least one embodiment, if the output from the primary computer and the output from the auxiliary computer conflict, the supervisory MCU decides how to reconcile the conflict to ensure safe operation.

[0226] In at least one embodiment, the host computer may be configured to provide a confidence score to the supervisory MCU to indicate the host computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the instructions of the host computer regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, in the case where the confidence score does not meet the threshold and where the host computer and the secondary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine an appropriate result.

[0227] In at least one embodiment, the supervisory MCU may be configured to run a neural network that is trained and configured to determine, at least in part based on outputs from the host computer and from the secondary computer, the conditions under which the secondary computer provides a false alarm. In at least one embodiment, the neural network in the supervisory MCU may learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system identifies a metallic object that is not actually a hazard, such as a drain grate or manhole cover that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when there is a cyclist or pedestrian present and when lane departure is actually the safest course of action. In at least one embodiment, the supervisory MCU may include at least one of a DLA or a GPU suitable for running a neural network with an associated memory. In at least one embodiment, the supervisory MCU may be included as and / or be a component of one or more SoCs 1104.

[0228] In at least one embodiment, the ADAS system 1138 may include a secondary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the secondary computer may use classical computer vision rules (if-then), and the presence of the neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementation and intentional non-identity make the overall system more fault-tolerant, especially for faults caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the host computer and the different software code running on the secondary computer provides a consistent overall result, the supervisory MCU may be more confident that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not result in a significant error.

[0229] In at least one embodiment, the output of the ADAS system 1138 can be input into the perception module of the host computer and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1138 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the auxiliary computer can have its own neural network, which is trained to reduce the risk of false positives.

[0230] In at least one embodiment, the vehicle 1100 can further include an infotainment SoC 1130 (e.g., in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1130 may not be an SoC and can include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1130 can include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movie, streaming, etc.), telephone (e.g., hands-free call), network connection (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assistance, radio data system, vehicle-related information such as fuel level, total covered distance, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1100. For example, the infotainment SoC 1130 can include a radio, disk player, navigation system, video player, USB and Bluetooth connections, car, in-vehicle entertainment system, WiFi, steering wheel audio control, hands-free voice control, head-up display (“HUD”), HMI display 1134, telematics device, control panel (e.g., for controlling various components, features, and / or systems and / or interacting therewith), and / or other components. In at least one embodiment, the infotainment SoC 1130 can further be used to provide information (e.g., visual and / or auditory) to the user of the vehicle 1100, such as information from the ADAS system 1138, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0231] In at least one embodiment, the infotainment SoC 1130 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1130 may communicate with other devices, systems, and / or components of the vehicle 1100 via the bus 1102. In at least one embodiment, the infotainment SoC 1130 may be coupled to a monitoring MCU such that the GPU of the infotainment system can perform some autonomous driving functions in the event of a failure of the main controller 1136 (e.g., the main computer and / or standby computer of the vehicle 1100). In at least one embodiment, the infotainment SoC 1130 may cause the vehicle 1100 to enter a driver-to-safe stop mode as described herein.

[0232] In at least one embodiment, the vehicle 1100 may further include a dashboard 1132 (e.g., a digital dashboard, an electronic dashboard, a digital instrument cluster, etc.). In at least one embodiment, the dashboard 1132 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, the dashboard 1132 may include, but is not limited to, any number and combination of a set of gauges, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine fault lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1130 and the dashboard 1132. In at least one embodiment, the dashboard 1132 may be included as part of the infotainment SoC 1130 and vice versa.

[0233] The inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described in connection with Figure 8A and / or Figure 8B Details of the inference and / or training logic 815 are provided. In at least one embodiment, the inference and / or training logic 815 may be used in a system Figure 11C to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0234] Figure 11D is according to at least one embodiment between a cloud-based server and Figure 11A1100. In at least one embodiment, the system 1176 may include, but is not limited to, one or more servers 1178, one or more networks 1190, and any number and type of vehicles, including the vehicle 1100. In at least one embodiment, the one or more servers 1178 may include, but are not limited to, multiple GPUs 1184(A)-1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(A)-1182(D) (collectively referred to herein as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (collectively referred to herein as CPUs 1180), the GPUs 1184, the CPUs 1180, and the PCIe switches 1182 may be interconnected with high-speed connections, such as, but not limited to, the NVLink interface 1388 developed by NVIDIA and / or PCIe connections 1186. In at least one embodiment, the GPUs 1184 are connected via NVLink and / or NVSwitch SoC, and the GPUs 1184 and PCIe switches 1182 are connected via PCIe interconnects. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1178 may include, but is not limited to, any combination of any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182. For example, in at least one embodiment, one or more servers 1178 may each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0235] In at least one embodiment, one or more servers 1178 may receive image data representing an image from a vehicle via one or more networks 1190 that shows an unexpected or changed road condition, such as a recently started road project. In at least one embodiment, one or more servers 1178 may transmit an updated neural network 1192, and / or map information 1194, including but not limited to information about traffic and road conditions, via one or more networks 1190 and to the vehicle. In at least one embodiment, updates to the map information 1194 may include but are not limited to updates to the HD map 1122, such as information about construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1192 and / or map information 1194 may be generated by new training and / or experience represented in data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1178 and / or other servers).

[0236] In at least one embodiment, one or more servers 1178 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by a vehicle and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., in cases where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., in cases where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1190), and / or the machine learning model may be used by one or more servers 1178 to remotely monitor the vehicle.

[0237] In at least one embodiment, one or more servers 1178 may receive data from a vehicle and apply the data to a most recent real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1178 may include a deep learning supercomputer powered by one or more GPUs 1184 and / or a dedicated AI computer, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1178 may include a deep learning infrastructure of a data center powered by a CPU.

[0238] In at least one embodiment, the deep learning infrastructure of one or more servers 1178 may be capable of performing fast, real-time inference and may use that capability to evaluate and verify the health of processors, software, and / or associated hardware in vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1100, such as an image sequence and / or objects that vehicle 1100 has located in that image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to the objects identified by vehicle 1100, and if the results do not match and the deep learning infrastructure determines that the AI in vehicle 1100 is malfunctioning, one or more servers 1178 may send a signal to vehicle 1100 to instruct the fail-safe computer in vehicle 1100 to take control, notify the passengers, and complete a safe parking operation.

[0239] In at least one embodiment, one or more servers 1178 may include one or more GPUs 1184 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 device). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, for example, in cases where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, the hardware architecture 815 is used to execute one or more embodiments. This document describes in conjunction with Figure 8A and / or Figure 8B provide details about the hardware architecture 815.

[0240] Computer system

[0241] Figure 12 is a block diagram showing an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system with interconnected devices and components, a system-on-chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, according to the present disclosure, for example, the embodiments described herein, the computer system 1200 may include, but is not limited to, components such as a processor 1202, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, the computer system 1200 may include a processor, such as those available from Intel Corporation of Santa Clara, California, processor families, XeonTM, XScaleTM, and / or StrongARMTM, Core TM or Nervana TM microprocessors, although other systems (including PCs, engineering workstations, set-top boxes, etc. with other microprocessors) may also be used. In at least one embodiment, the computer system 1200 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0242] Embodiments can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, an embedded application can include a microcontroller, a digital signal processor (“DSP”), a system-on-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0243] In at least one embodiment, computer system 1200 can include, but is not limited to, a processor 1202 that can include, but is not limited to, one or more execution units 1208 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1200 is a single-processor desktop or server system, but in another embodiment, computer system 1200 can be a multi-processor system. In at least one embodiment, processor 1202 can include, but is not limited to, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing an instruction set combination, or any other processor device such as a digital signal processor. In at least one embodiment, processor 1202 can be coupled to a processor bus 1210 that can transfer data signals between processor 1202 and other components in computer system 1200.

[0244] In at least one embodiment, processor 1202 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 1204. In at least one embodiment, processor 1202 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can reside external to processor 1202. Other embodiments can also include a combination of internal and external caches depending on the specific implementation and requirements. In at least one embodiment, register file 1206 can store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0245] In at least one embodiment, execution unit 1208, which includes, but is not limited to, logic for performing integer and floating point operations, is also located in processor 1202. In at least one embodiment, processor 1202 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode for certain macroinstructions. In at least one embodiment, execution unit 1208 may include logic for processing an encapsulated instruction set 1209. In at least one embodiment, by including the encapsulated instruction set 1209 in the instruction set of a general-purpose processor and the associated circuitry for the instructions to be executed, operations used by many multimedia applications can be performed using the encapsulated data in processor 1202. In one or more embodiments, operations can be performed on the encapsulated data by using the full width of the data bus of the processor to accelerate and more efficiently execute many multimedia applications, which may not require transferring smaller data units on the data bus of the processor to perform one or more operations on one data element at a time.

[0246] In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, memory 1220 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or another storage device. In at least one embodiment, memory 1220 may store instructions 1219 and / or data 1221 represented by data signals that can be executed by processor 1202.

[0247] In at least one embodiment, the system logic chip may be coupled to the processor bus 1210 and the memory 1220. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1216, and the processor 1202 may communicate with the MCH 1216 via the processor bus 1210. In at least one embodiment, the MCH 1216 may provide a high-bandwidth memory path 1218 to the memory 1220 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1216 may initiate data signals among the processor 1202, the memory 1220, and other components in the computer system 1200, and bridge data signals among the processor bus 1210, the memory 1220, and the system I / O interface 1222. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1216 may be coupled to the memory 1220 via the high-bandwidth memory path 1218, and the graphics / video card 1212 may be coupled to the MCH 1216 via an Accelerated Graphics Port (“AGP”) interconnect 1214.

[0248] In at least one embodiment, the computer system 1200 may use the system I / O interface 1222 as a proprietary hub interface bus to couple the MCH 1216 to an I / O controller hub (“ICH”) 1230. In at least one embodiment, the ICH 1230 may provide a direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1220, the chipset, and the processor 1202. Examples may include, but are not limited to, an audio controller 1229, a firmware hub (“Flash BIOS”) 1228, a wireless transceiver 1226, a data storage 1224, a legacy I / O controller 1223 including a user input and a keyboard interface, a serial expansion port 1227 (such as a Universal Serial Bus (USB) port), and a network controller 1234. In at least one embodiment, the data storage 1224 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage devices.

[0249] In at least one embodiment, Figure 12 a system including interconnected hardware devices or “chips” is shown, while in other embodiments, Figure 12 an SoC may be shown. In at least one embodiment, Figure 12The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using Compute Express Link (CXL) interconnects.

[0250] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in conjunction with Figure 8A and / or Figure 8B Details regarding inference and / or training logic 815 are provided. In at least one embodiment, inference and / or training logic 815 can be used in a Figure 12 system for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0251] Figure 13 is a block diagram showing an electronic device 1300 for utilizing processor 1310 according to at least one embodiment. In at least one embodiment, electronic device 1300 can be, for example but not limited to, a laptop computer, a tower server, a rack server, a blade server, a laptop, a desktop computer, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0252] In at least one embodiment, electronic device 1300 can include, but is not limited to, processor 1310 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1310 is coupled using a bus or interface, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advanced Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 13 shows a system that includes interconnected hardware devices or “chips,” while in other embodiments, Figure 13 an exemplary SoC can be shown. In at least one embodiment, Figure 13 the devices shown can be interconnected with proprietary interconnect lines, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 13 one or more components of are interconnected using Compute Express Link (CXL) interconnect lines.

[0253] In at least one embodiment, Figure 13It may include a display 1324, a touch screen 1325, a touchpad 1330, a near field communication unit (“NFC”) 1345, a sensor hub 1340, a thermal sensor 1346, an embedded controller (“EC”) 1335, a trusted platform module (“TPM”) 1338, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320 (such as a solid state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1350, a Bluetooth unit 1352, a wireless wide area network unit (“WWAN”) 1356, a global positioning system (GPS) unit 1355, a camera (“USB 3.0 camera”) 1354 (such as a USB 3.0 camera) and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1315 implemented in accordance with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0254] In at least one embodiment, other components may be communicatively coupled to the processor 1310 via the components described herein. In at least one embodiment, an accelerometer 1341, an ambient light sensor (“ALS”) 1342, a compass 1343, and a gyroscope 1344 may be communicatively coupled to the sensor hub 1340. In at least one embodiment, a thermal sensor 1339, a fan 1337, a keyboard 1336, and a touchpad 1330 may be communicatively coupled to the EC 1335. In at least one embodiment, a speaker 1363, a headset 1364, and a microphone (“mic”) 1365 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 1362, which may in turn be communicatively coupled to the DSP 1360. In at least one embodiment, the audio unit 1362 may include, for example but not limited to, an audio encoder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a subscriber identity module (“SIM”) 1357 may be communicatively coupled to the WWAN unit 1356. In at least one embodiment, components (such as the WLAN unit 1350, the Bluetooth unit 1352, and the WWAN unit 1356) may be implemented in a next generation form factor (NGFF).

[0255] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 815 are provided herein in connection with Figure 8A and / or Figure 8B and / or. In at least one embodiment, the inference and / or training logic 815 may be in the system Figure 15is used, for example, to infer or predict operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0256] Figure 14 FIG. 1400 illustrates a computer system 1400 in accordance with at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement the various processes and methods described throughout this disclosure.

[0257] In at least one embodiment, the computer system 1400 includes, but is not limited to, at least one central processing unit (“CPU”) 1402 that is coupled to a communication bus 1410 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1400 includes, but is not limited to, a main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in the main memory 1404 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1422 provides an interface to other computing devices and networks for receiving data using the computer system 1400 and transmitting data to other systems.

[0258] In at least one embodiment, the computer system 1400 includes, but is not limited to, an input device 1408, a parallel processing system 1412, and a display device 1406 in at least one embodiment, which may be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”) display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from the input device 1408 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein may be located on a single semiconductor platform to form a processing system.

[0259] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 8A and / or Figure 8B provides details regarding the inference and / or training logic 815. In at least one embodiment, the inference and / or training logic 815 may be used in a system Figure 14 to perform inference or prediction operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0260] Figure 15 FIG. 1500 shows a computer system according to at least one embodiment. In at least one embodiment, computer system 1500 includes, but is not limited to, computer 1510 and USB drive 1520. In at least one embodiment, computer 1510 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, computer 1510 includes, but is not limited to, servers, cloud instances, laptops, and desktop computers.

[0261] In at least one embodiment, USB drive 1520 includes, but is not limited to, processing unit 1530, USB interface 1540, and USB interface logic 1550. In at least one embodiment, processing unit 1530 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1530 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1530 includes an application specific integrated circuit (“ASIC”) that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, processing unit 1530 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1530 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0262] In at least one embodiment, USB interface 1540 can be any type of USB connector or USB socket. For example, in at least one embodiment, USB interface 1540 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1550 may include any number and type of logic that enables processing unit 1530 to connect to a device (such as computer 1510) via USB connector 1540.

[0263] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in connection with Figure 8A and / or Figure 8B In at least one embodiment, inference and / or training logic 815 may be used in a system Figure 15 to infer or predict operations, at least in part, based on weight parameters, neural network functions, and / or architectures calculated using neural network training operations or neural network use cases described herein.

[0264] Figure 16A illustrates an exemplary architecture in which multiple GPUs 1610(1)-1610(N) are communicatively coupled to multiple multi-core processors 1605(1)-1605(M) via high-speed links 1640(1)-1640(N) (e.g., bus / peer-to-peer interconnect, etc.). In at least one embodiment, the high-speed links 1640(1)-1640(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, and their values may vary from figure to figure.

[0265] In addition, in one embodiment, two or more GPUs 1610 are interconnected via high-speed links 1629(1)-1629(2), which can be implemented using a protocol / link similar to or different from the protocol / link used for the high-speed links 1640(1)-1640(N). Similarly, two or more multi-core processors 1605 can be connected via a high-speed link 1628, which can be a symmetric multi-processor (SMP) bus operating at a speed of 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, all communications between the various system components shown Figure 16A can be accomplished using a similar protocol / link (e.g., via a common interconnect structure).

[0266] In one embodiment, each multi-core processor 1605 is communicatively coupled to a processor memory 1601(1)-1601(M) via a memory interconnect 1626(1)-1626(M), respectively, and each GPU 1610(1)-1610(N) is communicatively coupled to a GPU memory 1620(1)-1620(N) via a GPU memory interconnect 1650(1)-1650(N), respectively. In at least one embodiment, the memory interconnects 1626 and 1650 can utilize similar or different memory access technologies. By way of example and not limitation, the processor memories 1601(1)-1601(M) and the GPU memories 1620 can be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of the processor memory 1601 can be volatile memory while another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0267] As described herein, although various multi-core processors 1605 and GPUs 1610 can be physically coupled to specific memories 1601, 1620 respectively, and / or a unified memory architecture can be implemented, where a virtual system address space (also referred to as the "effective address" space) is distributed among the respective physical memories. For example, processor memories 1601(1)-1601(M) can each contain 64 GB of the system memory address space, and GPU memories 1620(1)-1620(N) can each contain 32 GB of the system memory address space, such that when M = 2 and N = 4, it results in a total addressable memory size of 256 GB. N and M can also be other values.

[0268] Figure 16B Additional details for the interconnection between a multi-core processor 1607 and a graphics acceleration module 1646 are shown in accordance with one exemplary embodiment. In at least one embodiment, the graphics acceleration module 1646 can include one or more GPU chips integrated on a line card that is coupled to the processor 1607 via a high-speed link 1640 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1646 can be selectively integrated on a package or chip with the processor 1607.

[0269] In at least one embodiment, the processor 1607 includes multiple cores 1660A-1660D, each core having a translation lookaside buffer ("TLB") 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, the cores 1660A-1660D can include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1662A-1662D can include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1656 can be included in the caches 1662A-1662D and shared by groups of cores 1660A-1660D. For example, one embodiment of the processor 1607 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1607 and the graphics acceleration module 1646 are connected to a system memory 1614, which can include Figure 16A the processor memories 1601(1)-1601(M) therein.

[0270] In at least one embodiment, cache coherence for data and instructions stored in respective caches 1662A - 1662D, 1656, and system memory 1614 is maintained via an inter-core communication through coherence bus 1664. In at least one embodiment, for example, each cache may have cache coherence logic / circuit associated therewith to communicate via coherence bus 1664 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via coherence bus 1664 to snoop cache accesses.

[0271] In at least one embodiment, proxy circuit 1625 communicatively couples graphics acceleration module 1646 to coherence bus 1664, thereby allowing graphics acceleration module 1646 to participate in the cache coherence protocol as a peer of cores 1660A - 1660D. In particular, in at least one embodiment, interface 1635 provides a connection to proxy circuit 1625 via high-speed link 1640, and interface 1637 connects graphics acceleration module 1646 to high-speed link 1640.

[0272] In at least one embodiment, accelerator integrated circuit 1636 provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines 1631(1) - 1631(N) of the graphics acceleration module. In at least one embodiment, graphics processing engines 1631(1) - 1631(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, graphics processing engines 1631(1) - 1631(N) may selectively include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1646 may be a GPU having multiple graphics processing engines 1631(1) - 1631(N), or graphics processing engines 1631(1) - 1631(N) may be individual GPUs integrated on a common package, line card, or chip.

[0273] In at least one embodiment, the accelerator integrated circuit 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and also includes a memory access protocol for accessing system memory 1614. In at least one embodiment, the MMU 1639 may also include a translation lookaside buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, the cache 1638 may store commands and data for efficient access by the graphics processing engines 1631(1)-1631(N). In at least one embodiment, a fetch unit 1644 may be used to keep the data stored in the cache 1638 and the graphics memories 1633(1)-1633(M) consistent with the core caches 1662A-1662D, 1656, and system memory 1614. As previously described, this task may be accomplished via proxy circuitry 1625 representing the cache 1638 and the graphics memories 1633(1)-1633(M) (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 1662A-1662D, 1656 to the cache 1638 and receiving updates from the cache 1638).

[0274] In at least one embodiment, a set of registers 1645 stores context data for threads executed by the graphics processing engines 1631(1)-1631(N), and a context management circuit 1648 manages thread contexts. For example, the context management circuit 1648 may perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread may be executed by the graphics processing engine). For example, the context management circuit 1648 may store the current register values into a specified area in memory (e.g., identified by a context pointer) when a context switch occurs. Then, the register values may be restored when the context is returned. In at least one embodiment, an interrupt management circuit 1647 receives and processes interrupts received from system devices.

[0275] In one implementation, the MMU 1639 converts virtual / valid addresses from the graphics processing engine 1631 into real / physical addresses in the system memory 1614. In at least one embodiment, the accelerator integrated circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1646 can be dedicated to a single application executing on the processor 1607, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, in which the resources of the graphics processing engines 1631(1)-1631(N) are shared among multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" based on processing requirements and priorities associated with the VMs and / or applications, and these slices are allocated to different VMs and / or applications.

[0276] In at least one embodiment, the accelerator integrated circuit 1636 functions as a bridge for the system of the graphics accelerator modules 1646 and provides address translation and system memory cache services. Additionally, in at least one embodiment, the accelerator integrated circuit 1636 can provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1631(1)-1631(N).

[0277] In at least one embodiment, since the hardware resources of the graphics processing engines 1631(1)-1631(N) are explicitly mapped to the real address space seen by the host processor 1607, any host processor can directly address these resources using valid address values. In at least one embodiment, one function of the accelerator integrated circuit 1636 is to physically isolate the graphics processing engines 1631(1)-1631(N) such that they appear as independent units to the system.

[0278] In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are coupled to each of the graphics processing engines 1631(1)-1631(N), respectively, and N = M. In at least one embodiment, the graphics memories 1633(1)-1633(M) store instructions and data that are processed by each of the graphics processing engines 1631(1)-1631(N). In at least one embodiment, the graphics memories 1633(1)-1633(M) can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3DXPoint or Nano-Ram.

[0279] In one embodiment, to reduce data traffic on the high-speed link 1640, a biasing technique is used to ensure that the data stored in the graphics memories 1633(1)-1633(M) is the most frequently used by the graphics processing engines 1631(1)-1631(N), and preferably data that is not used (or at least not frequently used) by the cores 1660A-1660D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data required by the cores (and preferably not the graphics processing engines 1631(1)-1631(N)) in the caches 1662A-1662D, 1656, and the system memory 1614.

[0280] Figure 16C Another exemplary embodiment is shown where the accelerator integrated circuit 1636 is integrated within the processor 1607. In this embodiment, the graphics processing engines 1631(1)-1631(N) communicate directly with the accelerator integrated circuit 1636 via the interfaces 1637 and 1635 (which can also be any form of bus or interface protocol) over the high-speed link 1640. In at least one embodiment, the accelerator integrated circuit 1636 can perform operations similar to those described with respect to Figure 16B However, due to its close proximity to the coherence bus 1664 and the caches 1662A-1662D, 1656, it may have higher throughput. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include programming models controlled by the accelerator integrated circuit 1636 and programming models controlled by the graphics acceleration module 1646.

[0281] In at least one embodiment, the graphics processing engines 1631(1)-1631(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to the graphics processing engines 1631(1)-1631(N), thereby providing virtualization within the VM / partition.

[0282] In at least one embodiment, the graphics processing engines 1631(1)-1631(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize the graphics processing engines 1631(1)-1631(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns the graphics processing engines 1631(1)-1631(N). In at least one embodiment, the operating system can virtualize the graphics processing engines 1631(1)-1631(N) to provide access to each process or application.

[0283] In at least one embodiment, the graphics acceleration module 1646 or an individual graphics processing engine 1631(1)-1631(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1614 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1631(1)-1631(N) (i.e., calling the system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0284] Figure 16D An exemplary accelerator integration slice 1690 is shown. In at least one embodiment, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1636. In at least one embodiment, an application is an effective address space 1682 in the system memory 1614 that stores a process element 1683. In at least one embodiment, in response to a GPU call 1681 from an application 1680 executing on the processor 1607, the process element 1683 is stored. In at least one embodiment, the process element 1683 contains the process state of the corresponding application 1680. In one embodiment, the work descriptor (WD) 1684 contained in the process element 1683 can be a single job requested by the application or can contain a pointer to a job queue. In at least one embodiment, the WD 1684 is a pointer to a job request queue in the effective address space 1682 of the application.

[0285] In at least one embodiment, the graphics acceleration module 1646 and / or the individual graphics processing engines 1631(1)-1631(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure can be included for setting the process state and sending the WD 1684 to the graphics acceleration module 1646 to start a job in a virtualized environment.

[0286] In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1646 or an individual graphics processing engine 1631. In at least one embodiment, when the graphics acceleration module 1646 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1646 is assigned, the operating system initializes the accelerator integrated circuit 1636 for the owned process.

[0287] In at least one embodiment, in operation, the WD fetch unit 1691 in the accelerator integrated slice 1690 fetches the next WD 1684, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1646. In at least one embodiment, data from the WD 1684 can be stored in the register 1645 and used by the MMU 1639, the interrupt management circuit 1647, and / or the context management circuit 1648, as shown. For example, one embodiment of the MMU 1639 includes a segment / page walk circuit for accessing the segment / page table 1686 within the OS virtual address space 1685. In at least one embodiment, the interrupt management circuit 1647 can process the interrupt event 1692 received from the graphics acceleration module 1646. In at least one embodiment, when performing a graphics operation, the virtual address 1693 generated by the graphics processing engine 1631(1)-1631(N) is translated to a physical address by the MMU 1639.

[0288] In one embodiment, the register 1645 is replicated for each graphics processing engine 1631(1)-1631(N) and / or the graphics acceleration module 1646, and the register 1645 can be initialized by the hypervisor or the operating system. In at least one embodiment, each of these replicated registers can be included in the accelerator integrated slice 1690. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0289] Table 1 - Hypervisor Initialized Registers

[0290] Register # Description

[0291] 1 Slice control register

[0292] 2 Physical address (RA) scheduled process area pointer

[0293] 3 Permission mask override register

[0294] 4 Interrupt vector table entry offset

[0295] 5 Interrupt vector table entry limit

[0296] 6 Status register

[0297] 7 Logical partition ID

[0298] 8 Physical address (RA) hypervisor accelerator utilization record pointer

[0299] 9 Storage description register

[0300] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0301] Table 2 – Registers for Operating System Initialization

[0302] Register # Description

[0303] 1 Process and Thread Identification

[0304] 2 Effective Address (EA) Context Save / restore Pointer

[0305] 3 Virtual Address (VA) Accelerator Utilization Record Pointer

[0306] 4 Virtual Address (VA) Storage Segment Table Pointer

[0307] 5 Privilege Mask

[0308] 6 Work Descriptor

[0309] In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engine 1631(1)-1631(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1631(1)-1631(N) to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0310] Figure 16E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1698 in which a list of process elements 1699 is stored. In at least one embodiment, the hypervisor real address space 1698 can be accessed via a hypervisor 1696 that virtualizes the graphics acceleration module engine for the operating system 1695.

[0311] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1646. In at least one embodiment, there are two programming models in which the graphics acceleration module 1646 is shared by multiple processes and partitions, namely, time-slicing sharing and graphics-oriented sharing.

[0312] In at least one embodiment, in the model, the hypervisor 1696 owns the graphics acceleration module 1646 and makes its functions available to all operating systems 1695. In at least one embodiment, for the graphics acceleration module 1646 to support virtualization through the hypervisor 1696, the graphics acceleration module 1646 may have to comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., do not need to maintain state between jobs), or the graphics acceleration module 1646 must provide a context save and restore mechanism, (2) the graphics acceleration module 1646 guarantees that the job requests of the application are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1646 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, fairness must be ensured between the graphics acceleration module 1646 processes.

[0313] In at least one embodiment, the application 1680 is required to use the graphics acceleration module type, work descriptor (WD), access mask register (AMR) value, and context save / restore area pointer (CSRP) for operating system 1695 system calls. In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1646 and can take the form of a graphics acceleration module 1646 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1646.

[0314] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1636 (not shown) and the graphics acceleration module 1646 does not support the user access mask override register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1696 may selectively apply the current access mask override register (AMOR) value before placing the AMR in the process element 1683. In at least one embodiment, the CSRP is one of the registers 1645 that contains the valid address of a region in the application's valid address space 1682 for the graphics acceleration module 1646 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be a fixed system memory.

[0315] When receiving a system call, the operating system 1695 can verify that the application 1680 has been registered and is granted permission to use the graphics acceleration module 1646. Then, in at least one embodiment, the operating system 1695 uses the information shown in Table 3 to call the hypervisor 1696.

[0316] Table 3 - Call Parameters from Operating System to Hypervisor

[0317] Parameter # Description

[0318] 1 Work Descriptor (WD)

[0319] 2 Access Mask Register (AMR) Value (May be Masked)

[0320] 3 Effective Address (EA) Context Save / Restore Area Pointer (CSRP)

[0321] 4 Process ID (PID) and Optional Thread ID (TID)

[0322] 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP)

[0323] 6 Virtual Address of Storage Segment Table Pointer (SSTP)

[0324] 7 Logical Interrupt Service Number (LISN)

[0325] In at least one embodiment, when receiving a hypervisor call, the hypervisor 1696 verifies that the operating system 1695 has been registered and is granted permission to use the graphics acceleration module 1646. Then, in at least one embodiment, the hypervisor 1696 places the process element 1683 into the corresponding linked list of process elements of the graphics acceleration module 1646 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0326] Table 4 - Process Element Information

[0327] Element # Description

[0328] 1 Work Descriptor (WD)

[0329] 2 Access Mask Register (AMR) Value (May be Masked)

[0330] 3 Effective Address (EA) Context Save / Restore Area Pointer (CSRP)

[0331] 4 Process ID (PID) and Optional Thread ID (TID)

[0332] 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP)

[0333] 6 Virtual Address of Storage Segment Table Pointer (SSTP)

[0334] 7 Logical Interrupt Service Number (LISN)

[0335] 8 Interrupt Vector Table Derived from Hypervisor Call Parameters

[0336] 9 Status Register (SR) Value

[0337] 10 Logical Partition ID (LPID)

[0338] 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer

[0339] 12 Storage Descriptor Register (SDR)

[0340] In at least one embodiment, the hypervisor initializes a plurality of accelerator integrated slice 1690 registers 1645.

[0341] As Figure 16F shown, in at least one embodiment, a unified memory is used, which can be addressed via a common virtual memory address space for accessing physical processor memories 1601(1)-1601(N) and GPU memories 1620(1)-1620(N). In this implementation, operations executed on GPUs 1610(1)-1610(N) utilize the same virtual / effective memory address space to access processor memories 1601(1)-1601(M), and vice versa, thus simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1601(1), a second portion is allocated to second processor memory 1601(N), a third portion is allocated to GPU memory 1620(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1601 and GPU memories 1620, allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0342] In one embodiment, bias / coherency management circuits 1694A-1694E within one or more MMUs 1639A-1639E ensure cache coherency between one or more host processors (e.g., 1605) and the caches of GPUs 1610, and implement a bias technique for physical memory indicating where certain types of data should be stored. In at least one embodiment, although Figure 16FMultiple instances of the bias / coherence management circuitry 1694A - 1694E are shown, but the bias / coherence circuitry may be implemented within the MMU of one or more host processors 1605 and / or within the accelerator integrated circuit 1636.

[0343] One embodiment allows the GPU memory 1620 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) techniques, without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access the GPU memory 1620 as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows software of the host processor 1605 to set operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies include driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU memory 1620 without cache coherence overhead may be critical to the execution time of offloaded computations. In at least one embodiment, for example, in the presence of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1610. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0344] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page - granularity structure (e.g., controlled at the granularity of memory pages), and this page - granularity structure includes 1 or 2 bits per GPU - attached memory page. In at least one embodiment, with or without a bias cache in the GPU 1610 (e.g., for caching frequently / most recently used entries of the bias table), the bias table may be implemented in the stolen memory ranges of one or more GPU memories 1620. Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0345] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1620 is accessed, thereby causing the following operations. In at least one embodiment, local requests from the GPU 1610 that find their pages in the GPU bias are directly forwarded to the corresponding GPU memory 1620. In at least one embodiment, local requests from the GPU that find their pages in the host bias are forwarded to the processor 1605 (e.g., via the high-speed link described herein). In at least one embodiment, requests from the processor 1605 that find the requested page in the host processor bias complete a request similar to a normal memory read. Alternatively, requests pointing to GPU bias pages can be forwarded to the GPU 1610. In at least one embodiment, if the GPU is not currently using a page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a software mechanism assisted by hardware, or, in limited cases, by a purely hardware-based mechanism.

[0346] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently calls the device driver of the GPU. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and perform a cache flush operation in the host in certain migrations. In at least one embodiment, the cache flush operation is used for migrations from the host processor 1605 bias to the GPU bias, but not for the reverse migration.

[0347] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 1605. In at least one embodiment, to access these pages, the processor 1605 can request access from the GPU 1610, and the GPU 1610 may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between the processor 1605 and the GPU 1610, it is beneficial to ensure that GPU bias pages are pages required by the GPU rather than by the host processor 1605, and vice versa.

[0348] One or more hardware structures 815 are used to execute one or more embodiments. Details regarding one or more hardware structures 815 may be provided herein in conjunction with Figure 8A and / or Figure 8B provide details regarding one or more hardware structures 815.

[0349] Figure 17Illustrated is an exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein, which may be fabricated using one or more IP cores. In addition to the illustration, in at least one embodiment other logic and circuits may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0350] Figure 17 FIG. 4 is a block diagram of an exemplary system on a chip integrated circuit 1700 that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1700 includes one or more application processors 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1700 includes peripheral or bus logic that includes a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I22S / I22C controller 1740. In at least one embodiment, integrated circuit 1700 may include a display device 1745 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1750 and a mobile industry processor interface (MIPI) display interface 1755. In at least one embodiment, storage may be provided by a flash memory subsystem 1760, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1765 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1770.

[0351] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in connection with Figure 8A and / or Figure 8B In at least one embodiment, inference and / or training logic 815 may be in integrated circuit 1700 for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0352] Figure 18A and Figure 18B Illustrated is an exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein, which may be fabricated using one or more IP cores. In addition to the illustration, in at least one embodiment other logic and circuits may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0353] Figure 18A and Figure 18B is a block diagram showing an exemplary graphics processor used within a SoC in accordance with an embodiment described herein. Figure 18A An exemplary graphics processor 1810 for a system-on-chip integrated circuit in accordance with at least one embodiment is shown, which may be fabricated using one or more IP cores. Figure 18B Another exemplary graphics processor 1840 for a system-on-chip integrated circuit in accordance with at least one embodiment is shown, which may be fabricated using one or more IP cores. In at least one embodiment, Figure 18A the graphics processor 1810 is a low-power graphics processor core. In at least one embodiment, Figure 18B the graphics processor 1840 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1810, 1840 may be Figure 17 a variant of the graphics processor 1710.

[0354] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A - 1815N (e.g., 1815A, 1815B, 1815C, 1815D to 1815N-1, and 1815N). In at least one embodiment, the graphics processor 1810 may execute different shader programs via separate logic such that the vertex processor 1805 is optimized to execute operations for a vertex shader program, while the one or more fragment processors 1815A - 1815N perform fragment (e.g., pixel) shading operations for a fragment or pixel or shader program. In at least one embodiment, the vertex processor 1805 executes the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1815A - 1815N use the primitives and vertex data generated by the vertex processor 1805 to generate a frame buffer to be displayed on a display device. In at least one embodiment, the one or more fragment processors 1815A - 1815N are optimized to execute a fragment shader program as provided in the OpenGL API, which may be used to perform operations similar to those of a pixel shader program provided in the Direct 3D API.

[0355] In at least one embodiment, the graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A - 1820B, one or more caches 1825A - 1825B, and one or more circuit interconnects 1830A - 1830B. In at least one embodiment, one or more MMUs 1820A - 1820B provide virtual - to - physical address mapping for the graphics processor 1810, including for the vertex processor 1805 and / or the fragment processors 1815A - 1815N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1825A - 1825B. In at least one embodiment, one or more MMUs 1820A - 1820B may be synchronized with other MMUs within the system, including one or more MMUs associated with Figure 17 one or more application processors 1705, image processors 1715, and / or video processors 1720 such that each processor 1705 - 1720 may participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A - 1830B enable the graphics processor 1810 to connect to other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0356] In at least one embodiment, the graphics processor 1840 includes one or more shader cores 1855A - 1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F to 1855N - 1 and 1855N), as Figure 18B shown, which provides a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1840 includes an inter - core task manager 1845, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1855A - 1855N and a tiling unit 1858 to accelerate tiling operations for tile - based rendering, where the rendering operation of a scene is subdivided in the image space, e.g., to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0357] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described in connection with Figure 8A and / or Figure 8BProvide details regarding inference and / or training logic 815. In at least one embodiment, the inference and / or training logic 815 may be in an integrated circuit Figure 18A and / or Figure 18B for performing inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions or architectures, or neural network use cases described herein.

[0358] Figure 19A and Figure 19B illustrates additional exemplary graphics processor logic in accordance with embodiments described herein. In at least one embodiment, Figure 19A illustrates a graphics core 1900 that may be included within Figure 17 a graphics processor 1710, and in at least one embodiment, it may be a unified shader core 1855A - 1855N as Figure 18B shown. Figure 19B illustrates a highly parallel general - purpose graphics processing unit (“GPGPU”) 1930 suitable for deployment on a multi - chip module in at least one embodiment.

[0359] In at least one embodiment, the graphics core 1900 includes a shared instruction cache 1902, texture units 1918, and cache / shared memory 1920, which are common to the execution resources within the graphics core 1900. In at least one embodiment, the graphics core 1900 may include multiple slices 1901A - 1901N or partitions per core, and the graphics processor may include multiple instances of the graphics core 1900. In at least one embodiment, the slices 1901A - 1901N may include support logic, which includes local instruction caches 1904A - 1904N, thread schedulers 1906A - 1906N, thread dispatchers 1908A - 1908N, and a set of registers 1910A - 1910N. In at least one embodiment, the slices 1901A - 1901N may include a set of additional functional units (AFU 1912A - 1912N), floating - point units (FPU 1914A - 1914N), integer arithmetic logic units (ALU 1916A - 1916N), address calculation units (ACU 1913A - 1913N), double - precision floating - point units (DPFPU1915A - 1915N), and matrix processing units (MPU 1917A - 1917N).

[0360] In at least one embodiment, the FPU 1914A - 1914N may perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while the DPFPU 1915A - 1915N performs double - precision (64 - bit) floating - point operations. In at least one embodiment, the ALU 1916A - 1916N may perform variable - precision integer operations with 8 - bit, 16 - bit, and 32 - bit precision and may be configured for mixed - precision operations. In at least one embodiment, the MPU 1917A - 1917N may also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, the MPU 1917 - 1917N may perform various matrix operations to accelerate machine - learning application frameworks, including enabling support for accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, the AFU 1912A - 1912N may perform additional logic operations not supported by the floating - point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0361] The inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 815 are provided herein in connection with Figure 8A and / or Figure 8B the use case of neural networks. In at least one embodiment, the inference and / or training logic 815 may be used in the graphics core 1900 to infer or predict operations based at least in part on weight parameters calculated using neural - network training operations, neural - network functions, and / or architectures or neural - network use cases described herein.

[0362] Figure 19BIllustrated is a general - purpose processing unit (GPGPU) 1930 in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a set of graphics processing units. In at least one embodiment, GPGPU 1930 can be directly linked to other instances of GPGPU 1930 to create a multi - GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1930 includes a host interface 1932 to enable connection to a host processor. In at least one embodiment, host interface 1932 is a PCI Express interface. In at least one embodiment, host interface 1932 can be a vendor - specific communication interface or communication fabric. In at least one embodiment, GPGPU 1930 receives commands from the host processor and uses a global scheduler 1934 to allocate execution threads associated with those commands to a set of compute clusters 1936A - 1936H. In at least one embodiment, compute clusters 1936A - 1936H share a cache memory 1938. In at least one embodiment, cache memory 1938 can be used as a higher - level cache for the cache memories within compute clusters 1936A - 1936H.

[0363] In at least one embodiment, GPGPU 1930 includes memories 1944A - 1944B, which are coupled to compute clusters 1936A - 1936H via a set of memory controllers 1942A - 1942B. In at least one embodiment, memories 1944A - 1944B can include various types of memory devices, including dynamic random - access memory (DRAM) or graphics random - access memory, such as synchronous graphics random - access memory (SGRAM), which includes graphics double - data rate (GDDR) memory.

[0364] In at least one embodiment, each of compute clusters 1936A - 1936H includes a set of graphics cores, such as Figure 19A graphics core 1900, which can include various types of integer and floating - point logic units that can perform computing operations over a variety of precision ranges of a computer, including precisions suitable for machine - learning computations. For example, in at least one embodiment, at least one subset of the floating - point units in each of compute clusters 1936A - 1936H can be configured to perform 16 - bit or 32 - bit floating - point operations, while different subsets of the floating - point units can be configured to perform 64 - bit floating - point operations.

[0365] In at least one embodiment, multiple instances of GPGPU 1930 may be configured to function as compute clusters. In at least one embodiment, the communication for synchronization and data exchange in compute clusters 1936A - 1936H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to GPU link 1940, enabling direct connection to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU - to - GPU bridge that enables communication and synchronization between multiple instances of GPGP 1930. In at least one embodiment, GPU link 1940 is coupled to a high - speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate data processing systems and communicate via network devices accessible through host interface 1932. In at least one embodiment, GPU link 1940 can be configured to enable connection to a processor other than or in place of host interface 1932.

[0366] In at least one embodiment, GPGPU 1930 may be configured to train neural networks. In at least one embodiment, GPGPU 1930 can be used within an inference platform. In at least one embodiment, in cases where GPGPU 1930 is used for inference, GPGPU 1930 may include fewer compute clusters 1936A - 1936H compared to when GPGPU 1930 is used to train neural networks. In at least one embodiment, the memory technologies associated with memories 1944A - 1944B may differ between inference and training configurations, with higher - bandwidth memory technologies dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 1930 may support inference - specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8 - bit integer dot - product instructions that can be used during the inference operations of a deployed neural network.

[0367] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 8A and / or Figure 8BProvide details regarding inference and / or training logic 815. In at least one embodiment, the inference and / or training logic 815 can be used in the GPGPU 1930 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0368] Figure 20 FIG. shows a block diagram of a computer system 2000 in accordance with at least one embodiment. In at least one embodiment, the computer system 2000 includes a processing subsystem 2001 having one or more processors 2002 and a system memory 2004, the system memory 2004 communicating via an interconnect path that can include a memory hub 2005. In at least one embodiment, the memory hub 2005 can be a separate component within a chipset component or can be integrated within one or more processors 2002. In at least one embodiment, the memory hub 2005 is coupled to an I / O subsystem 2011 via a communication link 2006. In one embodiment, the I / O subsystem 2011 includes an I / O hub 2007, which can enable the computer system 2000 to receive input from one or more input devices 2008. In at least one embodiment, the I / O hub 2007 can enable a display controller to provide output to one or more display devices 2010A, which can be included in one or more processors 2002. In at least one embodiment, one or more display devices 2010A coupled to the I / O hub 2007 can include a local, internal, or embedded display device.

[0369] In at least one embodiment, the processing subsystem 2001 includes one or more parallel processors 2012 coupled to the memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 can use any of a number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the one or more parallel processors 2012 form a parallel or vector processing system in a compute cluster, which can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 2012 form a graphics processing subsystem that can output pixels to one of the one or more display devices 2010A coupled via the I / O hub 2007. In at least one embodiment, the parallel processors 2012 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 2010B.

[0370] In at least one embodiment, the system storage unit 2014 may be connected to the I / O hub 2007 to provide a storage mechanism for the computer system 2000. In at least one embodiment, the I / O switch 2016 may be used to provide an interface mechanism to enable connections between the I / O hub 2007 and other components, such as network adapter 2018 and / or wireless network adapter 2019 that may be integrated into the platform, as well as various other devices that may be added via one or more additional devices 2020. In at least one embodiment, the network adapter 2018 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2019 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0371] In at least one embodiment, the computer system 2000 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2007. In at least one embodiment, any suitable protocol (such as a PCI (Peripheral Component Interconnect)-based protocol (such as PCI-Express) or other bus or point-to-point communication interface and / or protocol) may be used to implement the communication paths between the various components, such as NV-Link high-speed interconnect or interconnect protocol. Figure 20 among the various components, such as NV-Link high-speed interconnect or interconnect protocol.

[0372] In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for graphics and video processing, which includes, for example, video output circuitry and constitutes a Graphics Processing Unit (GPU). In at least one embodiment, the parallel processors 2012 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of the computer system 2000 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processors 2012, memory hub 2005, processor 2002, and I / O hub 2007 may be integrated into a System-on-Chip (SoC) integrated circuit. In at least one embodiment, the components of the computer system 2000 may be integrated into a single package to form a System-in-Package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2000 may be integrated into a Multi-Chip Module (MCM), which may be interconnected with other multi-chip modules into a modular computer system.

[0373] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection withFigure 8A and / or Figure 8B Provide details about the inference and / or training logic 815. In at least one embodiment, the inference and / or training logic 815 can be used in the Figure 20 system 2000 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0374] processor

[0375] Figure 21A FIG. shows a parallel processor 2100 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2100 can be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2100 is a variant of the Figure 20 one or more parallel processors 2012 shown in the exemplary embodiment.

[0376] In at least one embodiment, the parallel processor 2100 includes a parallel processing unit 2102. In at least one embodiment, the parallel processing unit 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of the parallel processing unit 2102. In at least one embodiment, the I / O unit 2104 can be directly connected to other devices. In at least one embodiment, the I / O unit 2104 is connected to other devices using a hub or switch interface (e.g., a memory hub 2105). In at least one embodiment, the connection between the memory hub 2105 and the I / O unit 2104 forms a communication link 2113. In at least one embodiment, the I / O unit 2104 is connected to a host interface 2106 and a memory crossbar 2116, where the host interface 2106 receives commands for performing processing operations and the memory crossbar 2116 receives commands for performing memory operations.

[0377] In at least one embodiment, when the host interface 2106 receives a command buffer via the I / O unit 2104, the host interface 2106 may initiate work operations to execute those commands to the front end 2108. In at least one embodiment, the front end 2108 is coupled to a scheduler 2110 that is configured to allocate commands or other work items to an array of processing clusters 2112. In at least one embodiment, the scheduler 2110 ensures that the array of processing clusters 2112 is properly configured and in an active state before tasks are allocated to it. In at least one embodiment, the scheduler 2110 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2110 can be configured to perform complex scheduling and work allocation operations at both a coarse-grained and a fine-grained level, enabling fast preemption and context switching of threads executing on the processing array 2112. In at least one embodiment, host software may attest to a workload for scheduling on the processing array 2112 via one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically allocated on the processing array 2112 by the scheduler 2110 logic within a microcontroller that includes the scheduler 2110.

[0378] In at least one embodiment, the array of processing clusters 2112 may include up to "N" processing clusters (e.g., clusters 2114A, 2114B through 2114N), where "N" represents a positive integer (which may be a different integer than the integer "N" used in other figures). In at least one embodiment, each of the clusters 2114A - 2114N of the array of processing clusters 2112 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2114A - 2114N of the array of processing clusters 2112, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2110, or may be assisted in part by compiler logic during the compilation of program logic configured to be executed by the array of processing clusters 2112. In at least one embodiment, different ones of the clusters 2114A - 2114N of the array of processing clusters 2112 may be assigned to process different types of programs or to perform different types of computations.

[0379] In at least one embodiment, the processing cluster array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2112 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2112 can include logic for performing processing tasks that include filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data conversions.

[0380] In at least one embodiment, the processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2112 can include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2112 can be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2102 can transfer data from the system memory via the I / O unit 2104 for processing. In at least one embodiment, during processing, the transferred data can be stored in on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to the system memory.

[0381] In at least one embodiment, when the parallel processing unit 2102 is used to perform graphics processing, the scheduler 2110 can be configured to divide the processing workload into tasks of approximately equal size to better distribute the graphics processing operations to the multiple clusters 2114A - 2114N of the processing cluster array 2112. In at least one embodiment, portions of the processing cluster array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2114A - 2114N can be stored in a buffer to allow transfer of the intermediate data between the clusters 2114A - 2114N for further processing.

[0382] In at least one embodiment, the processing cluster array 2112 can receive processing tasks to be executed via a scheduler 2110 that receives commands defining the processing tasks from a front end 2108. In at least one embodiment, the processing tasks can include indices of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as status parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2110 can be configured to obtain an index corresponding to the task or can receive the index from the front end 2108. In at least one embodiment, the front end 2108 can be configured to ensure that the processing cluster array 2112 is configured in an effective state before starting a workload specified by an incoming command buffer (e.g., batch-buffer, push buffer, etc.).

[0383] In at least one embodiment, each of one or more instances of the parallel processing units 2102 can be coupled to a parallel processor memory 2122. In at least one embodiment, the parallel processor memory 2122 can be accessed via a memory crossbar 2116 that can receive memory requests from the processing cluster array 2112 as well as the I / O unit 2104. In at least one embodiment, the memory crossbar 2116 can access the parallel processor memory 2122 via a memory interface 2118. In at least one embodiment, the memory interface 2118 can include a plurality of partitioning units (e.g., partitioning unit 2120A, partitioning unit 2120B to partitioning unit 2120N), each of which can be coupled to a portion (e.g., a memory unit) of the parallel processor memory 2122. In at least one embodiment, the plurality of partitioning units 2120A-2120N are configured to be equal to the number of memory units such that the first partitioning unit 2120A has a corresponding first memory unit 2124A, the second partitioning unit 2120B has a corresponding memory unit 2124B, and the Nth partitioning unit 2120N has a corresponding Nth memory unit 2124N. In at least one embodiment, the number of partitioning units 2120A-2120N can be not equal to the number of memory units.

[0384] In at least one embodiment, the memory units 2124A-2124N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2124A-2124N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across the memory units 2124A-2124N, allowing the partitioning units 2120A-2120N to write portions of each render target in parallel to effectively utilize the available bandwidth of the parallel processor memory 2122. In at least one embodiment, a local instance of the parallel processor memory 2122 may be excluded in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0385] In at least one embodiment, any one of the clusters 2114A-2114N in the cluster array 2112 of processing clusters may process data to be written into any of the memory units 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 may be configured to transfer the output of each cluster 2114A-2114N to any of the partitioning units 2120A-2120N or another cluster 2114A-2114N, where the cluster 2114A-2114N may perform additional processing operations on the output. In at least one embodiment, each cluster 2114A-2114N may communicate with the memory interface 2118 through the memory crossbar 2116 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar 2116 has a connection to the memory interface 2118 to communicate with the I / O unit 2104, as well as a connection to a local instance of the parallel processor memory 2122, enabling processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to the parallel processing units 2102. In at least one embodiment, the memory crossbar 2116 may use virtual channels to separate the traffic flow between the clusters 2114A-2114N and the partitioning units 2120A-2120N.

[0386] In at least one embodiment, multiple instances of the parallel processing unit 2102 may be provided on a single insertion card, or multiple insertion cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2102 may be configured to operate with each other, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2102 may include floating-point units with higher precision relative to other instances. In at least one embodiment, a system incorporating one or more instances of the parallel processing unit 2102 or parallel processor 2100 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, gaming consoles, and / or embedded systems.

[0387] Figure 21B is a block diagram of a partitioning unit 2120 according to at least one embodiment. In at least one embodiment, the partitioning unit 2120 is Figure 21A an instance of one of the partitioning units 2120A - 2120N. In at least one embodiment, the partitioning unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and a ROP 2126 (raster operation unit). In at least one embodiment, the L2 cache 2121 is a read / write cache configured to perform load and store operations received from the memory crossbar 2116 and the ROP 2126. In at least one embodiment, the L2 cache 2121 outputs read misses and urgent write-back requests to the frame buffer interface 2125 for processing. In at least one embodiment, updates may also be sent to the frame buffer via the frame buffer interface 2125 for processing. In at least one embodiment, the frame buffer interface 2125 interacts with one of the memory units (such as Figure 21A the memory units 2124A - 2124N (e.g., within the parallel processor memory 2122)) of

[0388] In at least one embodiment, ROP 2126 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, ROP 2126 then outputs the processed graphics data stored in the graphics memory. In at least one embodiment, ROP 2126 includes compression logic to compress depth or color data written to the memory and decompress depth or color data read from the memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP2126 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, delta color compression is performed based on depth and color data on a per-tile basis.

[0389] In at least one embodiment, ROP 2126 is included within each processing cluster (e.g., Figure 21A clusters 2114A - 2114N), rather than within the partitioning unit 2120. In at least one embodiment, read and write requests for pixel data are made through the memory crossbar 2116 rather than pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as Figure 22 one of one or more display devices 2210), routed by the processor 2202 for further processing, or routed by Figure 21A one of the processing entities within the parallel processor 2100 for further processing.

[0390] Figure 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is Figure 21A an instance of one of the processing clusters 2114A - 2114N. In at least one embodiment, the processing cluster 2114 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0391] In at least one embodiment, the operation of the processing cluster 2114 can be controlled by assigning processing tasks to the pipeline manager 2132 of the SIMT parallel processor. In at least one embodiment, the pipeline manager 2132 receives from Figure 21AThe scheduler 2110 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2134 and / or the texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2114. In at least one embodiment, one or more instances of the graphics multiprocessor 2134 may be included within the processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 may process data, and the data crossbar 2140 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2132 may facilitate the distribution of the processed data by specifying the destination of the processed data to be allocated via the data crossbar 2140.

[0392] In at least one embodiment, each graphics multiprocessor 2134 within the processing cluster 2114 may include the same set of functional execution logic (e.g., arithmetic logic units, load store units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipeline manner, where new instructions may be issued before the completion of previous instructions. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, boolean operations, shifts, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may exist.

[0393] In at least one embodiment, the instructions transmitted to the processing cluster 2114 constitute threads. In at least one embodiment, a set of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2134. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during the loop in which the thread group is being processed. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2134, processing may be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups may be executed simultaneously on the graphics multiprocessor 2134.

[0394] In at least one embodiment, the graphics multiprocessor 2134 includes an internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2134 can forgo the internal cache and use the cache memory (e.g., L1 cache 2148) within the processing cluster 2114. In at least one embodiment, each graphics multiprocessor 2134 can also access the L2 cache within the partition units (e.g., Figure 21A partition units 2120A - 2120N) of Figure 21A , which are shared among all processing clusters 2114 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2134 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to the parallel processing unit 2102 can be used as global memory. In at least one embodiment, the processing cluster 2114 includes multiple instances of the graphics multiprocessor 2134, which can share common instructions and data that can be stored in the L1 cache 2148.

[0395] In at least one embodiment, each processing cluster 2114 can include a memory management unit (“MMU”) 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2145 can reside within Figure 21A the memory interface 2118 of Figure 21A . In at least one embodiment, the MMU 2145 includes a set of page table entries (PTEs) that are used to map virtual addresses to the physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2145 can include a translation lookaside buffer (TLB) or a cache that can reside within the graphics multiprocessor 2134 or the L1 cache 2148 or the processing cluster 2114. In at least one embodiment, the physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index can be used to determine whether a request to a cache line is a hit or a miss.

[0396] In at least one embodiment, the processing cluster 2114 can be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from the L1 cache within the graphics multiprocessor 2134, and texture data is fetched from the L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2134 outputs the processed task to the data crossbar 2140 to provide the processed task to another processing cluster 2114 for further processing or store the processed task in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 2116. In at least one embodiment, the preROP 2142 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2134 and direct the data to a ROP unit that can be located with the partitioning units (e.g., Figure 21A partitioning units 2120A - 2120N) described herein. In at least one embodiment, the PreROP 2142 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0397] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 815 are provided herein in connection with Figure 8A and / or Figure 8B In at least one embodiment, the inference and / or training logic 815 can be in the graphics processing cluster 2114 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0398] Figure 21D FIG. shows a graphics multiprocessor 2134 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2134 is coupled to the pipeline manager 2132 of the processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 has an execution pipeline that includes, but is not limited to, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more general-purpose graphics processing unit (GPGPU) cores 2162, and one or more load / store units 2166. In at least one embodiment, the GPGPU cores 2162 and the load / store units 2166 are coupled to a cache memory 2172 and a shared memory 2170 via a memory and cache interconnect 2168.

[0399] In at least one embodiment, the instruction cache 2152 receives a stream of instructions to be executed from the pipeline manager 2132. In at least one embodiment, the instructions are cached in the instruction cache 2152 and dispatched for execution by the instruction unit 2154. In one embodiment, the instruction unit 2154 may dispatch instructions as a thread group (e.g., a warp), with each thread of the thread group assigned to a different execution unit within the GPGPU core 2162. In at least one embodiment, instructions may access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, the address mapping unit 2156 may be used to translate an address in the unified address space into a different memory address that can be accessed by the load / store unit 2166.

[0400] In at least one embodiment, the register file 2158 provides a set of registers for the functional units of the graphics multiprocessor 2134. In at least one embodiment, the register file 2158 provides temporary storage for the operands of the data paths of the functional units (e.g., GPGPU core 2162, load / store unit 2166) connected to the graphics multiprocessor 2134. In at least one embodiment, the register file 2158 is partitioned among each functional unit such that a dedicated portion of the register file 2158 is assigned to each functional unit. In at least one embodiment, the register file 2158 is partitioned among different warps being executed by the graphics multiprocessor 2134.

[0401] In at least one embodiment, the GPGPU cores 2162 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of the graphics multiprocessor 2134. In at least one embodiment, the GPGPU cores 2162 may be architecturally similar or may have different architectures. In at least one embodiment, a first portion of the GPGPU core 2162 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2134 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copy rectangle or pixel blend operations. In at least one embodiment, one or more of the GPGPU cores 2162 may also include fixed or special-function logic.

[0402] In at least one embodiment, the GPGPU core 2162 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2162 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0403] In at least one embodiment, the memory and cache interconnect 2168 is an interconnect network that connects each functional unit of the graphics multiprocessor 2134 to the register file 2158 and the shared memory 2170. In at least one embodiment, the memory and cache interconnect 2168 is a crossbar interconnect that allows the load / store unit 2166 to perform load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 can operate at the same frequency as the GPGPU core 2162, resulting in very low latency for data transfer between the GPGPU core 2162 and the register file 2158. In at least one embodiment, the shared memory 2170 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2134. In at least one embodiment, the cache memory 2172 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 2136. In at least one embodiment, the shared memory 2170 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in the cache memory 2172, threads executing on the GPGPU core 2162 can also programmatically store data in the shared memory.

[0404] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on a package or die and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or die). In at least one embodiment, regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0405] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided below in conjunction with Figure 8A and / or Figure 8B In at least one embodiment, the inference and / or training logic 815 can be in the graphics multiprocessor 2134 to perform inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0406] Figure 22FIG. 2200 shows a multi-GPU computing system 2200 according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2200 may include a processor 2202 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2206A-D via a host interface switch 2204. In at least one embodiment, the host interface switch 2204 is a PCI Express switch device that couples the processor 2202 to a PCI Express bus, and the processor 2202 may communicate with the GPGPUs 2206A-D via the PCI Express bus. In at least one embodiment, the GPGPUs 2206A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2216. In at least one embodiment, the GPU-to-GPU link 2216 is connected to each of the GPGPUs 2206A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU link 2216 enables direct communication between each of the GPGPUs 2206A-D without communicating through the host interface bus 2204 to which the processor 2202 is connected. In at least one embodiment, in the case where GPU-to-GPU traffic is directed to the P2P GPU link 2216, the host interface bus 2204 remains available for system memory access or communication with other instances of the multi-GPU computing system 2200 via, for example, one or more network devices. Although in at least one embodiment, the GPGPUs 2206A-D are connected to the processor 2202 via the host interface switch 2204, in at least one embodiment, the processor 2202 includes direct support for the P2P GPU link 2216 and may be directly connected to the GPGPUs 2206A-D.

[0407] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in connection with Figure 8A and / or Figure 8B at least partially based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0408] Figure 23Block diagram of a graphics processor 2300 according to at least one embodiment. In at least one embodiment, the graphics processor 2300 includes a ring interconnect 2302, a pipeline front end 2304, a media engine 2337, and graphics cores 2380A - 2380N. In at least one embodiment, the ring interconnect 2302 couples the graphics processor 2300 to other processing units, the processing units including other graphics processors or one or more general - purpose processor cores. In at least one embodiment, the graphics processor 2300 is one of many processors integrated within a multi - core processing system.

[0409] In at least one embodiment, the graphics processor 2300 receives multiple batches of commands via the ring interconnect 2302. In at least one embodiment, the input commands are interpreted by a command streamer 2303 in the pipeline front end 2304. In at least one embodiment, the graphics processor 2300 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2380A - 2380N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2303 provides the commands to the geometry pipeline 2336. In at least one embodiment, for at least some media processing commands, the command streamer 2303 provides the commands to the video front end 2334, which is coupled to the media engine 2337. In at least one embodiment, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post - processing, and a multi - format encode / decode (MFX) 2333 engine for providing hardware - accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2336 and the media engine 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380.

[0410] In at least one embodiment, the graphics processor 2300 includes scalable thread execution resources having graphics cores 2380A-2380N (which may be modular and sometimes referred to as core slices), each graphics core having a plurality of sub-cores 2350A-2350N, 2360A-2360N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2300 may have any number of graphics cores 2380A. In at least one embodiment, the graphics processor 2300 includes a graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, the graphics processor 2300 is a low-power processor having a single sub-core (e.g., 2350A). In at least one embodiment, the graphics processor 2300 includes a plurality of graphics cores 2380A-2380N, each graphics core including a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. In at least one embodiment, each of the first sub-cores 2350A-2350N includes at least a first set of execution units 2352A-2352N and media / texture samplers 2354A-2354N. In at least one embodiment, each of the second sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each of the sub-cores 2350A-2350N, 2360A-2360N shares a set of shared resources 2370A-2370N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0411] The inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 815 are provided herein in connection with Figure 8A and / or Figure 8B In at least one embodiment, the inference and / or training logic 815 may be in the graphics processor 2300 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0412] Figure 24is a block diagram of a microarchitecture for a processor 2400 according to the description of at least one embodiment. The processor 2400 may include logic circuitry for executing instructions. In at least one embodiment, the processor 2400 may execute instructions including x86 instructions, ARM instructions, special instructions for application specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2400 may include registers for storing packed data, such as the 64-bit wide MMXTM registers in the microprocessors enabled with MMX technology by Intel Corporation in Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating-point forms may operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, the 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX or later versions (generally referred to as “SSEx” technology) may hold such packed data operands. In at least one embodiment, the processor 2400 may execute instructions to accelerate machine learning or deep learning algorithms, training or inference.

[0413] In at least one embodiment, the processor 2400 includes an in-order front end (“front end”) 2401 to fetch instructions to be executed and prepare the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2401 may include several units. In at least one embodiment, the instruction prefetcher 2426 fetches instructions from memory and provides the instructions to the instruction decoder 2428, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2428 decodes the received instructions into one or more operations of so-called “microinstructions” or “micro-operations” (also referred to as “micro-ops” or “microinstructions”) that are machine-executable. In at least one embodiment, the instruction decoder 2428 parses the instructions into an opcode and corresponding data and control fields, which may be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 2430 may assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2434 for execution. In at least one embodiment, when the trace cache 2430 encounters a complex instruction, the microcode ROM 2432 provides the microinstructions required to complete the operation.

[0414] In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions may require several micro-operations to complete the entire operation. In at least one embodiment, if more than four microinstructions are required to complete an instruction, the instruction decoder 2428 may access the microcode ROM 2432 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of microinstructions for processing at the instruction decoder 2428. In at least one embodiment, if multiple microinstructions are required to complete the operation, the instruction may be stored in the microcode ROM 2432. In at least one embodiment, the trace cache 2430 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer for reading a microcode sequence from the microcode ROM 2432 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2432 has completed sorting the micro-operations for an instruction, the front end 2401 of the machine may resume fetching micro-operations from the trace cache 2430.

[0415] In at least one embodiment, an out-of-order execution engine (“out-of-order engine”) 2403 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance as the instructions descend down the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2403 includes, but is not limited to, an allocator / register renamer 2440, a memory micro-instruction queue 2442, an integer / floating-point micro-instruction queue 2444, a memory scheduler 2446, a fast scheduler 2402, a slow / general floating-point scheduler (“slow / general FP scheduler”) 2404, and a simple floating-point scheduler (“simple FP scheduler”) 2406. In at least one embodiment, the fast scheduler 2402, the slow / general floating-point scheduler 2404, and the simple floating-point scheduler 2406 are also collectively referred to as “micro-instruction schedulers 2402, 2404, 2406”. In at least one embodiment, the allocator / register renamer 2440 allocates the machine buffers and resources required for each micro-instruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2440 renames logical registers to entries in the register file. In at least one embodiment, the allocator / register renamer 2440 also allocates entries for each micro-instruction in one of two micro-instruction queues, the memory micro-instruction queue 2442 for memory operations and the integer / floating-point micro-instruction queue 2444 for non-memory operations, in front of the memory scheduler 2446 and the micro-instruction schedulers 2402, 2404, 2406. In at least one embodiment, the micro-instruction schedulers 2402, 2404, 2406 determine when a micro-instruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of execution resources micro-instructions that need to be completed. The fast scheduler 2402 of at least one embodiment may be scheduled on each half of the main clock cycle, while the slow / general floating-point scheduler 2404 and the simple floating-point scheduler 2406 may be scheduled once per main processor clock cycle. In at least one embodiment, the micro-instruction schedulers 2402, 2404, 2406 arbitrate the scheduling ports to schedule micro-instructions for execution.

[0416] In at least one embodiment, execution block 2411 includes, but is not limited to, integer register file / branch network 2408, floating-point register file / branch network (“FP register file / branch network”) 2410, address generation units (“AGU”) 2412 and 2414, fast arithmetic logic units (“fast ALU”) 2416 and 2418, slow arithmetic logic unit (“slow ALU”) 2420, floating-point ALU (“FP”) 2422, and floating-point move unit (“FP move”) 2424. In at least one embodiment, integer register file / branch network 2408 and floating-point register file / bypass network 2410 are also referred to herein as “register files 2408, 2410”. In at least one embodiment, AGU 2412 and 2414, fast ALU 2416 and 2418, slow ALU 2420, floating-point ALU 2422, and floating-point move unit 2424 are also referred to herein as “execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424”. In at least one embodiment, execution block 2411 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0417] In at least one embodiment, register networks 2408, 2410 may be arranged between microinstruction schedulers 2402, 2404, 2406 and execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424. In at least one embodiment, integer register file / branch network 2408 performs integer operations. In at least one embodiment, floating-point register file / branch network 2410 performs floating-point operations. In at least one embodiment, each of register networks 2408, 2410 may include, but is not limited to, a branch network that may bypass or forward a just-completed result that has not yet been written to the register file to a new dependent. In at least one embodiment, register networks 2408, 2410 may communicate data with each other. In at least one embodiment, integer register file / branch network 2408 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating-point register file / branch network 2410 may include, but is not limited to, 128-bit-wide entries since floating-point instructions typically have operands with widths of 64 to 128 bits.

[0418] In at least one embodiment, execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424 may execute instructions. In at least one embodiment, register networks 2408, 2410 store integer and floating-point data operand values that the microinstructions need to execute. In at least one embodiment, processor 2400 may include, but is not limited to, any number of execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424 and their combinations. In at least one embodiment, floating-point ALU 2422 and floating-point move unit 2424 may execute floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2422 may include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, instructions involving floating-point values may be processed by floating-point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2416, 2418. In at least one embodiment, fast ALUs 2416, 2418 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations enter slow ALU 2420 because slow ALU 2420 may include, but is not limited to, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by AGUs 2412, 2414. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 may be implemented to support various data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating-point ALU 2422 and floating-point move unit 2424 may be implemented to support a certain range of operands with various widths of bits, for example, may operate on 128-bit wide packed data operands in combination with SIMD and multimedia instructions.

[0419] In at least one embodiment, the microinstruction schedulers 2402, 2404, 2406 schedule dependent operations before the completion of the execution of the parent load. In at least one embodiment, since microinstructions can be scheduled and executed speculatively in the processor 2400, the processor 2400 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be dependent operations running in the pipeline that leave the scheduler temporarily without the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that used incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0420] In at least one embodiment, a "register" may refer to an on-board processor storage location that can be part of an instruction that serves to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from the programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuitry. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques by circuitry within the processor, such as dedicated physical registers, physical registers dynamically allocated using register renaming, combinations of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also contains eight multimedia SIMD registers for encapsulating data.

[0421] Inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 815 are provided herein in connection with Figure 8A and / or Figure 8B and / or. In at least one embodiment, part or all of the inference and / or training logic 815 may be incorporated into execution block 2411 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2411. Additionally, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), and the registers and / or register configuration the ALUs of execution block 2411 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0422] Figure 25Shown is a deep learning application processor 2500 according to at least one embodiment. In at least one embodiment, the deep learning application processor 2500 uses instructions which, if executed by the deep learning application processor 2500, cause the deep learning application processor 2500 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2500 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2500 performs matrix multiplication operations or is “hardwired” into the hardware as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2500 includes, but is not limited to, processing clusters 2510(1)-2510(12), inter-chip links (“ICL”) 2520(1)-2520(12), inter-chip controllers (“ICC”) 2530(1)-2530(2), second generation high bandwidth memories (“HBM2”) 2540(1)-2540(4), memory controllers (“Mem Ctrlr”) 2542(1)-2542(4), high bandwidth memory physical layers (“HBM PHY”) 2544(1)-2544(4), management controller central processing units (“management controller CPU”) 2550, serial peripheral interfaces, inter-integrated circuits and general purpose input / output blocks (“SPI, I2C, GPIO”) 2560, peripheral component interconnect express controllers and direct memory access blocks (“PCIe controllers and DMA”) 2570, and sixteen-channel peripheral component interconnect express ports (“PCI Express x16”) 2580.

[0423] In at least one embodiment, the processing clusters 2510 may perform deep learning operations, including inference or prediction operations based on weight parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2510 may include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2500 may include any number and type of processing clusters 2500. In at least one embodiment, the inter-chip link 2520 is bi-directional. In at least one embodiment, the inter-chip link 2520 and the inter-chip controller 2530 enable multiple deep learning application processors 2500 to exchange information, including activation information resulting from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2500 may include any number (including zero) and type of ICL 2520 and ICC 2530.

[0424] In at least one embodiment, the HBM2 2540 provides a total of 32 GB of memory. In at least one embodiment, the HBM2 2540(i) is associated with both a memory controller 2542(i) and an HBM PHY 2544(i), where "i" is any integer. In at least one embodiment, any number of HBM2 2540s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2542 and HBM PHYs 2544. In at least one embodiment, any number and type of blocks can replace the SPI, I2C, GPIO 3360, PCIe controller 2560, and DMA 2570 and / or PCIe 2580 to implement any number and type of communication standards in any technically feasible manner.

[0425] The inference and / or training logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 815 are provided herein in connection with Figure 8A and / or Figure 8B In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2500. In at least one embodiment, the deep learning application processor 2500 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2500. In at least one embodiment, the processor 2500 can be used to execute one or more of the neural network use cases described herein. In at least one embodiment, the processor 2500 can be used to perform Figure 1 media optimization during playback.

[0426] Figure 26is a block diagram of a neuromorphic processor 2600 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2600 may receive one or more inputs from a source external to the neuromorphic processor 2600. In at least one embodiment, these inputs may be transmitted to one or more neurons 2602 within the neuromorphic processor 2600. In at least one embodiment, the neurons 2602 and their components may be implemented using circuitry or logic that includes one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2600 may include, but is not limited to, thousands of instances of neurons 2602, but any suitable number of neurons 2602 may be used. In at least one embodiment, each instance of a neuron 2602 may include a neuron input 2604 and a neuron output 2606. In at least one embodiment, the neurons 2602 may generate outputs that may be transmitted as inputs to other instances of the neurons 2602. In at least one embodiment, the neuron inputs 2604 and the neuron outputs 2606 may be interconnected via synapses 2608.

[0427] In at least one embodiment, neurons 2602 and synapses 2608 may be interconnected such that neuromorphic processor 2600 operates to process or analyze information received by neuromorphic processor 2600. In at least one embodiment, a neuron 2602 may send an output pulse (or "fire" or "spike") when an input received via neuron input 2604 exceeds a threshold. In at least one embodiment, a neuron 2602 may sum or integrate signals received at neuron input 2604. For example, in at least one embodiment, a neuron 2602 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as "membrane potential") exceeds a threshold, the neuron 2602 may use a transfer function such as a sigmoid or threshold function to produce an output (or "fire"). In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron input 2604 into a membrane potential and may apply an exponential decay factor (or leak) to decrease the membrane potential. In at least one embodiment, if multiple input signals are received at neuron input 2604 fast enough to exceed the threshold (i.e., before the membrane potential decays too low to fire), the leaky integrate-and-fire neuron may fire. In at least one embodiment, a neuron 2602 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Additionally, in at least one embodiment, a neuron 2602 may include, but is not limited to, comparator circuitry or logic that produces an output spike at neuron output 2606 when the result of applying a transfer function to neuron input 2604 exceeds a threshold. In at least one embodiment, once a neuron 2602 fires, it may ignore previously received input information, for example, by resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, the neuron 2602 may resume normal operation after a suitable period of time (or refractory period).

[0428] In at least one embodiment, neurons 2602 may be interconnected by synapses 2608. In at least one embodiment, synapses 2608 may operate to transmit a signal from the output of a first neuron 2602 to the input of a second neuron 2602. In at least one embodiment, a neuron 2602 may transmit information over more than one instance of synapses 2608. In at least one embodiment, one or more instances of neuron outputs 2606 may be connected to instances of neuron inputs 2604 in the same neuron 2602 by instances of synapses 2608. In at least one embodiment, an instance of neuron 2602 that produces an output to be transmitted over an instance of synapse 2608 may be referred to as a "presynaptic neuron" relative to that instance of synapse 2608. In at least one embodiment, an instance of neuron 2602 that receives an input transmitted over an instance of synapse 2608 may be referred to as a "postsynaptic neuron" relative to that instance of synapse 2608. In at least one embodiment, with respect to various instances of synapses 2608, since an instance of neuron 2602 may receive inputs from one or more instances of synapses 2608 and may also transmit outputs over one or more instances of synapses 2608, a single instance of neuron 2602 may be both a "presynaptic neuron" and a "postsynaptic neuron".

[0429] In at least one embodiment, neurons 2602 may be organized into one or more layers. In at least one embodiment, each instance of neuron 2602 may have a neuron output 2606 that may fan out through one or more synapses 2608 to one or more neuron inputs 2604. In at least one embodiment, the neuron output 2606 of neurons 2602 in the first layer 2610 may be connected to the neuron inputs 2604 of neurons 2602 in the second layer 2612. In at least one embodiment, layer 2610 may be referred to as a "feedforward layer". In at least one embodiment, each instance of neuron 2602 in an instance of the first layer 2610 may fan out to each instance of neuron 2602 in the second layer 2612. In at least one embodiment, the first layer 2610 may be referred to as a "fully connected feedforward layer". In at least one embodiment, each instance of neuron 2602 in each instance of the second layer 2612 fans out to fewer than all instances of neuron 2602 in the third layer 2614. In at least one embodiment, the second layer 2612 may be referred to as a "sparsely connected feedforward layer". In at least one embodiment, neurons 2602 in the second layer 2612 may fan out to neurons 2602 in multiple other layers, including also fanning out to neurons 2602 in the second layer 2612. In at least one embodiment, the second layer 2612 may be referred to as a "recurrent layer". In at least one embodiment, the neuromorphic processor 2600 may include any suitable combination of, but not limited to, recurrent layers and feedforward layers, including but not limited to sparsely connected feedforward layers and fully connected feedforward layers.

[0430] In at least one embodiment, the neuromorphic processor 2600 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnections to connect synapses 2608 to neurons 2602. In at least one embodiment, the neuromorphic processor 2600 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2602 as needed, based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2608 may be connected to neurons 2602 using an interconnect structure such as a network-on-chip or through dedicated connections. In at least one embodiment, circuitry or logic may be used to implement the synapse interconnections and their components.

[0431] Figure 27A processing system according to at least one embodiment is shown. In at least one embodiment, system 2700 includes one or more processors 2702 and one or more graphics processors 2708, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2702 or processor cores 2707. In at least one embodiment, system 2700 is a processing platform integrated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0432] In at least one embodiment, system 2700 can be included in or incorporated into a server-based gaming platform, including a game console such as a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, system 2700 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 2700 can also be coupled to or integrated within a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2700 is a television or set-top box device having one or more processors 2702 and a graphical interface generated by one or more graphics processors 2708.

[0433] In at least one embodiment, each of the one or more processors 2702 includes one or more processor cores 2707 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2707 is configured to process a specific instruction sequence 2709. In at least one embodiment, the instruction sequence 2709 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction word (VLIW). In at least one embodiment, the processor cores 2707 can each process different instruction sequences 2709, which can include instructions that help to emulate other instruction sequences. In at least one embodiment, the processor cores 2707 can also include other processing devices, such as a digital signal processor (DSP).

[0434] In at least one embodiment, the processor 2702 includes a cache memory 2704. In at least one embodiment, the processor 2702 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among the various components of the processor 2702. In at least one embodiment, the processor 2702 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), and the external cache can be shared among the processor cores 2707 using known cache coherence techniques. In at least one embodiment, the processor 2702 further includes a register file 2706, and the processor may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). In at least one embodiment, the register file 2706 may include general-purpose registers or other registers.

[0435] In at least one embodiment, one or more processors 2702 are coupled to one or more interface buses 2710 to transfer communication signals, such as address, data, or control signals, between the processor 2702 and other components in the system 2700. In at least one embodiment, the interface bus 2710 may be a processor bus, such as a version of the direct media interface (DMI) bus, in one embodiment. In at least one embodiment, the interface bus 2710 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2702 includes an integrated memory controller 2716 and a platform controller hub 2730. In at least one embodiment, the memory controller 2716 facilitates communication between the memory device and other components of the processing system 2700, while the platform controller hub (PCH) 2730 provides connections to input / output (I / O) devices via a local I / O bus.

[0436] In at least one embodiment, the memory device 2720 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or have suitable performance to be used as a processor memory. In at least one embodiment, the storage device 2720 may be used as the system memory of the processing system 2700 to store data 2722 and instructions 2721 for use when one or more processors 2702 execute an application or process. In at least one embodiment, the memory controller 2716 is also coupled to an optional external graphics processor 2712, which may communicate with one or more of the graphics processors 2708 in the processor 2702 to perform graphics and media operations. In at least one embodiment, the display device 2711 may be connected to the processor 2702. In at least one embodiment, the display device 2711 may include one or more of internal display devices, such as in a mobile electronic device or a laptop device or an external display device connected through a display interface (such as DisplayPort, etc.). In at least one embodiment, the display device 2711 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) applications or augmented reality (AR) applications.

[0437] In at least one embodiment, the platform controller hub 2730 enables peripheral devices to be connected to the storage device 2720 and the processor 2702 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2746, a network controller 2734, a firmware interface 2728, a wireless transceiver 2726, a touch sensor 2725, and a data storage device 2724 (e.g., a hard disk drive, a flash memory, etc.). In at least one embodiment, the data storage device 2724 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2725 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2726 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2728 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 2734 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2710. In at le...

Claims

1. A processor, comprising: One or more circuits for interpreting the speech at least in part based on the content of the speech and one or more audible features of the environment of one or more listeners using one or more neural networks; Wherein: A first neural network among the one or more neural networks is used to generate text data from the content of the speech; A second neural network among the one or more neural networks is used to determine context information about the text data; A third neural network among the one or more neural networks determines confidence information at least in part based on the one or more audible features of the environment of the one or more listeners; and The one or more neural networks are further used to determine an adjustment value at least in part based on the context information and the confidence information; Wherein interpreting the speech includes adjusting the playback of the speech in the environment of the one or more listeners.

2. The processor according to claim 1, wherein the confidence information is further determined by the third neural network at least in part based on the geographical location of the one or more listeners.

3. The processor according to claim 1, wherein the confidence information is further determined by the third neural network at least in part based on the regional accent applied to the speech.

4. The processor according to claim 1, wherein the adjustment value indicates whether the speech is to be slowed down or sped up.

5. The processor according to claim 1, wherein the adjustment value indicates whether the volume associated with the speech is to be increased or decreased.

6. The processor according to claim 1, wherein the context information includes one or more categories of each item in the text data.

7. The processor according to claim 6, wherein the context information is generated by the second neural network, and the second neural network includes one or more bidirectional encoder representations (BERT) networks from transformers.

8. The processor according to claim 1, wherein the speech is from the playback of one or more audio or video data items.

9. The processor according to claim 1, wherein the speech is interpreted for the one or more listeners.

10. A system, comprising: One or more processors for interpreting the speech at least in part based on the content of the speech and one or more audible features of the environment of one or more listeners using one or more neural networks; Wherein: Text data is generated from the speech by a speech-to-text neural network; and Based at least in part on the text data, an adjustment to a playback device is determined according to a confidence measure calculated from the one or more audible features of the environment of the one or more listeners and one or more context values calculated by a bidirectional encoder representation (BERT) network from transformers; Wherein interpreting the speech includes adjusting the playback of the speech in the environment of the one or more listeners.

11. The system according to claim 10, wherein the confidence metric is further calculated at least in part based on whether the language used in the speech is different from the native language of the one or more listeners.

12. The system according to claim 10, wherein the confidence metric is further calculated at least in part based on the geographical location of the one or more listeners.

13. The system according to claim 10, wherein the adjustment indicates whether the speech is to be turned down or up.

14. The system according to claim 10, wherein the one or more context values calculated by the BERT network indicate whether a first portion of the text data is relevant to a second portion of the text data.

15. The system according to claim 10, wherein the speech-to-text neural network further generates speech-to-text confidence.

16. The system according to claim 15, wherein the confidence metric is further calculated at least in part based on the speech-to-text confidence.

17. A machine-readable medium having a set of instructions stored thereon, which if executed by one or more processors, cause the one or more processors to at least: train one or more neural networks to interpret the speech at least in part based on the content of the speech and one or more audible features of the environment of the one or more listeners, Among them, the set of instructions, if executed by the one or more processors, further cause the one or more processors to: train a first neural network of the one or more neural networks to generate text data from the content of the speech; train a second neural network of the one or more neural networks to calculate context information regarding the text data; train a third neural network of the one or more neural networks to calculate a confidence metric at least in part based on the one or more audible features of the environment of the one or more listeners; and train a fourth neural network of the one or more neural networks to determine an adjustment indicator at least in part based on the context information and the confidence metric, wherein interpreting the speech includes adjusting the playback of the speech in the environment of the one or more listeners.

18. The machine-readable medium according to claim 17, wherein the third neural network is further trained to calculate the confidence metric at least in part based on a regional accent imposed on the speech.

19. The machine-readable medium according to claim 17, wherein the adjustment indicator indicates whether the speech is to be slowed down or accelerated.

20. The machine-readable medium according to claim 17, wherein the adjustment indicator indicates whether the volume associated with the speech is to be increased or decreased.

21. The machine-readable medium according to claim 17, wherein: the second neural network includes a Bidirectional Encoder Representations from Transformers (BERT) network; and the context information includes one or more categories of each item in the text data.

22. The machine-readable medium according to claim 17, wherein the voice is from the playback of one or more media items.

23. A method, comprising: using one or more neural networks to interpret the voice based at least in part on the content of the voice and one or more audible features of the environment of one or more listeners; the method further comprising: using a first neural network of the one or more neural networks to generate text data from the content of the voice; using a second neural network of the one or more neural networks to infer one or more context values regarding the text data, the second neural network comprising a Bidirectional Encoder Representations from Transformers (BERT) network; using a third neural network of the one or more neural networks to infer a confidence value based at least in part on the one or more audible features of the environment of the one or more listeners; and determining an adjustment value based at least in part on the one or more context values and the confidence value, wherein interpreting the voice comprises adjusting the playback of the voice in the environment of the one or more listeners.

24. The method according to claim 23, wherein the confidence value is inferred by the third neural network based at least in part on one or more additional inputs, the one or more additional inputs including at least a regional accent used by the one or more listeners.

25. The method according to claim 23, wherein the one or more context values inferred by the second neural network indicate whether a first portion of the text data and a second portion of the text data share a similar context.

26. The method according to claim 23, wherein the adjustment value indicates whether the voice is to be slowed down or sped up.

27. The method according to claim 26, wherein the adjustment value further indicates whether the volume associated with the voice is to be increased or decreased.

28. The method according to claim 23, wherein the voice is from the playback of one or more audio or video data items.

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