Methods for fabricating semiconductor packages, semiconductor packages and embedded PCB modules

Abstract

A method for fabricating a semiconductor package includes: providing a semiconductor wafer including a first side and an opposite second side, the semiconductor wafer being disposed on the first carrier such that the second side of the semiconductor wafer faces the carrier; masking a slit line on the first side of the semiconductor wafer using a mask; depositing a first metal layer on the masked first side of the semiconductor wafer by cold spraying, high-velocity oxygen fuel spraying, or cold plasma-assisted deposition such that the first metal layer does not cover the slit line, the deposited first metal layer having a thickness of 50 μm or greater; individually dicing the semiconductor wafer into a plurality of semiconductor dies by sawing the semiconductor wafer along the slit line; and encapsulating the plurality of semiconductor dies with an encapsulation material such that the first metal layer is exposed on the first side of the encapsulation material.

Description

Technical Field

[0001] This disclosure generally relates to a method for manufacturing a semiconductor package, a semiconductor package, and an embedded PCB module. Background Technology

[0002] Semiconductor packages, particularly power semiconductor packages, may include one or more metal layers disposed on the front and / or back sides of a semiconductor die. These metal layers may have relatively high thicknesses to improve the conductivity and / or heat dissipation capabilities of the semiconductor package. However, providing these thick metal layers can increase the overall cost and / or fabrication time of the semiconductor package. Furthermore, semiconductor wafer warpage, planarity requirements, processing tolerances, and slow soldering processes can all be problematic. Improved methods for fabricating semiconductor packages, improved semiconductor packages, and improved embedded PCB modules can help address these and other issues. Summary of the Invention

[0003] Several aspects relate to a method for fabricating a semiconductor package, the method comprising: providing a semiconductor wafer including a first side and an opposite second side, the semiconductor wafer being disposed on the first carrier such that the second side of the semiconductor wafer faces the carrier; masking a slit line on the first side of the semiconductor wafer using a mask; depositing a first metal layer on the masked first side of the semiconductor wafer by cold spraying or high-velocity oxygen fuel spraying or by cold plasma-assisted deposition such that the first metal layer does not cover the slit line, the deposited first metal layer having a thickness of 50 μm or greater; individually dicing the semiconductor wafer into a plurality of semiconductor dies by sawing the semiconductor wafer along the slit line; and encapsulating the plurality of semiconductor dies with an encapsulation material such that the first metal layer is exposed on the first side of the encapsulation material.

[0004] Several aspects relate to a semiconductor package comprising: a semiconductor die including a first side and an opposite second side; a seed layer deposited on the first side of the semiconductor die; a first metal layer deposited on the seed layer; and an encapsulation material encapsulating the semiconductor die, wherein the first metal layer is exposed on the first side of the encapsulation material, the first metal layer has a different crystal structure from the seed layer, and the first metal layer has a thickness of at least 50 μm measured perpendicular to the first side of the semiconductor die. Attached Figure Description

[0005] The accompanying drawings illustrate examples and, together with the specification, serve to explain the principles of this disclosure. Other examples and numerous anticipated advantages of this disclosure will be readily understood, as they become even more apparent with reference to the following detailed description. The elements in the drawings are not necessarily to scale relative to each other. Identical or similar reference numerals denote corresponding identical or similar parts.

[0006] Figure 1 A cross-sectional view of a semiconductor package is shown, which includes a relatively thick metal layer on the first side of a semiconductor die.

[0007] Figure 2 A cross-sectional view of a semiconductor package is shown, comprising relatively thick metal layers on two opposite sides of a semiconductor die.

[0008] Figure 3 A cross-sectional view of the embedded PCB module is shown.

[0009] Figures 4A to 4G A cross-sectional view of a semiconductor package is shown at various manufacturing stages according to a method for manufacturing a semiconductor package.

[0010] Figure 5 A top-down view is shown of a semiconductor wafer and a shadow mask arranged on the semiconductor wafer.

[0011] Figure 6 An apparatus for depositing a metal layer by applying a cold gas spraying technique is illustrated schematically.

[0012] Figure 7 The illustration schematically shows a supersonic nozzle that provides an airflow including particles to be deposited on a target.

[0013] Figure 8 This is a flowchart of an example method for fabricating a semiconductor package. Detailed Implementation

[0014] With regard to the terms “comprising,” “having,” “with,” or other variations thereof used in the detailed description or claims, these terms are intended to indicate inclusion in a manner similar to the term “comprising.” The terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, whether they are in direct physical or electrical contact, or whether they are not in direct contact with each other; an intermediary element or intermediary layer may be provided between elements that are “joined,” “attached,” or “connected.” However, elements that are “joined,” “attached,” or “connected” may also be in direct contact with each other. Furthermore, the term “exemplary” is merely meant as an example, not as the best or optimal.

[0015] The examples of semiconductor packages described below can use various types of semiconductor dies or circuits incorporated in semiconductor dies, such as AC / DC or DC / DC converter circuits, power MOS transistors, power Schottky diodes, JFETs (Junction Gate Field Effect Transistors), power bipolar transistors, logic integrated circuits, analog integrated circuits, power integrated circuits, chips with integrated passive components, etc.

[0016] Semiconductor dies can be made from specific semiconductor materials such as Si, SiC, SiGe, GaAs, GaN or any other semiconductor material. In addition, they can contain one or more inorganic and organic materials that are not semiconductors, such as insulators, plastics or metals.

[0017] The semiconductor package described below may include one or more semiconductor dies. For example, it may include one or more semiconductor power dies. Furthermore, one or more logic integrated circuits may be included in the semiconductor package. The logic integrated circuits may be configured to control other semiconductor dies, such as power semiconductor dies. The logic integrated circuits may be implemented as logic dies.

[0018] Figure 1 A cross-sectional view of a semiconductor package 100 is shown, comprising a semiconductor die 110, a seed layer 120, a first metal layer 130, and an encapsulation material 140.

[0019] Semiconductor die 110 includes a first side 111 and an opposite second side 112. A seed layer 120 is deposited on the first side 111 of the semiconductor die 110. A first metal layer 130 is deposited on the seed layer 120. An encapsulating material 140 encapsulates the semiconductor die 110 such that the first metal layer 130 is exposed on the first side 141 of the encapsulating material 140.

[0020] The first metal layer 130 differs from the seed layer 120 at least in that it has a different crystal structure from the seed layer 120.

[0021] Semiconductor die 110 may be, for example, a power semiconductor die configured to operate at high voltage and / or high current. Semiconductor die 110 may include, for example, a first load electrode (e.g., source electrode, drain electrode, emitter electrode, or collector electrode) located on its first side 111 and a second load electrode located on its second side 112. Semiconductor die 110 may also include a control electrode (e.g., gate electrode) located on its first side 111 or on its second side 112.

[0022] The semiconductor die 110 can have any suitable dimensions, for example, the length and width (measured in the plane of the first side 111) are in the range of 2 mm to 2 cm, for example, about 5 mm. The semiconductor die 110 can have a thickness (measured perpendicular to the first side 111) in the range of 50 μm to 800 μm, for example.

[0023] The seed layer 120 can be disposed on the electrodes of the semiconductor die, such as on the load electrode or the control electrode. The seed layer 120 and the first metal layer 130 can be configured as electrical contacts for the respective electrodes of the semiconductor die 110.

[0024] According to one example, seed layer 120 may include or be composed of Al, Cu, or Fe, or any other suitable metal or metal alloy. Seed layer 120 may include a single layer or a stack of layers composed of different metal layers. Seed layer 120 may be configured to act as an anchor for depositing first metal layer 130. Seed layer 120 may have a thickness in the micrometer range, for example, in the range of 1 μm to 20 μm, particularly about 10 μm.

[0025] The seed layer 120 can be deposited on the semiconductor die 110, for example, by electroplating, by vapor deposition, by sputtering, or by any other suitable technique. According to one example, the seed layer 120 is disposed directly on the semiconductor die 110. According to another example, one or more additional metal layers can be disposed between the semiconductor die 110 and the seed layer. For example, a diffusion barrier layer can be disposed between the seed layer 120 and the semiconductor die 110. The one or more additional metal layers can, for example, comprise or consist of Ti, W, or TiW. The one or more additional metal layers can, for example, have a thickness in the nanometer range, for example, in the range of 50 nm to 500 nm.

[0026] Seed layer 120 can completely cover the first side 111 of semiconductor die 110. However, it is also possible that only a portion of the first side 111 is covered by seed layer 120, for example, as shown below. Figure 1 As shown. Seed layer 120 can be an unstructured (homogeneous) layer, or it can be a structured layer (seed layer 120 can be structured, for example, by etching or laser ablation). For example, seed layer 120 can be structured such that it does not cover the edge of semiconductor die 110, or a first portion of seed layer 120 covers the load electrode and a second portion of seed layer 120 spaced apart from the first portion covers the control electrode.

[0027] According to one example, the first metal layer 130 comprises or is composed of Cu, Fe, Al, or any other suitable metal or metal alloy. The first metal layer 130 may completely cover the seed layer 120. The first metal layer 130 may be disposed directly on the seed layer 120; in other words, no additional layer may be disposed between the seed layer 120 and the first metal layer 130.

[0028] The first metal layer 130 can be deposited on the seed layer, for example, using techniques including cold spraying, high-velocity oxygen fuel spraying, or cold plasma-assisted deposition. These deposition techniques can include accelerating solid (powder) particles of the material forming the first metal layer 130 toward the seed layer 120. The accelerated particles can impact the seed layer 120, undergoing plastic deformation and adhering to it. Therefore, the first metal layer 130 can have a granular microstructure. Furthermore, these particles can aggregate to form structures much more stable than those achievable using, for example, sintering processes. If a sintering process were used instead, the bonds between the particles in the metal layer might be looser, potentially leading to greater brittleness of the metal layer and requiring additional processing to achieve sufficient stability, thus increasing fabrication time and cost.

[0029] Particle impact can deform the surface of the seed layer 120. For example, the seed layer 120 may have a substantially flat surface before the deposition of the first metal layer 130. However, impacting particles can produce a surface with a roughness of, for example, several micrometers. Since the particles forming the first metal layer 130 may not necessarily be accelerated onto the seed layer 120 in a uniform spatial distribution, the seed layer 120 may be affected to varying degrees (i.e., at different depths) across its entire surface.

[0030] In the semiconductor package 100, the first metal layer 130 has a thickness of at least 50 μm measured perpendicular to a first side 111 of the semiconductor die 110. The first metal layer 130 may have any thickness, such as about 50 μm or more, about 100 μm or more, about 200 μm or more, about 500 μm or more, or about 1 mm or more.

[0031] Deposition methods such as cold spraying, high-velocity oxygen fuel spraying, or cold plasma-assisted deposition can allow for the fabrication of layers much thicker than, for example, electroplating or sputtering, with reasonable process time and cost. For at least this reason, using such deposition techniques to fabricate a relatively thick first metal layer 130 may be advantageous. Furthermore, using such deposition techniques to fabricate the first metal layer 130 can also offer certain advantages compared to, for example, fabricating it by placing a metal sheet on a semiconductor die 110. For example, using a metal sheet can lead to problems with processing tolerances, flatness, and wafer warping.

[0032] The encapsulation material 140 may be, for example, a molded body and may comprise a polymer material. The encapsulation material 140 may be configured to protect the semiconductor die from environmental influences. The encapsulation material 140 may include recesses in which a seed layer 120 and a first metal layer 130 are disposed. The first metal layer 130 may include an outer surface 131 exposed at a first side 141 of the encapsulation material 140. According to one example, the outer surface 131 and the first side 141 may be substantially coplanar. According to another example, the outer surface 131 protrudes from the first side 141. The first metal layer 130 may also include a lateral side 132 that may be covered by the encapsulation material 140.

[0033] According to one example, the encapsulating material 140 at least partially covers the first side 111 of the semiconductor die 110 (i.e., those portions not covered by the seed layer 120 and the first metal layer 130). According to one example, the encapsulating material 140 partially or completely covers the second side 112 of the semiconductor die 110. According to one example, the encapsulating material 140 completely or partially covers the lateral portion of the semiconductor die 110 connecting the first side 111 and the second side 112.

[0034] The semiconductor package 100 may have dimensions only slightly larger than the semiconductor die 110 itself. For example, the semiconductor package may have a length and width in the range of 2 mm to 2 cm, for example, about 5 mm, and a thickness in the range of 100 μm to 1 mm.

[0035] Figure 2 A cross-sectional view of another semiconductor package 200 is shown, which may be similar to or the same as semiconductor package 100, except for the differences described below.

[0036] Semiconductor package 200 may include all the portions described in conjunction with semiconductor package 100, and it also includes a second metal layer 150. The second metal layer 150 may be similar to or the same as the first metal layer 130. The second metal layer 150 may be disposed on a second side 112 of the semiconductor die opposite to the first metal layer 130.

[0037] The semiconductor package 200 may further include a second seed layer 160 disposed on a second side 112 of the semiconductor die 110 between the semiconductor die 110 and the second metal layer 150. The second seed layer 160 may be similar to or the same as the seed layer 120.

[0038] According to one example, the second metal layer 150 comprises the same material or material composition as the first metal layer 130. According to another example, the first and second metal layers 130, 150 comprise different materials or material compositions. The second metal layer 150 can be fabricated using the same deposition technique as the first metal layer 130. The first and second metal layers 130, 150 can have substantially the same thickness, or they can have different thicknesses.

[0039] According to one example, the second metal layer 150 can be structured. Figure 2 In the example shown, the second metal layer 150 is structured such that a first portion 151 is disposed, for example, over a load or power electrode of the semiconductor die 110, and a second portion 152 is disposed, for example, over a control electrode of the semiconductor die 110. The first and second portions 151, 152 may be spaced apart from each other by a gap 170. The gap 170 may be filled with an encapsulating material 140.

[0040] The second metal layer 150 may include an outer surface 153 that may be exposed on a second side 142 of the encapsulating material opposite to the first side 141. According to one example, the outer surface 153 and the second side 142 may be substantially coplanar. According to another example, the outer surface 153 protrudes from the second side 142.

[0041] The second seed layer 160 and the second metal layer 150 can be fabricated using the same techniques as the seed layer 120 and the first metal layer 130. According to one example, arranging the first and second metal layers 130, 150 on opposite first and second sides 111, 112 of the semiconductor die 110 can help prevent wafer warping. According to one example, the first and second metal layers 130, 150, as well as the seed layer 120 and the second seed layer 160, can be configured to provide electrical connections to the semiconductor die 110 with low resistance and thermal resistance.

[0042] As an example, semiconductor packages 100 and 200 can be embedded in a printed circuit board (PCB) module. Such embedded modules can advantageously have a smaller form factor than other types of modules.

[0043] Figure 3 A cross-sectional view of an embedded PCB module 300 is shown, including a substrate 310, an additional layer 320, and a semiconductor package 100. According to another example, the embedded PCB module 300 includes the semiconductor package 100 instead of the semiconductor package 200.

[0044] According to one example, substrate 310 is electrically insulating, for example, due to an electrically insulating surface treatment. According to another example, substrate 310 is conductive. Substrate 310 may comprise or be composed of, for example, Al, Cu, or Fe. A coupling layer, such as an adhesive, may be disposed between the substrate and the semiconductor package 100. According to one example, substrate 310 may be configured to be disposed on a heat sink configured to dissipate heat from the semiconductor package 100. A thermal interface material (TIM) may be disposed between substrate 310 and the heat sink.

[0045] An additional layer 320 is disposed on the substrate 310. The additional layer 320 may be electrically insulating and may, for example, comprise or consist of a polymer or epoxy resin. According to one example, the additional layer 320 is a prepreg layer. According to another example, the additional layer 320 comprises or consists of a conductive material, such as copper. The semiconductor die 110 may be insulated from the additional layer 320 by an encapsulation material 140. The additional layer 320 includes a cavity 330 in which the semiconductor package 100 is disposed. The additional layer 320 may, for example, have substantially the same thickness as the semiconductor package 100.

[0046] According to one example, the embedded PCB module 300 includes multiple semiconductor packages, which may be identical semiconductor packages or semiconductor packages of different types. An additional layer 320 may include multiple cavities 330, for example, such that each semiconductor package is disposed within a different cavity 330.

[0047] The embedded PCB module 300 also includes a top plate 340 disposed above the additional layer 320 and the semiconductor package 100. The top plate may include an electrically insulating material, such as epoxy resin or a polymer. The top plate 340 may include one or more vias electrically coupled to the semiconductor package 100 (i.e., coupled to the first metal layer 130 and / or the second metal layer 150). The top plate 340 may also include conductive traces coupled to the vias. The top plate 340 may be configured to have one or more semiconductor devices, such as logic chips for controlling the semiconductor package 100, disposed on its surface.

[0048] The embedded PCB module 300 can be, for example, a power electronic module that includes a three-phase driver circuit. Compared to other modules that do not embed semiconductor packages in the manner described above, the embedded PCB module 300 can provide improved electrical and thermal performance, lower thermal resistance, and a reduced form factor.

[0049] Combination Figures 4A to 4G The diagram illustrates a semiconductor package 200 at different fabrication stages according to an example of a method for fabricating a semiconductor package. The semiconductor package 100 can be fabricated in substantially the same manner. However, in this case, it is not necessary to perform the reference process. Figure 4D The described operation.

[0050] Figure 4A A semiconductor wafer 400 is shown, comprising a first side 401 and an opposite second side 402. The semiconductor wafer 400 is disposed on a first carrier 410 such that the second side 402 of the semiconductor wafer 400 faces the first carrier 410. The semiconductor wafer 400 may be, for example, a thin wafer obtained by grinding a thick wafer.

[0051] In one example, the semiconductor wafer 400 is attached to the first carrier 410 via an adhesive foil 420. In another example, the adhesive foil 420 is not used.

[0052] According to one example, seed layer 120 and / or second seed layer 160 are deposited over a first side 401 and a second side 402 of semiconductor wafer 400. Seed layer 120 and / or second seed layer 160 can be deposited, for example, by electroplating or sputtering. Seed layer 120 and / or second seed layer 160 can be... Figure 4A The deposition occurred in the process steps prior to the manufacturing state shown.

[0053] like Figure 4B As shown, a mask or shadow mask 430 is disposed on a first side 401 of the semiconductor wafer 400. The shadow mask 430 is configured to mask the saw lines 440 on the first side 401 of the semiconductor wafer 400. Furthermore, the shadow mask 430 may also be configured to mask the first side 401, such that a first metal layer 130 may be deposited on the semiconductor wafer 400 only on one or more electrodes.

[0054] The shadow mask 430 may include or be composed of any suitable material, such as a material that does not form a weld bond with the material constituting the first metal layer 130. According to one example, the shadow mask 430 may include or be composed of stainless steel. However, the shadow mask 430 may also include or be composed of a material that forms a weld bond with the material constituting the first metal layer 130. In that case, the shadow mask 430 may be a disposable item that is replaced after each use. Figure 4C As shown, the shadow mask 430 can be suspended above the first side 401 of the semiconductor wafer 400 without contacting the first side 401. This helps to avoid damage to the semiconductor wafer 400. However, the shadow mask 430 can also be arranged on the semiconductor wafer 400 such that it contacts the first side 401.

[0055] Based on one example, shade 430 is not as... Figure 4CInstead of being arranged on the semiconductor wafer 400 as shown, the material layer 430 is deposited on a first side 401 of the semiconductor wafer 400 and then structured as described above to cover the saw lines 440. For example, the shadow mask 430 may be a photoresist mask, which can be deposited and structured using any suitable technique known in the art. The shadow mask 430 may include or be composed of ceramic or organic compounds, for example. The materials constituting the first metal layer 130 may not readily adhere to these materials.

[0056] When the first metal layer 130 is deposited, the deposited shadow mask 430 can be removed by grinding. Therefore, the thickness of the deposited shadow mask 430 may need to be adjusted accordingly, for example, so that there is little or no shadow mask 430 residue after the first metal layer 130 has been deposited. For example, the thickness of the deposited shadow mask 430 should be approximately two times, approximately 2.5 times, or approximately three times the thickness of the first metal layer 130. After the first metal layer 130 has been deposited, the shadow mask 430 or any residual portion of the shadow mask 430 can be removed from the first side 401.

[0057] like Figure 4C As shown, a first metal layer 130 is deposited on a masked first side 401 of the semiconductor wafer 400. Due to the presence of the shadow mask 430, no material is deposited on the saw line 440. The first metal layer 130 can be deposited on the first side 401, for example, by cold spraying, high-speed oxygen fuel spraying, or cold plasma-assisted deposition.

[0058] If a semiconductor package, such as semiconductor package 100, is fabricated that includes a deposited metal layer only on the first side 401, then the individualization process can follow the reference... Figure 4C The operation of depositing the first metal layer 130 is described below. However, if a semiconductor package is fabricated comprising deposited metal layers on both the first side 401 and the second side 402, it may be necessary to flip the semiconductor wafer 400 as described below.

[0059] Figure 4D A semiconductor wafer 400 is shown flipped and positioned on a second carrier 450 such that a first side 401 faces the second carrier 450. The second carrier 450 may be similar to or identical to the first carrier 410. (See reference...) Figure 4B As described, the saw cut line 440 above the second side 402 is shaded by a shading 430'.

[0060] According to one example, shadow masks 430 and 430' are the same shadow mask. According to another example, shadow mask 430' is different from shadow mask 430. For example, shadow mask 430' may include additional segments 431 configured to allow deposition of a second metal layer 150 in the form of different portions 151, 152 spaced apart by gaps 170. The second metal layer 150 may be deposited in the same manner as the first metal layer 130.

[0061] According to one example, some material from the second metal layer 150 and / or the second seed layer 160 may be deposited in the gap 170. This excess material can be removed by a dedicated removal process, such as etching or laser ablation, or any other suitable technique.

[0062] like Figure 4E As shown, the semiconductor wafer 400 is individually divided into multiple semiconductor dies 110 by sawing along the saw line 440. Since there is no relatively thick material of the first metal layer 130 and / or the second metal layer 150 arranged above the saw line 440, it may not be necessary to use a special removal process to remove the blocking material at the saw line 440 before individualization.

[0063] like Figure 4F As shown, the film 460 can be disposed on the second metal layer 150 such that it covers the outer surface 153. In the case of fabricating a semiconductor package 100 that does not include the second metal layer 150 on the second side 112 of the semiconductor die 110, the film 460 can alternatively cover the second side 112.

[0064] Subsequently, a molding process can be performed to encapsulate multiple semiconductor dies 110 using encapsulation material 140. A first metal layer 130 is exposed on a first side 141 of the encapsulation material 140, for example, because it is covered by adhesive foil 420. A second metal layer 150 may be exposed on a second side 142 of the encapsulation material 140, for example, because it is covered by film 460.

[0065] According to one example, the molding process can be performed without covering the outer surface 153 of the second metal layer 150 (or the second side 112 of the semiconductor die 110) with the film 460.

[0066] like Figure 4G As shown, the semiconductor package 200 (or semiconductor package 100) can be individually separated from the semiconductor wafer 400 by cutting the encapsulation material 140 along the saw line 440. Furthermore, Figure 4GIt is also shown that the outer surfaces 131, 153 of the first and second metal layers 130, 150 may have at least some degree of unevenness or roughness, for example, because no special planarization process was used to planarize the outer surfaces 131, 153 after deposition. Nevertheless, the outer surfaces 131, 153 may be smooth enough to serve as electrical contacts of the semiconductor package 200.

[0067] According to another example, a planarization process, such as a grinding process, is used to smooth the outer surfaces 131 and 153 for use as electrical contacts.

[0068] Figure 5 As shown Figure 4B The image shows a top-down view of the semiconductor wafer 400 and shadow mask 430. Additionally, the positions of the two exemplary vertical saw lines 440 are shown. Figure 5 The middle is represented by a dashed line.

[0069] Figure 6 An apparatus 600 for applying cold gas spraying (also known as "cold spraying") technology is schematically shown. The apparatus 600 can be used, for example, to deposit a first metal layer 130 and / or a second metal layer 150.

[0070] The apparatus 600 may include a gas control module 610, an electric heater 620, a powder feeder 630, and a supersonic nozzle 640. A working gas, such as N2 or He, may enter the apparatus 600 at the inlet. In the upper processing path, the gas control module 610 may deliver a controlled amount of working gas to the electric heater 620, which may heat the gas. The heated working gas stream may then be delivered to the supersonic nozzle 640. In the lower processing path, the powder feeder 630 may provide solid powder particles of the deposited material to the supersonic nozzle 640. For example, the powder particles may have a diameter from about 1 micrometer to about 50 micrometers. The powder particles may enter the nozzle inlet under high pressure and may be accelerated to velocities up to about 500 m / s to about 1000 m / s in the supersonic gas jet. The gas flow 650, including the powder particles exiting the supersonic nozzle 640, may have a temperature in the range of about 100°C to about 500°C. The gas flow 650 may impinge on a target 660 that may be disposed on a substrate 670.

[0071] Cold plasma spraying (also known as "cold plasma-assisted deposition") technology can be similar to cold gas spraying technology. In cold plasma spraying, the material to be deposited is not accelerated by a supersonic gas jet, but rather receives the kinetic energy required for acceleration from the plasma. In a similar manner, the accelerated deposition material can be provided by a "plasma nozzle".

[0072] Figure 7A supersonic nozzle 700 is schematically shown providing an airflow including particles 710 to be deposited on a target 660. During impact with the target 660, the particles 710 may undergo plastic deformation and adhere to the surface of the target 660. Typically, cold gas spraying can be used to deposit metals, polymers, ceramics, composites, and nanocrystalline powders. The powder used in cold gas spraying does not necessarily melt during the spraying process. In particular, the surface of the material deposited by cold gas spraying technology can have, for example, […]. Figure 7 The surface structure including pits is shown exemplary in the side sectional view.

[0073] Figure 8 This is a flowchart of a method 800 for manufacturing a semiconductor package. For example, method 800 can be used to manufacture semiconductor packages 100 and 200.

[0074] Method 800 includes: in step 801, providing a semiconductor wafer including a first side and an opposite second side, the semiconductor wafer being disposed on a first carrier such that the second side of the semiconductor wafer faces the first carrier; in step 802, masking a slit line on the first side of the semiconductor wafer using a mask; in step 803, depositing a first metal layer on the masked first side of the semiconductor wafer by cold spraying, high-speed oxygen fuel spraying, or cold plasma-assisted deposition such that the first metal layer does not cover the slit line, the deposited first metal layer having a thickness of 50 μm or greater; in step 804, individually dividing the semiconductor wafer into multiple semiconductor dies by sawing the semiconductor wafer along the slit line; and in step 805, encapsulating the multiple semiconductor dies with an encapsulation material such that the first metal layer is exposed on the first side of the encapsulation material.

[0075] Example

[0076] Below, specific examples are used to further describe the methods for fabricating semiconductor packages and semiconductor packages.

[0077] Example 1 is a method for fabricating a semiconductor package, the method comprising: providing a semiconductor wafer including a first side and an opposite second side, the semiconductor wafer being disposed on the first carrier such that the second side of the semiconductor wafer faces the carrier; masking a slit line on the first side of the semiconductor wafer using a mask; depositing a first metal layer on the masked first side of the semiconductor wafer by cold spraying, high-velocity oxygen fuel spraying, or cold plasma-assisted deposition such that the first metal layer does not cover the slit line, the deposited first metal layer having a thickness of 50 μm or greater; individually dicing the semiconductor wafer into a plurality of semiconductor dies by sawing the semiconductor wafer along the slit line; and encapsulating the plurality of semiconductor dies with an encapsulation material such that the first metal layer is exposed on the first side of the encapsulation material.

[0078] Example 2 is the method of Example 1, which further includes: masking a slit line on a second side of a semiconductor wafer; and depositing a second metal layer on the masked second side of the semiconductor wafer by cold spraying, high-speed oxygen fuel spraying, or cold plasma-assisted deposition, such that the second metal layer does not cover the slit line, wherein the plurality of semiconductor dies are encapsulated such that the second metal layer is exposed on a second side of the encapsulation material opposite to the first side.

[0079] Example 3 is the method of Example 2, wherein the second metal layer on the semiconductor die among the plurality of semiconductor dies includes a power contact portion coupled to a power electrode of the semiconductor die and a control contact portion coupled to a control electrode of the semiconductor die.

[0080] Example 4 is a method of Example 2 or 3, the method further comprising: transferring a semiconductor wafer from a first carrier to a second carrier prior to depositing a second metal layer, wherein the semiconductor wafer is disposed on the second carrier such that a first side of the semiconductor wafer faces the second carrier.

[0081] Example 5 is a method of any one of Examples 2 to 4, the method further comprising: covering a first metal layer and / or a second metal layer with a film before encapsulating the plurality of semiconductor dies; and removing the film after encapsulation.

[0082] Example 6 is a method of any of the foregoing examples, the method further comprising: depositing a seed layer on a semiconductor wafer prior to depositing a first metal layer, the seed layer being deposited by electroplating or sputtering.

[0083] Example 7 is a method of any of the foregoing examples, wherein the mask is a shaped part disposed on the semiconductor wafer, or the mask is a deposited and structured layer of organic material.

[0084] Example 8 is a method of any of the preceding examples, wherein the mask is removed before the semiconductor wafer is individually segmented.

[0085] Example 9 is a method of any of the foregoing examples, wherein the first metal layer is not planarized before encapsulating the plurality of semiconductor dies.

[0086] Example 10 is a method of any of the preceding examples, wherein the first metal layer comprises or is composed of Cu.

[0087] Example 11 is a semiconductor package comprising: a semiconductor die including a first side and an opposite second side; a seed layer deposited on the first side of the semiconductor die; a first metal layer deposited on the seed layer; and an encapsulation material encapsulating the semiconductor die, wherein the first metal layer is exposed on the first side of the encapsulation material, the first metal layer has a different crystal structure from the seed layer, and the first metal layer has a thickness of at least 50 μm measured perpendicular to the first side of the semiconductor die.

[0088] Example 12 is a semiconductor package of Example 11, wherein the first metal layer is deposited by cold spraying, high-speed oxygen fuel spraying, or cold plasma-assisted deposition.

[0089] Example 13 is a semiconductor package of Example 11 or 12, wherein the semiconductor package further includes: a second metal layer deposited on a second side of a semiconductor die, wherein the second metal layer is exposed on a second side of the encapsulating material opposite to the first side, and the second metal layer has a thickness of at least 50 μm.

[0090] Example 14 is a semiconductor package of any one of Examples 11 to 13, wherein a first side of the encapsulating material is disposed in a first plane parallel to the first side of the semiconductor die, and a first metal layer extends from the seed layer to the first plane and beyond the first plane.

[0091] Example 15 is a semiconductor package of any one of Examples 11 to 14, wherein the outer surface of the first metal layer has a rough, non-planarized structure.

[0092] Example 16 is an embedded PCB module comprising: a substrate, an additional layer on the substrate including one or more cavities, a semiconductor package according to any one of Examples 11 to 15 embedded in at least one of the cavities, and a top plate.

[0093] Example 17 is an apparatus that includes means for performing the methods of any one of Examples 1 to 10.

[0094] While this disclosure has been described and illustrated in conjunction with one or more embodiments, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, regarding the various functions performed by the aforementioned components or structures (components, devices, circuits, systems, etc.), unless otherwise indicated, the terminology used to describe these components (including references to “device”) is intended to correspond to any component or structure performing the specified function of the described component (e.g., functionally equivalent), even if structurally not equivalent to the disclosed structure performing that function in the exemplary embodiments of this disclosure shown herein.

Claims

1. A method for fabricating a semiconductor package (100), the method comprising: A semiconductor wafer (400) is provided, comprising a first side (401) and an opposite second side (402), the semiconductor wafer (400) being disposed on a first carrier (410) such that the second side (402) of the semiconductor wafer (400) faces the first carrier (410). A mask (430) is used to mask the saw cut lines (440) on the first side (401) of the semiconductor wafer (400). A first metal layer (130) is deposited on the masked first side (401) of a semiconductor wafer (400) by cold spraying, high-speed oxygen fuel spraying, or cold plasma-assisted deposition, such that the first metal layer (130) does not cover the saw line (440), and the deposited first metal layer (130) has a thickness of 50 μm or greater. The semiconductor wafer (400) is individually divided into multiple semiconductor dies (110) by sawing along the saw line (440), and The plurality of semiconductor dies (110) are encapsulated with an encapsulating material (140) such that a first metal layer (130) is exposed on a first side (141) of the encapsulating material (140).

2. The method according to claim 1, wherein, The method further includes: The saw cut lines (440) are masked on the second side (402) of the semiconductor wafer (400), and A second metal layer (150) is deposited on the masked second side (402) of a semiconductor wafer (400) by cold spraying, high-speed oxygen fuel spraying, or cold plasma-assisted deposition, such that the second metal layer (150) does not cover the sawing line (440). The plurality of semiconductor dies (110) are encapsulated such that the second metal layer (150) is exposed on the second side (142) of the encapsulation material (140) opposite to the first side (141) of the encapsulation material.

3. The method according to claim 2, wherein, The second metal layer (150) on the semiconductor die (110) among the plurality of semiconductor dies (110) includes a power contact portion (151) coupled to a power electrode of the semiconductor die (110) and a control contact portion (152) coupled to a control electrode of the semiconductor die (110).

4. The method according to claim 2 or 3, wherein, The method further includes: Before depositing the second metal layer (150), the semiconductor wafer (400) is transferred from the first carrier (410) to the second carrier (450). In this arrangement, a semiconductor wafer (400) is disposed on a second carrier (450) such that a first side (401) of the semiconductor wafer (400) faces the second carrier (450).

5. The method according to claim 2 or 3, wherein, The method further includes: Before encapsulating the plurality of semiconductor dies (110), a first metal layer (130) and / or a second metal layer (150) are covered with a film (460), and Remove the membrane (460) after encapsulation.

6. The method according to any one of claims 1-3, wherein, The method further includes: Before depositing the first metal layer (130), a seed layer (120) is deposited on the semiconductor wafer (400) by electroplating or sputtering.

7. The method according to any one of claims 1-3, wherein, The mask (430) is a shaped part disposed on the semiconductor wafer (400).

8. The method according to any one of claims 1-3, wherein, The mask (430) is a deposited and structured layer of organic material.

9. The method according to any one of claims 1-3, wherein, The mask (430) is removed before the semiconductor wafer (400) is individually diced.

10. The method according to any one of claims 1-3, wherein, The first metal layer (130) is not planarized before encapsulating the plurality of semiconductor dies (110).

11. The method according to any one of claims 1-3, wherein, The first metal layer (130) comprises Cu.

12. A semiconductor package (100), comprising: A semiconductor die (110) comprising a first side (111) and an opposite second side (112), A seed layer (120) is deposited on the first side (111) of the semiconductor die (110). The first metal layer (130) deposited on the seed layer (120), A second metal layer (150) deposited on the second side (111) of the semiconductor die (110), and Encapsulation material (140) for encapsulating semiconductor bare wafer (110), The first metal layer (130) is exposed on the first side (141) of the encapsulating material (140), and the first metal layer (130) and the seed layer (120) have different crystal structures. The first metal layer (130) has a thickness of at least 50 μm, measured perpendicular to a first side (111) of the semiconductor die (110). The second metal layer (150) is exposed on the second side (142) of the encapsulating material (140) opposite to the first side (141) of the encapsulating material, and The second metal layer has a thickness of at least 50 μm.

13. The semiconductor package (100) according to claim 12, wherein, The first metal layer (130) is deposited by cold spraying, high-speed oxygen fuel spraying, or cold plasma-assisted deposition.

14. The semiconductor package (100) according to claim 12 or 13, wherein, The first side (141) of the encapsulating material (140) is arranged in a first plane parallel to the first side (111) of the semiconductor die (110), and the first metal layer (130) extends from the seed layer (120) to the first plane and beyond the first plane.

15. The semiconductor package (100) according to claim 12 or 13, wherein, The outer surface (131) of the first metal layer (130) has a rough, non-planar structure.

16. An embedded PCB module (300), comprising: substrate(310); An additional layer (320) located on the substrate (310) and including at least one cavity (330); Semiconductor packages (100, 200) embedded in the at least one cavity (330); as well as Upper board(340), The semiconductor package includes: A semiconductor die (110) comprising a first side (111) and an opposite second side (112), A seed layer (120) is deposited on the first side (111) of the semiconductor die (110). The first metal layer (130) deposited on the seed layer (120), A second metal layer (150) deposited on the second side (111) of the semiconductor die (110), and Encapsulation material (140) for encapsulating semiconductor bare wafer (110), The first metal layer (130) is exposed on the first side (141) of the encapsulating material (140). The first metal layer (130) and the seed layer (120) have different crystal structures. The first metal layer (130) has a thickness of at least 50 μm, measured perpendicular to a first side (111) of the semiconductor die (110). The second metal layer (150) is exposed on the second side (142) of the encapsulating material (140) opposite to the first side (141) of the encapsulating material, and The second metal layer has a thickness of at least 50 μm.

17. A semiconductor package comprising: A semiconductor die (110) comprising a first side (111) and an opposite second side (112), A seed layer (120) is deposited on the first side (111) of the semiconductor die (110). The first metal layer (130) deposited on the seed layer (120), and Encapsulation material (140) for encapsulating semiconductor bare wafer (110), The first metal layer (130) is exposed on the first side (141) of the encapsulating material (140). The first metal layer (130) and the seed layer (120) have different crystal structures. The first metal layer (130) has a thickness of at least 50 μm, measured perpendicular to a first side (111) of the semiconductor die (110). The first side (141) of the encapsulating material (140) is arranged in a first plane parallel to the first side (111) of the semiconductor die (110), and The first metal layer (130) extends from the seed layer (120) to the first plane and beyond the first plane.

18. The semiconductor package according to claim 17, wherein, The first metal layer (130) is deposited by cold spraying, high-speed oxygen fuel spraying, or cold plasma-assisted deposition.

19. The semiconductor package according to claim 17 or 18, wherein, The semiconductor package further includes: A second metal layer (150) is deposited on the second side (112) of the semiconductor die (110). The second metal layer (150) is exposed on the second side (142) of the encapsulating material (140), opposite to the first side (141) of the encapsulating material. The second metal layer (150) has a thickness of at least 50 μm.

20. The semiconductor package according to claim 17 or 18, wherein, The outer surface (131) of the first metal layer (130) has a rough, non-planar structure.

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