Display device and method of manufacturing a display device

Abstract

A display device and a method of manufacturing the same are disclosed. The display device includes a first substrate having a display area and a non-display area adjacent to the display area, the first substrate including a substrate via penetrating the first substrate in a thickness direction, an etch stopper disposed on a first surface of the first substrate, the etch stopper including a stopper via overlapping the substrate via and penetrating the etch stopper in the thickness direction, a data line disposed on the etch stopper, a substrate connection electrode filling the substrate via and the stopper via, the substrate connection electrode disposed in the display area and electrically connected to the data line, and a first pad disposed on a second surface of the first substrate opposite the first surface and overlapping the substrate connection electrode. The first pad is electrically connected to the substrate connection electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0033223, filed on March 18, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device and a method for manufacturing the display device. Background Technology

[0004] With the development of multimedia technology, display devices have become increasingly important. Therefore, various types of display devices, such as organic light-emitting diode (OLED) devices and liquid crystal display (LCD) devices, are currently in use.

[0005] The display device is used to display images and may include a display panel such as an organic light-emitting display panel or a liquid crystal display panel. The light-emitting display panel may include light-emitting elements. For example, light-emitting diodes (LEDs) may include organic light-emitting diodes (OLEDs) that use organic materials as fluorescent materials and inorganic light-emitting diodes that use inorganic materials as fluorescent materials.

[0006] It should be understood that this background section is partly intended to provide useful context for understanding the art. However, this background section may also include ideas, concepts, or knowledge that were known or understood by one of ordinary skill in the art prior to the corresponding valid submission date of the subject matter disclosed herein. Summary of the Invention

[0007] This disclosure provides a display device in which a driving circuit can be disposed on the back side of a substrate.

[0008] It should be noted that the purpose of this disclosure is not limited to the objectives described above. Other objectives of the invention will be apparent to those skilled in the art from the following description.

[0009] According to embodiments of this disclosure, the driving circuit can be disposed on the back side of the substrate, thereby reducing dead zones.

[0010] According to an embodiment, a display device includes: a first substrate having a display area and a non-display area adjacent to the display area; the first substrate including a substrate through-hole penetrating the first substrate in the thickness direction; an etch stop member disposed on a first surface of the first substrate, the etch stop member including a stop member through-hole overlapping the substrate through-hole and penetrating the etch stop member in the thickness direction; a data line disposed on the etch stop member; a substrate connection electrode filling the substrate through-hole and the stop member through-hole, the substrate connection electrode being disposed in the display area and electrically connected to the data line; and a first pad disposed on a second surface of the first substrate opposite to the first surface and overlapping the substrate connection electrode. The first pad can be electrically connected to the substrate connection electrode.

[0011] The first surface of the first substrate can contact the etching stop element, and the substrate via can be surrounded by the extension line of the second surface of the first substrate, the extension line of the first surface of the first substrate, and the side surface of the first substrate.

[0012] The etching stop may include a first surface that can contact a first surface of the first substrate, and a second surface that can oppose the first surface of the etching stop. The stop via may be surrounded by an extension line of the first surface of the etching stop, an extension line of the second surface of the etching stop, and a side surface of the etching stop. The average slope of the side surface of the etching stop may be greater than the average slope of the side surface of the first substrate.

[0013] The terminating via can overlap with the first surface of the first substrate in the thickness direction.

[0014] The display device may further include a buffer layer disposed on a second surface of an etch stop member and between the etch stop member and the data line. The surface roughness of the buffer layer that contacts the substrate connection electrode may be greater than the surface roughness of the buffer layer that does not contact the substrate connection electrode.

[0015] The display device may further include: a buffer layer disposed on a second surface of an etch stop and between the etch stop and a data line; and an etch residue disposed on the surface of the buffer layer that contacts the substrate connection electrode, wherein the etch residue and the etch stop may be made of the same material.

[0016] The display device may further include: a buffer layer disposed between an etch stop member and a data line; and a first gate insulating layer disposed between the buffer layer and the data line, wherein the data line can be electrically connected to a substrate connection electrode through a data connection electrode that penetrates the first gate insulating layer and the buffer layer in the thickness direction.

[0017] The display device may further include: a connecting line disposed on a second surface of the first substrate, wherein the connecting line can be electrically connected to a first pad, and may include a chip-on-film disposed on the second surface of the first substrate and on which a driver chip is mounted; and a second pad disposed on the second surface of the first substrate, wherein the second pad can be electrically connected to the connecting line, and the chip-on-film can be electrically connected to the second pad.

[0018] The display area may include pixels, each pixel including an emitting area and a non-emitting area disposed adjacent to the emitting area, an outer dam may be disposed on a data line and may be disposed in the non-emitting area, a light-emitting element may be disposed in the emitting area, the emitting area may be adjacent to the outer dam, and the substrate connecting electrode may overlap with the emitting area.

[0019] The display device may further include: a buffer layer disposed between an etch stop member and a data line; a first gate insulating layer disposed between the buffer layer and the data line; a gate connection electrode disposed between the first gate insulating layer and the data line; and a first protective layer disposed between the gate connection electrode and the data line. The data line can be electrically connected to the gate connection electrode via a data connection electrode penetrating the first protective layer, and the gate connection electrode can be electrically connected to a substrate connection electrode via a gate connection electrode penetrating the first gate insulating layer and the buffer layer.

[0020] According to another embodiment, a method of manufacturing a display device may include: forming a plurality of modified regions by irradiating a first mother substrate with a laser, the first mother substrate including a first surface and a second surface opposite to the first surface; forming an etch stop on the first surface of the first mother substrate to cover the plurality of modified regions; disposing a plurality of upper display modules on the etch stop such that each of the plurality of upper display modules overlaps with a corresponding modified region among the plurality of modified regions; and disposing an encapsulation element on the plurality of upper display modules.

[0021] The method may further include: after setting up the packaged components, using a wet etching mask to perform masking on the area other than the second surface of the first mother substrate.

[0022] The method may further include: after performing a masking process, forming a substrate via penetrating the first surface from the second surface of the first mother substrate by etching at each of the plurality of modified regions.

[0023] Etching can include wet etching.

[0024] The method may further include: removing the wet etch mask after forming the substrate vias, and performing cell cutting on each of the plurality of upper display modules.

[0025] The method may further include: after the execution unit is cut, forming a termination via that penetrates the etch termination in the portion that overlaps with the substrate via.

[0026] The method may further include: after forming the terminating via, forming a substrate connection electrode to fill the substrate via and the terminating via; and after forming the substrate connection electrode, forming a first pad. The first pad may overlap with the substrate connection electrode and may be disposed on a second surface of a first substrate cut from a first mother substrate.

[0027] Forming an etch stop on the first surface of the first mother substrate may include forming the etch stop as an integral stop.

[0028] Forming an etch stop on a first surface of a first mother substrate may include: forming a plurality of etch stopes, each of which may overlap with a corresponding modified region in a plurality of modified regions, and each of which may be separate from one another.

[0029] The method may further include: performing unit cutting on each of the plurality of upper display modules after setting the packaged elements; and performing masking on the area other than the second surface of the first substrate using a wet lithography mask after performing unit cutting.

[0030] The method may further include: after performing a masking process, forming a substrate via penetrating the first surface from the second surface of the first substrate by etching at each of the plurality of modified regions. Etching may include wet etching.

[0031] The method may further include: after performing a masking process, forming a terminating via that penetrates the etch terminating via in a portion overlapping with the substrate via; after forming the terminating via, forming a substrate connection electrode to fill the substrate via and the terminating via; and after forming the substrate connection electrode, forming a first pad that overlaps with the substrate connection electrode and is disposed on a second surface of the first substrate.

[0032] It should be noted that the purpose of this disclosure is not limited to the objectives described above. Other objectives of the invention will be apparent to those skilled in the art from the following description.

[0033] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be apparent to those skilled in the art from the following description. Attached Figure Description

[0034] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments of this disclosure with reference to the accompanying drawings, in which:

[0035] Figure 1 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0036] Figure 2 It is along Figure 1 A schematic cross-sectional view taken from line I-I' in the diagram.

[0037] Figure 3 This is a schematic plan view of a display device according to an embodiment of the present disclosure when viewed from above.

[0038] Figure 4 yes Figure 3 A magnified schematic planar view of the pixels.

[0039] Figure 5 It is along Figure 4 Schematic cross-sectional views taken from lines IV-IV', V-V', and VI-VI'.

[0040] Figure 6 This is a schematic plan view of a display device according to an embodiment of the present disclosure when viewed from the bottom.

[0041] Figure 7 It is along Figure 3 and Figure 6 Schematic cross-sectional views taken from lines II-II' and III-III'.

[0042] Figure 8 yes Figure 7 A magnified schematic cross-sectional view of region A.

[0043] Figure 9 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment of the present disclosure.

[0044] Figure 10 , Figure 11 , Figure 13 , Figure 15 , Figure 17 and Figure 18 This is a schematic perspective view illustrating the processing steps of a method for manufacturing a display device according to an embodiment of the present disclosure.

[0045] Figure 12 It is along Figure 11 A schematic cross-sectional view of line VII-VII'.

[0046] Figure 14 It is along Figure 13 A schematic cross-sectional view of line VIII-VIII'.

[0047] Figure 16 It is along Figure 15A schematic cross-sectional view of the line IX-IX'.

[0048] Figure 19 It is along Figure 18 A schematic cross-sectional view of the line X-X'.

[0049] Figures 20 to 24 This is a schematic cross-sectional view illustrating the processing steps of a method for manufacturing a display device according to an embodiment of the present disclosure.

[0050] Figures 25 to 28 This is a schematic perspective view illustrating the processing steps of a method for manufacturing a display device according to another embodiment of the present disclosure.

[0051] Figure 29 It is along Figure 28 A schematic cross-sectional view of the line XI-XI'.

[0052] Figures 30 to 31 This is a schematic cross-sectional view illustrating the processing steps of a method for manufacturing a display device according to another embodiment of the present disclosure.

[0053] Figure 32 This is a flowchart illustrating a method for manufacturing a display device according to another embodiment of the present disclosure.

[0054] Figures 33 to 34 This is a schematic perspective view illustrating the processing steps of a method for manufacturing a display device according to another embodiment of the present disclosure.

[0055] Figures 35 to 40 This is a schematic cross-sectional view illustrating the processing steps of a method for manufacturing a display device according to another embodiment of the present disclosure.

[0056] Figure 41 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0057] Figure 42 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0058] Figure 43 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0059] Figure 44 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0060] Figure 45 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0061] Figure 46 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0062] Figure 47 This is a schematic plan view of a display device according to another embodiment of the present disclosure.

[0063] Figure 48 This is a schematic plan view of a display device according to another embodiment of the present disclosure when viewed from above.

[0064] Figure 49 This is a schematic plan view of a display device according to another embodiment of the present disclosure when viewed from the bottom. Detailed Implementation

[0065] The specific structural and functional descriptions of the embodiments of the present invention disclosed herein are for illustrative purposes only. The present invention can be embodied in many different forms without departing from its spirit and distinctive features. Therefore, the embodiments of the present invention are disclosed for illustrative purposes only and should not be construed as limiting the present invention. That is, the present invention is defined only by the scope of the claims (including any equivalents).

[0066] It will be understood that when an element is referred to as being related to another element, such as being “coupled” or “connected” to another element, it can be directly coupled or connected to the other element, or there can be intermediate elements between them. Conversely, it should be understood that when an element is referred to as being directly related to another element, such as being “directly coupled” or “directly connected” to another element, there may be no intermediate elements. Other expressions used to explain the relationships between elements, such as “between,” “directly between,” “proximately to,” or “directly adjacent to,” should be understood in the same way.

[0067] Throughout the specification, the same reference numerals will refer to the same or similar parts.

[0068] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another. Therefore, without departing from the teachings of this document, the “first element,” “component,” “region,” “layer,” or “section” discussed below may be referred to as a second element, component, region, layer, or section.

[0069] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both singular and plural forms unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as a limiting “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising,” “having,” or “including” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0070] The term “overlap” can include layering, stacking, facing or confronting, extending on, extending below, covering or partially covering, or any other suitable term that will be recognized and understood by a person of ordinary skill in the art. The expression “non-overlap” can include “separated from” or “separated from” or “offset from”, and any other suitable equivalent expression that will be recognized and understood by a person of ordinary skill in the art.

[0071] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, relative terms are also intended to encompass different orientations of the device. For example, if a device in a figure is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Thus, the term “down” can encompass both “down” and “up” orientations depending on the specific orientation in the figure. Similarly, if a device in a figure is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the term “below” or “under” can encompass both “up” and “down” orientations.

[0072] Taking into account the problematic measurement and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the term “approximately” or “about” as used herein includes specified values ​​and averages within an acceptable range of deviation from a given value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the specified value.

[0073] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0074] Exemplary embodiments are described herein with reference to schematic cross-sectional views as idealized embodiments. Therefore, variations in the illustrated shapes can be expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include, for example, deviations in shape due to manufacturing processes. For example, regions illustrated or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the sharp corners shown may be rounded. Therefore, the regions shown in the figures may be schematic in nature, and their shapes are not intended to show the precise shape of the regions, nor are they intended to limit the scope of the claims.

[0075] In the following description, embodiments of the invention will be illustrated with reference to the accompanying drawings.

[0076] Figure 1 This is a schematic plan view of a display device according to an embodiment of the present disclosure. Figure 2 It is along Figure 1 A schematic cross-sectional view taken from line I-I'.

[0077] Figure 1 and Figure 2 The display device 1 shown can be used in a variety of electronic devices, including: small and medium-sized electronic devices such as tablet computers, smartphones, vehicle navigation units, cameras, central information displays (CIDs) installed in vehicles, wrist-worn electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), and game consoles; and large and medium-sized electronic devices such as televisions, electronic billboards, monitors, personal computers, and laptops. It should be understood that the electronic devices listed above are merely illustrative, and the display device 10 can be used in a variety of other electronic devices without departing from the scope of this disclosure.

[0078] In some embodiments, the display device 1 may have a rectangular shape when viewed from above. The display device 1 may include two first sides extending in a first direction DR1 and two second sides extending in a second direction DR2 intersecting the first direction DR1. Although the angle where the first and second sides of the display device 1 meet may form a right angle, this is merely illustrative. The display device 1 may have rounded corners. In some embodiments, the first side may be longer than the second side, but this disclosure is not limited thereto. The shape of the display device 1 when viewed from above is not limited to the shape shown in the figures. The display device 70 may have a circular shape or other shapes.

[0079] The display device 1 may include a display area DA for displaying images and a non-display area NDA for not displaying images. In some embodiments, the non-display area NDA may be disposed around the display area DA to surround the display area DA.

[0080] According to embodiments of this disclosure, the display device 1 may include a first display substrate 10 and a second display substrate 20 facing the first display substrate 10, and may further include a sealing member SEAL coupling the first display substrate 10 and the second display substrate 20, and a filling material FM located between the first display substrate 10 and the second display substrate 20. The sealing member SEAL may be disposed in the non-display area NDA and may not overlap with the display area DA.

[0081] The first display substrate 10 may include elements and circuitry for displaying images, such as pixel circuitry including switching elements, an outer perimeter defining emitting and non-emitting regions (described later) in the display area DA, and self-emissive elements. In one embodiment, the self-emissive element may include at least one of organic light-emitting diodes, quantum dot light-emitting diodes, inorganic micro-light-emitting diodes (e.g., micro-LEDs), and inorganic nano-light-emitting diodes (e.g., nano-LEDs).

[0082] The second display substrate 20 may be located on the first display substrate 10 and may face the first display substrate 10. The second display substrate 20 may include a color conversion pattern for converting the color of incident light. In some embodiments, the color conversion pattern may include a color filter and / or a color control layer.

[0083] A sealing member SEAL can be disposed in the non-display area NDA between the first display substrate 10 and the second display substrate 20. When viewed from above, the sealing member SEAL can be disposed along the edges of the first display substrate 10 and the second display substrate 20 in the non-display area NDA to surround the display area DA. The first display substrate 10 and the second display substrate 20 can be coupled to each other through the sealing member SEAL. In some embodiments, the sealing member SEAL can be made of an organic material. For example, the sealing member SEAL can be made of, but is not limited to, epoxy resin.

[0084] A filler material FM can be disposed in the space between the first display substrate 10 and the second display substrate 20, which is surrounded by a sealing member SEAL. The space between the first display substrate 10 and the second display substrate 20 can be filled with the filler material FM. The filler material FM can be made of a light-transmitting material. In some embodiments, the filler material FM can be made of an organic material. For example, the filler material FM can be made of, but is not limited to, silicon-based organic materials, epoxy-based organic materials, or combinations thereof. In some embodiments, the filler material FM can be removed.

[0085] Figure 3 This is a schematic plan view of a display device according to an embodiment of the present disclosure when viewed from above.

[0086] refer to Figure 3 Pixels PX can be set in the display area DA. Pixels PX can be arranged in a matrix along a first direction DR1 and a second direction DR2. Pixels PX arranged along the first direction DR1 can form pixel rows. There can be more than one pixel row. Pixel rows can be arranged along the second direction DR2. Similarly, pixels PX arranged along the second direction DR2 can form pixel columns. There can be more than one pixel column. Pixel columns can be arranged along the first direction DR1.

[0087] A scan driver SP can be disposed in a non-display area NDA. The scan driver SP may include at least one thin-film transistor. The scan driver SP can be electrically connected to a scan line SL. More than one scan driver SP may exist. The scan driver SP may be located in the non-display area NDA, which is situated on one side (or right side) and the other side (or left side) of the display area DA in the first direction DR1. In some embodiments, there may be only one scan driver SP. The scan driver SP may be disposed in the non-display area NDA, which is situated on one side or the other side of the display area DA in the first direction DR1. In some embodiments, there may be two scan driver SPs. The two scan driver SPs may be disposed in the non-display area NDA, which is situated on one side and the other side of the display area DA in the first direction DR1.

[0088] Scan lines SL can extend along pixel rows. More than one scan line SL can exist. Scan lines SL can be arranged along a second direction DR2. Scan lines SL arranged along the second direction DR2 can be electrically connected to pixel rows individually.

[0089] Data lines DL can extend along pixel columns. More than one data line DL can exist. Data lines DL can be arranged along a first direction DR1. Data lines DL arranged along the first direction DR1 can be electrically connected to pixel columns individually.

[0090] The data line DL can be electrically connected to the substrate connection electrode CNTb. More than one substrate connection electrode CNTb may exist. Each substrate connection electrode CNTb can be associated with a data line DL. Although in Figure 3 In the example shown, the substrate connection electrodes CNTb can be arranged along the first direction DR1, but the arrangement of the substrate connection electrodes CNTb is not limited to this. For example, the substrate connection electrodes CNTb can be arranged in a zigzag pattern instead of along the first direction DR1.

[0091] As described below, the data cable DL can be connected via the data connection electrode CNTa (see below). Figure 7 ), Etching Termination Part ES (see Figure 7 The substrate connection electrode CNTb is electrically connected to the first pad PAD1 (see...). Figure 6 and Figure 7 ).

[0092] Each pixel in pixel PX may include an emission region EMA and a non-emission region NEA surrounding the emission region EMA. As described above, the non-emission region NEA and the emission region EMA can be separated by an outer embankment 45 (see [link to documentation]). Figure 5 ) and light-emitting element 30 (see Figure 5 The outer dam 45 can be disposed in the non-emitting region NEA, and the light-emitting element 30 can be disposed in the emitting region EMA. Alternatively, the outer dam 45 may not be disposed in the emitting region EMA, and the light-emitting element 30 may not be disposed in the non-emitting region NEA. The substrate connection electrode CNTb and the data connection electrode CNTa may be disposed in the emitting region EMA.

[0093] Figure 4 yes Figure 3 A magnified schematic planar view of the pixels. Figure 5 It is along Figure 4 Schematic cross-sectional views taken from lines IV-IV', V-V', and VI-VI'.

[0094] refer to Figure 4 In a pixel, one pixel PX can emit light of a first color, another pixel PX can emit light of a second color, and yet another pixel PX can emit light of a third color. The first color can be red, the second color can be green, and the third color can be blue. However, it should be understood that this disclosure is not limited thereto. All pixels PX can emit light of the same color.

[0095] Each pixel in the pixel PX of the display device 1 may include a region defined as an emission region EMA. The emission region EMA can be defined as a region in which the light-emitting element 30 included in the display device 1 is configured to emit light of a specific wavelength band. The light-emitting element 30 includes an active layer that can emit light of a specific wavelength band without directionality. Light emitted from the active layer of the light-emitting element 30 can exit from both sides of the light-emitting element 30. The emission region EMA may include a region in which the light-emitting element 30 is disposed, and may include a region adjacent to the light-emitting element 30, from which light emitted from the light-emitting element 30 exits.

[0096] However, it should be understood that this disclosure is not limited thereto. The emission region EMA may also include the area in which light emitted from the light-emitting element 30 is reflected or refracted by other elements and emitted. The light-emitting elements 30 may be disposed in the pixels PX, and the emission region EMA may include the area where the light-emitting elements are disposed as well as adjacent areas.

[0097] Although not shown in the figure, each pixel in the pixel PX of the display device 1 may include a non-emissive region NEA, which is defined as the area other than the emissive region EMA. In the non-emissive region NEA, the light-emitting element 30 may not be provided, and light emitted from the light-emitting element 30 may not reach that area, and therefore no light is emitted from there. An outer embankment 45 may be provided in the non-emissive region NEA.

[0098] Combination Figure 4 For reference Figure 5 The display device 1 may include a first substrate 11 or a first base substrate, and a circuit element layer and a display element layer disposed on the first substrate 11. The display device 1 may also include an etch stop element ES disposed on the first substrate 11. A semiconductor layer, a conductive layer, and an insulating layer may be disposed on the first substrate 11, and they may form the circuit element layer and the display element layer. The conductive layer may include: a first gate conductive layer, a second gate conductive layer, a first data conductive layer, and a second data conductive layer, disposed below the first planarization layer 19 to form the circuit element layer; and electrodes 21, 22, and a contact electrode 26, disposed above the first planarization layer 19 to form the display element layer. The insulating layer may include a buffer layer 12, a first gate insulating layer 13, a first protective layer 15, a first interlayer dielectric layer 17, a second interlayer dielectric layer 18, and a first planarization layer 19, a first insulating layer 51, a second insulating layer 52, a third insulating layer 53, a fourth insulating layer 54, etc.

[0099] Specifically, the first substrate 11 may be an insulating substrate. The first substrate 11 may be made of an insulating material such as glass, quartz, polymer resin, or combinations thereof. The first substrate 11 may be a rigid substrate or a flexible substrate that can be bent, folded, or rolled up.

[0100] An etch stop element ES can be disposed on a first substrate 11. The first substrate 11 may include a first surface on which the etch stop element ES can be disposed, and a second surface opposite to the first surface. The etch stop element ES can be disposed on the first surface of the first substrate 11. The etch stop element ES can be directly disposed on the first surface of the first substrate 11.

[0101] The etch stop element ES may include an organic material. In some embodiments, the etch stop element ES may include an inorganic material.

[0102] The etch stop element ES can prevent the etch solution from spreading to the first surface of the first substrate during the process of forming substrate vias, which will be described later.

[0103] Light-shielding layers BML1 and BML2 may be disposed on the etch stop element ES. Light-shielding layers BML1 and BML2 may include a first light-shielding layer BML1 and a second light-shielding layer BML2. The first light-shielding layer BML1 and the second light-shielding layer BML2 at least overlap with the first active material layer DT_ACT of the driving transistor DT and the second active material layer ST_ACT of the switching transistor ST, respectively. Light-shielding layers BML1 and BML2 may include a light-blocking material, thereby preventing light from incident on the first active material layer DT_ACT and the second active material layer ST_ACT. For example, the first light-shielding layer BML1 and the second light-shielding layer BML2 may be made of an opaque metallic material that blocks light transmission. However, it should be understood that this disclosure is not limited thereto. In some embodiments, light-shielding layers BML1 and BML2 may be removed.

[0104] Buffer layer 12 can be disposed on light-shielding layers BML1 and BML2. Buffer layer 12 can be formed on the first substrate 11 to protect the thin-film transistors DT and ST of the pixel from moisture penetrating through the first substrate 11, which may be susceptible to moisture penetration, thus providing a flat surface. Buffer layer 12 can be formed from inorganic layers stacked alternately on top of each other. For example, buffer layer 12 can be composed of multiple layers, including silicon oxide (SiO2). x ), silicon nitride (SiN) x Inorganic layers of at least one of silicon oxynitride (SiON) can be stacked alternately on each other.

[0105] A semiconductor layer may be disposed on the buffer layer 12. The semiconductor layer may include a first active material layer DT_ACT for driving transistor DT and a second active material layer ST_ACT for switching transistor ST. These may be configured to partially overlap with the gate electrodes DT_G and ST_G of the first gate conductive layer, which will be described later, and the light-emitting element 30.

[0106] According to embodiments of this disclosure, the semiconductor layer may include polycrystalline silicon, monocrystalline silicon, oxide semiconductor, or combinations thereof. Polycrystalline silicon can be formed by crystallizing amorphous silicon. When the semiconductor layer includes polycrystalline silicon, the first active material layer DT_ACT may include a first doped region DT_ACTa, a second doped region DT_ACTb, and a first channel region DT_ACTc. The first channel region DT_ACTc may be disposed between the first doped region DT_ACTa and the second doped region DT_ACTb. The second active material layer ST_ACT may include a third doped region ST_ACTa, a fourth doped region ST_ACTb, and a second channel region ST_ACTc. The second channel region ST_ACTc may be disposed between the third doped region ST_ACTa and the fourth doped region ST_ACTb. The first doped region DT_ACTa, the second doped region DT_ACTb, the third doped region ST_ACTa, and the fourth doped region ST_ACTb may be formed by doping impurities in some regions of the first active material layer DT_ACT and the second active material layer ST_ACT.

[0107] In another embodiment, the first active material layer DT_ACT and the second active material layer ST_ACT may include an oxide semiconductor. The doped regions of the first active material layer DT_ACT and the second active material layer ST_ACT may be conductive. The oxide semiconductor may be an indium (In)-containing oxide semiconductor. In some embodiments, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), etc. However, it should be understood that this disclosure is not limited thereto.

[0108] A first gate insulating layer 13 may be disposed on the semiconductor layer and the buffer layer 12. The first gate insulating layer 13 may include a semiconductor layer and may be disposed on the buffer layer 12. The first gate insulating layer 13 can be used as the gate insulating layer for a driving transistor DT and a switching transistor ST. The first gate insulating layer 13 may be made of materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x It can be formed by inorganic layers of inorganic materials such as silicon oxynitride (SiON) and silicon oxynitride (SiON), or by stacking these materials.

[0109] A first gate conductive layer may be disposed on a first gate insulating layer 13. The first gate conductive layer may include a first gate electrode DT_G of a driving transistor DT and a second gate electrode ST_G of a switching transistor ST. The first gate electrode DT_G may be configured to overlap with a first channel region DT_ACTc of a first active material layer DT_ACT in the thickness direction, and the second gate electrode ST_G may be configured to overlap with a second channel region ST_ACTc of a second active material layer ST_ACT in the thickness direction.

[0110] The first gate conductive layer may consist of a single layer or multiple layers of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, it should be understood that this disclosure is not limited thereto.

[0111] A first protective layer 15 may be disposed on the first gate conductive layer. The first protective layer 15 may be configured to cover the first gate conductive layer for protecting it. The first protective layer 15 may be made of materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x It can be formed by inorganic layers of inorganic materials such as silicon oxynitride (SiON) and silicon oxynitride (SiON), or by stacking these materials.

[0112] A second gate conductive layer may be disposed on the first protective layer 15. The second gate conductive layer may include a first capacitor electrode CE1, which is configured to at least partially overlap with the first gate electrode DT_G in the thickness direction, forming a storage capacitor. The first capacitor electrode CE1 overlaps with the first gate electrode DT_G in the thickness direction, the first protective layer 15 is located between the first capacitor electrode CE1 and the first gate electrode DT_G, and a storage capacitor may be formed between the first capacitor electrode CE1 and the first gate electrode DT_G. The second gate conductive layer may consist of a single layer or multiple layers of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, it should be understood that this disclosure is not limited thereto.

[0113] The first interlayer dielectric layer 17 can be disposed on the second gate conductive layer. The first interlayer dielectric layer 17 can serve as an insulating layer between the second gate conductive layer and other layers disposed thereon. The first interlayer dielectric layer 17 can be made of materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x It can be formed by inorganic layers of inorganic materials such as silicon oxynitride (SiON) and silicon oxynitride (SiON), or by stacking these materials.

[0114] The first data conductive layer may be disposed on the first interlayer dielectric layer 17. The first gate conductive layer may include the first source / drain electrode DT_SD1 and the second source / drain electrode DT_SD2 of the driving transistor DT, and the first source / drain electrode ST_SD1 and the second source / drain electrode ST_SD2 of the switching transistor ST.

[0115] The first source / drain electrode DT_SD1 and the second source / drain electrode DT_SD2 of the driving transistor DT can contact the first doped region DT_ACTa and the second doped region DT_ACTb of the first active material layer DT_ACT, respectively, through contact holes penetrating the first interlayer insulating layer 17 and the first gate insulating layer 13. The first source / drain electrode ST_SD1 and the second source / drain electrode ST_SD2 of the switching transistor ST can contact the second doped region ST_ACTa and the fourth doped region ST_ACTb of the second active material layer ST_ACT, respectively, through contact holes penetrating the first interlayer insulating layer 17 and the first gate insulating layer 13. The first source / drain electrode DT_SD1 of the driving transistor DT and the first source / drain electrode ST_SD1 of the switching transistor ST can be electrically connected to the first light-shielding layer BML1 and the second light-shielding layer BML2, respectively, through other contact holes. When one of the first source / drain electrode DT_SD1 and the second source / drain electrode DT_SD2 of the driving transistor DT can be a source electrode, the other can be a drain electrode. In the case where one of the first source / drain electrode ST_SD1 and the second source / drain electrode ST_SD2 of the switching transistor ST can be a source electrode, the other can be a drain electrode. However, it should be understood that this disclosure is not limited thereto. In the case where one of the first source / drain electrode ST_SD1 and the second source / drain electrode ST_SD2 is a drain electrode, the other can be a source electrode. In the case where one of the first source / drain electrode ST_SD1 and the second source / drain electrode ST_SD2 is a drain electrode, the other can be a source electrode.

[0116] The first data conductive layer may consist of a single layer or multiple layers of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, it should be understood that this disclosure is not limited thereto.

[0117] The second interlayer dielectric layer 18 can be disposed on the first data conductive layer. The second interlayer dielectric layer 18 can cover the first data conductive layer and can be entirely disposed on the first interlayer dielectric layer 17 to protect the first data conductive layer. The second interlayer dielectric layer 18 can be made of materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x Inorganic layers of inorganic materials such as silicon oxynitride (SiON) are formed, or can be formed by stacking these materials.

[0118] A second data conductive layer may be disposed on the second interlayer dielectric layer 18. The second data conductive layer may include a first voltage line VL1, a second voltage line VL2, and a first conductive pattern CDP. A high-level voltage (or a first power supply voltage) may be applied to the first voltage line VL1 to supply the driving transistor DT, and a low-level voltage (or a second power supply voltage) may be applied to the second voltage line VL2 to supply the second electrode 22. During the manufacturing process of the display device 1, an alignment signal required to align the light-emitting element 30 may be applied to the second voltage line VL2.

[0119] The first conductive pattern CDP can be electrically connected to the first source / drain electrode DT_SD1 of the driving transistor DT through contact holes formed in the second interlayer dielectric layer 18. The first conductive pattern CDP can also contact the first electrode 21, which will be described later. The driving transistor DT can transmit a first power supply voltage applied from the first voltage line VL1 to the first electrode 21 through the first conductive pattern CDP. Although in the example shown in the figures, the second data conductive layer includes a second voltage line VL2 and a first voltage line VL1, this disclosure is not limited thereto. The second data conductive layer may include more than one first voltage line VL1 and a second voltage line VL2.

[0120] The second conductive layer may consist of a single layer or multiple layers of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, it should be understood that this disclosure is not limited thereto.

[0121] The first planarization layer 19 may be disposed on the second data conductive layer. The first planarization layer 19 may include an organic insulating material, such as an organic material like polyimide (PI), to provide a flat surface.

[0122] Inner embankments 41 and 42, electrodes 21 and 22, outer embankment 45, contact electrode 26, and light-emitting element 30 may be disposed on the first planarization layer 19. Insulating layers 51, 52, 53, and 54 may be further disposed on the first planarization layer 19.

[0123] Inner embankments 41 and 42 can be directly disposed on the first planarization layer 19. Inner embankments 41 and 42 may include a first inner embankment 41 and a second inner embankment 42 disposed adjacent to the center of each pixel in pixel PX.

[0124] The first inner dam 41 and the second inner dam 42 can be spaced apart from each other and face each other in the first direction DR1. Since the inner dams 41 and 42 can be spaced apart, an area can exist in which the light-emitting element 30 can be disposed. The first inner dam 41 and the second inner dam 42 can extend in the second direction DR2 and can terminate at the boundary of each pixel in pixel PX, such that they do not extend into adjacent pixels PX in the second direction DR2. Therefore, the first inner dam 41 and the second inner dam 42 can be disposed in each pixel in pixel PX to form a pattern on the entire surface of the display device 1. Although... Figure 4 and Figure 5 Only one first inner dam 41 and one second inner dam 42 are shown, but this disclosure is not limited thereto. More than one inner dam 41 and 42 may be provided depending on the number of electrodes 21 and 22, which will be described later.

[0125] The first inner dam 41 and the second inner dam 42 may have a structure that can at least partially protrude from the upper surface of the first planarization layer 19. The protruding portion of each of the first inner dam 41 and the second inner dam 42 may have an inclined side surface. Light emitted from the light-emitting element 30 may travel toward the inclined side surfaces of the inner dams 41 and 42. As will be described later, the electrodes 21 and 22 respectively disposed on the inner dams 41 and 42 may comprise a material with high reflectivity, and light emitted from the light-emitting element 30 may be reflected from the electrodes 21 and 22 disposed on the side surfaces of the inner dams 41 and 42, such that light may exit toward the upper side of the first planarization layer 19. For example, the inner dams 41 and 42 may provide an area in which the light-emitting element 30 is disposed, and may also serve as reflective barriers reflecting light emitted upward from the light-emitting element 30. In one embodiment, the inner dams 41 and 42 may include, but are not limited to, organic insulating materials such as polyimide (PI).

[0126] Electrodes 21 and 22 may be disposed on inner embankments 41 and 42 and on the first planarization layer 19. Electrodes 21 and 22 may be electrically connected to the light-emitting element 30 and may be subjected to a predetermined voltage, such that the light-emitting element 30 may emit light of a specific wavelength band. At least a portion of electrodes 21 and 22 may be used to form an electric field within the pixel PX to align the light-emitting element 30.

[0127] Electrodes 21 and 22 may include a first electrode 21 disposed on the first inner dam 41 and a second electrode 22 disposed on the second inner dam 42.

[0128] The first electrode 21 and the second electrode 22 may include electrode stems 21S and 22S extending respectively in the first direction DR1 (see Figure 7), and one or more electrode branches 21B and 22B that branch from electrode trunks 21S and 22S respectively and extend in a second direction DR2 that intersects the first direction D1.

[0129] The first electrode 21 may include a first electrode trunk 21S extending in the first direction DR1, and at least one first electrode branch 21B branching from the first electrode trunk 21S and extending in the second direction DR2.

[0130] The two ends of the first electrode stem 21S can be terminated such that they can be spaced apart between pixels PX, and can lie on a straight line substantially the same as the first electrode stem 21S of the next adjacent pixel in the same row, for example, in the first direction DR1. Since the two ends of the first electrode stem 21S in each pixel of pixel PX can be spaced apart between pixels, different electrical signals can be applied to the first electrode branch 21B, thereby allowing the first electrode branch 21B to be driven individually. The first electrode 21 can be electrically connected to the first source / drain electrode DT_SD1 of the driving transistor DT by contacting the first conductive pattern CDP through the first contact hole CT1 penetrating the first planarization layer 19.

[0131] The first electrode branch 21B may branch from at least a portion of the first electrode trunk 21S to extend in the second direction D2, and may be terminated such that it may be spaced apart from the second electrode trunk 22S, which may be opposite to the first electrode trunk 21S.

[0132] The second electrode 22 may include a second electrode trunk 22S extending in the first direction DR1 and spaced apart from the first electrode trunk 21S in the second direction D2, and a second electrode branch 22B branching from the second electrode trunk 22S and extending in the second direction D2.

[0133] The second electrode stem 22S can extend along the first direction DR1 and can be positioned outside the boundary with another adjacent pixel PX. The second electrode stem 22S extending across pixel PX can extend outside the display area DA or from a portion extending along a direction from the non-display area NDA. The second electrode 22 can contact the second voltage line VL2 through the second contact hole CT2 penetrating the first planarization layer 19. As shown, the second electrodes 22 of pixels PX adjacent to each other along the first direction DR1 can be electrically connected to a second electrode stem 22S and can be electrically connected to the second voltage line VL2 through the second contact hole CT2. However, it should be understood that this disclosure is not limited thereto. In some embodiments, the second contact hole CT2 can be formed in each pixel of pixel PX.

[0134] The second electrode branch 22B may be spaced apart from and face the first electrode branch 21B, and may be terminated, thereby being spaced apart from the first electrode trunk 21S. The second electrode branch 22B may be electrically connected to the second electrode trunk 22S, and the end of the second electrode branch 22B may be spaced apart from the first electrode trunk 21S in pixel PX.

[0135] Although two first electrode branches 21B and one second electrode branch 22B can be provided for each pixel PX in the figure, this disclosure is not limited thereto. In some embodiments, a greater number of first electrode branches 21B and second electrode branches 22B can be provided for each pixel PX. The first electrode 21 and the second electrode 22 provided in each pixel PX do not necessarily have to have a shape extending in one direction, but can be provided in a variety of structures.

[0136] The first electrode 21 and the second electrode 22 can be respectively disposed on the first inner dam 41 and the second inner dam 42, and they can be spaced apart from each other. The electrode branches 21B and 22B of the first electrode 21 and the second electrode 22 can be respectively disposed on the first inner dam 41 and the second inner dam 42, and at least some of their regions can be directly disposed on the planarization layer 19. At least one end of the light-emitting element 30 disposed between the first inner dam 41 and the second inner dam 42 can be electrically connected to the first electrode 21 and the second electrode 22.

[0137] Each electrode in electrodes 21 and 22 may comprise a transparent conductive material. For example, each electrode in electrode layers 21 and 22 may comprise, but is not limited to, materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or combinations thereof. In some embodiments, each electrode in electrodes 21 and 22 may comprise a conductive material with high reflectivity. For example, each electrode in electrodes 21 and 22 may comprise a metal such as silver (Ag), copper (Cu), aluminum (Al), or combinations thereof as a material with high reflectivity. In this case, light incident on each electrode in electrodes 21 and 22 can be reflected and emitted toward the top of each pixel in pixel PX.

[0138] Each of electrodes 21 and 22 may have a structure in which one or more layers of transparent conductive material and a metal layer with high reflectivity may be stacked, or it may be composed of a single layer. In one embodiment, each of electrodes 21 and 22 may have a stacked structure of ITO / silver (Ag) / ITO / IZO, or it may be an alloy including aluminum (Al), nickel (Ni), lanthanum (La), etc. However, it should be understood that this disclosure is not limited thereto.

[0139] Electrodes 21 and 22 can be electrically connected to the light-emitting element 30 and can receive a predetermined voltage, enabling the light-emitting element 30 to emit light. For example, electrodes 21 and 22 can be electrically connected to the light-emitting element 30 via contact electrode 26, which will be described later, and an electrical signal applied thereto can be transmitted to the light-emitting element 30 via contact electrode 26.

[0140] In one embodiment, the first electrode 21 can be disconnected from pixel to pixel PX, while the second electrode 22 can be a common electrode electrically connected across pixels PX. One of the first electrode 21 and the second electrode 22 can be the anode electrode of the light-emitting element 30, and the other electrode can be the cathode electrode of the light-emitting element 30. However, it should be understood that this disclosure is not limited thereto. For example, the first electrode 21 can be the cathode electrode, and the second electrode 22 can be the anode electrode.

[0141] Electrodes 21 and 22 can be used to form an electric field within the pixel PX to align the light-emitting element 30. The light-emitting element 30 can be positioned between the first electrode 21 and the second electrode 22 by applying an alignment signal to the first electrode 21 and the second electrode 22. During the inkjet printing process, the light-emitting element 30, dispersed in ink, can be ejected onto the first electrode 21 and the second electrode 22. By applying an alignment signal between the first electrode 21 and the second electrode 22 to apply a dielectric force, the light-emitting element 30 can be aligned between the first electrode 21 and the second electrode 22.

[0142] A first insulating layer 51 may be disposed on the first planarization layer 19, the first electrode 21, and the second electrode 22. The first insulating layer 51 may be configured to partially cover the first electrode 21 and the second electrode 22. The first insulating layer 51 may cover a portion (e.g., most) of the upper surface of each of the first electrode 21 and the second electrode 22, and may expose a portion of each of the first electrode 21 and the second electrode 22. The first insulating layer 51 may be configured to expose a portion of the upper surface of the first electrode 21 and the second electrode 22, for example, a portion of the upper surface of the first electrode branch 21B disposed on the first inner embankment 41 and a portion of the upper surface of the second electrode branch 22B disposed on the inner embankment 42. The first insulating layer 51 may be substantially entirely formed on the first planarization layer 19 and may include openings that partially expose the first electrode 21 and the second electrode 22.

[0143] In one embodiment, the first insulating layer 51 may have a step, such that a portion of its upper surface is recessed between the first electrode 21 and the second electrode 22. In some embodiments, the first insulating layer 51 may comprise an inorganic insulating material, and a portion of the upper surface of the first insulating layer 51, configured to cover the first electrode 21 and the second electrode 22, may be recessed due to the step of an element disposed beneath the first insulating layer 51. The light-emitting element 30 disposed on the first insulating layer 51 located between the first electrode 21 and the second electrode 22 may form an empty space with the recessed upper surface of the first insulating layer 51. The light-emitting element 30 may be partially spaced from the upper surface of the first insulating layer 51, and this space may be filled with the material of the second insulating layer 52, which will be described later. However, it should be understood that this disclosure is not limited thereto. The first insulating layer 51 may form a flat upper surface, on which the light-emitting element 30 is disposed.

[0144] The first insulating layer 51 protects the first electrode 21 and the second electrode 22 and insulates them from each other. It prevents the light-emitting element 30, which is disposed on the first insulating layer 51, from contacting other elements and being damaged. It should be understood that the shape and structure of the first insulating layer 51 are not limited thereto.

[0145] The outer dam 45 may be disposed on the first insulating layer 51. In some embodiments, the outer dam 45 may not include the area where the inner dams 41 and 42 and electrodes 21 and 22 are disposed on the first insulating layer 51, and may be disposed at the boundary between pixels PX and surround the area where the light-emitting element 30 is disposed. The outer dam 45 may be disposed in the non-emitting region NEA. The outer dam 45 may be configured to have a shape extending in the first direction DR1 and the second direction DR2 to form a grid pattern on the entire surface of the display region DA.

[0146] According to one embodiment of this disclosure, the height of the outer dike 45 may be greater than the height of the inner dikes 41 and 42. Unlike the inner dikes 41 and 42, the outer dike 45 can separate adjacent pixels PX from each other and can prevent ink used to form the light-emitting element 30 from overflowing into adjacent pixels PX during the inkjet printing process in the manufacturing process of the display device 1. The outer dike 45 can separate different pixels PX from each other, so that the ink in which the light-emitting element 30 is dispersed can not be mixed. The outer dike 45 may be, like the inner dikes 41 and 42, including but not limited to polyimide (PI).

[0147] Light-emitting elements 30 may be disposed between electrodes 21 and 22. For example, light-emitting elements 30 may be disposed between electrode branches 21B and 22B. Light-emitting elements 30 may be spaced apart from each other and may be substantially parallel to each other. Here, the spacing between light-emitting elements 30 is not particularly limited. In some embodiments, some light-emitting elements 30 may be arranged close to each other to form a group, and other light-emitting elements 30 may be arranged close to each other to form another group that may be spaced apart from the group. In another embodiment, light-emitting elements 30 may be arranged in a non-uniform density. In this embodiment, light-emitting elements 30 have a shape extending in one direction. The direction in which electrodes 21 and 22 extend may be substantially perpendicular to the direction in which light-emitting elements 30 extend. However, it should be understood that this disclosure is not limited thereto. Light-emitting elements 30 may be tilted toward the direction in which electrodes 21 and 22 extend, rather than perpendicular to that direction.

[0148] The light-emitting element 30 according to embodiments of the present disclosure may include an active layer comprising different materials to emit light of different wavelength bands to the outside. The display device 1 may include the light-emitting element 30, which emits light of different wavelengths.

[0149] The light-emitting element 30 can be disposed on a first insulating layer 51 located between inner embankments 41 and 42 or between electrodes 21 and 22. For example, the light-emitting element 30 can be disposed on the first insulating layer 51 disposed between inner embankments 41 and 42. The light-emitting element 30 can be arranged to partially overlap with electrodes 21 and 22 in the thickness direction. One end of each light-emitting element 30 can overlap with and be located on the first electrode 21 in the thickness direction, and its other end can overlap with and be located on the second electrode 22 in the thickness direction. However, it should be understood that the present disclosure is not limited thereto. Although not shown in the figures, at least some of the light-emitting elements 30 disposed in each pixel PX can be disposed in areas other than the area formed between inner embankments 41 and 42, for example, in areas other than the area located between electrode branches 21B and 22B, or can be disposed between inner embankments 41 and 42 and outer embankment 45.

[0150] Each light-emitting element in the light-emitting element 30 may have one end in contact with the first contact electrode 26a and its other end in contact with the second contact electrode 26b. According to embodiments of this disclosure, an insulating layer may not be formed on one end of the light-emitting element 30 in its extending direction, thus exposing a portion of the semiconductor layer, which may contact the first contact electrode 26a and the second contact electrode 26b, as described below. However, it should be understood that this disclosure is not limited thereto. In some embodiments, at least a portion of the insulating layer may be removed, thus partially exposing the side surfaces at both ends of the semiconductor layer.

[0151] The second insulating layer 52 may be partially disposed on the light-emitting element 30 disposed between the first electrode 21 and the second electrode 22. The second insulating layer 52 may be configured to partially surround the outer surface of the light-emitting element 30. When viewed from above, a portion of the second insulating layer 52 disposed on the light-emitting element 30 may have a shape extending along a second direction DR2 between the first electrode 21 and the second electrode 22. For example, the second insulating layer 52 may form a striped or island-shaped pattern in each pixel PX.

[0152] A second insulating layer 52 may be disposed on the light-emitting element 30, and may expose one end and the opposite end of each light-emitting element in the light-emitting element 30. The exposed ends of each light-emitting element in the light-emitting element 30 may contact the contact electrode 26, which will be described later. The shape of the second insulating layer 52 may be formed using a typical masking process by patterning the material of the second insulating layer 52. The mask used to form the second insulating layer 52 may have a width smaller than the length of the light-emitting element 30. The material of the second insulating layer 52 may be patterned such that both ends of each light-emitting element in the light-emitting element 30 are exposed. However, it should be understood that this disclosure is not limited thereto.

[0153] The contact electrode 26 can be disposed on the first electrode 21, the second electrode 22, and the second insulating layer 52. The third insulating layer 53 can be disposed on one of the contact electrodes 26.

[0154] The contact electrode 26 may have a shape that extends in one direction. The contact electrode 26 may contact the light-emitting element 30 and the electrodes 21 and 22, and the light-emitting element 30 may receive electrical signals from the electrodes 21 and 22 through the contact electrode 26.

[0155] The contact electrode 26 may include a first contact electrode 26a and a second contact electrode 26b. The first contact electrode 26a and the second contact electrode 26b may be disposed on the first electrode 21 and the second electrode 22, respectively. Each of the first contact electrode 26a and the second contact electrode 26b may have a shape extending in a second direction DR2. The first contact electrode 26a and the second contact electrode 26b may be spaced apart from each other in a first direction DR1, and the first contact electrode 26a and the second contact electrode 26b may form a stripe pattern in the emission region EMA of each pixel PX.

[0156] A portion of the upper surface of each of the first electrode 21 and the second electrode 22 may be exposed, and the first contact electrode 26a and the second contact electrode 26b may contact the exposed upper surface of each of the first electrode 21 and the second electrode 22. For example, the first contact electrode 26a may contact the portion of the first electrode 21 located on the first inner embankment 41, and the second contact electrode 26b may contact the portion of the second electrode 22 located on the second inner embankment 42. However, it should be understood that this disclosure is not limited thereto. In some embodiments, the width of the first contact electrode 26a and the second contact electrode 26b may be smaller than the width of the first electrode 21 and the second electrode 22, so as to cover only the exposed portion of the upper surface.

[0157] According to embodiments of this disclosure, the semiconductor layer may be exposed at both ends on one side of the extending direction of the light-emitting element 30, and therefore, the first contact electrode 26a and the second contact electrode 26b may contact the light-emitting element 30 at the exposed ends of the semiconductor layer. However, it should be understood that this disclosure is not limited thereto. In some embodiments, the semiconductor layer may be exposed at both ends of the light-emitting element 30, and each of the contact electrodes 26 may contact the exposed semiconductor layer. One end of each light-emitting element in the light-emitting element 30 may be electrically connected to the first electrode 21 via the first contact electrode 26a, and its other end may be electrically connected to the second electrode 22 via the second contact electrode 26b.

[0158] Although two first contact electrodes 26a and one second contact electrode 26b can be provided in a pixel PX in the figure, this disclosure is not limited thereto. The number of first contact electrodes 26a and second contact electrodes 26b can be varied according to the number of first electrode branches 21B and second electrode branches 22B provided in each pixel PX.

[0159] Contact electrode 26 may include a conductive material. For example, contact electrode 26 may include ITO, IZO, ITZO, aluminum (Al), or combinations thereof. For example, contact electrode 26 may include a transparent conductive material, and light emitted from light-emitting element 30 may pass through contact electrode 26 to travel toward electrodes 21 and 22. Each of electrodes 21 and 22 may include a material with high reflectivity, and electrodes 21 and 22 placed on the inclined side surfaces of inner embankments 41 and 42 may cause incident light to be reflected toward the upper side of the first substrate 11. However, it should be understood that this disclosure is not limited thereto.

[0160] A third insulating layer 53 may be disposed on the first contact electrode 26a. The third insulating layer 53 can electrically insulate the first contact electrode 26a from the second contact electrode 26b. The third insulating layer 53 may be configured to cover the first contact electrode 26a and may not be disposed on the other end of the light-emitting element 30, thereby allowing the light-emitting element 30 to contact the second contact electrode 26b. The third insulating layer 53 may contact a portion of each of the first contact electrode 26a and the second insulating layer 52 on the upper surface of the second insulating layer 52. The side surface of the third insulating layer 53 located on the side where the second electrode 22 is disposed may be aligned with the side surface of the second insulating layer 52. The third insulating layer 53 may also be disposed in the non-emitting region (NEA), for example, on the first insulating layer 51 disposed on the first planarization layer 19. However, it should be understood that this disclosure is not limited thereto.

[0161] The fourth insulating layer 54 can be completely disposed on the first substrate 11. The fourth insulating layer 54 can be used to protect the components disposed on the first substrate 11 from the influence of the external environment.

[0162] Each of the aforementioned first insulating layer 51, second insulating layer 52, third insulating layer 53, and fourth insulating layer 54 may comprise an inorganic insulating material or an organic insulating material. According to embodiments of this disclosure, the first insulating layer 51, second insulating layer 52, third insulating layer 53, and fourth insulating layer 54 may comprise materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y Inorganic insulating materials may include aluminum oxide (Al2O3), aluminum nitride (AlN), or combinations thereof. In another embodiment, they may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, calomel resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate, polymethyl methacrylate-polycarbonate synthetic resin, etc., or combinations thereof, as organic insulating materials. However, it should be understood that this disclosure is not limited thereto.

[0163] Figure 6 This is a schematic plan view of a display device according to an embodiment of the present disclosure when viewed from the bottom.

[0164] refer to Figure 6 The data line DL can be electrically connected to the substrate connection electrode CNTb. The data line DL can also be connected via the data connection electrode CNTa (see...). Figure 7 ), Etching Termination Part ES (see Figure 7 The substrate connection electrode CNTb is electrically connected to the first pad PAD1 (see...). Figure 6 and Figure 7 ).

[0165] The interconnect line CL can be directly disposed on the second surface of the first substrate 11. One end of the interconnect line CL can form a first pad PAD1, and the other end of the interconnect line CL can form a second pad PAD2. Although in Figure 6 One end of the connecting line CL can form a first pad PAD1, and the other end of the connecting line CL can form a second pad PAD2. However, it can be stated that the connecting line CL can be electrically connected to each of the first pad PAD1 and the second pad PAD2. The second pad PAD2 can be associated with the connecting line CL separately. The second pad PAD2 can be configured. The second pad PAD2 can be arranged along a first direction DR1. Some connecting lines in the connecting line CL can be electrically connected to the first pad PAD1, and can include at least one bent portion extending downward in the second direction DR2.

[0166] For example, the connector CL may include an extension extending from one end of the connector CL in the second direction DR2, and a fan-out routing disposed between the curved portion and the second pad PAD2. In the fan-out routing, adjacent connector CLs may be closer to each other. One end of the fan-out routing may be electrically connected to the extension of the connector CL, and the other end of the fan-out routing may be electrically connected to the second pad PAD2.

[0167] A chip-on-film (COF) can be disposed on adjacent second pads PAD2. The COF can be attached to adjacent second pads PAD2. More than one COF can be disposed. The COFs can be arranged to be spaced apart from each other in the first direction DR1. Adjacent second pads PAD2 can form a pad group. Multiple pad groups can exist. Pad groups can be arranged to be spaced apart from each other in the first direction DR1. Pad groups can be electrically connected to different COFs. Driver chip ICs can be mounted on the COFs. The COF can be disposed in the display area DA of the display device 1. The COF can be disposed on the second surface of the first substrate 11 of the display device 1 and can be disposed in the display area DA, thereby avoiding dead zones that may occur when disposing of the COF.

[0168] Figure 7 It is along Figure 3 and Figure 6 Schematic cross-sectional views taken from lines II-II' and III-III'. No further details will be provided. Figure 7 can be with Figure 5 The same elements as those in the description are used.

[0169] refer to Figure 5 and Figure 7 An etch stop element ES can be disposed on the first surface of the first substrate 11. The etch stop element ES can be disposed between the light-shielding layers BML1 and BML2 and the first surface of the first substrate 11. The etch stop element ES can be directly disposed on the first surface of the first substrate 11. The etch stop element ES can cover the substrate via TH. The etch stop element ES can be disposed on the entire surface of the first substrate 11.

[0170] Data cable DL can be used in conjunction with the above references. Figure 5 The first data conductive layer is disposed on the same layer as described. The data line DL can be disposed on the same layer as the first source / drain electrode DT_SD1 and the second source / drain electrode DT_SD2 disposed on the first data conductive layer, and can include the same material.

[0171] The data line DL can be electrically connected to the data connection electrode CNTa, which penetrates the first interlayer dielectric layer 17, the first protective layer 15, the first gate insulating layer 13, and the buffer layer 12. The data connection electrode CNTa may include the same material as the data line DL, but this disclosure is not limited thereto. They may include different materials.

[0172] The data line DL can be electrically connected to the substrate connection electrode CNTb, which will be described later, via the data connection electrode CNTa.

[0173] The first substrate 11 may include a substrate via TH. The substrate via TH can completely penetrate the first substrate 11 from a first surface to a second surface in the thickness direction. The substrate via TH may be formed in the emitter region EMA. However, it should be understood that this disclosure is not limited thereto. The substrate via TH may be formed in the non-emitter region NEA.

[0174] The etch stop element ES may include a stop element via THa that overlaps with the substrate via TH. The stop element via THa may completely penetrate the etch stop element ES in the thickness direction.

[0175] The substrate via TH and the termination via THa can be filled by the substrate connection electrode CNTb. The substrate via TH and the termination via THa can be completely filled by the substrate connection electrode CNTb. The substrate connection electrode CNTb can contact the side surface (or inner surface) of the substrate via TH of the first substrate 11 and the side surface (or inner surface) of the termination via THa of the etched termination ES. The substrate connection electrode CNTb can include a conductive material. For example, the substrate connection electrode CNTb can include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The substrate connection electrode CNTb can be constructed by a single layer made of the above materials. In some embodiments, the substrate connection electrode CNTb can be constructed by a multilayer made of the above materials. The substrate connection electrode CNTb can be electrically connected to the data connection electrode CNTa. The substrate connection electrode CNTb can contact the data connection electrode CNTa. The substrate connection electrode CNTb can be electrically connected to the data connection electrode CNTa.

[0176] The connection line CL can be disposed on another surface (or back surface) of the first substrate 11. The connection line CL can also be directly disposed on the second surface of the first substrate 11. One end of the connection line CL can be electrically connected to the first pad PAD1, and the other end can be electrically connected to the second pad PAD2. The first pad PAD1 can overlap with the substrate connection electrode CNTb in the thickness direction and can be in direct contact with the substrate connection electrode CNTb. The first pad PAD1 can be electrically connected to the substrate connection electrode CNTb. The connection line CL, the first pad PAD1, and the second pad PAD2 can be disposed on the same layer and can comprise the same material. However, it should be understood that this disclosure is not limited thereto. The connection line CL, the first pad PAD1, and the second pad PAD2 can comprise different materials.

[0177] The connecting wire CL may include a conductive material. For example, the connecting wire CL may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The connecting wire CL may be constructed as a single layer made of the above-mentioned materials. In some embodiments, the connecting wire CL may be constructed as a multilayer made of the above-mentioned materials.

[0178] The chip-on-film (COF) can be attached to a second pad PAD2. The COF may include leads LE. An anisotropic conductive film (ACF) can be disposed between the leads LE and the second pad PAD2. The leads LE can be electrically connected to the second pad PAD2 using the anisotropic conductive film ACF. A driver chip IC can be mounted on the COF. The driver chip IC can be mounted on a surface opposite to the surface of the COF where the leads LE are disposed, but this disclosure is not limited thereto. The leads LE and the driver chip IC can be disposed on the same surface of the COF.

[0179] The driver chip IC can be used to apply data signals to each data line DL. The data signals provided by the driver chip IC can be transmitted to the data line DL through the second pad PAD2, the connection line CL, the first pad PAD1, the substrate connection electrode CNTb, and the data connection electrode CNTa.

[0180] In some embodiments, the chip COF on the film can be removed. In this case, the driver chip IC can overlap with the second pad PAD2 in the thickness direction. For example, the driver chip IC can be electrically connected to the second pad PAD2 via an anisotropic conductive film ACF. The driver chip IC can be electrically connected to the second pad PAD2.

[0181] In the following text, reference will be made to Figure 8 To describe the shape of the through-hole TH on the substrate.

[0182] Figure 8 yes Figure 7 A magnified schematic cross-sectional view of region A.

[0183] refer to Figure 8 The first substrate 11 may include a first surface and a second surface 11b. The first substrate 11 may also include a side surface 11a that contacts the substrate via TH. The etch stop element ES may include a first surface and a second surface ESb opposite to the first surface. The etch stop element ES may also include a side surface ESa that contacts the etch stop element via THa.

[0184] The via TH of the substrate can be surrounded by an extension line of a first surface of the first substrate 11, an extension line of a second surface 11b of the first substrate 11, and a side surface 11a of the first substrate 11. The extension line of the first surface of the first substrate 11 can meet an adjacent first surface of the first substrate 11. The extension line of the second surface 11b of the first substrate 11 can meet an adjacent second surface 11b of the first substrate 11. Each side surface 11a of the first substrate 11 can connect the point where the extension line of the first surface of the first substrate 11 meets the first surface of the first substrate 11 to the point where the extension line of the second surface 11b of the first substrate 11 meets the second surface 11b of the first substrate 11.

[0185] The width of the substrate via TH can decrease from the extension line of the second surface 11b of the first substrate 11 toward the extension line of the first surface of the first substrate 11. The width of the substrate via TH may include a second width W2 equal to the length of the extension line of the first surface of the first substrate 11, and a first width W1 equal to the length of the extension line of the second surface 11b of the first substrate 11. According to embodiments of the present disclosure, the second width W2 may be smaller than the first width W1.

[0186] The side surface 11a of the first substrate 11 forming through hole TH can form a curved surface CR.

[0187] The curved surface CR formed by the side surface 11a of the first substrate 11 can have a convex cross-sectional shape that faces the substrate through hole TH.

[0188] Furthermore, the slope of each side surface 11a of the first substrate 11 can gradually become steeper from the point where the extension line of the second surface 11b of the first substrate 11 meets the second surface 11b of the first substrate 11 toward the point where the extension line of the first surface of the first substrate 11 meets the first surface of the first substrate 11.

[0189] The etch stop element ES may include a first surface and a second surface ESb that contacts the first surface of the first substrate 11. Furthermore, the etch stop element ES may also include a side surface ESa that contacts the etch stop via THa. The first surface of the etch stop element ES may contact the first surface 12a of the buffer layer 12. The etch stop via THa may be surrounded by an extension line of the first surface of the etch stop element ES, an extension line of the second surface ESb of the etch stop element ES, and a side surface ESa of the etch stop element ES.

[0190] The average slope of the side surface ESa of the etch stop element ES can be greater than the average slope of the side surface 11a of the first substrate 11.

[0191] In the terminating via THa, the width of the extension line of the first surface of the etched terminating element ES, or the upper width of the terminating via THa, can be equal to the width of the extension line of the second surface ESb of the etched terminating element ES, or the lower width of the terminating via THa. For example, the width W3 of the terminating via THa can be constant along the thickness direction. In this case, the direction in which the side surface ESa of the etched terminating element ES extends can be perpendicular to the direction in which the second surface ESb of the etched terminating element ES extends.

[0192] The width W3 of the extension line of the second surface ESb of the etch stop ES can be substantially equal to the width W2 of the substrate via TH. In this case, the side surface ESa of the etch stop ES and the side surface 11a of the first substrate 11 can be continuously connected.

[0193] According to embodiments of this disclosure, substrate vias (TH) can be formed by laser irradiation and wet etching.

[0194] For example, a laser can be directed at the location where a via (TH) will be formed on the substrate. The laser can be a femtosecond laser. In this document, a femtosecond laser can refer to a laser with a pulse width of approximately 200 to approximately 500 femtoseconds. However, it should be understood that this disclosure is not limited thereto. Laser LS (see...) Figure 11 It can be light in a short wavelength range from near-infrared (IR) laser to ultraviolet (UV) laser, or it can be light in a multi-wavelength range that includes various wavelength ranges.

[0195] A laser can be irradiated from the second surface 11b of the first substrate 11 toward the first surface that contacts the etch stop element ES. The laser focal point can be formed at multiple locations. According to embodiments of the present disclosure, the laser focal point can be formed on, but is not limited to, the first surface of the first substrate 11.

[0196] When a laser is irradiated at the location where a via TH will be formed in the substrate, the structure at that location may be deformed. For example, the Si-O bonds in the glass at the location where the first substrate 11 is formed may be broken. Therefore, the etching selectivity to the etching solution at this location may be greater than the etching selectivity at other locations without laser irradiation.

[0197] After laser irradiation, the entire surface of the first substrate 11 can be etched. Wet etching can be used during the etching process. Alkaline solutions such as potassium hydroxide (KOH) and sodium hydroxide (NaOH) or acidic solutions such as hydrofluoric acid (HF) can be used as the etching solution during the etching step. Wet etching can be performed on the entire surface of the first substrate 11.

[0198] As described above, the etching selectivity of the etching solution at the laser-irradiated location can be greater than that at other locations not irradiated by the laser. Therefore, as a result of wet etching, the substrate via TH can be formed at the laser-irradiated location.

[0199] During the etching process, the etching selectivity of the first substrate 11 to the etching solution can be much greater than that of the etching terminator ES. Therefore, even if the etching solution comes into contact with the etching terminator ES during the etching process, the first surface of the etching terminator ES will not be etched.

[0200] According to embodiments of this disclosure, laser irradiation and wet etching can be performed simultaneously during the process of forming substrate vias TH, thereby achieving good processing quality, high speed, and high aspect ratio (thickness relative to width of substrate via TH). Furthermore, compared to laser drilling, which uses a laser to drill substrate vias, the physical damage to the substrate can be minimal, and the substrate strength can be excellent.

[0201] Furthermore, the etching stop element ES can be configured to cover the substrate via TH, thereby preventing the etching solution from diffusing to the first surface of the first substrate 11 during the process of forming the substrate via TH. In this way, corrosion and / or etching of the electrodes on the first substrate 11 due to the etching solution can be prevented.

[0202] Furthermore, as described above, since the substrate connection electrode CNTb is disposed in the display area DA, the chip-on-film (COF) electrically connected to the substrate connection electrode CNTb can be disposed on the second surface 11b of the first substrate 11 of the display device 1, and can also be disposed in the display area DA. In this way, dead zones caused by the chip-on-film (COF) and fan-out wiring can be reduced.

[0203] In the following description, a method for manufacturing display device 1 according to an embodiment of the present disclosure will be described. In the following description, the same or similar elements will be indicated by the same or similar reference numerals, and redundant descriptions will be omitted or briefly described.

[0204] Figure 9 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment of the present disclosure. Figure 10 , Figure 11 , Figure 13 , Figure 15 , Figure 17 and Figure 18 This is a schematic perspective view illustrating the processing steps of a method for manufacturing a display device according to an embodiment of the present disclosure. Figure 12 It is along Figure 11 A schematic cross-sectional view of line VII-VII'. Figure 14It is along Figure 13 A schematic cross-sectional view of line VIII-VIII. Figure 16 It is along Figure 15 A schematic cross-sectional view of the line IX-IX'. Figure 19 It is along Figure 18 A schematic cross-sectional view of the line X-X'. Figures 20 to 24 This is a schematic cross-sectional view illustrating the processing steps of a method for manufacturing a display device according to an embodiment of the present disclosure.

[0205] First, you can refer to Figure 9 and Figure 10 The first mother substrate 11' is prepared to be an insulating substrate. The first mother substrate 11' can be made of an insulating material such as glass, quartz, polymer resin, or combinations thereof. The first mother substrate 11' can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled up. The first mother substrate 11' can be as described above. Figure 5 and Figure 7 The mother substrate of the first substrate 11 described.

[0206] The first mother substrate 11' may have a rectangular or square shape. The first mother substrate 11' may include a first side extending in a first direction DR1 and a second side extending in a second direction DR2.

[0207] Alignment mark AK can be formed near the corner where the first and second sides of the first mother substrate 11' meet. Alignment mark AK can be formed by laser or the like. In some embodiments, alignment mark AK can be formed by electron beam.

[0208] refer to Figure 9 , Figure 11 and Figure 12 A first mother substrate 11', including a first surface and a second surface opposite to the first surface, can be irradiated with a laser LS to form a first mother substrate 11_1' including a modified region HA (step S10). The region other than the modified region HA can be defined as a non-modified region NHA. The modified region HA can become a substrate via TH, which will be described later.

[0209] A laser LS can be a femtosecond laser. In this document, a femtosecond laser can refer to a laser with a pulse width of approximately 200 to approximately 500 femtoseconds. However, it should be understood that this disclosure is not limited thereto. A laser LS can be light in a short wavelength range from near-infrared (IR) lasers to ultraviolet (UV) lasers, or it can be light in a multi-wavelength range encompassing various wavelength ranges.

[0210] A laser LS can be applied from a first surface of the first mother substrate 11' to a second surface. The focal point of the laser LS can be formed at different locations. According to embodiments of this disclosure, the focal point of the laser LS can be formed on, but is not limited to, the second surface of the first mother substrate 11'.

[0211] The structure of the first mother substrate 11'_1 may be deformed at the modified region HA. For example, the Si-O bonds of the illustrated glass used to form the first mother substrate 11'_1 at this location may be broken. Therefore, the etching selectivity for the etching solution at this location may be greater than that at other locations without laser LS irradiation.

[0212] Subsequently, reference Figure 9 , Figure 13 and Figure 14 An etch stop element ES' can be formed on the first surface of the first mother substrate 11'_1 to cover the modified region HA (step S20). The modified region HA can overlap with the etch stop element ES' in the thickness direction. The etch stop element ES can include an organic material. In some embodiments, the etch stop element ES' can include an inorganic material.

[0213] refer to Figure 9 , Figure 15 and Figure 16 An upper display module UDM can be set on the etching termination element ES', such that the upper display module UDM overlaps with the modified region HA (step S30). The upper display module UDM can refer to being set on the above reference. Figure 5 and Figure 7 The element on the described etch stopper ES.

[0214] Despite Figure 15 In the example shown, four upper display modules (UDMs) can be disposed on the first mother substrate 11'_1, but the number of upper display modules (UDMs) is not limited to four. The number of upper display modules (UDMs) can be one, two, three, five, or more.

[0215] The upper display modules UDM can be physically separated from each other. The upper display modules UDM can be set relative to the alignment mark AK mentioned above.

[0216] refer to Figure 16 The diagram shows a data line DL, which is located on the first interlayer dielectric layer 17 as the upper display module UDM, and a data connection electrode CNTa electrically connected to the data line DL and penetrating the first interlayer dielectric layer 17, the first protective layer 15, the first gate insulating layer 13, and the buffer layer 12. The data connection electrode CNTa may contact the etch stop element ES'.

[0217] Subsequently, reference Figure 9 and Figure 17 A packaged component can be disposed on the upper display module UDM (step S40). The packaged component may include, for example, a second mother substrate 20'. The second mother substrate 20' may be the one referenced above. Figure 2 The mother substrate of the second display substrate 20 described.

[0218] An etch stop element ES' and an upper display module UDM can be disposed between the second mother substrate 20' and the first mother substrate 11'_1. Furthermore, the second mother substrate 20' and the first mother substrate 11'_1 can be coupled to each other via a sealing member, which will be described later.

[0219] Subsequently, reference Figure 9 , Figure 18 and Figure 19 Wet etching mask EMK can be used for... Figure 17 The remaining areas or other components, excluding the second surface of the first mother substrate 11'_1, are subjected to masking processing (step S50). For example, a wet etching mask EMK can be used to perform masking processing on the side surfaces of the first mother substrate 11'_1, the side surfaces of the second mother substrate 20', and the top surface of the second mother substrate 20'. The wet etching mask EMK may include a material that is hardly etched relative to the wet etching solution. Therefore, during the process of forming vias in the substrate by etching, the remaining areas or other components, excluding the second surface of the first mother substrate 11'_1, can be prevented from contacting the wet etching solution and being etched.

[0220] A sealing member SEAL can be provided on each side surface (first side surface and second side surface) of each upper display module in the upper display module UDM. The sealing member SEAL can be provided between the second mother substrate 20' and the first mother substrate 11'_1. The sealing member SEAL can be provided between the etch stop member ES' and the second mother substrate 20'.

[0221] According to embodiments of this disclosure, before the second mother substrate 20' can be formed, a sealing member SEAL can be formed on each side surface of each side surface of the upper display module UDM, and the space surrounded by the sealing member SEAL can be filled with a filler material FM. After the second mother substrate 20' is formed, the filler material FM can be disposed between the second mother substrate 20' and the upper display module UDM, and the filler material FM can contact the second mother substrate 20' and the upper display module UDM.

[0222] Subsequently, reference Figure 9 and Figure 20A substrate via TH penetrating the first surface from the second surface of the first mother substrate 11'_1 can be formed by etching in each modified region of the modified region HA (step S60). The wet lithography mask EMK can be removed (step S70).

[0223] according to Figure 20 The thickness of the first mother substrate 11'_2 in the example can be less than that according to Figure 19 The thickness of the first mother substrate 11'_1 in the example is shown. This is because the total thickness of the first mother substrate 11'_1 can be reduced by etching.

[0224] Wet etching can be used during etching. The etching solution used during the etching step can be an alkaline solution such as potassium hydroxide (KOH) and sodium hydroxide (NaOH), or an acidic solution such as hydrofluoric acid (HF). Wet etching can be performed on the entire surface of the first mother substrate 11'_1.

[0225] The first mother substrate 11'_1 can be etched from the second surface using an etching solution, thereby allowing the thickness to gradually decrease. As described above, the modified region HA (see...) Figure 19 The etching selectivity of the etching solution at the ) location can be greater than that of the unmodified NHA region (see Figure 19 The etching selectivity of the etching solution at this location. Therefore, as a result of wet etching, vias TH on the substrate can be formed at locations such as... Figure 20 and Figure 7 The modified region HA shown (see Figure 19 ) place.

[0226] Subsequently, reference Figure 9 and Figure 21 Cell cutting can be performed on each upper display module in the upper display module UDM. As a result of cell cutting S70, such as... Figure 21 As shown, the side surface of the etch stop ES'_1 can be exposed to the outside.

[0227] Subsequently, reference Figure 9 and Figure 22 This can be done in the etch-terminated part ES'_1 (see Figure 21 A terminating via THa is formed in the substrate, completely penetrating the etch terminating via ES'_1, such that the terminating via THa can overlap with the substrate via TH (step S80). As a result, as... Figure 22 As shown, an etch stop element ES'_2, including a terminating via THa, can be formed.

[0228] The termination via THa can be formed by dry etching (step S80). Since the termination via THa is formed by dry etching, while the substrate via TH is formed by wet etching, the side surface ESa of the termination ES'_2 is etched (see...). Figure 8 The average slope of the first substrate 11'_3 can be greater than that of the side surface 11a (see [reference]). Figure 8 The average slope of ).

[0229] Because the terminating via THa is formed by dry etching, a high aspect ratio (the thickness of the terminating via THa relative to its width) can be achieved. In some embodiments, the terminating via THa can also be formed by wet etching.

[0230] Subsequently, reference Figure 9 and Figure 23 The substrate connection electrode CNTb can be used to fill the substrate via TH and the termination via THa (step S90). The substrate connection electrode CNTb can be connected to the data connection electrode CNTa (see...). Figure 16 It is electrically connected to the data cable DL (see Figure 16 ).

[0231] After forming the substrate connection electrode CNTb (step S90), a planarization process can also be performed on the lower surface of the substrate connection electrode CNTb adjacent to the second surface of the first substrate 11'_3.

[0232] Subsequently, reference Figure 9 and Figure 24 After forming the substrate connection electrode CNTb in S90, a first pad PAD1 can be formed, which overlaps with the substrate connection electrode CNTb and is disposed on the second surface of the first substrate 11'_3 (step S100).

[0233] Subsequently, reference Figure 7 This can form the first pad PAD1, the connecting line CL, and the second pad PAD2.

[0234] A first pad PAD1, a connecting line CL, and a second pad PAD2 can be disposed on a second surface (or back surface) of the first substrate 11'_3. One end of the connecting line CL can be electrically connected to the first pad PAD1, and the other end of the connecting line CL can be electrically connected to the second pad PAD2. The first pad PAD1 can overlap with the substrate connection electrode CNTb in the thickness direction and can be in direct contact with the substrate connection electrode CNTb. The first pad PAD1 can be electrically connected to the substrate connection electrode CNTb. The connecting line CL, the first pad PAD1, and the second pad PAD2 can be disposed on the same layer and can comprise the same material. However, it should be understood that this disclosure is not limited thereto. The connecting line CL, the first pad PAD1, and the second pad PAD2 can comprise different materials. The connecting line CL can comprise a conductive material. For example, the connecting line CL can comprise at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The connecting line CL can be constructed by a single layer made of the above materials. In some embodiments, the connecting line CL can be constructed by multiple layers made of the aforementioned materials.

[0235] Subsequently, the on-film chip (COF) can be mounted on the second pad PAD2 using an anisotropic conductive film (ACF). The leads LE of the on-film chip (COF) can be electrically connected to the second pad PAD2 via the anisotropic conductive film (ACF).

[0236] According to the method for manufacturing a display device according to embodiments of the present disclosure, laser irradiation and wet etching can be performed simultaneously during the process of forming a substrate via TH, thereby achieving good processing quality, high speed and high aspect ratio (thickness of the substrate via TH relative to its width).

[0237] Furthermore, the etch stop element ES can be configured to cover the substrate via TH, thereby preventing the etch solution from diffusing to the first surface of the first mother substrate during the process of forming the substrate via TH. In this way, corrosion and / or etching of the electrodes on the first mother substrate due to the etch solution can be prevented.

[0238] Figures 25 to 28 This is a schematic perspective view illustrating the processing steps of a method for manufacturing a display device according to another embodiment of the present disclosure. Figure 29 It is along Figure 28 A schematic cross-sectional view of the line XI-XI'. Figures 30 to 31 This is a schematic cross-sectional view illustrating the processing steps of a method for manufacturing a display device according to another embodiment of the present disclosure.

[0239] according to Figures 25 to 31 The method of the embodiment shown Figure 13The difference in the method is that multiple etch stop elements ES” can be formed on the first surface of the first mother substrate 11'_1 to cover the modified region HA respectively, and the etch stop elements ES” overlap with the modified region HA respectively, and can be spaced apart from each other.

[0240] refer to Figure 26 Each etch stop element in the “Etching Stop Element ES” can be disposed on the corresponding upper display module UDM. The side surface of each etch stop element in the “Etching Stop Element ES” can be aligned with the side surface of the corresponding upper display module UDM. However, it should be understood that this disclosure is not limited thereto. The side surface of the “Etching Stop Element ES” may protrude from the side surface of the upper display module UDM, or the side surface of the upper display module UDM may protrude from the side surface of the “Etching Stop Element ES”.

[0241] refer to Figure 27 A packaged component can be mounted on the upper display module UDM. The packaged component may include, for example, a second mother substrate 20'. The second mother substrate 20' may be as described above. Figure 2 The mother substrate of the second display substrate 20 described.

[0242] An etch stop element ES and an upper display module UDM can be disposed between the second mother substrate 20' and the first mother substrate 11'_1. Furthermore, the second mother substrate 20' and the first mother substrate 11'_1 can be coupled to each other by a sealing member, which will be described later.

[0243] Subsequently, reference Figure 28 and Figure 29 Wet etching mask EMK can be used for... Figure 27 The remaining areas or other elements shown, excluding the second surface of the first mother substrate 11'_1, undergo masking. According to this embodiment of the present disclosure, before forming the second mother substrate 20', a sealing member SEAL can be formed on each side surface of each side surface of the upper display module in the upper display module UDM, and the space surrounded by the sealing member SEAL can be filled with a filling material FM. Other elements may be the same as those described above; therefore, redundant descriptions will be omitted.

[0244] A sealing member SEAL can be disposed on each side surface (first side surface and second side surface) of each upper display module in the upper display module UDM. The sealing member SEAL can be directly disposed between the second mother substrate 20' and the first mother substrate 11'_1. The sealing member SEAL can contact the side surface of the etch stop member ES". However, it should be understood that this disclosure is not limited thereto.

[0245] Subsequently, reference Figure 30 This can form a through-hole (TH) in the substrate. This can be referenced above. Figure 20 The substrate vias TH are formed in essentially the same way as described; therefore, redundant descriptions will be omitted.

[0246] Subsequently, as Figure 31 As shown, the wet etched mask (EMK) can be removed and cell cutting can be performed. This process can be combined with... Figure 20 and Figure 21 The removal of wet etched mask EMK and cell cutting shown are essentially the same; therefore, redundant descriptions will be omitted.

[0247] Subsequently, you can refer to the above. Figure 22 , Figure 23 and Figure 24 In the etch stop element overlapping the described substrate via TH, a termination via THa that penetrates the etch stop element is formed. A substrate connection electrode CNTb that fills the substrate via TH and the termination via THa can be formed (step S90), and a first pad PAD1 that overlaps with the substrate connection electrode CNTb and can be disposed on the second surface of the first substrate can be formed (step S100). These processes can be the same as those described above; therefore, redundant descriptions will be omitted.

[0248] A method for manufacturing a display device according to another embodiment of the present disclosure will now be described.

[0249] Figure 32 This is a flowchart illustrating a method for manufacturing a display device according to another embodiment of the present disclosure. Figures 33 to 34 This is a schematic perspective view illustrating the processing steps of a method for manufacturing a display device according to another embodiment of the present disclosure. Figures 35 to 40 This is a schematic cross-sectional view illustrating the processing steps of a method for manufacturing a display device according to another embodiment of the present disclosure.

[0250] Figures 32 to 40 The processes of forming the first mother substrate 11'_1 (step S10), forming the etch stop element ES' (step S20), setting the upper display module UDM (step S30), and setting the packaging element (step S40) can be substantially the same as those processes of the method according to the above embodiments.

[0251] According to this embodiment of the disclosure, reference is made to Figure 33 After setting the encapsulation components (step S40), unit cutting can be performed on each upper display module (step S51).

[0252] Subsequently, reference Figure 34 and Figure 35Wet etching mask (EMK) can be used to perform masking on the remaining area or other components after cell cutting, excluding the second surface of the first mother substrate 11".

[0253] Subsequently, reference Figure 36 A substrate via TH penetrating the first surface from the second surface of the first substrate 11'_3 can be formed by etching at each modified region in the modified region HA (step S53).

[0254] Subsequently, reference Figure 37 This can remove the wet etched mask EMK, and then refer to... Figure 38 This can form a termination through hole THa (step S80).

[0255] Subsequently, reference Figure 39 The substrate can be connected to the electrode CNTb to fill the substrate via TH and the termination via THa (step S90).

[0256] Subsequently, reference Figure 40 A first pad PAD1 can be formed on the second surface of the first substrate 11'_3 to overlap with the substrate connection electrode CNTb.

[0257] The processes of cell cutting (step S51), mask processing (step S52), forming substrate via TH (step S53), forming termination via THa (step S80), forming substrate connection electrode CNTb (step S90), and forming first pad PAD1 (step S100) can be the same as those processes of the method according to the above embodiments; and therefore, redundant descriptions will be omitted.

[0258] Figure 41 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0259] refer to Figure 41 In the terminating via THa_1, the width of the extension line of the second surface ESb of the etched terminating via ES_1 can be equal to the width of the extension line of the first surface of the etched terminating via ES_1. The upper width of the terminating via THa_1 can be equal to the lower width W3_1 of the terminating via THa_1.

[0260] The width W3_1 of the extension line of the second surface ESb of the etch stop ES_1 can be greater than the width W2 of the substrate via TH. For example, the stop via THa_1 can overlap with the substrate via TH in the thickness direction and can overlap with the first surface of the first substrate 11, for example, partially overlap.

[0261] If the termination via THa_1 was etched during its formation process, it can be formed Figure 41The structure shown is such that the first surface of the first substrate 11 can be partially exposed by the etch stop element ES_1.

[0262] Figure 42 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0263] according to Figure 42 The terminating via THa_2 of the etch stop element ES_2 in the embodiment is with Figure 8 The difference between the etch stop element ES and the terminating via THa can be that the width of the terminating via THa_2 gradually decreases from the extension line of the second surface ESb of the etch stop element ES_2 to the extension line of the first surface.

[0264] According to embodiments of this disclosure, the inclined cross-sectional shape of the side surface ESa_1 of the etch stop ES_2 that contacts the etch stop via THa_2 can have a straight line shape inclined relative to the third direction DR3. For example, the inclination angle formed by the side surface ESa_1 of the etch stop ES_2 and the second surface ESb of the etch stop ES_2 can be constant.

[0265] Figure 43 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0266] according to Figure 43 The buffer layer of the embodiment and according to Figure 8 The difference in the embodiment of the buffer layer 12 is that the first surface 12a_1 of the buffer layer 12 includes a first portion 12a1_1 and a second portion 12a2_1.

[0267] More specifically, the surface roughness of the first portion 12a1_1 can be less than that of the second portion 12a2_1. The second portion 12a2_1 can contact the substrate connection electrode CNTb, while the first portion 12a1_1 can not contact the substrate connection electrode CNTb. The second portion 12a2_1 can be formed by partially etching the surface of the buffer layer 12 with a dry etching solution during the etching process.

[0268] Other components can be referenced above. Figure 8 The components described are the same; therefore, redundant descriptions will be omitted.

[0269] Figure 44 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0270] Figure 44 Implementation examples and Figure 8The difference in the embodiment is that the etching residue ER can remain on the first surface CNTas of the data connection electrode CNTa in the termination via THa and on the first surface 12a of the buffer layer 12.

[0271] More specifically, etching residue ER may remain on the first surface CNTas of the data connection electrode CNTa in the termination via THa and on the first surface 12a of the buffer layer 12.

[0272] According to embodiments of this disclosure, after forming the termination via THa, residue from the etched termination ES may remain on the first surface CNTas of the data connection electrode CNTa and the first surface 12a of the buffer layer 12, and the residue may not be completely removed. The etch residue ER may comprise the same material as the etched termination ES. The etch residue ER may contact the substrate connection electrode CNTb in the termination via THa. However, it should be noted that the structure formed by the material of the etch residue ER may differ from the structure formed by the material of the etched termination ES. For example, the material in the etch residue ER may undergo some changes, such as carbonization, during a laser irradiation process. However, it should be understood that this disclosure is not limited thereto. The structure formed by the material of the etch residue ER may be the same as the structure formed by the material of the etched termination ES.

[0273] Other components may be the same as those mentioned above; therefore, redundant descriptions will be omitted.

[0274] Figure 45 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0275] according to Figure 45 The first substrate 11 and substrate via TH_1 of the embodiment are in accordance with Figure 8 The difference between the first substrate 11 and the substrate via TH in the embodiment is that the first substrate 11 includes a substrate via TH_1, and the inclined cross-sectional shape of the side surface 11a_1 of the first substrate 11 that contacts the substrate via TH_1 has a straight shape.

[0276] For example, the tilt angle of the side surface 11a_1 of the first substrate 11 can be constant.

[0277] According to embodiments of this disclosure, a substrate via TH_1 can be formed by adjusting the etching solution or etching time.

[0278] The substrate via TH_1 according to the embodiment can be formed by dry etching.

[0279] Figure 46 This is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0280] according to Figure 46 The display device 2 of the embodiment and Figure 8 The difference in the display device 1 is that it also includes a gate connection electrode GCE electrically connected to the data line DL, and another gate connection electrode CNTc connecting the gate connection electrode GCE to the substrate connection electrode CNTb.

[0281] The gate connection electrode GCE can be set at the above reference. Figure 7 On the first gate conductive layer as described. Another gate connection electrode CNTc can penetrate the first gate insulating layer 13 and the buffer layer 12 in the thickness direction.

[0282] In some embodiments, the gate connection electrode GCE may be disposed on the second gate conductive layer. Another gate connection electrode CNTc may penetrate the first protective layer 15, the first gate insulating layer 13, and the buffer layer 12 in the thickness direction.

[0283] According to this embodiment, a gate connection electrode GCE and another gate connection electrode CNTc can also be formed, thereby reducing the total resistance of the current path from the data line DL to the first pad PAD1.

[0284] Figure 47 This is a schematic plan view of a display device according to another embodiment of the present disclosure.

[0285] according to Figure 47 The display device 2 in the embodiment is a spliced ​​display device 2 that includes the display device 1 according to the above embodiments of the present disclosure.

[0286] Since the display device 1 included in the display device 2 has already been described above, redundant descriptions will be omitted.

[0287] The long or short sides of the display device 1 can extend from each other. Some display devices 1 can form one side of the display device 2, some display devices 1 can be located at the corners of the display device 2 to form two adjacent sides, and some display devices 1 can be located inside the display device and surrounded by other display devices 1. The display devices 1 can have different border shapes depending on their position, or they can have the same border shape.

[0288] Figure 48 This is a schematic plan view of a display device according to another embodiment of the present disclosure when viewed from above. Figure 49 This is a schematic plan view of a display device according to another embodiment of the present disclosure when viewed from the bottom.

[0289] according to Figure 48 and Figure 49The display device 3 of the embodiment differs from the display device 1 according to the above embodiment in that the substrate connection electrode CNTb can be electrically connected to the scan line SL. According to embodiments of this disclosure, the above references can be removed. Figure 3 The described scan driver SP. According to this embodiment, the substrate connection electrodes CNTb can be arranged along the first direction DR1.

[0290] Connector CL can be disposed on the second surface of the first substrate. One end of connector CL can form a first pad PAD1, and the other end of connector CL can form a second pad PAD2. Although in Figure 48 and Figure 49 One end of the connecting line CL can form a first pad PAD1, and the other end of the connecting line CL can form a second pad PAD2. However, it can be stated that the connecting line CL can be electrically connected to each of the first pad PAD1 and the second pad PAD2. The second pad PAD2 can be associated with the connecting line CL individually. Multiple second pads PAD2 can be provided. The second pads PAD2 can be arranged along a second direction DR2. Some connecting lines in the connecting line CL can be electrically connected to the first pad PAD1, and can include at least one bent portion extending downwards in the first direction DR1.

[0291] For example, each of the connecting lines CL may include an extension extending from one end of the connecting line CL in the first direction DR1, and a fan-out routing disposed between the curved portion and the second pad PAD2. In the fan-out routing, adjacent connecting lines CL may be closer to each other. One end of the fan-out routing may be electrically connected to the extension of the connecting line CL, and the other end of the fan-out routing may be electrically connected to the second pad PAD2.

[0292] The chip-on-film (COF) can be disposed on an adjacent second pad PAD2. The COF can be attached to the adjacent second pad PAD2. The COF can be disposed on the second surface of the first substrate 11 of the display device 3, and can be disposed in the display area DA, thereby avoiding dead zones that may occur when disposing of the COF.

[0293] While the embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will recognize that various modifications, additions, and substitutions may be made without departing from the scope and spirit of the invention as disclosed in the appended claims (including any equivalents).

Claims

1. A display device, comprising: A first substrate has a display area and a non-display area adjacent to the display area, and the first substrate includes a substrate through-hole penetrating the first substrate in the thickness direction; An etching stop element is disposed on a first surface of the first substrate. The etching stop element includes a stop element through hole, which overlaps with a through hole in the substrate and penetrates the etching stop element in the thickness direction. The data line is disposed on the etched termination element; A substrate connection electrode fills the substrate through-hole and the termination through-hole; the substrate connection electrode is disposed in the display area and electrically connected to the data line; and A first pad is disposed on a second surface of the first substrate opposite to the first surface and overlaps with the substrate connection electrode. The first pad is electrically connected to the substrate connection electrode. The etching stopper includes a first surface that contacts the first surface of the first substrate and a second surface that is opposite to the first surface of the etching stopper. The substrate connection electrode includes: The first surface that is coplanar with the second surface of the etching termination element; A second surface coplanar with the second surface of the first substrate, the second surface of the substrate connecting the electrode has a first width; The side surface is bent to form the substrate through-hole between the first surface of the first substrate and the second surface of the first substrate; The second width between the first surface of the first substrate and the second surface of the first substrate, wherein the second width of the substrate connecting electrode is smaller than the first width of the substrate connecting electrode; and The third width above the first surface of the first substrate, wherein the third width of the substrate connecting electrode is greater than the second width of the substrate connecting electrode.

2. The display device according to claim 1, wherein, The substrate via is surrounded by an extension line of the second surface of the first substrate, an extension line of the first surface of the first substrate, and a side surface of the first substrate.

3. The display device according to claim 2, wherein, The terminating via is surrounded by the extension line of the first surface of the etching terminating element, the extension line of the second surface of the etching terminating element, and the side surface of the etching terminating element. The average slope of the side surface of the etch stop element is greater than the average slope of the side surface of the first substrate.

4. The display device according to claim 3, wherein, The terminating via overlaps with the first surface of the first substrate in the thickness direction.

5. The display device according to claim 3, further comprising: A buffer layer is disposed on the second surface of the etch stop member and between the etch stop member and the data line. The surface roughness of the buffer layer that contacts the electrode of the substrate is greater than the surface roughness of the buffer layer that does not contact the electrode of the substrate.

6. A method for manufacturing a display device, the method comprising: Multiple modified regions are formed by irradiating a first mother substrate with a laser. The first mother substrate includes a first surface and a second surface opposite to the first surface. An etch stop is formed on the first surface of the first mother substrate to cover the plurality of modified regions; Multiple upper display modules are provided on the etching termination component, such that each of the multiple upper display modules overlaps with the corresponding modified region in the multiple modified regions; An encapsulation element is disposed on the plurality of upper display modules; A substrate via is formed by etching in each of the plurality of modified regions to penetrate the first surface from the second surface of the first mother substrate. A termination via is formed that penetrates the etching termination, such that the termination via overlaps with the substrate via. as well as A substrate connection electrode is formed to fill the through-holes in the substrate and the through-holes in the termination element. The etching stop element includes a first surface that contacts the first surface of the first mother substrate and a second surface that is opposite to the first surface of the etching stop element. The substrate connection electrode includes: The first surface that is coplanar with the second surface of the etching termination element; The second surface coplanar with the second surface of the first mother substrate, and the second surface of the substrate connecting the electrode has a first width; The side surface is bent to form the substrate through-hole between the first surface of the first mother substrate and the second surface of the first mother substrate; The second width between the first surface of the first mother substrate and the second surface of the first mother substrate, wherein the second width of the substrate connecting electrode is smaller than the first width of the substrate connecting electrode; and The third width above the first surface of the first mother substrate, wherein the third width of the substrate connecting electrode is greater than the second width of the substrate connecting electrode.

7. The method according to claim 6, further comprising: After the packaging element is set up, a wet etching mask is used to perform masking on the area other than the second surface of the first mother substrate.

8. The method according to claim 7, wherein, The etching includes wet etching.

9. The method according to claim 7, further comprising: After forming the through-holes in the substrate, the wet etching mask is removed; as well as Unit cutting is performed on each of the plurality of upper display modules.

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