A computing device and neural network system

Abstract

The application provides a computing device and a neural network system. The computing device comprises: input processing circuitry configured to input a first input signal to a first input port of a computing array and input a second input signal to a second input port of the computing array after determining that first input data is a negative value, wherein the first input signal is used to indicate an absolute value of the first input data, and the second input signal is used to indicate that the first input data is a negative value; and the computing array is configured to perform a calculation on the first input data and a first weight value stored in the computing array based on the first input signal and the second input signal to obtain a first calculation result. The computing device provided by the application can directly receive input data with a negative value and perform a calculation on the input data with a negative value, thereby reducing the number of calculations, improving the calculation efficiency, saving the calculation resources, and reducing the calculation cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to a computing device and a neural network system. BACKGROUND

[0002] Neural networks are widely used in various fields such as speech and image processing. Using Flash memory as a computing array to implement the multiply-add computation of neural networks can effectively improve the processing speed of data, reduce the power consumption of data movement, and thus improve the computing performance.

[0003] The existing computing array can be built in an array form by a plurality of Flash devices. If the input data input to the computing array is a negative value, the Flash device cannot work normally due to the performance of the Flash device itself, and thus the computation cannot be completed. In view of this, the input data is split into a first matrix that only retains the elements with positive values in the input data and a second matrix that only retains the absolute values of the elements with negative values in the input data, and the first matrix and the second matrix are input to the computing array for computation, so as to obtain two computation results corresponding to the first matrix and two computation results corresponding to the second matrix, and finally obtain the computation result of the input data according to the computation results of the two matrices.

[0004] In the above computation process, the number of computations is increased, so that more computing resources (such as device overhead and power consumption, etc.) are occupied, resulting in low computation efficiency. SUMMARY

[0005] The embodiments of the present application provide a computing device and a neural network system, which can save computing resources and improve computation efficiency.

[0006] A first aspect of the embodiments of the present application provides a computing device, which comprises an input processing circuit and a computing array, and the input processing circuit is connected to the computing array. After receiving first input data from the outside, the input processing circuit can first determine the positive and negative of the first input data. After determining that the first input data is negative, the input processing circuit inputs a first input signal to a first input port of the computing array and inputs a second input signal to a second input port of the computing array. The first input signal is used to indicate the absolute value of the first input data, and the second input signal is used to indicate that the first input data is negative. After receiving the first input signal and the second input signal, the computing array can perform computation on the first input data and a first weight value stored in the computing array based on the first input signal and the second input signal, to obtain a first computation result.

[0007] As can be seen from the above computing device, since the computing array has two input ports, the first input port can receive a first input signal for indicating an absolute value of the first input data, and the second input port can receive a second input signal for indicating that the first input data is a negative value, after receiving the first input signal and the second input signal from the input processing circuit, the computing array is equivalent to receiving the first input data being a negative value, and then the computing array can complete the calculation on the first input data being a negative value. Therefore, the computing device provided in the embodiment can directly receive the input data being a negative value and complete the calculation on the input data being a negative value, so that the number of calculations can be reduced, the calculation efficiency can be improved, the calculation resources can be saved, and the calculation cost can be reduced.

[0008] In a possible implementation, the input processing circuit is further configured to input, to the first input port of the computing array, a third input signal for indicating an absolute value of the second input data, and input, to the second input port of the computing array, a fourth input signal for indicating that the second input data is a positive value, after determining that the second input data is a positive value. The computing array is further configured to perform calculation on the second input data and a second weight value stored in the computing array based on the third input signal and the fourth input signal, to obtain a second calculation result.

[0009] Through the above implementation, the computing array can implement the calculation on the input data being a negative value, and also can implement the calculation on the input data being a positive value.

[0010] In a possible implementation, the computing array includes a first computing unit and a second computing unit, and the first computing unit and the second computing unit are connected to a first bit line in the computing array. The first computing unit is configured to perform calculation on the first input data and a first weight value stored in the computing array based on the first input signal and the second input signal, to obtain a first calculation result. The second computing unit is configured to perform calculation on the second input data and a second weight value stored in the computing array based on the third input signal and the fourth input signal, to obtain a second calculation result. The computing array is further configured to output a first output signal for indicating the calculation results of a plurality of computing units connected to the first bit line, and the calculation results of the plurality of computing units include the first calculation result and the second calculation result.

[0011] In a possible implementation, the computing array includes a plurality of computing units, and each computing unit includes at least one ferroelectric field effect transistor.

[0012] In the above implementation, the computing array can be implemented by the ferroelectric field effect transistor, and the ferroelectric field effect transistor works in a sub-threshold region, has small output current and low power consumption, and can further save the calculation cost.

[0013] In one possible implementation, the drains of the field effect transistors in the same column of the computing units are connected to the same bit line, the gates of the field effect transistors in the same row of the computing units are connected to the same word line, and the sources of the field effect transistors in the same row are connected to the same source line.

[0014] In one possible implementation, the computing array further includes a plurality of reference units, each of which includes at least one ferroelectric field effect transistor. One reference unit and one computing unit in the same row can constitute a current mirror.

[0015] A second aspect of the embodiments of the present application provides a neural network system, which includes: a processor configured to input first input data to a neural network computing chip. The neural network chip is connected to the processor and includes an input processing circuit and a computing array connected to the input processing circuit. Wherein:

[0016] The input processing circuit is configured to receive the first input data, and after determining that the first input data is negative, input a first input signal to a first input port of the computing array and input a second input signal to a second input port of the computing array, wherein the first input signal is used to indicate the absolute value of the first input data, and the second input signal is used to indicate that the first input data is negative. The computing array is configured to perform a calculation on the first input data and a first weight value stored in the computing array based on the first input signal and the second input signal to obtain a first calculation result.

[0017] As can be seen from the above neural network system, since the computing array has two input ports, the first input port can receive the first input signal used to indicate the absolute value of the first input data, and the second input port can receive the second input signal used to indicate that the first input data is negative. Therefore, after receiving the first input signal and the second input signal from the input processing circuit, the computing array is equivalent to receiving the first input data which is negative, and then the computing array can complete the calculation on the first input data which is negative. Therefore, the neural network system provided in the embodiment can directly receive the input data which is negative and complete the calculation on the input data which is negative, so as to reduce the number of calculations, improve the calculation efficiency, save the calculation resources, and reduce the calculation cost.

[0018] In one possible implementation, the input processing circuit is further configured to, after determining that the second input data is positive, input a third input signal to the first input port of the computing array and input a fourth input signal to the second input port of the computing array, wherein the third input signal is used to indicate the absolute value of the second input data, and the fourth input signal is used to indicate that the second input data is positive. The computing array is further configured to perform a calculation on the second input data and a second weight value stored in the computing array based on the third input signal and the fourth input signal to obtain a second calculation result.

[0019] Through the implementation manner, the computing array can implement the calculation of the input data with a negative value and the calculation of the input data with a positive value.

[0020] In a possible implementation manner, the computing array includes a first computing unit and a second computing unit, where the first computing unit and the second computing unit are connected to a first bit line in the computing array. The first computing unit is configured to calculate first input data and a first weight value stored in the computing array based on a first input signal and a second input signal, to obtain a first calculation result. The second computing unit is configured to calculate second input data and a second weight value stored in the computing array based on a third input signal and a fourth input signal, to obtain a second calculation result. The computing array is further configured to output a first output signal, where the first output signal is used to indicate the calculation results of a plurality of computing units connected to the first bit line, and the calculation results of the plurality of computing units include the first calculation result and the second calculation result.

[0021] In a possible implementation manner, the computing array includes a plurality of computing units, and each computing unit includes at least one ferroelectric field effect transistor.

[0022] In the implementation manner, the computing array can be implemented by the ferroelectric field effect transistor, where the ferroelectric field effect transistor works in a sub-threshold region, has small output current and low power consumption, and can further save the calculation cost.

[0023] In a possible implementation manner, the drains of the field effect transistors in the same column of computing units are connected to the same bit line, the gates of the field effect transistors in the same row of computing units are connected to the same word line, and the sources of the field effect transistors in the same row are connected to the same source line.

[0024] In a possible implementation manner, the computing array further includes a plurality of reference units, and each reference unit includes at least one ferroelectric field effect transistor. One reference unit and one computing unit in the same row can constitute a current mirror.

[0025] As can be seen from the above technical solutions, in the computing device and the neural network system provided by the embodiments of the present application, the computing array has two input ports, the first input port can receive a first input signal used to indicate the absolute value of the first input data, and the second input port can receive a second input signal used to indicate that the first input data is negative. Therefore, after receiving the first input signal and the second input signal from the input processing circuit, the computing array is equivalent to receiving the first input data with a negative value, and then the computing array can complete the calculation of the first input data with a negative value. Therefore, the computing device provided by the present application can directly receive the input data with a negative value and complete the calculation of the input data with a negative value, so that the number of calculations can be reduced, the calculation efficiency can be improved, the calculation resources can be saved, and the calculation cost can be reduced. Attached Figure Description

[0026] Figure 1 A schematic diagram of the structure of a neural network system provided in an embodiment of this application;

[0027] Figure 2 A schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0028] Figure 3 A schematic diagram of the weight data provided in the embodiments of this application;

[0029] Figure 4 This is a schematic diagram illustrating an application example of the computing device provided in the embodiments of this application. Detailed Implementation

[0030] This application provides a computing device and a neural network system. A neural network, also known as an artificial neural network (ANN) or a neural network-like system, is a mathematical or computational model in machine learning and cognitive science that mimics the structure and function of biological neural networks (the central nervous system of animals, especially the brain) for estimating or approximating functions. Artificial neural networks can include convolutional neural networks (CNNs), deep neural networks (DNNs), multilayer perceptrons (MLPs), and other types of neural networks.

[0031] Figure 1 This is a schematic diagram of the structure of a neural network system provided in an embodiment of this application. Figure 1 As shown, the neural network system 100 may include a host 110 and a neural network circuit 120. The neural network circuit 120 is connected to the host 110 via a host interface. The host interface may include a standard host interface and a network interface. For example, the host interface may include a peripheral component interconnect express (PCIe) interface. Figure 1 As shown, the neural network circuit 120 can be connected to the host 110 via the PCIe bus 130. Therefore, data can be input to the neural network circuit 120 via the PCIe bus 130, and processed data can be received from the neural network circuit 120 via the PCIe bus 130. Furthermore, the host 110 can monitor the operating status of the neural network circuit 120 through the host interface.

[0032] The host 110 can include a processor 1102 and a memory 1104. It should be understood that, in addition to the devices shown, the host 110 can also include a communication interface and other devices such as a disk as an external memory (not shown in the figure), without limitation. Figure 1 The host 110 can include a processor 1102 and a memory 1104. It should be understood that, in addition to the devices shown, the host 110 can also include a communication interface and other devices such as a disk as an external memory (not shown in the figure), without limitation. Figure 1 The host 110 can include a processor 1102 and a memory 1104. It should be understood that, in addition to the devices shown, the host 110 can also include a communication interface and other devices such as a disk as an external memory (not shown in the figure), without limitation.

[0033] The processor 1102 is the operation core and control core of the host 110. The processor 1102 can include multiple processor cores. The processor 1102 can be a super-large scale integrated circuit. The processor 1102 is installed with an operating system and other software programs, so that the processor 1102 can realize access to the memory 1104, cache, disk, and peripheral devices (such as the neural network circuit in the figure) in the host 110. It can be understood that, in the embodiments of the present application, the core in the processor 1102 can be a central processing unit (CPU), and can also be an application specific integrated circuit (ASIC). Figure 1

[0034] The memory 1104 is the main memory of the host 110. The memory 1104 is connected to the processor 1102 through a double data rate (DDR) bus. The memory 1104 is usually used to store various running software in the operating system, input and output data, and information exchanged with the external memory, etc. In order to improve the access speed of the processor 1102, the memory 1104 needs to have the advantage of fast access speed. In the traditional computer system architecture, a dynamic random access memory (DRAM) is usually used as the memory 1104. The processor 1102 can access the memory 1104 at high speed through a memory controller (not shown in the figure), and perform read and write operations on any one storage unit in the memory 1104. In the embodiments of the present application, the memory 1104 can be used to store input data to be subjected to neural network calculation. Figure 1

[0035] The neural network circuit 120 is a chip array composed of multiple neural network chips. For example, as shown in the figure, the neural network circuit 120 includes a plurality of neural network chips 1201, 1202, 1203, and 1204. Figure 1 ​​As shown, the neural network circuit 120 includes a plurality of neural network chips (chips) 1201 that perform data processing. For the convenience of description, the neural network chip 1201 in the present application is referred to as chip 1201. In the neural network circuit 120, the plurality of chips 1201 are connected to each other, for example, a certain chip 1201 can be connected to one or more adjacent chips 1201. Data transmission can be performed between the chips 1201.

[0036] The neural network system can include a plurality of neural network layers, and each neural network layer can input data through an input port 1203 and then output the calculation result thereof to the next neural network layer through an output port 1204. Figure 1 In the present application, the neural network layer is a logical layer concept, and the neural network layer can include a convolution layer, a pooling layer, etc. (not shown in the figure). One neural network layer refers to performing one neural network operation. Figure 1

[0037] Figure 2 A structural schematic diagram of a computing device provided in an embodiment of the present application. It should be noted that the computing device shown in the figure can refer to the chip 1201 in the figure, or can refer to a part of the chip 1201, which is not limited here. As shown in the figure, Figure 2 the computing device shown in the figure can refer to the chip 1201 in the figure, or can refer to a part of the chip 1201, which is not limited here. As shown in the figure, Figure 1 the computing device shown in the figure can refer to the chip 1201 in the figure, or can refer to a part of the chip 1201, which is not limited here. As shown in the figure, Figure 2 the computing device shown in the figure can refer to the chip 1201 in the figure, or can refer to a part of the chip 1201, which is not limited here. As shown in the figure, Figure 2 the computing device shown in the figure can refer to the chip 1201 in the figure, or can refer to a part of the chip 1201, which is not limited here. As shown in the figure,

[0038] ​The computing array 202 comprises multiple memory cells constructed in an array configuration. Each memory cell may contain at least one memory device, such as eFlash, NOR Flash, ReRAM, or a ferroelectric field-effect transistor (FeFET). For ease of explanation, the following description will assume that each memory cell contains one FeFET. It should be noted that the FeFETs in this embodiment typically operate in the subthreshold region. This means that the gate voltage of the FeFET is close to the threshold voltage, and there is a weak current between the source and drain of the FeFET, called the subthreshold current, which is exponentially related to the gate voltage. In this case, the FeFET has a small output current and low power consumption, which helps to save computing costs.

[0039] like Figure 2 As shown, the computing array 202 is an array containing N rows and M columns of FeFETs. In the computing array 202, the first column of FeFETs (i.e., Figure 2 Each FeFET in the leftmost column of the computation array 202 can serve as a reference cell. Each FeFET in columns 2 through M can serve as a computation cell in the computation array 202. Specifically, the drain and gate of the FeFETs in the same column of reference cells are connected; the drain of the FeFETs in the same column of computation cells is connected to the same bitline (BL); the gate of the FeFETs in the same row of computation cells is connected to the same wordline (WL); and the source of the FeFETs in the same row is connected to the same sourceline (SL). It is worth noting that all WLs of the computation array 202 are the first input ports of the computation array 202, all SLs of the computation array 202 are the second input ports of the computation array 202, and all BLs of the computation array 202 are the output ports of the computation array 202.

[0040] Based on the aforementioned interconnections of multiple FeFETs, a reference cell and a computation cell located in the same row can form a current mirror, for example... Figure 2 The first reference unit 2021 and the first calculation unit 2023 can form a current mirror, the second reference unit 2022 and the second calculation unit 2024 can form a current mirror, the first reference unit 2021 and the third calculation unit 2025 can form a current mirror, and so on. It should be understood that... Figure 2 The illustration uses only the leftmost column of FeFETs as the reference cell. In practical applications, any column of FeFETs in the computing array 202 can be used as the reference cell, and there is no restriction here.

[0041] Furthermore, weight data is typically used to represent the importance of input data to output data. In neural networks, weight data is usually represented by a real number matrix. Figure 3 This is a schematic diagram of the weight data provided in an embodiment of this application. Figure 3 As shown, the weight data is an N x M matrix, where each element represents a weight value. It should be understood that a neural network layer can include, for example,... Figure 3 The one or more weight data shown are not limited here.

[0042] In this embodiment, the weights of the computational units can be pre-configured. Specifically, each element in a weight matrix is ​​configured in a corresponding computational unit of the computational array 202, thereby allowing the computational array 202 to calculate the input data and the configured weight values. During the configuration process, the weights can be pre-configured. Figure 3 The weight data shown is configured to Figure 2 In the computation array 202 shown, each weight value is assigned to a corresponding computation unit. For example, Figure 3 element W 0,0 Configured to Figure 3 In the first computing unit 2023, Figure 3 element W 1,0 Configured to Figure 2 In the second computing unit 2024, Figure 3 The elements W0,1 are configured to Figure 2 The third computational unit 2025 is in the middle. Each element in the weight matrix corresponds to a computational unit. After configuration, the computational array 202 stores (is configured) the weight values ​​corresponding to each computational unit.

[0043] After configuration, the computing device can perform neural network calculations. Specifically, after receiving input data from the processor 1102, the input processing circuit 201 can preprocess the input data. The input processing circuit 201 can be a digital circuit. After processing the input data, the processing result can be converted into a voltage signal by a digital-to-analog converter (DAC) and input into the computing array 202. Since the processing result can be used to indicate the input data, the computing array 202 can calculate the result based on the input data and the weight values ​​stored in the computing array. The calculation result can be biased and converted into a digital signal by an analog-to-digital converter (ADC) as the final output signal of the computing array 202.

[0044] To further understand, the following will combine Figure 2 The aforementioned calculation process will be further explained.

[0045] As shown in FIG. 2, the first computing unit 2023 and the second computing unit 2024 are connected to the first BL (in the order from left to right in FIG. 2, the first BL is the first BL among all the BLs). After the input processing circuit 201 determines that the first input data is negative, the input processing circuit 201 generates a first input signal and a second input signal (both are voltage signals), the first input signal is used to indicate the absolute value of the first input data, and the second input signal is used to indicate that the first input data is negative. Then, the input processing circuit 201 inputs the first input signal to the first row of FeFETs through the first WL (in the order from top to bottom in FIG. 2, the WL connected to the first row of FeFETs), and inputs the second input signal to the first row of FeFETs through the first SL (the SL connected to the first row of FeFETs). After the input operation of the first input data is completed, the input operation of the second input data can be performed. After the input processing circuit 201 determines that the second input data is positive, the input processing circuit 201 generates a third input signal and a fourth input signal, the third input signal is used to indicate the absolute value of the second input data, and the fourth input signal is used to indicate that the second input data is positive. Then, the input processing circuit 201 inputs the third input signal to the second row of FeFETs through the second WL, and inputs the fourth input signal to the second row of FeFETs through the second SL. Figure 2 Figure 2 Figure 2

[0046] In addition to the first input data and the second input data, there can be other input data (such as third input data, fourth input data, and the like) to be input into the computing array 202. The input positions of the other input data in the computing array 202 are the other FeFETs except the FeFETs input by the first input data and the second input data. For example, the other input data can be input to the third row of FeFETs and / or the fourth row of FeFETs, and the like.

[0047] ​​​After the input operation of all input data is completed, the calculation operation of the input data can be performed. Specifically, the first calculation unit 2023 performs calculation on the first input data and the first weight value (i.e., the weight value corresponding to the first calculation unit 2023 stored in the calculation array 202) after receiving the first input signal and the second input signal (equivalent to receiving the first input data with a negative value), to obtain the first calculation result. The second calculation unit 2024 performs calculation on the second input data and the second weight value (i.e., the weight value corresponding to the second calculation unit 2024 stored in the calculation array 202) after receiving the third input signal and the fourth input signal (equivalent to receiving the second input data with a positive value), to obtain the second calculation result. Similarly, the remaining calculation results can also be obtained, i.e., the results obtained by performing calculation on the remaining input data by the remaining calculation units in the plurality of calculation units connected to the first BL, except the first calculation unit 2023 and the second calculation unit 2024.

[0048] When the calculation units of the first BL complete the calculation operation, the first BL can output the first output signal. The first output signal is used to indicate the calculation results of the plurality of calculation units connected to the first BL, which not only includes the first calculation result and the second calculation result, but also includes the remaining calculation results. In addition, the corresponding calculation units of the remaining BLs (e.g., the second BL, the third BL, etc.) can also perform the calculation operation as described above, so that the remaining BLs can also output the corresponding output signals, which will not be described here.

[0049] In the embodiment of the present application, since the calculation array 202 has two input ports, the first input port can receive the first input signal used to indicate the absolute value of the first input data, and the second input port can receive the second input signal used to indicate that the first input data is negative, so that the calculation array 202 receives the first input signal and the second input signal from the input processing circuit, which is equivalent to receiving the first input data with a negative value, and then the calculation array can complete the calculation on the first input data with a negative value. Therefore, the calculation device provided by the embodiment of the present application can directly receive the input data with a negative value and complete the calculation on the input data with a negative value, so as to reduce the number of calculations, improve the calculation efficiency, save the calculation resources, and reduce the calculation cost.

[0050] In order to further understand, the following will be combined with an application example to further introduce the calculation device provided by the embodiment of the present application. Figure 4 The application example of the calculation device provided by the embodiment of the present application is shown in FIG. 2. Figure 4 As shown in FIG. 2, the calculation device includes an input processing circuit 201 and a calculation array 202.

[0051] The computing array 202 comprises N x M threshold-voltage-variable FeFETs, and it is to be noted that one computing unit of the computing array 202 comprises one FeFET. The drain of FeFETs in the same column is connected to the same BL, the gate of FeFETs in the same row is connected to the same WL, the source of FeFETs in the same row is connected to the same SL, and the drain and the gate of the FeFET in the kth column are connected (k = 1 is schematically shown in the figure). N ≥ 1, M ≥ 2, k = 1, 2, …, M, and i = 1, 2, …, N. Figure 4

[0052] The input processing circuit 201 comprises an input judging unit 2011, an input processing unit 2012, and a potential setting unit 2013. The input judging unit 2011 is connected to the input processing unit 2012 and the potential setting unit 2013. The output end of the input processing unit 2012 is connected to all the WLs of the computing array 202, and the output end of the potential setting unit 2013 is connected to all the SLs of the computing array 202.

[0053] Suppose that N input data need to be implemented on the computing array 202 to perform multiplication and addition calculation. The following will describe how the N input data are input to the computing array. Take the ith input data as an example. The ith input data can be input to the input judging unit 2011, the input processing unit 2012, and the potential setting unit 2013. In addition, along with the input of the ith input data to the input processing unit 2012 and the potential setting unit 2013, the ith address signal can also be input to the input processing unit 2012 and the potential setting unit 2013, and the ith address signal is used to indicate the ith row of FeFETs.

[0054] After the input judging unit 2011 receives the ith input data, it first judges the positive and negative of the ith input data. After determining the positive and negative of the ith input data, the input judging unit 2011 generates the ith judging signal according to the positive and negative of the ith input data, and sends the ith judging signal to the input processing unit 2012 and the potential setting unit 2013. The ith judging signal is used to notify the input processing unit 2012 and the potential setting unit 2013 of the positive and negative of the ith input data.

[0055] ​After receiving the i-th input data, the i-th judgment signal and the i-th address signal, the input processing unit 2012 determines the positive or negative of the i-th input data based on the i-th judgment signal. If the i-th input data is negative, the input processing unit 2012 generates the i-th input signal (i.e., taking the absolute value of the i-th input data, and generating the i-th input signal based on the absolute value of the i-th input data), and sends the i-th input signal to the i-th row of FeFETs through the i-th WL based on the i-th address signal. If the i-th input data is positive, the input processing unit 2012 generates the i-th input signal (i.e., generating the i-th input signal based on the i-th input data), and sends the i-th input signal to the i-th row of FeFETs through the i-th WL based on the i-th address signal.

[0056] After receiving the i-th input data, the i-th judgment signal and the i-th address signal, the potential setting unit 2013 determines the positive or negative of the i-th input data based on the i-th judgment signal. If the i-th input data is negative, the potential setting unit 2013 generates the i+1-th input signal, and sends the i+1-th input signal to the i-th row of FeFETs through the i-th SL based on the i-th address signal, the i+1-th input signal is used to set the source potential of the i-th row of FeFETs to a negative potential. If the i-th input data is positive, the potential setting unit 2013 generates the i+1-th input signal, and sends the i+1-th input signal to the i-th row of FeFETs through the i-th SL based on the i-th address signal, the i+1-th input signal is used to set the source potential of the i-th row of FeFETs to a positive potential. It can be understood that if the source potential of the i-th row of FeFETs is set to a positive potential, it is equivalent to that the i-th input data input to the i-th row of FeFETs is positive. If the source potential of the i-th row of FeFETs is set to a negative potential, it is equivalent to that the i-th input data input to the i-th row of FeFETs is negative.

[0057] After inputting the i-th input data to the calculation array 202, the input of the i+1-th input data can be continued until the input of N input data is completed. After the N rows of FeFETs all receive the corresponding input data, the calculation array 202 performs calculation according to the N input data, and finally outputs M-1 output signals through the remaining BLs except the k-th BL.

[0058] It is worth noting that in the M-1 output signals, the j-th output signal is:

[0059]

[0060] wherein, is the j-th output signal; is the weight value of the FeFET in the i-th row and j-th column; if the i-th input data is negative, the i-th input data is denoted as , if the i-th input data is positive, the i-th input data is denoted as ; is the threshold voltage of the k-th FeFET in the i-th row; is the threshold voltage of the j-th FeFET in the i-th row; is a preset voltage parameter, which is approximately equal to 26 mV at room temperature; is a sub-threshold slope.

[0061] In addition, the input judging unit 2011, the input processing unit 2012 and the potential setting unit 2013 are usually digital circuits. The computing device in the application example can be provided with a DAC 203 between the computing array 202 and the input processing unit 2012. The DAC 203 is used to convert the processing result of the input data from the input processing unit 2012 into a voltage signal (i.e., the aforementioned input signal), and then send the voltage signal to the computing array 202.

[0062] Furthermore, the computing device further includes an ADC 204. The ADC 204 is connected with the BL in the computing array 202, so as to convert the M-1 output signals output by the computing array 202 into digital signals, for use by an external target digital circuit.

[0063] It can be clearly understood by those skilled in the art that, for the convenience and brevity of description, the specific working processes of the devices and the apparatuses described above and the technical effects produced can refer to the corresponding processes and technical effects in the foregoing method embodiments, which will not be described herein.

[0064] In several embodiments provided in the present application, the disclosed system, device and method can be implemented in other ways. For example, some features of the method embodiments described above can be omitted or not executed. The device embodiments described above are merely illustrative, and the division of units is merely a logical function division, and actual implementation can have another division manner, and multiple units or components can be combined or integrated into another system. In addition, the coupling between units or the coupling between components can be direct coupling or indirect coupling, and the above coupling includes electrical, mechanical or other forms of connection.

[0065] It should be understood that, in various embodiments of the present application, the size of the serial number of each process does not mean the execution order, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0066] In addition, the terms "system" and "network" are often used interchangeably herein. The term "and / or", merely describes an associated relationship, which means that there can be three relationships, for example, A and / or B, which can represent: A alone, A and B together, and B alone. In addition, the character " / " generally represents an "or" relationship between the front and back associated objects.

[0067] In summary, the above only describes the preferred embodiments of the technical scheme of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A computing device, characterized in that, The computing device includes: An input processing circuit is configured to, after determining that the first input data is negative, input a first input signal to a first input port of a computing array connected to the input processing circuit, and input a second input signal to a second input port of the computing array, wherein the first input signal is used to indicate the absolute value of the first input data, and the second input signal is used to indicate that the first input data is negative; the computing array includes a first computing unit and a second computing unit, wherein the first computing unit and the second computing unit are connected to the first bit line in the computing array; The computing array is used to calculate a first calculation result by combining the first input data with the first weight value stored in the computing array based on the first input signal and the second input signal. The first calculation unit is configured to perform calculations based on the first input signal and the second input signal, using the first input data and the first weight value stored in the calculation array, to obtain a first calculation result; The input processing circuit is further configured to, after determining that the second input data is positive, input a third input signal to the first input port of the computing array and input a fourth input signal to the second input port of the computing array, wherein the third input signal is used to indicate the absolute value of the second input data and the fourth input signal is used to indicate that the second input data is positive. The computing array is further configured to perform calculations on the second input data and the second weight value stored in the computing array based on the third input signal and the fourth input signal to obtain a second calculation result; The second calculation unit is used to calculate the second input data and the second weight value stored in the calculation array based on the third input signal and the fourth input signal to obtain a second calculation result; The computing array is further configured to output a first output signal, which indicates the calculation results of a plurality of computing units connected to the first bit line, wherein the calculation results of the plurality of computing units include the first calculation result and the second calculation result.

2. The computing device according to claim 1, characterized in that, The computing array includes multiple computing units, and each computing unit includes at least one ferroelectric field-effect transistor.

3. The computing device according to claim 2, characterized in that, The drains of field-effect transistors in the same column of computing units are connected to the same bit line, the gates of field-effect transistors in the same row of computing units are connected to the same word line, and the sources of field-effect transistors in the same row are connected to the same source line.

4. The computing device according to claim 3, characterized in that, The computing array also includes multiple reference units, each of which includes at least one ferroelectric field-effect transistor. A reference cell and a calculation cell located in the same row can form a current mirror.

5. A neural network system, characterized in that, include: The processor is used to input the first input data into the neural network computing chip; A neural network chip, connected to the processor and including an input processing circuit and a computing array connected to the input processing circuit, wherein: The input processing circuit is configured to receive the first input data, and after determining that the first input data is negative, input a first input signal to the first input port of the computing array and input a second input signal to the second input port of the computing array, wherein the first input signal is used to indicate the absolute value of the first input data, and the second input signal is used to indicate that the first input data is negative; the computing array includes a first computing unit and a second computing unit, wherein the first computing unit and the second computing unit are connected to the first bit line in the computing array; The computing array is used to calculate a first calculation result by combining the first input data with the first weight value stored in the computing array based on the first input signal and the second input signal. The first calculation unit is configured to perform calculations based on the first input signal and the second input signal, using the first input data and the first weight value stored in the calculation array, to obtain a first calculation result; The input processing circuit is further configured to, after determining that the second input data is positive, input a third input signal to the first input port of the computing array and input a fourth input signal to the second input port of the computing array, wherein the third input signal is used to indicate the absolute value of the second input data and the fourth input signal is used to indicate that the second input data is positive. The computing array is further configured to perform calculations on the second input data and the second weight value stored in the computing array based on the third input signal and the fourth input signal to obtain a second calculation result; The second calculation unit is used to calculate the second input data and the second weight value stored in the calculation array based on the third input signal and the fourth input signal to obtain a second calculation result; The computing array is further configured to output a first output signal, which indicates the calculation results of a plurality of computing units connected to the first bit line, wherein the calculation results of the plurality of computing units include the first calculation result and the second calculation result.

6. The neural network system according to claim 5, characterized in that, The computing array includes multiple computing units, and each computing unit includes at least one ferroelectric field-effect transistor.

7. The neural network system according to claim 6, characterized in that, The drains of field-effect transistors in the same column of computing units are connected to the same bit line, the gates of field-effect transistors in the same row of computing units are connected to the same word line, and the sources of field-effect transistors in the same row are connected to the same source line.

8. The neural network system according to claim 7, characterized in that, The computing array also includes multiple reference units, each of which includes at least one ferroelectric field-effect transistor. A reference cell and a calculation cell located in the same row can form a current mirror.

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